Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6961984

1

T1

18

T2

35

T3

37481

auto[1]

2580132

1

T4

27

T5

11742

T6

396

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2560720

1

T4

54

T5

11913

T6

567

auto[1]

6981396

1

T1

18

T2

35

T3

37481

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6244943

1

T3

37481

T4

68

T6

607

auto[1]

3297173

1

T1

18

T2

35

T4

69

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6135372	1			T1	18		T2	3		T3	35931
fifo_depth[1]	465339	1			T2	3		T3	1097		T4	6
fifo_depth[2]	384517	1			T2	7		T3	337		T4	5
fifo_depth[3]	313391	1			T2	4		T3	96		T4	4
fifo_depth[4]	268466	1			T2	3		T3	16		T4	9
fifo_depth[5]	238810	1			T2	2		T3	3		T4	3
fifo_depth[6]	228020	1			T2	5		T3	1		T4	9
fifo_depth[7]	199911	1			T2	1		T4	5		T5	1457
fifo_depth[8]	179435	1			T2	3		T4	3		T5	1235
fifo_depth[9]	123450	1			T2	2		T4	6		T5	901
fifo_depth[10]	94794	1			T2	1		T4	2		T5	645
fifo_depth[11]	57982	1			T2	1		T4	4		T5	360
fifo_depth[12]	57422	1			T4	1		T5	185		T47	94
fifo_depth[13]	28916	1			T5	96		T47	34		T14	7
fifo_depth[14]	37484	1			T5	42		T47	15		T14	5
fifo_depth[15]	24062	1			T5	14		T47	8		T60	6
fifo_depth[16]	102583	1			T5	11		T47	4		T60	4

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3522608

1

T2

32

T3

1550

T4

57

auto[1]

6019508

1

T1

18

T2

3

T3

35931

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9426252

1

T1

18

T2

35

T3

37481

auto[1]

115864

1

T20

2

T21

2

T22

6048

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

219638

1

T6

34

T17

52

T13

212

auto[0]

auto[0]

auto[0]

auto[1]

257467

1

T6

19

T13

217

T29

104

auto[0]

auto[0]

auto[1]

auto[0]

1084675

1

T3

1550

T6

55

T8

3037

auto[0]

auto[0]

auto[1]

auto[1]

221911

1

T17

40

T13

101

T29

3

auto[0]

auto[1]

auto[0]

auto[0]

412875

1

T4

26

T5

2475

T7

9

auto[0]

auto[1]

auto[0]

auto[1]

434404

1

T4

10

T5

5298

T6

20

auto[0]

auto[1]

auto[1]

auto[0]

446245

1

T2

32

T4

15

T5

4574

auto[0]

auto[1]

auto[1]

auto[1]

445393

1

T4

6

T5

2340

T6

19

auto[1]

auto[0]

auto[0]

auto[0]

243696

1

T4

5

T6

125

T7

29

auto[1]

auto[0]

auto[0]

auto[1]

228773

1

T4

2

T6

135

T7

30

auto[1]

auto[0]

auto[1]

auto[0]

3765832

1

T3

35931

T4

56

T6

231

auto[1]

auto[0]

auto[1]

auto[1]

222951

1

T4

5

T6

8

T7

27

auto[1]

auto[1]

auto[0]

auto[0]

386041

1

T4

8

T5

1306

T6

171

auto[1]

auto[1]

auto[0]

auto[1]

377826

1

T4

3

T5

2834

T6

63

auto[1]

auto[1]

auto[1]

auto[0]

402982

1

T1

18

T2

3

T5

2405

auto[1]

auto[1]

auto[1]

auto[1]

391407

1

T4

1

T5

1270

T6

132

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

450965

1

T4

5

T6

159

T7

29

auto[0]

auto[0]

auto[0]

auto[1]

470384

1

T4

2

T6

154

T7

30

auto[0]

auto[0]

auto[1]

auto[0]

4838395

1

T3

37481

T4

56

T6

286

auto[0]

auto[0]

auto[1]

auto[1]

432245

1

T4

5

T6

8

T7

27

auto[0]

auto[1]

auto[0]

auto[0]

783801

1

T4

34

T5

3781

T6

171

auto[0]

auto[1]

auto[0]

auto[1]

796467

1

T4

13

T5

8132

T6

83

auto[0]

auto[1]

auto[1]

auto[0]

833038

1

T1

18

T2

35

T4

15

auto[0]

auto[1]

auto[1]

auto[1]

820957

1

T4

7

T5

3610

T6

151

auto[1]

auto[0]

auto[0]

auto[0]

12369

1

T22

830

T53

1

T44

154

auto[1]

auto[0]

auto[0]

auto[1]

15856

1

T21

1

T22

1119

T44

365

auto[1]

auto[0]

auto[1]

auto[0]

12112

1

T22

404

T23

1

T53

2

auto[1]

auto[0]

auto[1]

auto[1]

12617

1

T22

263

T39

1

T44

87

auto[1]

auto[1]

auto[0]

auto[0]

15115

1

T20

1

T22

1292

T44

9

auto[1]

auto[1]

auto[0]

auto[1]

15763

1

T22

1197

T23

1

T54

1

auto[1]

auto[1]

auto[1]

auto[0]

16189

1

T20

1

T22

210

T55

1

auto[1]

auto[1]

auto[1]

auto[1]

15843

1

T21

1

T22

733

T53

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	256065	1			T4	5		T6	125		T7	29
fifo_depth[0]	auto[0]	auto[0]	auto[1]	244629	1			T4	2		T6	135		T7	30
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3777944	1			T3	35931		T4	56		T6	231
fifo_depth[0]	auto[0]	auto[1]	auto[1]	235568	1			T4	5		T6	8		T7	27
fifo_depth[0]	auto[1]	auto[0]	auto[0]	401156	1			T4	8		T5	1306		T6	171
fifo_depth[0]	auto[1]	auto[0]	auto[1]	393589	1			T4	3		T5	2834		T6	63
fifo_depth[0]	auto[1]	auto[1]	auto[0]	419171	1			T1	18		T2	3		T5	2405
fifo_depth[0]	auto[1]	auto[1]	auto[1]	407250	1			T4	1		T5	1270		T6	132
fifo_depth[1]	auto[0]	auto[0]	auto[0]	19700	1			T6	5		T17	12		T13	97
fifo_depth[1]	auto[0]	auto[0]	auto[1]	18692	1			T6	3		T13	148		T29	45
fifo_depth[1]	auto[0]	auto[1]	auto[0]	234694	1			T3	1097		T6	16		T8	1656
fifo_depth[1]	auto[0]	auto[1]	auto[1]	18820	1			T17	12		T13	63		T29	1
fifo_depth[1]	auto[1]	auto[0]	auto[0]	42517	1			T4	2		T5	261		T7	3
fifo_depth[1]	auto[1]	auto[0]	auto[1]	42782	1			T4	1		T5	590		T6	3
fifo_depth[1]	auto[1]	auto[1]	auto[0]	45429	1			T2	3		T4	2		T5	505
fifo_depth[1]	auto[1]	auto[1]	auto[1]	42705	1			T4	1		T5	254		T6	1
fifo_depth[2]	auto[0]	auto[0]	auto[0]	16421	1			T6	6		T17	23		T13	67
fifo_depth[2]	auto[0]	auto[0]	auto[1]	15824	1			T6	8		T13	46		T29	35
fifo_depth[2]	auto[0]	auto[1]	auto[0]	180149	1			T3	337		T6	13		T8	821
fifo_depth[2]	auto[0]	auto[1]	auto[1]	16261	1			T17	15		T13	20		T29	1
fifo_depth[2]	auto[1]	auto[0]	auto[0]	38241	1			T4	1		T5	274		T7	3
fifo_depth[2]	auto[1]	auto[0]	auto[1]	38292	1			T4	2		T5	576		T6	2
fifo_depth[2]	auto[1]	auto[1]	auto[0]	40948	1			T2	7		T4	1		T5	500
fifo_depth[2]	auto[1]	auto[1]	auto[1]	38381	1			T4	1		T5	269		T6	8
fifo_depth[3]	auto[0]	auto[0]	auto[0]	13069	1			T6	4		T17	13		T13	30
fifo_depth[3]	auto[0]	auto[0]	auto[1]	12730	1			T6	3		T13	18		T29	20
fifo_depth[3]	auto[0]	auto[1]	auto[0]	136459	1			T3	96		T6	8		T8	387
fifo_depth[3]	auto[0]	auto[1]	auto[1]	13032	1			T17	10		T13	12		T29	1
fifo_depth[3]	auto[1]	auto[0]	auto[0]	33972	1			T4	2		T5	282		T47	144
fifo_depth[3]	auto[1]	auto[0]	auto[1]	33965	1			T5	615		T6	1		T7	2
fifo_depth[3]	auto[1]	auto[1]	auto[0]	36639	1			T2	4		T4	1		T5	523
fifo_depth[3]	auto[1]	auto[1]	auto[1]	33525	1			T4	1		T5	258		T47	94
fifo_depth[4]	auto[0]	auto[0]	auto[0]	12347	1			T6	16		T17	4		T13	15
fifo_depth[4]	auto[0]	auto[0]	auto[1]	12675	1			T6	2		T13	4		T29	2
fifo_depth[4]	auto[0]	auto[1]	auto[0]	99710	1			T3	16		T6	13		T8	131
fifo_depth[4]	auto[0]	auto[1]	auto[1]	12684	1			T17	2		T13	6		T27	12
fifo_depth[4]	auto[1]	auto[0]	auto[0]	32208	1			T4	4		T5	289		T7	3
fifo_depth[4]	auto[1]	auto[0]	auto[1]	32405	1			T4	2		T5	598		T6	11
fifo_depth[4]	auto[1]	auto[1]	auto[0]	34700	1			T2	3		T5	514		T6	19
fifo_depth[4]	auto[1]	auto[1]	auto[1]	31737	1			T4	3		T5	277		T6	9
fifo_depth[5]	auto[0]	auto[0]	auto[0]	10473	1			T6	2		T13	1		T29	5
fifo_depth[5]	auto[0]	auto[0]	auto[1]	10548	1			T6	1		T13	1		T29	1
fifo_depth[5]	auto[0]	auto[1]	auto[0]	82406	1			T3	3		T6	2		T8	33
fifo_depth[5]	auto[0]	auto[1]	auto[1]	11202	1			T17	1		T27	4		T15	7
fifo_depth[5]	auto[1]	auto[0]	auto[0]	30322	1			T5	271		T47	132		T48	1
fifo_depth[5]	auto[1]	auto[0]	auto[1]	30514	1			T4	1		T5	561		T6	1
fifo_depth[5]	auto[1]	auto[1]	auto[0]	33296	1			T2	2		T4	2		T5	490
fifo_depth[5]	auto[1]	auto[1]	auto[1]	30049	1			T5	253		T47	91		T48	1
fifo_depth[6]	auto[0]	auto[0]	auto[0]	10286	1			T6	1		T13	2		T15	7
fifo_depth[6]	auto[0]	auto[0]	auto[1]	11804	1			T6	2		T29	1		T15	3
fifo_depth[6]	auto[0]	auto[1]	auto[0]	72111	1			T3	1		T6	1		T8	4
fifo_depth[6]	auto[0]	auto[1]	auto[1]	11535	1			T27	2		T15	18		T60	46
fifo_depth[6]	auto[1]	auto[0]	auto[0]	30014	1			T4	4		T5	264		T47	149
fifo_depth[6]	auto[1]	auto[0]	auto[1]	30029	1			T4	4		T5	554		T6	1
fifo_depth[6]	auto[1]	auto[1]	auto[0]	32940	1			T2	5		T4	1		T5	531
fifo_depth[6]	auto[1]	auto[1]	auto[1]	29301	1			T5	231		T6	1		T47	89
fifo_depth[7]	auto[0]	auto[0]	auto[0]	9407	1			T29	1		T15	3		T60	106
fifo_depth[7]	auto[0]	auto[0]	auto[1]	10095	1			T15	2		T60	70		T21	153
fifo_depth[7]	auto[0]	auto[1]	auto[0]	58032	1			T8	5		T17	17		T27	2
fifo_depth[7]	auto[0]	auto[1]	auto[1]	10362	1			T15	4		T60	35		T21	137
fifo_depth[7]	auto[1]	auto[0]	auto[0]	27546	1			T4	3		T5	253		T47	154
fifo_depth[7]	auto[1]	auto[0]	auto[1]	27749	1			T5	533		T17	10		T47	274
fifo_depth[7]	auto[1]	auto[1]	auto[0]	29841	1			T2	1		T4	2		T5	438
fifo_depth[7]	auto[1]	auto[1]	auto[1]	26879	1			T5	233		T47	82		T48	1
fifo_depth[8]	auto[0]	auto[0]	auto[0]	9392	1			T15	2		T60	85		T21	119
fifo_depth[8]	auto[0]	auto[0]	auto[1]	11586	1			T15	3		T60	52		T21	129
fifo_depth[8]	auto[0]	auto[1]	auto[0]	45732	1			T6	2		T17	8		T14	82
fifo_depth[8]	auto[0]	auto[1]	auto[1]	10859	1			T15	5		T60	40		T21	102
fifo_depth[8]	auto[1]	auto[0]	auto[0]	25091	1			T4	1		T5	204		T47	147
fifo_depth[8]	auto[1]	auto[0]	auto[1]	25560	1			T5	457		T6	1		T17	1
fifo_depth[8]	auto[1]	auto[1]	auto[0]	26974	1			T2	3		T4	2		T5	365
fifo_depth[8]	auto[1]	auto[1]	auto[1]	24241	1			T5	209		T47	63		T48	1
fifo_depth[9]	auto[0]	auto[0]	auto[0]	6205	1			T60	62		T21	97		T62	3
fifo_depth[9]	auto[0]	auto[0]	auto[1]	6972	1			T60	33		T21	88		T22	58
fifo_depth[9]	auto[0]	auto[1]	auto[0]	30648	1			T14	65		T60	66		T21	392
fifo_depth[9]	auto[0]	auto[1]	auto[1]	6958	1			T60	27		T21	90		T62	10
fifo_depth[9]	auto[1]	auto[0]	auto[0]	18127	1			T4	4		T5	153		T47	92
fifo_depth[9]	auto[1]	auto[0]	auto[1]	17837	1			T5	331		T17	1		T47	190
fifo_depth[9]	auto[1]	auto[1]	auto[0]	19426	1			T2	2		T4	2		T5	280
fifo_depth[9]	auto[1]	auto[1]	auto[1]	17277	1			T5	137		T47	36		T48	2
fifo_depth[10]	auto[0]	auto[0]	auto[0]	5523	1			T60	44		T21	69		T62	2
fifo_depth[10]	auto[0]	auto[0]	auto[1]	7154	1			T60	25		T21	69		T22	56
fifo_depth[10]	auto[0]	auto[1]	auto[0]	21044	1			T17	1		T14	32		T60	42
fifo_depth[10]	auto[0]	auto[1]	auto[1]	6285	1			T60	11		T21	62		T62	11
fifo_depth[10]	auto[1]	auto[0]	auto[0]	13444	1			T4	2		T5	111		T47	63
fifo_depth[10]	auto[1]	auto[0]	auto[1]	13587	1			T5	235		T47	114		T48	2
fifo_depth[10]	auto[1]	auto[1]	auto[0]	14792	1			T2	1		T5	185		T47	83
fifo_depth[10]	auto[1]	auto[1]	auto[1]	12965	1			T5	114		T47	34		T48	1
fifo_depth[11]	auto[0]	auto[0]	auto[0]	3068	1			T60	26		T21	35		T62	2
fifo_depth[11]	auto[0]	auto[0]	auto[1]	4676	1			T60	18		T21	33		T22	35
fifo_depth[11]	auto[0]	auto[1]	auto[0]	12388	1			T17	2		T14	27		T60	14
fifo_depth[11]	auto[0]	auto[1]	auto[1]	3885	1			T60	11		T21	31		T62	5
fifo_depth[11]	auto[1]	auto[0]	auto[0]	8167	1			T4	3		T5	55		T47	37
fifo_depth[11]	auto[1]	auto[0]	auto[1]	8598	1			T5	137		T47	82		T48	2
fifo_depth[11]	auto[1]	auto[1]	auto[0]	8784	1			T2	1		T4	1		T5	121
fifo_depth[11]	auto[1]	auto[1]	auto[1]	8416	1			T5	47		T47	14		T48	1
fifo_depth[12]	auto[0]	auto[0]	auto[0]	3637	1			T60	12		T21	29		T62	1
fifo_depth[12]	auto[0]	auto[0]	auto[1]	7602	1			T60	6		T21	11		T22	13
fifo_depth[12]	auto[0]	auto[1]	auto[0]	9848	1			T14	11		T60	12		T21	63
fifo_depth[12]	auto[0]	auto[1]	auto[1]	4953	1			T60	3		T21	13		T62	4
fifo_depth[12]	auto[1]	auto[0]	auto[0]	7592	1			T5	34		T47	21		T15	1
fifo_depth[12]	auto[1]	auto[0]	auto[1]	8148	1			T5	61		T47	48		T48	1
fifo_depth[12]	auto[1]	auto[1]	auto[0]	7814	1			T4	1		T5	55		T47	17
fifo_depth[12]	auto[1]	auto[1]	auto[1]	7828	1			T5	35		T47	8		T48	2
fifo_depth[13]	auto[0]	auto[0]	auto[0]	2015	1			T60	3		T21	13		T22	127
fifo_depth[13]	auto[0]	auto[0]	auto[1]	3673	1			T60	2		T21	4		T22	6
fifo_depth[13]	auto[0]	auto[1]	auto[0]	4701	1			T14	5		T60	9		T21	27
fifo_depth[13]	auto[0]	auto[1]	auto[1]	2605	1			T60	1		T21	3		T22	103
fifo_depth[13]	auto[1]	auto[0]	auto[0]	3850	1			T5	10		T47	5		T60	3
fifo_depth[13]	auto[1]	auto[0]	auto[1]	3816	1			T5	30		T47	14		T60	4
fifo_depth[13]	auto[1]	auto[1]	auto[0]	3817	1			T5	39		T47	12		T14	2
fifo_depth[13]	auto[1]	auto[1]	auto[1]	4439	1			T5	17		T47	3		T60	3
fifo_depth[14]	auto[0]	auto[0]	auto[0]	2985	1			T21	1		T22	85		T121	1
fifo_depth[14]	auto[0]	auto[0]	auto[1]	6217	1			T60	2		T21	1		T22	3
fifo_depth[14]	auto[0]	auto[1]	auto[0]	5411	1			T14	4		T60	1		T21	10
fifo_depth[14]	auto[0]	auto[1]	auto[1]	4015	1			T60	1		T21	2		T22	145
fifo_depth[14]	auto[1]	auto[0]	auto[0]	4368	1			T5	9		T47	6		T60	1
fifo_depth[14]	auto[1]	auto[0]	auto[1]	4553	1			T5	14		T47	3		T60	1
fifo_depth[14]	auto[1]	auto[1]	auto[0]	5069	1			T5	16		T47	3		T14	1
fifo_depth[14]	auto[1]	auto[1]	auto[1]	4866	1			T5	3		T47	3		T60	2
fifo_depth[15]	auto[0]	auto[0]	auto[0]	2039	1			T60	1		T21	4		T22	124
fifo_depth[15]	auto[0]	auto[0]	auto[1]	3632	1			T21	2		T22	5		T121	3
fifo_depth[15]	auto[0]	auto[1]	auto[0]	3165	1			T60	1		T21	6		T22	184
fifo_depth[15]	auto[0]	auto[1]	auto[1]	2630	1			T21	3		T22	165		T121	5
fifo_depth[15]	auto[1]	auto[0]	auto[0]	2775	1			T5	5		T47	2		T21	3
fifo_depth[15]	auto[1]	auto[0]	auto[1]	2880	1			T5	3		T47	2		T21	1
fifo_depth[15]	auto[1]	auto[1]	auto[0]	2929	1			T5	4		T47	1		T60	2
fifo_depth[15]	auto[1]	auto[1]	auto[1]	4012	1			T5	2		T47	3		T60	2
fifo_depth[16]	auto[0]	auto[0]	auto[0]	9409	1			T60	1		T22	1483		T44	284
fifo_depth[16]	auto[0]	auto[0]	auto[1]	14196	1			T22	76		T122	2		T44	1
fifo_depth[16]	auto[0]	auto[1]	auto[0]	13441	1			T21	2		T22	1616		T122	3
fifo_depth[16]	auto[0]	auto[1]	auto[1]	9803	1			T22	935		T123	1		T44	551
fifo_depth[16]	auto[1]	auto[0]	auto[0]	8461	1			T47	1		T21	1		T63	1
fifo_depth[16]	auto[1]	auto[0]	auto[1]	14629	1			T5	3		T93	2		T22	1202
fifo_depth[16]	auto[1]	auto[1]	auto[0]	14914	1			T5	7		T47	1		T60	2
fifo_depth[16]	auto[1]	auto[1]	auto[1]	17730	1			T5	1		T47	2		T60	1