Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	14195458	1			T1	71		T2	40		T3	69968
all_pins[1]	14195458	1			T1	71		T2	40		T3	69968
all_pins[2]	14195458	1			T1	71		T2	40		T3	69968

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	40426145	1			T1	201		T2	116		T3	201699
values[0x1]	2160229	1			T1	12		T2	4		T3	8205
transitions[0x0=>0x1]	2160052	1			T1	12		T2	4		T3	8205
transitions[0x1=>0x0]	2160074	1			T1	12		T2	4		T3	8205

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	14146628	1			T1	67		T2	36		T3	69774
all_pins[0]	values[0x1]	48830	1			T1	4		T2	4		T3	194
all_pins[0]	transitions[0x0=>0x1]	48759	1			T1	4		T2	4		T3	194
all_pins[0]	transitions[0x1=>0x0]	2110813	1			T1	8		T3	8011		T19	15
all_pins[1]	values[0x0]	14194921	1			T1	71		T2	40		T3	69968
all_pins[1]	values[0x1]	537	1			T27	3		T15	2		T21	3
all_pins[1]	transitions[0x0=>0x1]	484	1			T27	3		T21	3		T114	3
all_pins[1]	transitions[0x1=>0x0]	48777	1			T1	4		T2	4		T3	194
all_pins[2]	values[0x0]	12084596	1			T1	63		T2	40		T3	61957
all_pins[2]	values[0x1]	2110862	1			T1	8		T3	8011		T19	15
all_pins[2]	transitions[0x0=>0x1]	2110809	1			T1	8		T3	8011		T19	15
all_pins[2]	transitions[0x1=>0x0]	484	1			T27	2		T15	2		T21	3