Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 950 1 T27 17 T15 14 T21 10
all_values[1] 950 1 T27 17 T15 14 T21 10
all_values[2] 950 1 T27 17 T15 14 T21 10


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1393 1 T27 18 T15 16 T21 14
auto[1] 1457 1 T27 33 T15 26 T21 16


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1028 1 T27 14 T15 14 T21 13
auto[1] 1822 1 T27 37 T15 28 T21 17


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1634 1 T27 27 T15 23 T21 19
auto[1] 1216 1 T27 24 T15 19 T21 11


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 192 1 T27 1 T21 3 T114 1
all_values[0] auto[0] auto[0] auto[1] 95 1 T27 3 T15 2 T114 2
all_values[0] auto[0] auto[1] auto[0] 178 1 T27 2 T15 3 T21 2
all_values[0] auto[0] auto[1] auto[1] 83 1 T27 2 T15 1 T21 1
all_values[0] auto[1] auto[0] auto[1] 198 1 T27 2 T15 2 T21 4
all_values[0] auto[1] auto[1] auto[1] 204 1 T27 7 T15 6 T114 4
all_values[1] auto[0] auto[0] auto[0] 141 1 T27 2 T15 1 T21 1
all_values[1] auto[0] auto[0] auto[1] 108 1 T27 1 T15 2 T114 1
all_values[1] auto[0] auto[1] auto[0] 144 1 T27 3 T15 3 T21 2
all_values[1] auto[0] auto[1] auto[1] 137 1 T27 4 T15 2 T21 3
all_values[1] auto[1] auto[0] auto[1] 213 1 T27 5 T15 3 T21 1
all_values[1] auto[1] auto[1] auto[1] 207 1 T27 2 T15 3 T21 3
all_values[2] auto[0] auto[0] auto[0] 172 1 T27 1 T15 3 T21 2
all_values[2] auto[0] auto[0] auto[1] 84 1 T27 2 T15 1 T21 1
all_values[2] auto[0] auto[1] auto[0] 201 1 T27 5 T15 4 T21 3
all_values[2] auto[0] auto[1] auto[1] 99 1 T27 1 T15 1 T21 1
all_values[2] auto[1] auto[0] auto[1] 190 1 T27 1 T15 2 T21 2
all_values[2] auto[1] auto[1] auto[1] 204 1 T27 7 T15 3 T21 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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