Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.03 92.80 85.98 100.00 73.68 88.15 99.49 69.08


Total test records in report: 731
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T532 /workspace/coverage/default/14.hmac_burst_wr.1903178803 Mar 19 12:45:03 PM PDT 24 Mar 19 12:45:54 PM PDT 24 4657729521 ps
T533 /workspace/coverage/default/42.hmac_wipe_secret.4053947871 Mar 19 12:46:06 PM PDT 24 Mar 19 12:47:08 PM PDT 24 1623622444 ps
T534 /workspace/coverage/default/23.hmac_long_msg.1695379812 Mar 19 12:45:19 PM PDT 24 Mar 19 12:45:30 PM PDT 24 448269118 ps
T535 /workspace/coverage/default/22.hmac_alert_test.943630893 Mar 19 12:45:20 PM PDT 24 Mar 19 12:45:21 PM PDT 24 24906450 ps
T536 /workspace/coverage/default/23.hmac_burst_wr.3354677811 Mar 19 12:45:25 PM PDT 24 Mar 19 12:46:20 PM PDT 24 4543529465 ps
T537 /workspace/coverage/default/10.hmac_datapath_stress.2010327930 Mar 19 12:44:45 PM PDT 24 Mar 19 12:45:48 PM PDT 24 11095939801 ps
T538 /workspace/coverage/default/14.hmac_wipe_secret.3772114703 Mar 19 12:45:05 PM PDT 24 Mar 19 12:46:15 PM PDT 24 3835024573 ps
T539 /workspace/coverage/default/48.hmac_back_pressure.3408754110 Mar 19 12:46:16 PM PDT 24 Mar 19 12:46:22 PM PDT 24 306902844 ps
T540 /workspace/coverage/default/34.hmac_test_sha_vectors.3080468146 Mar 19 12:45:44 PM PDT 24 Mar 19 12:54:29 PM PDT 24 28712391489 ps
T541 /workspace/coverage/default/35.hmac_stress_all.798197149 Mar 19 12:45:36 PM PDT 24 Mar 19 12:54:00 PM PDT 24 38113521251 ps
T542 /workspace/coverage/default/9.hmac_back_pressure.525327622 Mar 19 12:44:51 PM PDT 24 Mar 19 12:45:18 PM PDT 24 3143511574 ps
T543 /workspace/coverage/default/9.hmac_error.928028415 Mar 19 12:44:47 PM PDT 24 Mar 19 12:46:57 PM PDT 24 9003394590 ps
T544 /workspace/coverage/default/47.hmac_test_sha_vectors.3116570580 Mar 19 12:46:11 PM PDT 24 Mar 19 12:54:42 PM PDT 24 50939261902 ps
T545 /workspace/coverage/default/25.hmac_datapath_stress.2946751575 Mar 19 12:45:24 PM PDT 24 Mar 19 12:46:51 PM PDT 24 1543933160 ps
T546 /workspace/coverage/default/42.hmac_datapath_stress.535769068 Mar 19 12:46:00 PM PDT 24 Mar 19 12:48:02 PM PDT 24 4154443935 ps
T547 /workspace/coverage/default/49.hmac_datapath_stress.488353213 Mar 19 12:46:16 PM PDT 24 Mar 19 12:46:57 PM PDT 24 2281282656 ps
T548 /workspace/coverage/default/34.hmac_smoke.2797741697 Mar 19 12:45:43 PM PDT 24 Mar 19 12:45:46 PM PDT 24 165154097 ps
T549 /workspace/coverage/default/12.hmac_datapath_stress.147327780 Mar 19 12:44:46 PM PDT 24 Mar 19 12:45:24 PM PDT 24 659234032 ps
T550 /workspace/coverage/default/10.hmac_test_hmac_vectors.3871605983 Mar 19 12:44:46 PM PDT 24 Mar 19 12:44:47 PM PDT 24 170246669 ps
T551 /workspace/coverage/default/22.hmac_burst_wr.1721432899 Mar 19 12:45:25 PM PDT 24 Mar 19 12:45:28 PM PDT 24 1574865393 ps
T552 /workspace/coverage/default/45.hmac_back_pressure.550154240 Mar 19 12:46:06 PM PDT 24 Mar 19 12:46:15 PM PDT 24 1296807233 ps
T553 /workspace/coverage/default/8.hmac_datapath_stress.3599116429 Mar 19 12:44:43 PM PDT 24 Mar 19 12:47:28 PM PDT 24 2892643704 ps
T554 /workspace/coverage/default/33.hmac_back_pressure.289308519 Mar 19 12:45:43 PM PDT 24 Mar 19 12:46:46 PM PDT 24 2067377153 ps
T555 /workspace/coverage/default/37.hmac_stress_all.2100619355 Mar 19 12:45:55 PM PDT 24 Mar 19 01:04:18 PM PDT 24 20674543562 ps
T556 /workspace/coverage/default/25.hmac_burst_wr.1100866778 Mar 19 12:45:25 PM PDT 24 Mar 19 12:46:15 PM PDT 24 3951198360 ps
T557 /workspace/coverage/default/8.hmac_error.2785372301 Mar 19 12:44:49 PM PDT 24 Mar 19 12:47:13 PM PDT 24 105688478334 ps
T558 /workspace/coverage/default/20.hmac_long_msg.4126424877 Mar 19 12:45:13 PM PDT 24 Mar 19 12:45:51 PM PDT 24 1184494572 ps
T559 /workspace/coverage/default/8.hmac_wipe_secret.3392617259 Mar 19 12:44:42 PM PDT 24 Mar 19 12:44:58 PM PDT 24 2035829017 ps
T560 /workspace/coverage/default/5.hmac_stress_all.558680398 Mar 19 12:44:53 PM PDT 24 Mar 19 12:46:11 PM PDT 24 15008726939 ps
T561 /workspace/coverage/default/3.hmac_stress_all.3071696295 Mar 19 12:46:07 PM PDT 24 Mar 19 01:01:05 PM PDT 24 18761523495 ps
T562 /workspace/coverage/default/3.hmac_back_pressure.2558905045 Mar 19 12:44:53 PM PDT 24 Mar 19 12:45:45 PM PDT 24 17005251482 ps
T92 /workspace/coverage/default/11.hmac_stress_all.1442430417 Mar 19 12:44:50 PM PDT 24 Mar 19 12:50:40 PM PDT 24 25065440678 ps
T51 /workspace/coverage/default/16.hmac_stress_all.518512672 Mar 19 12:45:07 PM PDT 24 Mar 19 01:06:46 PM PDT 24 26492077649 ps
T563 /workspace/coverage/default/46.hmac_back_pressure.2725901906 Mar 19 12:46:10 PM PDT 24 Mar 19 12:46:35 PM PDT 24 2854518713 ps
T564 /workspace/coverage/default/28.hmac_error.3063266144 Mar 19 12:45:35 PM PDT 24 Mar 19 12:47:07 PM PDT 24 7088460217 ps
T565 /workspace/coverage/default/33.hmac_error.1958609762 Mar 19 12:45:41 PM PDT 24 Mar 19 12:46:17 PM PDT 24 2649675445 ps
T566 /workspace/coverage/default/11.hmac_long_msg.2705173201 Mar 19 12:44:52 PM PDT 24 Mar 19 12:47:00 PM PDT 24 9578348491 ps
T567 /workspace/coverage/default/31.hmac_wipe_secret.169238293 Mar 19 12:45:29 PM PDT 24 Mar 19 12:46:33 PM PDT 24 4278886739 ps
T568 /workspace/coverage/default/29.hmac_smoke.2230511931 Mar 19 12:45:31 PM PDT 24 Mar 19 12:45:34 PM PDT 24 145956867 ps
T569 /workspace/coverage/default/5.hmac_long_msg.1273265677 Mar 19 12:44:40 PM PDT 24 Mar 19 12:45:19 PM PDT 24 5849433367 ps
T570 /workspace/coverage/default/23.hmac_back_pressure.2041334184 Mar 19 12:45:22 PM PDT 24 Mar 19 12:45:26 PM PDT 24 369570074 ps
T571 /workspace/coverage/default/18.hmac_test_hmac_vectors.3827681140 Mar 19 12:45:23 PM PDT 24 Mar 19 12:45:25 PM PDT 24 173735719 ps
T572 /workspace/coverage/default/29.hmac_back_pressure.795414053 Mar 19 12:45:30 PM PDT 24 Mar 19 12:46:13 PM PDT 24 1291711211 ps
T573 /workspace/coverage/default/34.hmac_test_hmac_vectors.3647176447 Mar 19 12:45:46 PM PDT 24 Mar 19 12:45:48 PM PDT 24 170923906 ps
T574 /workspace/coverage/default/32.hmac_back_pressure.872892256 Mar 19 12:45:31 PM PDT 24 Mar 19 12:45:57 PM PDT 24 13042328666 ps
T52 /workspace/coverage/default/37.hmac_error.103241972 Mar 19 12:45:44 PM PDT 24 Mar 19 12:48:31 PM PDT 24 105135968632 ps
T575 /workspace/coverage/default/0.hmac_burst_wr.378129398 Mar 19 12:44:35 PM PDT 24 Mar 19 12:44:52 PM PDT 24 346675452 ps
T576 /workspace/coverage/default/25.hmac_back_pressure.3354965018 Mar 19 12:45:25 PM PDT 24 Mar 19 12:46:01 PM PDT 24 860337743 ps
T577 /workspace/coverage/default/27.hmac_error.4254050944 Mar 19 12:45:24 PM PDT 24 Mar 19 12:46:57 PM PDT 24 1705797674 ps
T578 /workspace/coverage/default/17.hmac_back_pressure.2758201334 Mar 19 12:45:05 PM PDT 24 Mar 19 12:45:47 PM PDT 24 2254838542 ps
T579 /workspace/coverage/default/25.hmac_error.2878477865 Mar 19 12:45:27 PM PDT 24 Mar 19 12:47:23 PM PDT 24 2082539365 ps
T580 /workspace/coverage/default/5.hmac_alert_test.3230894988 Mar 19 12:44:43 PM PDT 24 Mar 19 12:44:44 PM PDT 24 14749078 ps
T581 /workspace/coverage/default/13.hmac_error.843000168 Mar 19 12:44:55 PM PDT 24 Mar 19 12:47:01 PM PDT 24 117319764920 ps
T582 /workspace/coverage/default/19.hmac_back_pressure.3323670446 Mar 19 12:45:18 PM PDT 24 Mar 19 12:45:54 PM PDT 24 11256602486 ps
T583 /workspace/coverage/default/6.hmac_smoke.676680578 Mar 19 12:44:47 PM PDT 24 Mar 19 12:44:48 PM PDT 24 201077168 ps
T584 /workspace/coverage/default/20.hmac_burst_wr.2994768451 Mar 19 12:45:20 PM PDT 24 Mar 19 12:46:09 PM PDT 24 2221536900 ps
T585 /workspace/coverage/default/18.hmac_back_pressure.4260647333 Mar 19 12:45:22 PM PDT 24 Mar 19 12:45:35 PM PDT 24 1048902261 ps
T586 /workspace/coverage/default/14.hmac_error.1622239933 Mar 19 12:45:01 PM PDT 24 Mar 19 12:45:49 PM PDT 24 23985524432 ps
T587 /workspace/coverage/default/26.hmac_test_sha_vectors.3055535523 Mar 19 12:45:25 PM PDT 24 Mar 19 12:53:02 PM PDT 24 107090036912 ps
T588 /workspace/coverage/default/38.hmac_test_sha_vectors.554630968 Mar 19 12:45:58 PM PDT 24 Mar 19 12:55:13 PM PDT 24 81362447419 ps
T589 /workspace/coverage/default/4.hmac_burst_wr.3916107586 Mar 19 12:44:48 PM PDT 24 Mar 19 12:45:37 PM PDT 24 1009697988 ps
T590 /workspace/coverage/default/10.hmac_error.2694700602 Mar 19 12:44:51 PM PDT 24 Mar 19 12:47:22 PM PDT 24 43312420847 ps
T591 /workspace/coverage/default/7.hmac_stress_all.2482280271 Mar 19 12:44:58 PM PDT 24 Mar 19 01:12:59 PM PDT 24 85792545114 ps
T592 /workspace/coverage/default/0.hmac_stress_all.1990255200 Mar 19 12:44:41 PM PDT 24 Mar 19 01:04:39 PM PDT 24 64863766107 ps
T593 /workspace/coverage/default/28.hmac_stress_all.3941474263 Mar 19 12:45:28 PM PDT 24 Mar 19 12:55:06 PM PDT 24 47395852275 ps
T594 /workspace/coverage/default/2.hmac_stress_all.1005752075 Mar 19 12:44:50 PM PDT 24 Mar 19 01:02:57 PM PDT 24 78499863681 ps
T595 /workspace/coverage/cover_reg_top/48.hmac_intr_test.1007889658 Mar 19 12:43:32 PM PDT 24 Mar 19 12:43:32 PM PDT 24 27771237 ps
T68 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3297488681 Mar 19 12:43:14 PM PDT 24 Mar 19 12:43:23 PM PDT 24 449405894 ps
T69 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3309795498 Mar 19 12:43:25 PM PDT 24 Mar 19 12:43:27 PM PDT 24 103193279 ps
T596 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1362900139 Mar 19 12:43:29 PM PDT 24 Mar 19 12:43:30 PM PDT 24 11521087 ps
T70 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2139090688 Mar 19 12:43:16 PM PDT 24 Mar 19 12:43:18 PM PDT 24 84341865 ps
T597 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1987443656 Mar 19 12:43:25 PM PDT 24 Mar 19 12:43:27 PM PDT 24 217232333 ps
T64 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1255364511 Mar 19 12:43:07 PM PDT 24 Mar 19 12:43:11 PM PDT 24 238811454 ps
T65 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.175609255 Mar 19 12:43:15 PM PDT 24 Mar 19 12:43:18 PM PDT 24 91778707 ps
T598 /workspace/coverage/cover_reg_top/6.hmac_intr_test.2341052623 Mar 19 12:43:08 PM PDT 24 Mar 19 12:43:09 PM PDT 24 53424457 ps
T599 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3361150842 Mar 19 12:43:26 PM PDT 24 Mar 19 12:43:27 PM PDT 24 36958744 ps
T600 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3510238071 Mar 19 12:43:16 PM PDT 24 Mar 19 12:43:19 PM PDT 24 145666150 ps
T601 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2772421079 Mar 19 12:43:32 PM PDT 24 Mar 19 12:43:34 PM PDT 24 106706212 ps
T602 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3603084118 Mar 19 12:43:21 PM PDT 24 Mar 19 12:43:22 PM PDT 24 22994543 ps
T603 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.625647380 Mar 19 12:43:13 PM PDT 24 Mar 19 12:43:16 PM PDT 24 52717613 ps
T98 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.312813025 Mar 19 12:43:14 PM PDT 24 Mar 19 12:43:16 PM PDT 24 127722180 ps
T66 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2529829984 Mar 19 12:43:16 PM PDT 24 Mar 19 12:43:21 PM PDT 24 2184328580 ps
T604 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3837657832 Mar 19 12:43:27 PM PDT 24 Mar 19 12:43:28 PM PDT 24 19434103 ps
T99 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.838779447 Mar 19 12:43:09 PM PDT 24 Mar 19 12:43:12 PM PDT 24 257301696 ps
T605 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2758862707 Mar 19 12:43:08 PM PDT 24 Mar 19 12:43:10 PM PDT 24 93123447 ps
T606 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.4272263650 Mar 19 12:43:18 PM PDT 24 Mar 19 12:43:20 PM PDT 24 110319910 ps
T607 /workspace/coverage/cover_reg_top/49.hmac_intr_test.665895505 Mar 19 12:43:27 PM PDT 24 Mar 19 12:43:28 PM PDT 24 30824668 ps
T115 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.84911885 Mar 19 12:43:09 PM PDT 24 Mar 19 12:43:12 PM PDT 24 908021214 ps
T608 /workspace/coverage/cover_reg_top/35.hmac_intr_test.766650609 Mar 19 12:43:27 PM PDT 24 Mar 19 12:43:27 PM PDT 24 31649706 ps
T609 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.658791685 Mar 19 12:43:16 PM PDT 24 Mar 19 12:43:18 PM PDT 24 281644324 ps
T610 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1378610556 Mar 19 12:43:22 PM PDT 24 Mar 19 12:43:22 PM PDT 24 16558708 ps
T611 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1864595145 Mar 19 12:43:10 PM PDT 24 Mar 19 12:43:13 PM PDT 24 110266389 ps
T612 /workspace/coverage/cover_reg_top/46.hmac_intr_test.1137939562 Mar 19 12:43:31 PM PDT 24 Mar 19 12:43:32 PM PDT 24 41223621 ps
T613 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1187234836 Mar 19 12:43:14 PM PDT 24 Mar 19 12:43:18 PM PDT 24 763309009 ps
T614 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1333170548 Mar 19 12:43:12 PM PDT 24 Mar 19 12:43:14 PM PDT 24 119629601 ps
T100 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.4101220904 Mar 19 12:43:13 PM PDT 24 Mar 19 12:43:14 PM PDT 24 115948658 ps
T101 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.4233856340 Mar 19 12:43:07 PM PDT 24 Mar 19 12:43:08 PM PDT 24 79084435 ps
T615 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3942421556 Mar 19 12:43:21 PM PDT 24 Mar 19 12:43:24 PM PDT 24 56202748 ps
T102 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2557630641 Mar 19 12:43:09 PM PDT 24 Mar 19 12:43:10 PM PDT 24 123784235 ps
T616 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.248918522 Mar 19 12:43:02 PM PDT 24 Mar 19 12:43:05 PM PDT 24 81342928 ps
T116 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3254106507 Mar 19 12:43:11 PM PDT 24 Mar 19 12:43:14 PM PDT 24 363738008 ps
T617 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1248571736 Mar 19 12:43:16 PM PDT 24 Mar 19 12:43:19 PM PDT 24 191528068 ps
T618 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2813486038 Mar 19 12:43:14 PM PDT 24 Mar 19 12:43:17 PM PDT 24 75139370 ps
T619 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3273008485 Mar 19 12:43:22 PM PDT 24 Mar 19 12:43:24 PM PDT 24 583665251 ps
T620 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2518350995 Mar 19 12:43:41 PM PDT 24 Mar 19 12:43:42 PM PDT 24 69512753 ps
T621 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.500498656 Mar 19 12:43:08 PM PDT 24 Mar 19 12:43:11 PM PDT 24 104277078 ps
T622 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3317901560 Mar 19 12:43:11 PM PDT 24 Mar 19 12:43:17 PM PDT 24 743536382 ps
T623 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1994802153 Mar 19 12:43:08 PM PDT 24 Mar 19 12:43:11 PM PDT 24 113297293 ps
T624 /workspace/coverage/cover_reg_top/5.hmac_intr_test.487013701 Mar 19 12:43:09 PM PDT 24 Mar 19 12:43:10 PM PDT 24 35043623 ps
T625 /workspace/coverage/cover_reg_top/20.hmac_intr_test.219208003 Mar 19 12:43:24 PM PDT 24 Mar 19 12:43:25 PM PDT 24 19816616 ps
T626 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.784143166 Mar 19 12:43:08 PM PDT 24 Mar 19 12:43:11 PM PDT 24 561318832 ps
T627 /workspace/coverage/cover_reg_top/21.hmac_intr_test.4259746154 Mar 19 12:43:23 PM PDT 24 Mar 19 12:43:24 PM PDT 24 16671692 ps
T628 /workspace/coverage/cover_reg_top/27.hmac_intr_test.2274168710 Mar 19 12:43:27 PM PDT 24 Mar 19 12:43:28 PM PDT 24 26202788 ps
T629 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2299965161 Mar 19 12:43:28 PM PDT 24 Mar 19 12:43:30 PM PDT 24 39009306 ps
T630 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.156943197 Mar 19 12:43:23 PM PDT 24 Mar 19 01:00:14 PM PDT 24 100375662258 ps
T631 /workspace/coverage/cover_reg_top/36.hmac_intr_test.721257675 Mar 19 12:43:23 PM PDT 24 Mar 19 12:43:24 PM PDT 24 27218334 ps
T632 /workspace/coverage/cover_reg_top/15.hmac_intr_test.388115408 Mar 19 12:43:27 PM PDT 24 Mar 19 12:43:27 PM PDT 24 22090954 ps
T633 /workspace/coverage/cover_reg_top/9.hmac_intr_test.1983974626 Mar 19 12:43:17 PM PDT 24 Mar 19 12:43:18 PM PDT 24 16326012 ps
T103 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3821372302 Mar 19 12:43:15 PM PDT 24 Mar 19 12:43:16 PM PDT 24 19080562 ps
T634 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.409424717 Mar 19 12:43:10 PM PDT 24 Mar 19 12:43:13 PM PDT 24 656534654 ps
T635 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1009929553 Mar 19 12:43:04 PM PDT 24 Mar 19 12:43:08 PM PDT 24 891771560 ps
T636 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.594303851 Mar 19 12:43:05 PM PDT 24 Mar 19 12:43:07 PM PDT 24 48320831 ps
T637 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3185714808 Mar 19 12:43:08 PM PDT 24 Mar 19 12:43:10 PM PDT 24 129037305 ps
T638 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2042447999 Mar 19 12:43:09 PM PDT 24 Mar 19 12:43:10 PM PDT 24 90260314 ps
T639 /workspace/coverage/cover_reg_top/30.hmac_intr_test.2395375392 Mar 19 12:43:23 PM PDT 24 Mar 19 12:43:24 PM PDT 24 14692454 ps
T640 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2177955156 Mar 19 12:43:23 PM PDT 24 Mar 19 12:43:25 PM PDT 24 328541100 ps
T641 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.191076055 Mar 19 12:43:16 PM PDT 24 Mar 19 12:43:19 PM PDT 24 488886205 ps
T642 /workspace/coverage/cover_reg_top/23.hmac_intr_test.3597828716 Mar 19 12:43:29 PM PDT 24 Mar 19 12:43:30 PM PDT 24 13026041 ps
T643 /workspace/coverage/cover_reg_top/31.hmac_intr_test.1234015232 Mar 19 12:43:28 PM PDT 24 Mar 19 12:43:29 PM PDT 24 17349544 ps
T644 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1950113182 Mar 19 12:43:28 PM PDT 24 Mar 19 12:43:29 PM PDT 24 18988539 ps
T104 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3093187382 Mar 19 12:43:09 PM PDT 24 Mar 19 12:43:10 PM PDT 24 82039236 ps
T118 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.852213820 Mar 19 12:43:12 PM PDT 24 Mar 19 12:43:14 PM PDT 24 180883092 ps
T645 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.183418338 Mar 19 12:43:06 PM PDT 24 Mar 19 12:43:07 PM PDT 24 24313979 ps
T105 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1133158498 Mar 19 12:43:03 PM PDT 24 Mar 19 12:43:04 PM PDT 24 127210728 ps
T646 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2053857202 Mar 19 12:43:24 PM PDT 24 Mar 19 12:43:27 PM PDT 24 168533877 ps
T647 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3739038061 Mar 19 12:43:31 PM PDT 24 Mar 19 12:43:32 PM PDT 24 46499903 ps
T648 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.555991690 Mar 19 12:43:25 PM PDT 24 Mar 19 12:43:28 PM PDT 24 339618144 ps
T107 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1775659123 Mar 19 12:43:07 PM PDT 24 Mar 19 12:43:13 PM PDT 24 1176995030 ps
T649 /workspace/coverage/cover_reg_top/38.hmac_intr_test.561005553 Mar 19 12:43:32 PM PDT 24 Mar 19 12:43:32 PM PDT 24 40773896 ps
T650 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2886299905 Mar 19 12:43:23 PM PDT 24 Mar 19 12:43:25 PM PDT 24 135695790 ps
T651 /workspace/coverage/cover_reg_top/0.hmac_intr_test.3518473437 Mar 19 12:43:05 PM PDT 24 Mar 19 12:43:06 PM PDT 24 10957489 ps
T652 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.235320815 Mar 19 12:43:15 PM PDT 24 Mar 19 12:43:17 PM PDT 24 155598478 ps
T653 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1518395662 Mar 19 12:43:10 PM PDT 24 Mar 19 12:43:12 PM PDT 24 922819325 ps
T111 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1654338704 Mar 19 12:43:26 PM PDT 24 Mar 19 12:43:27 PM PDT 24 89436361 ps
T654 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2343038445 Mar 19 12:43:32 PM PDT 24 Mar 19 12:43:33 PM PDT 24 40219681 ps
T655 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.4244745244 Mar 19 12:43:07 PM PDT 24 Mar 19 12:43:08 PM PDT 24 24273339 ps
T656 /workspace/coverage/cover_reg_top/26.hmac_intr_test.3412897774 Mar 19 12:43:28 PM PDT 24 Mar 19 12:43:29 PM PDT 24 24380089 ps
T657 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1511086707 Mar 19 12:43:24 PM PDT 24 Mar 19 12:43:26 PM PDT 24 33315036 ps
T658 /workspace/coverage/cover_reg_top/7.hmac_intr_test.3594004781 Mar 19 12:43:09 PM PDT 24 Mar 19 12:43:09 PM PDT 24 50334818 ps
T106 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.993978724 Mar 19 12:43:04 PM PDT 24 Mar 19 12:43:13 PM PDT 24 915325590 ps
T108 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2343570276 Mar 19 12:43:05 PM PDT 24 Mar 19 12:43:07 PM PDT 24 16233594 ps
T659 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.767024461 Mar 19 12:43:08 PM PDT 24 Mar 19 12:43:10 PM PDT 24 68425744 ps
T660 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.643486013 Mar 19 12:43:11 PM PDT 24 Mar 19 12:43:14 PM PDT 24 89316931 ps
T661 /workspace/coverage/cover_reg_top/11.hmac_intr_test.3055567207 Mar 19 12:43:16 PM PDT 24 Mar 19 12:43:17 PM PDT 24 45476266 ps
T662 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.526613154 Mar 19 12:43:19 PM PDT 24 Mar 19 12:43:21 PM PDT 24 24826322 ps
T663 /workspace/coverage/cover_reg_top/17.hmac_intr_test.3954039061 Mar 19 12:43:26 PM PDT 24 Mar 19 12:43:27 PM PDT 24 45740486 ps
T664 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.549403189 Mar 19 12:43:24 PM PDT 24 Mar 19 12:43:30 PM PDT 24 444837544 ps
T665 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2874261783 Mar 19 12:43:23 PM PDT 24 Mar 19 12:43:25 PM PDT 24 192027377 ps
T666 /workspace/coverage/cover_reg_top/24.hmac_intr_test.3511159959 Mar 19 12:43:26 PM PDT 24 Mar 19 12:43:27 PM PDT 24 46850778 ps
T667 /workspace/coverage/cover_reg_top/3.hmac_intr_test.1780153081 Mar 19 12:43:09 PM PDT 24 Mar 19 12:43:09 PM PDT 24 15119006 ps
T668 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3541916718 Mar 19 12:43:37 PM PDT 24 Mar 19 12:43:37 PM PDT 24 12039118 ps
T669 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3266251840 Mar 19 12:43:32 PM PDT 24 Mar 19 12:43:33 PM PDT 24 55266454 ps
T670 /workspace/coverage/cover_reg_top/40.hmac_intr_test.3050043253 Mar 19 12:43:27 PM PDT 24 Mar 19 12:43:28 PM PDT 24 28313085 ps
T671 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3124377588 Mar 19 12:43:25 PM PDT 24 Mar 19 12:43:26 PM PDT 24 13107678 ps
T672 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.109028627 Mar 19 12:43:16 PM PDT 24 Mar 19 12:43:17 PM PDT 24 49084432 ps
T673 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1307928954 Mar 19 12:43:22 PM PDT 24 Mar 19 12:43:24 PM PDT 24 26800376 ps
T112 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1325990209 Mar 19 12:43:12 PM PDT 24 Mar 19 12:43:13 PM PDT 24 26920631 ps
T109 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.784357941 Mar 19 12:43:09 PM PDT 24 Mar 19 12:43:10 PM PDT 24 18893869 ps
T674 /workspace/coverage/cover_reg_top/2.hmac_intr_test.3287386707 Mar 19 12:43:08 PM PDT 24 Mar 19 12:43:08 PM PDT 24 213436312 ps
T117 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3500867768 Mar 19 12:43:16 PM PDT 24 Mar 19 12:43:18 PM PDT 24 172694801 ps
T675 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1689277740 Mar 19 12:43:17 PM PDT 24 Mar 19 12:43:20 PM PDT 24 54860526 ps
T676 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2471583782 Mar 19 12:43:35 PM PDT 24 Mar 19 12:43:36 PM PDT 24 20393839 ps
T677 /workspace/coverage/cover_reg_top/8.hmac_intr_test.2165267628 Mar 19 12:43:10 PM PDT 24 Mar 19 12:43:11 PM PDT 24 99920346 ps
T678 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3416612359 Mar 19 12:43:15 PM PDT 24 Mar 19 12:43:15 PM PDT 24 18948223 ps
T110 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3078738346 Mar 19 12:43:04 PM PDT 24 Mar 19 12:43:16 PM PDT 24 3093444973 ps
T679 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1201896919 Mar 19 12:43:18 PM PDT 24 Mar 19 12:43:19 PM PDT 24 96361184 ps
T680 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3718515398 Mar 19 12:43:12 PM PDT 24 Mar 19 12:43:16 PM PDT 24 67118612 ps
T681 /workspace/coverage/cover_reg_top/33.hmac_intr_test.1601367245 Mar 19 12:43:22 PM PDT 24 Mar 19 12:43:23 PM PDT 24 38331014 ps
T682 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.924870531 Mar 19 12:43:04 PM PDT 24 Mar 19 12:43:05 PM PDT 24 32332730 ps
T683 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2905958335 Mar 19 12:43:28 PM PDT 24 Mar 19 12:43:29 PM PDT 24 30098753 ps
T684 /workspace/coverage/cover_reg_top/42.hmac_intr_test.336281873 Mar 19 12:43:42 PM PDT 24 Mar 19 12:43:42 PM PDT 24 43087474 ps
T685 /workspace/coverage/cover_reg_top/4.hmac_intr_test.3790388546 Mar 19 12:43:08 PM PDT 24 Mar 19 12:43:09 PM PDT 24 30690344 ps
T686 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3298326908 Mar 19 12:43:13 PM PDT 24 Mar 19 12:43:14 PM PDT 24 93343702 ps
T687 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1698928990 Mar 19 12:43:04 PM PDT 24 Mar 19 12:43:06 PM PDT 24 34764168 ps
T71 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2416980338 Mar 19 12:43:16 PM PDT 24 Mar 19 12:43:20 PM PDT 24 187123515 ps
T688 /workspace/coverage/cover_reg_top/16.hmac_intr_test.725495469 Mar 19 12:43:21 PM PDT 24 Mar 19 12:43:22 PM PDT 24 13708897 ps
T689 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1797290260 Mar 19 12:43:11 PM PDT 24 Mar 19 12:43:12 PM PDT 24 29070691 ps
T690 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2114898798 Mar 19 12:43:26 PM PDT 24 Mar 19 12:43:27 PM PDT 24 56104728 ps
T691 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1337883112 Mar 19 12:43:14 PM PDT 24 Mar 19 12:47:16 PM PDT 24 15982631476 ps
T692 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3814698478 Mar 19 12:43:09 PM PDT 24 Mar 19 12:43:10 PM PDT 24 51168280 ps
T693 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2309379045 Mar 19 12:43:22 PM PDT 24 Mar 19 12:43:24 PM PDT 24 87489525 ps
T694 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3235510966 Mar 19 12:43:08 PM PDT 24 Mar 19 12:43:24 PM PDT 24 3752174472 ps
T695 /workspace/coverage/cover_reg_top/44.hmac_intr_test.84469732 Mar 19 12:43:40 PM PDT 24 Mar 19 12:43:41 PM PDT 24 16286560 ps
T696 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2338705817 Mar 19 12:43:04 PM PDT 24 Mar 19 12:47:56 PM PDT 24 109694500265 ps
T697 /workspace/coverage/cover_reg_top/47.hmac_intr_test.823785585 Mar 19 12:43:42 PM PDT 24 Mar 19 12:43:43 PM PDT 24 60212358 ps
T698 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3373065699 Mar 19 12:43:27 PM PDT 24 Mar 19 12:43:28 PM PDT 24 12578002 ps
T699 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1581791936 Mar 19 12:43:12 PM PDT 24 Mar 19 12:43:14 PM PDT 24 90318812 ps
T700 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1002230723 Mar 19 12:43:08 PM PDT 24 Mar 19 12:43:10 PM PDT 24 60208108 ps
T701 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1880753868 Mar 19 12:43:16 PM PDT 24 Mar 19 12:43:17 PM PDT 24 13753792 ps
T702 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2807379985 Mar 19 12:43:15 PM PDT 24 Mar 19 12:43:16 PM PDT 24 37768719 ps
T119 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2539897353 Mar 19 12:43:12 PM PDT 24 Mar 19 12:43:15 PM PDT 24 158712545 ps
T703 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.754272284 Mar 19 12:43:12 PM PDT 24 Mar 19 12:43:21 PM PDT 24 463980506 ps
T704 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.892386232 Mar 19 12:43:27 PM PDT 24 Mar 19 12:43:28 PM PDT 24 23080215 ps
T705 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1252404107 Mar 19 12:43:16 PM PDT 24 Mar 19 12:43:20 PM PDT 24 329345006 ps
T706 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.979103386 Mar 19 12:43:16 PM PDT 24 Mar 19 12:43:18 PM PDT 24 34522379 ps
T707 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3797150361 Mar 19 12:43:25 PM PDT 24 Mar 19 12:43:27 PM PDT 24 176688434 ps
T708 /workspace/coverage/cover_reg_top/28.hmac_intr_test.1420756820 Mar 19 12:43:25 PM PDT 24 Mar 19 12:43:26 PM PDT 24 42916552 ps
T709 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2406849673 Mar 19 12:43:25 PM PDT 24 Mar 19 12:43:26 PM PDT 24 51200197 ps
T710 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1831221603 Mar 19 12:43:29 PM PDT 24 Mar 19 12:43:34 PM PDT 24 515636935 ps
T711 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2797942341 Mar 19 12:43:03 PM PDT 24 Mar 19 12:43:05 PM PDT 24 233486162 ps
T712 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3891198594 Mar 19 12:43:08 PM PDT 24 Mar 19 12:49:45 PM PDT 24 35675037494 ps
T713 /workspace/coverage/cover_reg_top/1.hmac_intr_test.3578722190 Mar 19 12:43:04 PM PDT 24 Mar 19 12:43:05 PM PDT 24 26375045 ps
T714 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3005366703 Mar 19 12:43:25 PM PDT 24 Mar 19 12:43:27 PM PDT 24 93687788 ps
T715 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2725971310 Mar 19 12:43:24 PM PDT 24 Mar 19 12:43:27 PM PDT 24 257923645 ps
T716 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.576984350 Mar 19 12:43:09 PM PDT 24 Mar 19 12:43:10 PM PDT 24 47467052 ps
T717 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1365493280 Mar 19 12:43:10 PM PDT 24 Mar 19 12:43:12 PM PDT 24 935840381 ps
T718 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.4149611105 Mar 19 12:43:16 PM PDT 24 Mar 19 12:43:18 PM PDT 24 419674676 ps
T719 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1392972857 Mar 19 12:43:15 PM PDT 24 Mar 19 12:43:17 PM PDT 24 61964307 ps
T720 /workspace/coverage/cover_reg_top/22.hmac_intr_test.1050411662 Mar 19 12:43:28 PM PDT 24 Mar 19 12:43:29 PM PDT 24 14076059 ps
T721 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2933673046 Mar 19 12:43:07 PM PDT 24 Mar 19 12:43:13 PM PDT 24 571124244 ps
T722 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.410892972 Mar 19 12:43:08 PM PDT 24 Mar 19 12:43:09 PM PDT 24 18979979 ps
T120 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2394221443 Mar 19 12:43:08 PM PDT 24 Mar 19 12:43:10 PM PDT 24 1908407611 ps
T723 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2829146920 Mar 19 12:43:11 PM PDT 24 Mar 19 12:43:19 PM PDT 24 669729010 ps
T724 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.421490034 Mar 19 12:43:08 PM PDT 24 Mar 19 12:43:10 PM PDT 24 34603807 ps
T725 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1307809232 Mar 19 12:43:17 PM PDT 24 Mar 19 12:43:17 PM PDT 24 51584570 ps
T726 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3230124707 Mar 19 12:43:03 PM PDT 24 Mar 19 12:43:07 PM PDT 24 713062425 ps
T727 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1295832584 Mar 19 12:43:19 PM PDT 24 Mar 19 12:43:20 PM PDT 24 20291709 ps
T728 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2169277357 Mar 19 12:43:23 PM PDT 24 Mar 19 12:43:28 PM PDT 24 859459942 ps
T729 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.305686652 Mar 19 12:43:16 PM PDT 24 Mar 19 12:43:21 PM PDT 24 619828858 ps
T730 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.354941823 Mar 19 12:43:23 PM PDT 24 Mar 19 12:43:27 PM PDT 24 3149828722 ps
T731 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.234169683 Mar 19 12:43:22 PM PDT 24 Mar 19 12:43:23 PM PDT 24 134961326 ps

Test location /workspace/coverage/default/13.hmac_smoke.1123241480
Short name T7
Test name
Test status
Simulation time 3503145197 ps
CPU time 5.58 seconds
Started Mar 19 12:45:04 PM PDT 24
Finished Mar 19 12:45:10 PM PDT 24
Peak memory 200440 kb
Host smart-843e59a6-5f46-48fd-9d32-337aedf8f29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123241480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1123241480
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/55.hmac_stress_all_with_rand_reset.1564414685
Short name T9
Test name
Test status
Simulation time 37310339748 ps
CPU time 1869.54 seconds
Started Mar 19 12:46:28 PM PDT 24
Finished Mar 19 01:17:37 PM PDT 24
Peak memory 242756 kb
Host smart-6b90af2d-3432-45f2-93f1-ac272ae97f8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1564414685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.hmac_stress_all_with_rand_reset.1564414685
Directory /workspace/55.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.hmac_stress_all.3768022954
Short name T21
Test name
Test status
Simulation time 23262871126 ps
CPU time 573.38 seconds
Started Mar 19 12:46:15 PM PDT 24
Finished Mar 19 12:55:49 PM PDT 24
Peak memory 208692 kb
Host smart-467d6bca-b4bb-4357-90dc-bb9b51439b82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768022954 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3768022954
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1175818416
Short name T15
Test name
Test status
Simulation time 459712726814 ps
CPU time 1596.83 seconds
Started Mar 19 12:45:31 PM PDT 24
Finished Mar 19 01:12:08 PM PDT 24
Peak memory 208672 kb
Host smart-da12d8cf-1910-4307-a5f4-7dfecfd43a0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175818416 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1175818416
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.1612995884
Short name T34
Test name
Test status
Simulation time 187585270 ps
CPU time 1.06 seconds
Started Mar 19 12:44:38 PM PDT 24
Finished Mar 19 12:44:39 PM PDT 24
Peak memory 219788 kb
Host smart-c6ab4ef4-015a-4949-a442-62ab5725ec9b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612995884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1612995884
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.175609255
Short name T65
Test name
Test status
Simulation time 91778707 ps
CPU time 2.83 seconds
Started Mar 19 12:43:15 PM PDT 24
Finished Mar 19 12:43:18 PM PDT 24
Peak memory 199964 kb
Host smart-526e98ca-6512-4888-8828-383d89b5c393
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175609255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.175609255
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/129.hmac_stress_all_with_rand_reset.1815799039
Short name T12
Test name
Test status
Simulation time 77423199978 ps
CPU time 3131.57 seconds
Started Mar 19 12:46:39 PM PDT 24
Finished Mar 19 01:38:51 PM PDT 24
Peak memory 249592 kb
Host smart-5076a907-be46-4c76-81da-d59b34a74452
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1815799039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.hmac_stress_all_with_rand_reset.1815799039
Directory /workspace/129.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2557630641
Short name T102
Test name
Test status
Simulation time 123784235 ps
CPU time 0.94 seconds
Started Mar 19 12:43:09 PM PDT 24
Finished Mar 19 12:43:10 PM PDT 24
Peak memory 199804 kb
Host smart-8509f3f0-7102-44c9-a00e-30280c6a7c3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557630641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2557630641
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2528600801
Short name T5
Test name
Test status
Simulation time 2588532691 ps
CPU time 156.02 seconds
Started Mar 19 12:45:07 PM PDT 24
Finished Mar 19 12:47:43 PM PDT 24
Peak memory 200488 kb
Host smart-e825b765-78bf-4d04-a42c-ab7a59125b5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2528600801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2528600801
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.455572707
Short name T33
Test name
Test status
Simulation time 9805201774 ps
CPU time 109.89 seconds
Started Mar 19 12:44:48 PM PDT 24
Finished Mar 19 12:46:38 PM PDT 24
Peak memory 200464 kb
Host smart-a524082e-89e5-46c4-95ae-9d140abca32d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455572707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.455572707
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_stress_all.2036906479
Short name T22
Test name
Test status
Simulation time 334188230738 ps
CPU time 1111.68 seconds
Started Mar 19 12:45:16 PM PDT 24
Finished Mar 19 01:03:48 PM PDT 24
Peak memory 200452 kb
Host smart-57c32d94-4767-419f-8ce3-543422997823
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036906479 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2036906479
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_alert_test.294255039
Short name T135
Test name
Test status
Simulation time 13599502 ps
CPU time 0.58 seconds
Started Mar 19 12:44:38 PM PDT 24
Finished Mar 19 12:44:39 PM PDT 24
Peak memory 195968 kb
Host smart-7a405b5e-ff30-4aee-bae8-eeb4e2d4e028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294255039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.294255039
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_error.3529283734
Short name T50
Test name
Test status
Simulation time 10124949125 ps
CPU time 142.07 seconds
Started Mar 19 12:45:40 PM PDT 24
Finished Mar 19 12:48:02 PM PDT 24
Peak memory 200428 kb
Host smart-e7217f1d-7831-425d-a9c0-162f9c149ab1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529283734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3529283734
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2529829984
Short name T66
Test name
Test status
Simulation time 2184328580 ps
CPU time 4.43 seconds
Started Mar 19 12:43:16 PM PDT 24
Finished Mar 19 12:43:21 PM PDT 24
Peak memory 200140 kb
Host smart-08c4ecad-c995-400b-9979-52ba86f4ec46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529829984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2529829984
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1255364511
Short name T64
Test name
Test status
Simulation time 238811454 ps
CPU time 4.3 seconds
Started Mar 19 12:43:07 PM PDT 24
Finished Mar 19 12:43:11 PM PDT 24
Peak memory 199928 kb
Host smart-e1707f2e-2431-4319-a3c9-2cf764ad13e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255364511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1255364511
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1229731647
Short name T29
Test name
Test status
Simulation time 5298347566 ps
CPU time 49.7 seconds
Started Mar 19 12:44:36 PM PDT 24
Finished Mar 19 12:45:26 PM PDT 24
Peak memory 200456 kb
Host smart-392e09ca-fbd7-477d-be88-c24a3014ce4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229731647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1229731647
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2416980338
Short name T71
Test name
Test status
Simulation time 187123515 ps
CPU time 3.88 seconds
Started Mar 19 12:43:16 PM PDT 24
Finished Mar 19 12:43:20 PM PDT 24
Peak memory 199948 kb
Host smart-400e5d3c-f93b-4461-87a3-ace6290d089f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416980338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2416980338
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2829146920
Short name T723
Test name
Test status
Simulation time 669729010 ps
CPU time 8.06 seconds
Started Mar 19 12:43:11 PM PDT 24
Finished Mar 19 12:43:19 PM PDT 24
Peak memory 199140 kb
Host smart-5c269fc2-9f5f-4511-99a5-984367e64902
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829146920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2829146920
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3317901560
Short name T622
Test name
Test status
Simulation time 743536382 ps
CPU time 5.84 seconds
Started Mar 19 12:43:11 PM PDT 24
Finished Mar 19 12:43:17 PM PDT 24
Peak memory 198304 kb
Host smart-911adbd5-91ae-44b7-8c8c-2ba915321b2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317901560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3317901560
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1133158498
Short name T105
Test name
Test status
Simulation time 127210728 ps
CPU time 0.97 seconds
Started Mar 19 12:43:03 PM PDT 24
Finished Mar 19 12:43:04 PM PDT 24
Peak memory 199812 kb
Host smart-4782587e-e27f-411a-941e-4ed3a8d7074c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133158498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1133158498
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2338705817
Short name T696
Test name
Test status
Simulation time 109694500265 ps
CPU time 292.34 seconds
Started Mar 19 12:43:04 PM PDT 24
Finished Mar 19 12:47:56 PM PDT 24
Peak memory 215532 kb
Host smart-d1b23b80-bb00-4c84-891c-fa7dfbfe7cba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338705817 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2338705817
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2343570276
Short name T108
Test name
Test status
Simulation time 16233594 ps
CPU time 0.8 seconds
Started Mar 19 12:43:05 PM PDT 24
Finished Mar 19 12:43:07 PM PDT 24
Peak memory 199760 kb
Host smart-bdb2eaee-9500-402e-9037-2629f3f7bea1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343570276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2343570276
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.3518473437
Short name T651
Test name
Test status
Simulation time 10957489 ps
CPU time 0.59 seconds
Started Mar 19 12:43:05 PM PDT 24
Finished Mar 19 12:43:06 PM PDT 24
Peak memory 194512 kb
Host smart-2c91b7c6-684a-49be-a47e-41916ccaeefe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518473437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3518473437
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.594303851
Short name T636
Test name
Test status
Simulation time 48320831 ps
CPU time 2.31 seconds
Started Mar 19 12:43:05 PM PDT 24
Finished Mar 19 12:43:07 PM PDT 24
Peak memory 199756 kb
Host smart-8bb51a63-1334-4268-9d6e-72d4eadc1e77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594303851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_
outstanding.594303851
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1009929553
Short name T635
Test name
Test status
Simulation time 891771560 ps
CPU time 3.66 seconds
Started Mar 19 12:43:04 PM PDT 24
Finished Mar 19 12:43:08 PM PDT 24
Peak memory 200076 kb
Host smart-218a7697-03a7-4561-9f40-504634a1a486
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009929553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1009929553
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3230124707
Short name T726
Test name
Test status
Simulation time 713062425 ps
CPU time 2.86 seconds
Started Mar 19 12:43:03 PM PDT 24
Finished Mar 19 12:43:07 PM PDT 24
Peak memory 199884 kb
Host smart-cf3dd298-e7d7-4ff1-a646-d852b7f19d8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230124707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3230124707
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.993978724
Short name T106
Test name
Test status
Simulation time 915325590 ps
CPU time 9.05 seconds
Started Mar 19 12:43:04 PM PDT 24
Finished Mar 19 12:43:13 PM PDT 24
Peak memory 199944 kb
Host smart-dd8e40b8-dab3-4159-b371-eef0af4e7f80
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993978724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.993978724
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3078738346
Short name T110
Test name
Test status
Simulation time 3093444973 ps
CPU time 12.02 seconds
Started Mar 19 12:43:04 PM PDT 24
Finished Mar 19 12:43:16 PM PDT 24
Peak memory 199276 kb
Host smart-1ed4aece-e83c-4ce9-be46-d8cae4e3987d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078738346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3078738346
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.924870531
Short name T682
Test name
Test status
Simulation time 32332730 ps
CPU time 0.84 seconds
Started Mar 19 12:43:04 PM PDT 24
Finished Mar 19 12:43:05 PM PDT 24
Peak memory 198912 kb
Host smart-f6ddc8cb-7e43-4e4e-9f3d-edfb5dffb2b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924870531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.924870531
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1698928990
Short name T687
Test name
Test status
Simulation time 34764168 ps
CPU time 2.15 seconds
Started Mar 19 12:43:04 PM PDT 24
Finished Mar 19 12:43:06 PM PDT 24
Peak memory 199984 kb
Host smart-07204086-a2e2-4b10-adbb-34e7ad1e96a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698928990 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1698928990
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.784357941
Short name T109
Test name
Test status
Simulation time 18893869 ps
CPU time 0.93 seconds
Started Mar 19 12:43:09 PM PDT 24
Finished Mar 19 12:43:10 PM PDT 24
Peak memory 198752 kb
Host smart-9412f190-97a9-4b0d-a946-576f5bab67a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784357941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.784357941
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.3578722190
Short name T713
Test name
Test status
Simulation time 26375045 ps
CPU time 0.59 seconds
Started Mar 19 12:43:04 PM PDT 24
Finished Mar 19 12:43:05 PM PDT 24
Peak memory 194464 kb
Host smart-050a8ca6-7692-46de-94e7-676c55821b16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578722190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.3578722190
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2797942341
Short name T711
Test name
Test status
Simulation time 233486162 ps
CPU time 1.26 seconds
Started Mar 19 12:43:03 PM PDT 24
Finished Mar 19 12:43:05 PM PDT 24
Peak memory 198000 kb
Host smart-9cf0012f-c059-4c7d-83fd-d7585bc00d14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797942341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2797942341
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.183418338
Short name T645
Test name
Test status
Simulation time 24313979 ps
CPU time 1.48 seconds
Started Mar 19 12:43:06 PM PDT 24
Finished Mar 19 12:43:07 PM PDT 24
Peak memory 199988 kb
Host smart-76ac6090-9957-4505-a4e8-f6764e233fdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183418338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.183418338
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.4272263650
Short name T606
Test name
Test status
Simulation time 110319910 ps
CPU time 2.51 seconds
Started Mar 19 12:43:18 PM PDT 24
Finished Mar 19 12:43:20 PM PDT 24
Peak memory 199992 kb
Host smart-5d80a825-a1b1-48ba-b97f-e0858b4c731a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272263650 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.4272263650
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1295832584
Short name T727
Test name
Test status
Simulation time 20291709 ps
CPU time 0.68 seconds
Started Mar 19 12:43:19 PM PDT 24
Finished Mar 19 12:43:20 PM PDT 24
Peak memory 197380 kb
Host smart-8da30c3d-a17d-47a2-8073-e30e3b8d1d35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295832584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1295832584
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1880753868
Short name T701
Test name
Test status
Simulation time 13753792 ps
CPU time 0.61 seconds
Started Mar 19 12:43:16 PM PDT 24
Finished Mar 19 12:43:17 PM PDT 24
Peak memory 194716 kb
Host smart-8d042516-8fe9-4f4d-8f22-fdfb9117b93d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880753868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1880753868
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.191076055
Short name T641
Test name
Test status
Simulation time 488886205 ps
CPU time 1.95 seconds
Started Mar 19 12:43:16 PM PDT 24
Finished Mar 19 12:43:19 PM PDT 24
Peak memory 199728 kb
Host smart-d56146da-b50d-4013-aba7-1041db339430
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191076055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr
_outstanding.191076055
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1689277740
Short name T675
Test name
Test status
Simulation time 54860526 ps
CPU time 3.04 seconds
Started Mar 19 12:43:17 PM PDT 24
Finished Mar 19 12:43:20 PM PDT 24
Peak memory 200056 kb
Host smart-229fef2e-297a-460d-aae0-c9b13dce0217
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689277740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1689277740
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.526613154
Short name T662
Test name
Test status
Simulation time 24826322 ps
CPU time 1.55 seconds
Started Mar 19 12:43:19 PM PDT 24
Finished Mar 19 12:43:21 PM PDT 24
Peak memory 199964 kb
Host smart-f4f4068b-c0a4-4732-abe2-bb92bd67068f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526613154 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.526613154
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3298326908
Short name T686
Test name
Test status
Simulation time 93343702 ps
CPU time 0.83 seconds
Started Mar 19 12:43:13 PM PDT 24
Finished Mar 19 12:43:14 PM PDT 24
Peak memory 198712 kb
Host smart-711e2c55-9ef2-4cc0-a182-dbfec11dcff3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298326908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3298326908
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.3055567207
Short name T661
Test name
Test status
Simulation time 45476266 ps
CPU time 0.64 seconds
Started Mar 19 12:43:16 PM PDT 24
Finished Mar 19 12:43:17 PM PDT 24
Peak memory 194536 kb
Host smart-f61a5179-3c33-4bc5-8ea0-db4e973e0919
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055567207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3055567207
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.235320815
Short name T652
Test name
Test status
Simulation time 155598478 ps
CPU time 1.18 seconds
Started Mar 19 12:43:15 PM PDT 24
Finished Mar 19 12:43:17 PM PDT 24
Peak memory 199632 kb
Host smart-bc5a2950-5288-44ea-9066-2322befd0a82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235320815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.235320815
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1248571736
Short name T617
Test name
Test status
Simulation time 191528068 ps
CPU time 2.72 seconds
Started Mar 19 12:43:16 PM PDT 24
Finished Mar 19 12:43:19 PM PDT 24
Peak memory 199984 kb
Host smart-d78618de-0eba-435c-b559-4df16696e296
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248571736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1248571736
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1201896919
Short name T679
Test name
Test status
Simulation time 96361184 ps
CPU time 1.72 seconds
Started Mar 19 12:43:18 PM PDT 24
Finished Mar 19 12:43:19 PM PDT 24
Peak memory 199972 kb
Host smart-51db374a-fb8b-4783-9b95-ecf82071934e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201896919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1201896919
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.4149611105
Short name T718
Test name
Test status
Simulation time 419674676 ps
CPU time 2.4 seconds
Started Mar 19 12:43:16 PM PDT 24
Finished Mar 19 12:43:18 PM PDT 24
Peak memory 200016 kb
Host smart-b18404b7-1ed3-4ef5-9243-ccd3a37c3e97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149611105 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.4149611105
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.312813025
Short name T98
Test name
Test status
Simulation time 127722180 ps
CPU time 0.92 seconds
Started Mar 19 12:43:14 PM PDT 24
Finished Mar 19 12:43:16 PM PDT 24
Peak memory 199752 kb
Host smart-93463aa4-052a-42f3-a282-94b221f0d7a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312813025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.312813025
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1307809232
Short name T725
Test name
Test status
Simulation time 51584570 ps
CPU time 0.63 seconds
Started Mar 19 12:43:17 PM PDT 24
Finished Mar 19 12:43:17 PM PDT 24
Peak memory 194468 kb
Host smart-c74d1af9-b621-490d-bc3a-d7cadbc68d84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307809232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1307809232
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2139090688
Short name T70
Test name
Test status
Simulation time 84341865 ps
CPU time 1.07 seconds
Started Mar 19 12:43:16 PM PDT 24
Finished Mar 19 12:43:18 PM PDT 24
Peak memory 199752 kb
Host smart-ef0ef916-5e36-41f1-9a4d-66923dfd314e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139090688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2139090688
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1392972857
Short name T719
Test name
Test status
Simulation time 61964307 ps
CPU time 1.71 seconds
Started Mar 19 12:43:15 PM PDT 24
Finished Mar 19 12:43:17 PM PDT 24
Peak memory 200024 kb
Host smart-e28c6648-d293-4428-9375-370eff3b64e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392972857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1392972857
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1337883112
Short name T691
Test name
Test status
Simulation time 15982631476 ps
CPU time 242.67 seconds
Started Mar 19 12:43:14 PM PDT 24
Finished Mar 19 12:47:16 PM PDT 24
Peak memory 215624 kb
Host smart-7f199756-597e-4006-b48b-c0d35eebaa16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337883112 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1337883112
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2807379985
Short name T702
Test name
Test status
Simulation time 37768719 ps
CPU time 0.98 seconds
Started Mar 19 12:43:15 PM PDT 24
Finished Mar 19 12:43:16 PM PDT 24
Peak memory 199268 kb
Host smart-1e401ffa-ab91-4db9-93c9-e55364e983b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807379985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2807379985
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3416612359
Short name T678
Test name
Test status
Simulation time 18948223 ps
CPU time 0.57 seconds
Started Mar 19 12:43:15 PM PDT 24
Finished Mar 19 12:43:15 PM PDT 24
Peak memory 194536 kb
Host smart-cde2f2eb-97da-4ff6-bea4-1794325f4b74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416612359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3416612359
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.979103386
Short name T706
Test name
Test status
Simulation time 34522379 ps
CPU time 1.65 seconds
Started Mar 19 12:43:16 PM PDT 24
Finished Mar 19 12:43:18 PM PDT 24
Peak memory 199988 kb
Host smart-ff69a2b9-3610-43c5-aa56-6c7d312f120a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979103386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr
_outstanding.979103386
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3510238071
Short name T600
Test name
Test status
Simulation time 145666150 ps
CPU time 3.06 seconds
Started Mar 19 12:43:16 PM PDT 24
Finished Mar 19 12:43:19 PM PDT 24
Peak memory 199980 kb
Host smart-74eb0856-02be-4f31-8c8a-6b1b723e1ded
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510238071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3510238071
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.305686652
Short name T729
Test name
Test status
Simulation time 619828858 ps
CPU time 4.22 seconds
Started Mar 19 12:43:16 PM PDT 24
Finished Mar 19 12:43:21 PM PDT 24
Peak memory 199908 kb
Host smart-112318a0-ed5e-4dec-96f4-6fe0f096294e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305686652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.305686652
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.156943197
Short name T630
Test name
Test status
Simulation time 100375662258 ps
CPU time 1011.36 seconds
Started Mar 19 12:43:23 PM PDT 24
Finished Mar 19 01:00:14 PM PDT 24
Peak memory 224772 kb
Host smart-9f0648c2-0e42-49a8-a548-3012c07f5395
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156943197 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.156943197
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3603084118
Short name T602
Test name
Test status
Simulation time 22994543 ps
CPU time 0.71 seconds
Started Mar 19 12:43:21 PM PDT 24
Finished Mar 19 12:43:22 PM PDT 24
Peak memory 197828 kb
Host smart-1cb90e64-6612-4e3c-81b8-cc5af41f5448
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603084118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3603084118
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1511086707
Short name T657
Test name
Test status
Simulation time 33315036 ps
CPU time 0.56 seconds
Started Mar 19 12:43:24 PM PDT 24
Finished Mar 19 12:43:26 PM PDT 24
Peak memory 194428 kb
Host smart-ecbd3ad0-37df-401c-bc5e-0d11e8388791
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511086707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1511086707
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3273008485
Short name T619
Test name
Test status
Simulation time 583665251 ps
CPU time 1.79 seconds
Started Mar 19 12:43:22 PM PDT 24
Finished Mar 19 12:43:24 PM PDT 24
Peak memory 199496 kb
Host smart-1a45baab-c876-4acd-b37d-262efd1bb932
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273008485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3273008485
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3797150361
Short name T707
Test name
Test status
Simulation time 176688434 ps
CPU time 1.3 seconds
Started Mar 19 12:43:25 PM PDT 24
Finished Mar 19 12:43:27 PM PDT 24
Peak memory 200044 kb
Host smart-91c57c02-826f-4357-bd71-865339bac8cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797150361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3797150361
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2874261783
Short name T665
Test name
Test status
Simulation time 192027377 ps
CPU time 1.88 seconds
Started Mar 19 12:43:23 PM PDT 24
Finished Mar 19 12:43:25 PM PDT 24
Peak memory 199920 kb
Host smart-3ee9656c-ad86-465c-a1fc-06f590fc87b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874261783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2874261783
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2886299905
Short name T650
Test name
Test status
Simulation time 135695790 ps
CPU time 1.75 seconds
Started Mar 19 12:43:23 PM PDT 24
Finished Mar 19 12:43:25 PM PDT 24
Peak memory 199940 kb
Host smart-65275198-f4e2-44a5-b9fb-3332d296326a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886299905 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2886299905
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1654338704
Short name T111
Test name
Test status
Simulation time 89436361 ps
CPU time 0.82 seconds
Started Mar 19 12:43:26 PM PDT 24
Finished Mar 19 12:43:27 PM PDT 24
Peak memory 199332 kb
Host smart-5e1b0115-c367-42d9-a059-6676041b84a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654338704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1654338704
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.388115408
Short name T632
Test name
Test status
Simulation time 22090954 ps
CPU time 0.58 seconds
Started Mar 19 12:43:27 PM PDT 24
Finished Mar 19 12:43:27 PM PDT 24
Peak memory 194452 kb
Host smart-ba0c0cce-7709-4928-a37f-aeffd4f35a81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388115408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.388115408
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2725971310
Short name T715
Test name
Test status
Simulation time 257923645 ps
CPU time 2.1 seconds
Started Mar 19 12:43:24 PM PDT 24
Finished Mar 19 12:43:27 PM PDT 24
Peak memory 199964 kb
Host smart-eb1d939f-a7a2-48d5-839a-0dcf915ae92e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725971310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2725971310
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1831221603
Short name T710
Test name
Test status
Simulation time 515636935 ps
CPU time 4.65 seconds
Started Mar 19 12:43:29 PM PDT 24
Finished Mar 19 12:43:34 PM PDT 24
Peak memory 200000 kb
Host smart-636b3bdb-98ba-41bd-a91b-1763a3f73ea1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831221603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1831221603
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2169277357
Short name T728
Test name
Test status
Simulation time 859459942 ps
CPU time 4.49 seconds
Started Mar 19 12:43:23 PM PDT 24
Finished Mar 19 12:43:28 PM PDT 24
Peak memory 200016 kb
Host smart-20686ec1-b893-419a-a4a9-1bbe7ea64aa3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169277357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2169277357
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1987443656
Short name T597
Test name
Test status
Simulation time 217232333 ps
CPU time 1.4 seconds
Started Mar 19 12:43:25 PM PDT 24
Finished Mar 19 12:43:27 PM PDT 24
Peak memory 199968 kb
Host smart-82a71208-a5f7-44d3-8a2e-05511cdbbf09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987443656 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.1987443656
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.234169683
Short name T731
Test name
Test status
Simulation time 134961326 ps
CPU time 0.93 seconds
Started Mar 19 12:43:22 PM PDT 24
Finished Mar 19 12:43:23 PM PDT 24
Peak memory 199632 kb
Host smart-1bead462-ecfe-46aa-94cc-a22a14022999
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234169683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.234169683
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.725495469
Short name T688
Test name
Test status
Simulation time 13708897 ps
CPU time 0.69 seconds
Started Mar 19 12:43:21 PM PDT 24
Finished Mar 19 12:43:22 PM PDT 24
Peak memory 194516 kb
Host smart-4a878332-1869-41cd-b483-e7bb21f19fda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725495469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.725495469
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1307928954
Short name T673
Test name
Test status
Simulation time 26800376 ps
CPU time 1.21 seconds
Started Mar 19 12:43:22 PM PDT 24
Finished Mar 19 12:43:24 PM PDT 24
Peak memory 198200 kb
Host smart-5b6a3861-2a69-4a59-be40-119e179a9539
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307928954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1307928954
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.892386232
Short name T704
Test name
Test status
Simulation time 23080215 ps
CPU time 1.26 seconds
Started Mar 19 12:43:27 PM PDT 24
Finished Mar 19 12:43:28 PM PDT 24
Peak memory 200012 kb
Host smart-5bc8e643-0278-463b-8179-c4a60c7fbf89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892386232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.892386232
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2177955156
Short name T640
Test name
Test status
Simulation time 328541100 ps
CPU time 1.88 seconds
Started Mar 19 12:43:23 PM PDT 24
Finished Mar 19 12:43:25 PM PDT 24
Peak memory 199956 kb
Host smart-06a5ea7e-5e32-4593-9cee-bcbf7af81ad5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177955156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2177955156
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3739038061
Short name T647
Test name
Test status
Simulation time 46499903 ps
CPU time 1.27 seconds
Started Mar 19 12:43:31 PM PDT 24
Finished Mar 19 12:43:32 PM PDT 24
Peak memory 199788 kb
Host smart-666ba5bc-f525-46df-8dee-feb7a5fdb4d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739038061 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.3739038061
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2406849673
Short name T709
Test name
Test status
Simulation time 51200197 ps
CPU time 0.76 seconds
Started Mar 19 12:43:25 PM PDT 24
Finished Mar 19 12:43:26 PM PDT 24
Peak memory 199116 kb
Host smart-f2f0b9cd-27d8-4c8a-82f7-de9d66429369
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406849673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2406849673
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.3954039061
Short name T663
Test name
Test status
Simulation time 45740486 ps
CPU time 0.59 seconds
Started Mar 19 12:43:26 PM PDT 24
Finished Mar 19 12:43:27 PM PDT 24
Peak memory 194468 kb
Host smart-fbfbc879-00bc-4cd1-91d0-0addc16ef0bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954039061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3954039061
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2053857202
Short name T646
Test name
Test status
Simulation time 168533877 ps
CPU time 2.22 seconds
Started Mar 19 12:43:24 PM PDT 24
Finished Mar 19 12:43:27 PM PDT 24
Peak memory 199592 kb
Host smart-286f42cd-2f30-4e97-8512-c40ee1f1e4d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053857202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2053857202
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3005366703
Short name T714
Test name
Test status
Simulation time 93687788 ps
CPU time 1.28 seconds
Started Mar 19 12:43:25 PM PDT 24
Finished Mar 19 12:43:27 PM PDT 24
Peak memory 200024 kb
Host smart-bf53c2c6-0d94-44e2-acc5-b5cab8fdf021
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005366703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.3005366703
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.555991690
Short name T648
Test name
Test status
Simulation time 339618144 ps
CPU time 3.07 seconds
Started Mar 19 12:43:25 PM PDT 24
Finished Mar 19 12:43:28 PM PDT 24
Peak memory 200020 kb
Host smart-eb74980f-031d-460b-b607-6f5c94b3c417
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555991690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.555991690
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2343038445
Short name T654
Test name
Test status
Simulation time 40219681 ps
CPU time 1.27 seconds
Started Mar 19 12:43:32 PM PDT 24
Finished Mar 19 12:43:33 PM PDT 24
Peak memory 199992 kb
Host smart-a5749219-0b35-4fe2-8ff9-ed089e508cb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343038445 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2343038445
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3361150842
Short name T599
Test name
Test status
Simulation time 36958744 ps
CPU time 0.68 seconds
Started Mar 19 12:43:26 PM PDT 24
Finished Mar 19 12:43:27 PM PDT 24
Peak memory 197480 kb
Host smart-3558d35f-7b96-4b66-bc9f-aceb215dfc76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361150842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3361150842
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2114898798
Short name T690
Test name
Test status
Simulation time 56104728 ps
CPU time 0.6 seconds
Started Mar 19 12:43:26 PM PDT 24
Finished Mar 19 12:43:27 PM PDT 24
Peak memory 194448 kb
Host smart-3e5ebe19-5dda-484e-bfc8-42eec1d29bec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114898798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2114898798
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2772421079
Short name T601
Test name
Test status
Simulation time 106706212 ps
CPU time 1.79 seconds
Started Mar 19 12:43:32 PM PDT 24
Finished Mar 19 12:43:34 PM PDT 24
Peak memory 199420 kb
Host smart-68818abe-7691-4dc3-8bfd-7305e039336d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772421079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.2772421079
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2299965161
Short name T629
Test name
Test status
Simulation time 39009306 ps
CPU time 2.33 seconds
Started Mar 19 12:43:28 PM PDT 24
Finished Mar 19 12:43:30 PM PDT 24
Peak memory 199964 kb
Host smart-cb9ca6a5-c2f0-476f-a307-df8671f32090
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299965161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2299965161
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.354941823
Short name T730
Test name
Test status
Simulation time 3149828722 ps
CPU time 3.15 seconds
Started Mar 19 12:43:23 PM PDT 24
Finished Mar 19 12:43:27 PM PDT 24
Peak memory 200124 kb
Host smart-a0c03a58-2284-462a-8ce7-cf39f5746c29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354941823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.354941823
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3942421556
Short name T615
Test name
Test status
Simulation time 56202748 ps
CPU time 3.63 seconds
Started Mar 19 12:43:21 PM PDT 24
Finished Mar 19 12:43:24 PM PDT 24
Peak memory 200000 kb
Host smart-52390f13-f913-4923-a709-5f110c1c09e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942421556 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3942421556
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3266251840
Short name T669
Test name
Test status
Simulation time 55266454 ps
CPU time 0.68 seconds
Started Mar 19 12:43:32 PM PDT 24
Finished Mar 19 12:43:33 PM PDT 24
Peak memory 197536 kb
Host smart-e6fcd1b0-0416-47b5-8e23-71caf0146eee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266251840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3266251840
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1362900139
Short name T596
Test name
Test status
Simulation time 11521087 ps
CPU time 0.57 seconds
Started Mar 19 12:43:29 PM PDT 24
Finished Mar 19 12:43:30 PM PDT 24
Peak memory 194448 kb
Host smart-ad7b6725-e855-4bfa-964b-92e93aff69f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362900139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1362900139
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3309795498
Short name T69
Test name
Test status
Simulation time 103193279 ps
CPU time 1.74 seconds
Started Mar 19 12:43:25 PM PDT 24
Finished Mar 19 12:43:27 PM PDT 24
Peak memory 199532 kb
Host smart-fd5209b9-2dc9-40cc-8e22-3e71d2af8cd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309795498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3309795498
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2309379045
Short name T693
Test name
Test status
Simulation time 87489525 ps
CPU time 1.84 seconds
Started Mar 19 12:43:22 PM PDT 24
Finished Mar 19 12:43:24 PM PDT 24
Peak memory 199956 kb
Host smart-c652e29b-c548-4169-a06d-6d14f17e8fac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309379045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2309379045
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.549403189
Short name T664
Test name
Test status
Simulation time 444837544 ps
CPU time 4.3 seconds
Started Mar 19 12:43:24 PM PDT 24
Finished Mar 19 12:43:30 PM PDT 24
Peak memory 200004 kb
Host smart-d7452c32-4923-489a-b6ed-108f316a1a79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549403189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.549403189
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.754272284
Short name T703
Test name
Test status
Simulation time 463980506 ps
CPU time 8.99 seconds
Started Mar 19 12:43:12 PM PDT 24
Finished Mar 19 12:43:21 PM PDT 24
Peak memory 199888 kb
Host smart-c1c0266d-fa44-43ec-8bc3-731f7a2b9449
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754272284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.754272284
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3235510966
Short name T694
Test name
Test status
Simulation time 3752174472 ps
CPU time 15.84 seconds
Started Mar 19 12:43:08 PM PDT 24
Finished Mar 19 12:43:24 PM PDT 24
Peak memory 199180 kb
Host smart-71cab704-0654-4614-93da-9b0d32aec319
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235510966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3235510966
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2042447999
Short name T638
Test name
Test status
Simulation time 90260314 ps
CPU time 0.76 seconds
Started Mar 19 12:43:09 PM PDT 24
Finished Mar 19 12:43:10 PM PDT 24
Peak memory 197532 kb
Host smart-eb9ed7fa-9380-4a4e-9c39-4d64b759da4e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042447999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2042447999
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3891198594
Short name T712
Test name
Test status
Simulation time 35675037494 ps
CPU time 396.39 seconds
Started Mar 19 12:43:08 PM PDT 24
Finished Mar 19 12:49:45 PM PDT 24
Peak memory 215912 kb
Host smart-0654c6d1-e618-4b26-9a03-48a7dbac3af6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891198594 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3891198594
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3814698478
Short name T692
Test name
Test status
Simulation time 51168280 ps
CPU time 0.87 seconds
Started Mar 19 12:43:09 PM PDT 24
Finished Mar 19 12:43:10 PM PDT 24
Peak memory 199748 kb
Host smart-9a889b5d-a72b-4260-b9da-fe4dc915dfdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814698478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.3814698478
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.3287386707
Short name T674
Test name
Test status
Simulation time 213436312 ps
CPU time 0.61 seconds
Started Mar 19 12:43:08 PM PDT 24
Finished Mar 19 12:43:08 PM PDT 24
Peak memory 194452 kb
Host smart-2c5b44a3-7aa3-4aed-a863-8df3ae7e8829
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287386707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3287386707
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.409424717
Short name T634
Test name
Test status
Simulation time 656534654 ps
CPU time 2.47 seconds
Started Mar 19 12:43:10 PM PDT 24
Finished Mar 19 12:43:13 PM PDT 24
Peak memory 198988 kb
Host smart-a96b7699-c2d6-4165-a4ca-80e8db977d78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409424717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_
outstanding.409424717
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.248918522
Short name T616
Test name
Test status
Simulation time 81342928 ps
CPU time 2.35 seconds
Started Mar 19 12:43:02 PM PDT 24
Finished Mar 19 12:43:05 PM PDT 24
Peak memory 199940 kb
Host smart-427ee517-4953-40e3-9e4e-fd46152f116b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248918522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.248918522
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2394221443
Short name T120
Test name
Test status
Simulation time 1908407611 ps
CPU time 1.99 seconds
Started Mar 19 12:43:08 PM PDT 24
Finished Mar 19 12:43:10 PM PDT 24
Peak memory 199948 kb
Host smart-f4325adc-4dd9-4e47-a165-621277f10eff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394221443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2394221443
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.219208003
Short name T625
Test name
Test status
Simulation time 19816616 ps
CPU time 0.57 seconds
Started Mar 19 12:43:24 PM PDT 24
Finished Mar 19 12:43:25 PM PDT 24
Peak memory 194560 kb
Host smart-ca24ffd9-6707-4b31-83fc-4dc5102e57d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219208003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.219208003
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.4259746154
Short name T627
Test name
Test status
Simulation time 16671692 ps
CPU time 0.68 seconds
Started Mar 19 12:43:23 PM PDT 24
Finished Mar 19 12:43:24 PM PDT 24
Peak memory 194720 kb
Host smart-35f0563b-f861-4172-9c1b-4ec1e5a25503
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259746154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.4259746154
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1050411662
Short name T720
Test name
Test status
Simulation time 14076059 ps
CPU time 0.64 seconds
Started Mar 19 12:43:28 PM PDT 24
Finished Mar 19 12:43:29 PM PDT 24
Peak memory 194476 kb
Host smart-e6968534-ea28-474e-ae90-3acb76975e8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050411662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1050411662
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.3597828716
Short name T642
Test name
Test status
Simulation time 13026041 ps
CPU time 0.62 seconds
Started Mar 19 12:43:29 PM PDT 24
Finished Mar 19 12:43:30 PM PDT 24
Peak memory 194536 kb
Host smart-b61c5d4a-edb5-4af8-93cd-149aecb2f621
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597828716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.3597828716
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3511159959
Short name T666
Test name
Test status
Simulation time 46850778 ps
CPU time 0.61 seconds
Started Mar 19 12:43:26 PM PDT 24
Finished Mar 19 12:43:27 PM PDT 24
Peak memory 194512 kb
Host smart-cc116e1f-ca8f-4f90-b33b-f6a4858ec29b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511159959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3511159959
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3837657832
Short name T604
Test name
Test status
Simulation time 19434103 ps
CPU time 0.59 seconds
Started Mar 19 12:43:27 PM PDT 24
Finished Mar 19 12:43:28 PM PDT 24
Peak memory 194452 kb
Host smart-070cc177-2f46-472d-8dbc-6fae1fc707c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837657832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3837657832
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3412897774
Short name T656
Test name
Test status
Simulation time 24380089 ps
CPU time 0.62 seconds
Started Mar 19 12:43:28 PM PDT 24
Finished Mar 19 12:43:29 PM PDT 24
Peak memory 194716 kb
Host smart-027be486-6ebc-415e-9bf7-eaf995f5fd2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412897774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3412897774
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2274168710
Short name T628
Test name
Test status
Simulation time 26202788 ps
CPU time 0.6 seconds
Started Mar 19 12:43:27 PM PDT 24
Finished Mar 19 12:43:28 PM PDT 24
Peak memory 194500 kb
Host smart-18eb9d36-45d4-4c4e-acb7-6db81886ed15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274168710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2274168710
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1420756820
Short name T708
Test name
Test status
Simulation time 42916552 ps
CPU time 0.57 seconds
Started Mar 19 12:43:25 PM PDT 24
Finished Mar 19 12:43:26 PM PDT 24
Peak memory 194780 kb
Host smart-b01771cb-6a61-4d3f-a4fe-45bca3f59043
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420756820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1420756820
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2905958335
Short name T683
Test name
Test status
Simulation time 30098753 ps
CPU time 0.64 seconds
Started Mar 19 12:43:28 PM PDT 24
Finished Mar 19 12:43:29 PM PDT 24
Peak memory 194552 kb
Host smart-3c1bacab-eb2e-4239-b1fc-17a6d6fcf50e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905958335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2905958335
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.838779447
Short name T99
Test name
Test status
Simulation time 257301696 ps
CPU time 3.09 seconds
Started Mar 19 12:43:09 PM PDT 24
Finished Mar 19 12:43:12 PM PDT 24
Peak memory 199248 kb
Host smart-e2715194-ca45-4f45-9276-66d40e248318
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838779447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.838779447
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1775659123
Short name T107
Test name
Test status
Simulation time 1176995030 ps
CPU time 5.81 seconds
Started Mar 19 12:43:07 PM PDT 24
Finished Mar 19 12:43:13 PM PDT 24
Peak memory 199904 kb
Host smart-260833a9-b3e1-471c-bef3-ca58af1dfff7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775659123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1775659123
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.410892972
Short name T722
Test name
Test status
Simulation time 18979979 ps
CPU time 0.74 seconds
Started Mar 19 12:43:08 PM PDT 24
Finished Mar 19 12:43:09 PM PDT 24
Peak memory 197564 kb
Host smart-8275ea2b-f52f-4b5e-ada0-a1f133926b02
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410892972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.410892972
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1994802153
Short name T623
Test name
Test status
Simulation time 113297293 ps
CPU time 2.66 seconds
Started Mar 19 12:43:08 PM PDT 24
Finished Mar 19 12:43:11 PM PDT 24
Peak memory 200076 kb
Host smart-41298c92-efc5-4237-908d-4bc806f35417
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994802153 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1994802153
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1797290260
Short name T689
Test name
Test status
Simulation time 29070691 ps
CPU time 0.82 seconds
Started Mar 19 12:43:11 PM PDT 24
Finished Mar 19 12:43:12 PM PDT 24
Peak memory 198932 kb
Host smart-aafd298c-0b0e-4bbc-9fc1-d91adf0b982a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797290260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1797290260
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.1780153081
Short name T667
Test name
Test status
Simulation time 15119006 ps
CPU time 0.6 seconds
Started Mar 19 12:43:09 PM PDT 24
Finished Mar 19 12:43:09 PM PDT 24
Peak memory 194512 kb
Host smart-41ff2901-c51e-4342-bef4-194ca7a01d95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780153081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.1780153081
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2758862707
Short name T605
Test name
Test status
Simulation time 93123447 ps
CPU time 2.21 seconds
Started Mar 19 12:43:08 PM PDT 24
Finished Mar 19 12:43:10 PM PDT 24
Peak memory 199860 kb
Host smart-ae821da2-22d6-4788-85c9-4d8c97cebc25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758862707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.2758862707
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1187234836
Short name T613
Test name
Test status
Simulation time 763309009 ps
CPU time 3.67 seconds
Started Mar 19 12:43:14 PM PDT 24
Finished Mar 19 12:43:18 PM PDT 24
Peak memory 199988 kb
Host smart-459dfe31-2af6-4987-bddc-9af70aebfb1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187234836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1187234836
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1581791936
Short name T699
Test name
Test status
Simulation time 90318812 ps
CPU time 1.85 seconds
Started Mar 19 12:43:12 PM PDT 24
Finished Mar 19 12:43:14 PM PDT 24
Peak memory 199920 kb
Host smart-042b7411-5562-4dc1-ad79-2bb8160d04ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581791936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1581791936
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.2395375392
Short name T639
Test name
Test status
Simulation time 14692454 ps
CPU time 0.59 seconds
Started Mar 19 12:43:23 PM PDT 24
Finished Mar 19 12:43:24 PM PDT 24
Peak memory 194536 kb
Host smart-a3cbba6a-6787-48d5-a178-4b50a956d33a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395375392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2395375392
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1234015232
Short name T643
Test name
Test status
Simulation time 17349544 ps
CPU time 0.62 seconds
Started Mar 19 12:43:28 PM PDT 24
Finished Mar 19 12:43:29 PM PDT 24
Peak memory 194536 kb
Host smart-a71aa6fc-33f2-44ed-b74f-ac8725bc1e30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234015232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1234015232
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1378610556
Short name T610
Test name
Test status
Simulation time 16558708 ps
CPU time 0.62 seconds
Started Mar 19 12:43:22 PM PDT 24
Finished Mar 19 12:43:22 PM PDT 24
Peak memory 194596 kb
Host smart-009314c0-2c80-4038-90cb-2374dc38204f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378610556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1378610556
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.1601367245
Short name T681
Test name
Test status
Simulation time 38331014 ps
CPU time 0.57 seconds
Started Mar 19 12:43:22 PM PDT 24
Finished Mar 19 12:43:23 PM PDT 24
Peak memory 194536 kb
Host smart-83564cfb-0984-4f19-85d2-95669d428d76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601367245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1601367245
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3124377588
Short name T671
Test name
Test status
Simulation time 13107678 ps
CPU time 0.58 seconds
Started Mar 19 12:43:25 PM PDT 24
Finished Mar 19 12:43:26 PM PDT 24
Peak memory 194524 kb
Host smart-d867d3d1-7a9f-44dd-b543-e9beb24d5b8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124377588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3124377588
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.766650609
Short name T608
Test name
Test status
Simulation time 31649706 ps
CPU time 0.61 seconds
Started Mar 19 12:43:27 PM PDT 24
Finished Mar 19 12:43:27 PM PDT 24
Peak memory 194576 kb
Host smart-816839a7-2956-4abc-a834-840530599ef4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766650609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.766650609
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.721257675
Short name T631
Test name
Test status
Simulation time 27218334 ps
CPU time 0.59 seconds
Started Mar 19 12:43:23 PM PDT 24
Finished Mar 19 12:43:24 PM PDT 24
Peak memory 194508 kb
Host smart-96875a75-1e6d-4057-9333-8c8efaf57170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721257675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.721257675
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2471583782
Short name T676
Test name
Test status
Simulation time 20393839 ps
CPU time 0.61 seconds
Started Mar 19 12:43:35 PM PDT 24
Finished Mar 19 12:43:36 PM PDT 24
Peak memory 194836 kb
Host smart-eb5cd3fa-b090-4bd1-9565-94604f5d88b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471583782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2471583782
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.561005553
Short name T649
Test name
Test status
Simulation time 40773896 ps
CPU time 0.6 seconds
Started Mar 19 12:43:32 PM PDT 24
Finished Mar 19 12:43:32 PM PDT 24
Peak memory 194716 kb
Host smart-7c2c8921-ebaf-4f2e-869f-af1666c442f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561005553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.561005553
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3541916718
Short name T668
Test name
Test status
Simulation time 12039118 ps
CPU time 0.58 seconds
Started Mar 19 12:43:37 PM PDT 24
Finished Mar 19 12:43:37 PM PDT 24
Peak memory 194460 kb
Host smart-3c90e315-3e8c-4343-90a5-f37980d36bcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541916718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3541916718
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3297488681
Short name T68
Test name
Test status
Simulation time 449405894 ps
CPU time 9 seconds
Started Mar 19 12:43:14 PM PDT 24
Finished Mar 19 12:43:23 PM PDT 24
Peak memory 199340 kb
Host smart-3ef8531f-d95b-46c2-b4f4-65a410378fb4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297488681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3297488681
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2933673046
Short name T721
Test name
Test status
Simulation time 571124244 ps
CPU time 5.87 seconds
Started Mar 19 12:43:07 PM PDT 24
Finished Mar 19 12:43:13 PM PDT 24
Peak memory 199932 kb
Host smart-c18209fc-3b6c-4f93-bf30-bde6a6bd106f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933673046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2933673046
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.4244745244
Short name T655
Test name
Test status
Simulation time 24273339 ps
CPU time 0.75 seconds
Started Mar 19 12:43:07 PM PDT 24
Finished Mar 19 12:43:08 PM PDT 24
Peak memory 197680 kb
Host smart-4a165420-8749-4156-a3fa-6b4676437265
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244745244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.4244745244
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1365493280
Short name T717
Test name
Test status
Simulation time 935840381 ps
CPU time 2.29 seconds
Started Mar 19 12:43:10 PM PDT 24
Finished Mar 19 12:43:12 PM PDT 24
Peak memory 200040 kb
Host smart-5f7b2be8-26b3-407e-8962-447aa9bb3f08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365493280 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1365493280
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1325990209
Short name T112
Test name
Test status
Simulation time 26920631 ps
CPU time 0.81 seconds
Started Mar 19 12:43:12 PM PDT 24
Finished Mar 19 12:43:13 PM PDT 24
Peak memory 199160 kb
Host smart-29c47e14-7f8b-46d5-ab84-b7a34a7bd852
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325990209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1325990209
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3790388546
Short name T685
Test name
Test status
Simulation time 30690344 ps
CPU time 0.61 seconds
Started Mar 19 12:43:08 PM PDT 24
Finished Mar 19 12:43:09 PM PDT 24
Peak memory 194516 kb
Host smart-4e204a2a-8510-4f4c-9aac-99d9f1dc25b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790388546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3790388546
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1518395662
Short name T653
Test name
Test status
Simulation time 922819325 ps
CPU time 1.75 seconds
Started Mar 19 12:43:10 PM PDT 24
Finished Mar 19 12:43:12 PM PDT 24
Peak memory 199916 kb
Host smart-667d7a37-de92-4b42-88bd-1aad04ffe6bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518395662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1518395662
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.643486013
Short name T660
Test name
Test status
Simulation time 89316931 ps
CPU time 2.42 seconds
Started Mar 19 12:43:11 PM PDT 24
Finished Mar 19 12:43:14 PM PDT 24
Peak memory 200032 kb
Host smart-a0099e45-0a35-4ab8-a13a-783b01cb5ca1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643486013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.643486013
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2539897353
Short name T119
Test name
Test status
Simulation time 158712545 ps
CPU time 3.06 seconds
Started Mar 19 12:43:12 PM PDT 24
Finished Mar 19 12:43:15 PM PDT 24
Peak memory 199960 kb
Host smart-6abd31c6-3773-4212-af70-e4785ff0510b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539897353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2539897353
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.3050043253
Short name T670
Test name
Test status
Simulation time 28313085 ps
CPU time 0.6 seconds
Started Mar 19 12:43:27 PM PDT 24
Finished Mar 19 12:43:28 PM PDT 24
Peak memory 194720 kb
Host smart-68be7a5c-7533-46ea-a1b2-e891a95d4544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050043253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3050043253
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2518350995
Short name T620
Test name
Test status
Simulation time 69512753 ps
CPU time 0.58 seconds
Started Mar 19 12:43:41 PM PDT 24
Finished Mar 19 12:43:42 PM PDT 24
Peak memory 194448 kb
Host smart-b3dbbd02-0421-4d61-8800-74ad975d29b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518350995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2518350995
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.336281873
Short name T684
Test name
Test status
Simulation time 43087474 ps
CPU time 0.58 seconds
Started Mar 19 12:43:42 PM PDT 24
Finished Mar 19 12:43:42 PM PDT 24
Peak memory 194584 kb
Host smart-e914d81d-ff0b-45ef-b5f6-9a896d268279
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336281873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.336281873
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3373065699
Short name T698
Test name
Test status
Simulation time 12578002 ps
CPU time 0.57 seconds
Started Mar 19 12:43:27 PM PDT 24
Finished Mar 19 12:43:28 PM PDT 24
Peak memory 194752 kb
Host smart-a1349945-50e6-474e-811e-390520744255
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373065699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3373065699
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.84469732
Short name T695
Test name
Test status
Simulation time 16286560 ps
CPU time 0.61 seconds
Started Mar 19 12:43:40 PM PDT 24
Finished Mar 19 12:43:41 PM PDT 24
Peak memory 194696 kb
Host smart-829c13f2-6e61-43df-89c1-2ee99b22c5d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84469732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.84469732
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1950113182
Short name T644
Test name
Test status
Simulation time 18988539 ps
CPU time 0.58 seconds
Started Mar 19 12:43:28 PM PDT 24
Finished Mar 19 12:43:29 PM PDT 24
Peak memory 194468 kb
Host smart-af056599-630c-463f-89a4-047dd4a799b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950113182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1950113182
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1137939562
Short name T612
Test name
Test status
Simulation time 41223621 ps
CPU time 0.65 seconds
Started Mar 19 12:43:31 PM PDT 24
Finished Mar 19 12:43:32 PM PDT 24
Peak memory 194704 kb
Host smart-b9ee5698-b4ff-4d96-984d-a00840a5c5be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137939562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1137939562
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.823785585
Short name T697
Test name
Test status
Simulation time 60212358 ps
CPU time 0.6 seconds
Started Mar 19 12:43:42 PM PDT 24
Finished Mar 19 12:43:43 PM PDT 24
Peak memory 194772 kb
Host smart-34de50d1-5b85-4826-b2e2-f7c55f306ed3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823785585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.823785585
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1007889658
Short name T595
Test name
Test status
Simulation time 27771237 ps
CPU time 0.6 seconds
Started Mar 19 12:43:32 PM PDT 24
Finished Mar 19 12:43:32 PM PDT 24
Peak memory 194720 kb
Host smart-acf6f1eb-5bc5-4596-a3c1-1f721b05c597
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007889658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1007889658
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.665895505
Short name T607
Test name
Test status
Simulation time 30824668 ps
CPU time 0.57 seconds
Started Mar 19 12:43:27 PM PDT 24
Finished Mar 19 12:43:28 PM PDT 24
Peak memory 194776 kb
Host smart-42a341a5-0f39-4de5-ba21-9824c3b4e6cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665895505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.665895505
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3185714808
Short name T637
Test name
Test status
Simulation time 129037305 ps
CPU time 2 seconds
Started Mar 19 12:43:08 PM PDT 24
Finished Mar 19 12:43:10 PM PDT 24
Peak memory 199980 kb
Host smart-f1c529be-293e-434f-b828-3e4d2e68c739
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185714808 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3185714808
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.487013701
Short name T624
Test name
Test status
Simulation time 35043623 ps
CPU time 0.57 seconds
Started Mar 19 12:43:09 PM PDT 24
Finished Mar 19 12:43:10 PM PDT 24
Peak memory 194684 kb
Host smart-697ff3a9-fa0b-47a7-801d-6d22f28b82a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487013701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.487013701
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.784143166
Short name T626
Test name
Test status
Simulation time 561318832 ps
CPU time 1.78 seconds
Started Mar 19 12:43:08 PM PDT 24
Finished Mar 19 12:43:11 PM PDT 24
Peak memory 199696 kb
Host smart-c449feec-9de9-401e-a1ef-a38744147307
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784143166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_
outstanding.784143166
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1002230723
Short name T700
Test name
Test status
Simulation time 60208108 ps
CPU time 1.56 seconds
Started Mar 19 12:43:08 PM PDT 24
Finished Mar 19 12:43:10 PM PDT 24
Peak memory 200048 kb
Host smart-56ecafe1-db8c-4283-b416-d1c7620e2534
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002230723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1002230723
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3254106507
Short name T116
Test name
Test status
Simulation time 363738008 ps
CPU time 2.82 seconds
Started Mar 19 12:43:11 PM PDT 24
Finished Mar 19 12:43:14 PM PDT 24
Peak memory 199940 kb
Host smart-33f745ce-f977-476c-b46b-bc47395e1c3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254106507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3254106507
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2813486038
Short name T618
Test name
Test status
Simulation time 75139370 ps
CPU time 2.43 seconds
Started Mar 19 12:43:14 PM PDT 24
Finished Mar 19 12:43:17 PM PDT 24
Peak memory 199992 kb
Host smart-baa6c150-b314-45a9-831a-0473d7cc0323
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813486038 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.2813486038
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.4101220904
Short name T100
Test name
Test status
Simulation time 115948658 ps
CPU time 0.88 seconds
Started Mar 19 12:43:13 PM PDT 24
Finished Mar 19 12:43:14 PM PDT 24
Peak memory 199188 kb
Host smart-d0953ead-7b60-44df-a4d9-5905ba8f982e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101220904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.4101220904
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2341052623
Short name T598
Test name
Test status
Simulation time 53424457 ps
CPU time 0.61 seconds
Started Mar 19 12:43:08 PM PDT 24
Finished Mar 19 12:43:09 PM PDT 24
Peak memory 194600 kb
Host smart-eeedcc7f-b03a-42a3-b315-64e5337a4fa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341052623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2341052623
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.767024461
Short name T659
Test name
Test status
Simulation time 68425744 ps
CPU time 1.13 seconds
Started Mar 19 12:43:08 PM PDT 24
Finished Mar 19 12:43:10 PM PDT 24
Peak memory 197952 kb
Host smart-d8516cac-c795-4d58-8f70-86d1f1ae8b83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767024461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_
outstanding.767024461
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.625647380
Short name T603
Test name
Test status
Simulation time 52717613 ps
CPU time 2.81 seconds
Started Mar 19 12:43:13 PM PDT 24
Finished Mar 19 12:43:16 PM PDT 24
Peak memory 199960 kb
Host smart-5e37955a-df0e-4e6d-8813-f3106a71b106
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625647380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.625647380
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.84911885
Short name T115
Test name
Test status
Simulation time 908021214 ps
CPU time 3.05 seconds
Started Mar 19 12:43:09 PM PDT 24
Finished Mar 19 12:43:12 PM PDT 24
Peak memory 199908 kb
Host smart-1680664a-bff5-42c2-b3a9-7bf6e1c62fa4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84911885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.84911885
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1333170548
Short name T614
Test name
Test status
Simulation time 119629601 ps
CPU time 1.25 seconds
Started Mar 19 12:43:12 PM PDT 24
Finished Mar 19 12:43:14 PM PDT 24
Peak memory 200040 kb
Host smart-4ad271ed-21f9-4504-aa49-33ba1dc73869
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333170548 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1333170548
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3093187382
Short name T104
Test name
Test status
Simulation time 82039236 ps
CPU time 0.87 seconds
Started Mar 19 12:43:09 PM PDT 24
Finished Mar 19 12:43:10 PM PDT 24
Peak memory 198900 kb
Host smart-d81cb761-e580-4525-b09f-b721175363fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093187382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3093187382
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.3594004781
Short name T658
Test name
Test status
Simulation time 50334818 ps
CPU time 0.59 seconds
Started Mar 19 12:43:09 PM PDT 24
Finished Mar 19 12:43:09 PM PDT 24
Peak memory 194600 kb
Host smart-a8f3dc08-0b08-42cf-8c47-ef1797872c1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594004781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3594004781
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.576984350
Short name T716
Test name
Test status
Simulation time 47467052 ps
CPU time 1.17 seconds
Started Mar 19 12:43:09 PM PDT 24
Finished Mar 19 12:43:10 PM PDT 24
Peak memory 198164 kb
Host smart-47bc2355-25b3-4390-8a3a-792727e7bc2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576984350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_
outstanding.576984350
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1864595145
Short name T611
Test name
Test status
Simulation time 110266389 ps
CPU time 3.31 seconds
Started Mar 19 12:43:10 PM PDT 24
Finished Mar 19 12:43:13 PM PDT 24
Peak memory 199984 kb
Host smart-9039c139-6b21-41e0-87e0-588e809f9c87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864595145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1864595145
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.852213820
Short name T118
Test name
Test status
Simulation time 180883092 ps
CPU time 1.71 seconds
Started Mar 19 12:43:12 PM PDT 24
Finished Mar 19 12:43:14 PM PDT 24
Peak memory 199944 kb
Host smart-30dd7e19-59db-4eb5-b5ad-4795c56c88ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852213820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.852213820
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.500498656
Short name T621
Test name
Test status
Simulation time 104277078 ps
CPU time 2.42 seconds
Started Mar 19 12:43:08 PM PDT 24
Finished Mar 19 12:43:11 PM PDT 24
Peak memory 199968 kb
Host smart-bd0a9c70-436e-46ed-a757-7182f5c3db11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500498656 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.500498656
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.4233856340
Short name T101
Test name
Test status
Simulation time 79084435 ps
CPU time 0.78 seconds
Started Mar 19 12:43:07 PM PDT 24
Finished Mar 19 12:43:08 PM PDT 24
Peak memory 198812 kb
Host smart-a7dc7da5-e1a6-4c15-9122-83ce2068ca61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233856340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.4233856340
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.2165267628
Short name T677
Test name
Test status
Simulation time 99920346 ps
CPU time 0.57 seconds
Started Mar 19 12:43:10 PM PDT 24
Finished Mar 19 12:43:11 PM PDT 24
Peak memory 194452 kb
Host smart-a712c14e-b814-4f6b-972f-656c1a449d99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165267628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2165267628
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.421490034
Short name T724
Test name
Test status
Simulation time 34603807 ps
CPU time 1.68 seconds
Started Mar 19 12:43:08 PM PDT 24
Finished Mar 19 12:43:10 PM PDT 24
Peak memory 200064 kb
Host smart-4021288a-4799-4e50-a75b-20aee9355e26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421490034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_
outstanding.421490034
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3718515398
Short name T680
Test name
Test status
Simulation time 67118612 ps
CPU time 3.66 seconds
Started Mar 19 12:43:12 PM PDT 24
Finished Mar 19 12:43:16 PM PDT 24
Peak memory 199968 kb
Host smart-60b5f8ac-327b-4912-b373-abc2919eeb6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718515398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3718515398
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.658791685
Short name T609
Test name
Test status
Simulation time 281644324 ps
CPU time 1.94 seconds
Started Mar 19 12:43:16 PM PDT 24
Finished Mar 19 12:43:18 PM PDT 24
Peak memory 200016 kb
Host smart-1dc928f6-57b9-4f9a-ac1e-8f86262f810f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658791685 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.658791685
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3821372302
Short name T103
Test name
Test status
Simulation time 19080562 ps
CPU time 0.69 seconds
Started Mar 19 12:43:15 PM PDT 24
Finished Mar 19 12:43:16 PM PDT 24
Peak memory 197448 kb
Host smart-81035a31-c5de-4598-8435-95d0ad8805f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821372302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3821372302
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1983974626
Short name T633
Test name
Test status
Simulation time 16326012 ps
CPU time 0.61 seconds
Started Mar 19 12:43:17 PM PDT 24
Finished Mar 19 12:43:18 PM PDT 24
Peak memory 194536 kb
Host smart-86728c14-7a64-4a7f-ad90-547d49cbe969
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983974626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1983974626
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.109028627
Short name T672
Test name
Test status
Simulation time 49084432 ps
CPU time 1.17 seconds
Started Mar 19 12:43:16 PM PDT 24
Finished Mar 19 12:43:17 PM PDT 24
Peak memory 199696 kb
Host smart-252d781a-5e95-45fb-b262-e5c83820d506
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109028627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.109028627
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1252404107
Short name T705
Test name
Test status
Simulation time 329345006 ps
CPU time 3.1 seconds
Started Mar 19 12:43:16 PM PDT 24
Finished Mar 19 12:43:20 PM PDT 24
Peak memory 199940 kb
Host smart-34bb5e16-95e8-4c70-b78f-9ecd2a0afbf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252404107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1252404107
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3500867768
Short name T117
Test name
Test status
Simulation time 172694801 ps
CPU time 1.74 seconds
Started Mar 19 12:43:16 PM PDT 24
Finished Mar 19 12:43:18 PM PDT 24
Peak memory 199976 kb
Host smart-92aef76f-ecf3-4850-9c75-c94a5dedc336
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500867768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.3500867768
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.506021821
Short name T375
Test name
Test status
Simulation time 129677703 ps
CPU time 4.78 seconds
Started Mar 19 12:44:42 PM PDT 24
Finished Mar 19 12:44:47 PM PDT 24
Peak memory 200356 kb
Host smart-9c09d046-08a7-4760-a807-c358772fdffe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=506021821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.506021821
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.378129398
Short name T575
Test name
Test status
Simulation time 346675452 ps
CPU time 16.69 seconds
Started Mar 19 12:44:35 PM PDT 24
Finished Mar 19 12:44:52 PM PDT 24
Peak memory 200336 kb
Host smart-b0c427d7-69c3-47e5-afb4-3dba0a7f3f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378129398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.378129398
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1624211350
Short name T489
Test name
Test status
Simulation time 2449494122 ps
CPU time 71.44 seconds
Started Mar 19 12:44:54 PM PDT 24
Finished Mar 19 12:46:05 PM PDT 24
Peak memory 200428 kb
Host smart-1a297ba8-0402-4335-a803-bd91bcf127e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1624211350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1624211350
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.453561425
Short name T282
Test name
Test status
Simulation time 9913876398 ps
CPU time 141.24 seconds
Started Mar 19 12:44:33 PM PDT 24
Finished Mar 19 12:46:55 PM PDT 24
Peak memory 200460 kb
Host smart-5ecd0e97-5467-4872-ac5b-ba6639e05f6d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453561425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.453561425
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3318578315
Short name T509
Test name
Test status
Simulation time 593342075 ps
CPU time 11.53 seconds
Started Mar 19 12:44:38 PM PDT 24
Finished Mar 19 12:44:49 PM PDT 24
Peak memory 200416 kb
Host smart-c4b5933d-17b6-438a-96d8-c4202dd79150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318578315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3318578315
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3333575416
Short name T38
Test name
Test status
Simulation time 55418264 ps
CPU time 0.86 seconds
Started Mar 19 12:44:36 PM PDT 24
Finished Mar 19 12:44:37 PM PDT 24
Peak memory 218836 kb
Host smart-e62feba5-ddcc-44ac-98d5-34e0af73e491
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333575416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3333575416
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.1674133769
Short name T259
Test name
Test status
Simulation time 132811714 ps
CPU time 2.24 seconds
Started Mar 19 12:44:41 PM PDT 24
Finished Mar 19 12:44:43 PM PDT 24
Peak memory 200408 kb
Host smart-9b667198-9061-4581-8d7c-6a72f118d46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674133769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1674133769
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.1990255200
Short name T592
Test name
Test status
Simulation time 64863766107 ps
CPU time 1197.94 seconds
Started Mar 19 12:44:41 PM PDT 24
Finished Mar 19 01:04:39 PM PDT 24
Peak memory 230160 kb
Host smart-575965d3-c9a3-470c-97ca-8be5bfd8b39b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990255200 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.1990255200
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.3475995540
Short name T59
Test name
Test status
Simulation time 44757885 ps
CPU time 1.11 seconds
Started Mar 19 12:44:36 PM PDT 24
Finished Mar 19 12:44:37 PM PDT 24
Peak memory 199464 kb
Host smart-a12a056e-b17b-446e-9fd8-4b8c9efcd8e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475995540 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.3475995540
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.1722352789
Short name T254
Test name
Test status
Simulation time 120019398555 ps
CPU time 511.88 seconds
Started Mar 19 12:44:38 PM PDT 24
Finished Mar 19 12:53:10 PM PDT 24
Peak memory 200432 kb
Host smart-0f026202-21a3-4172-bced-280a366d5e30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722352789 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.1722352789
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_alert_test.161780009
Short name T195
Test name
Test status
Simulation time 11419173 ps
CPU time 0.61 seconds
Started Mar 19 12:45:53 PM PDT 24
Finished Mar 19 12:45:54 PM PDT 24
Peak memory 192728 kb
Host smart-516b7706-4f07-42a5-a882-2cde8db342a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161780009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.161780009
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.341939336
Short name T348
Test name
Test status
Simulation time 3937586295 ps
CPU time 53.64 seconds
Started Mar 19 12:44:35 PM PDT 24
Finished Mar 19 12:45:29 PM PDT 24
Peak memory 231160 kb
Host smart-83c7b9a1-1e98-4c48-a7ff-c771ca5a4229
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=341939336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.341939336
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2307418438
Short name T216
Test name
Test status
Simulation time 464085472 ps
CPU time 11.46 seconds
Started Mar 19 12:44:47 PM PDT 24
Finished Mar 19 12:44:59 PM PDT 24
Peak memory 200372 kb
Host smart-a1e29da6-13f9-4044-8180-d77421944107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307418438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2307418438
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.379980264
Short name T47
Test name
Test status
Simulation time 1670101943 ps
CPU time 68.77 seconds
Started Mar 19 12:44:37 PM PDT 24
Finished Mar 19 12:45:46 PM PDT 24
Peak memory 200424 kb
Host smart-9223fc07-174e-462a-8c88-370bd674808e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=379980264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.379980264
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.811919687
Short name T293
Test name
Test status
Simulation time 9272633598 ps
CPU time 133.14 seconds
Started Mar 19 12:44:48 PM PDT 24
Finished Mar 19 12:47:02 PM PDT 24
Peak memory 200456 kb
Host smart-aaf6e44b-d2bf-4a6c-9ddc-a1e5cbbdf598
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811919687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.811919687
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2270484100
Short name T269
Test name
Test status
Simulation time 20078427275 ps
CPU time 139.95 seconds
Started Mar 19 12:44:45 PM PDT 24
Finished Mar 19 12:47:05 PM PDT 24
Peak memory 200400 kb
Host smart-e2922ea7-d15b-423a-9d46-b128f8940e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270484100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2270484100
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1447017612
Short name T35
Test name
Test status
Simulation time 89090559 ps
CPU time 0.8 seconds
Started Mar 19 12:44:37 PM PDT 24
Finished Mar 19 12:44:38 PM PDT 24
Peak memory 218756 kb
Host smart-7da4db2d-9a23-42d1-9e33-a683420141ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447017612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1447017612
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.860602944
Short name T423
Test name
Test status
Simulation time 62304472 ps
CPU time 1.39 seconds
Started Mar 19 12:44:40 PM PDT 24
Finished Mar 19 12:44:41 PM PDT 24
Peak memory 200408 kb
Host smart-01c4e7d2-a75d-4b8f-8637-aeb4e689fc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860602944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.860602944
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.4166394874
Short name T173
Test name
Test status
Simulation time 89500074247 ps
CPU time 417.41 seconds
Started Mar 19 12:44:46 PM PDT 24
Finished Mar 19 12:51:44 PM PDT 24
Peak memory 216036 kb
Host smart-b78a0b4e-8134-422d-834e-2667615a6649
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166394874 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.4166394874
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.1491164598
Short name T201
Test name
Test status
Simulation time 105600916 ps
CPU time 1.23 seconds
Started Mar 19 12:44:38 PM PDT 24
Finished Mar 19 12:44:40 PM PDT 24
Peak memory 200304 kb
Host smart-f9e3d685-4bb1-4033-8682-9494f26ed81b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491164598 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.1491164598
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.961142302
Short name T8
Test name
Test status
Simulation time 47428236623 ps
CPU time 459.35 seconds
Started Mar 19 12:44:36 PM PDT 24
Finished Mar 19 12:52:16 PM PDT 24
Peak memory 200352 kb
Host smart-b3f302f4-09a1-4d53-89bd-317e48b3c749
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961142302 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.961142302
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.4147867082
Short name T432
Test name
Test status
Simulation time 1611658773 ps
CPU time 61.51 seconds
Started Mar 19 12:46:07 PM PDT 24
Finished Mar 19 12:47:09 PM PDT 24
Peak memory 199656 kb
Host smart-5bf3d7a0-f4d4-481c-a765-01df39e07685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147867082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.4147867082
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3676598040
Short name T392
Test name
Test status
Simulation time 25201174 ps
CPU time 0.57 seconds
Started Mar 19 12:44:50 PM PDT 24
Finished Mar 19 12:44:51 PM PDT 24
Peak memory 195504 kb
Host smart-47651baa-a81a-4436-aa37-65169a65c65c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676598040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3676598040
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3479957785
Short name T262
Test name
Test status
Simulation time 491697263 ps
CPU time 16.34 seconds
Started Mar 19 12:44:54 PM PDT 24
Finished Mar 19 12:45:10 PM PDT 24
Peak memory 208560 kb
Host smart-26912ea7-de12-4074-bfb5-91e17f516b13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3479957785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3479957785
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.3441884408
Short name T177
Test name
Test status
Simulation time 456720659 ps
CPU time 7.66 seconds
Started Mar 19 12:44:50 PM PDT 24
Finished Mar 19 12:44:58 PM PDT 24
Peak memory 200372 kb
Host smart-f0f9e68e-b978-444c-9854-81f29821152b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441884408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3441884408
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.2010327930
Short name T537
Test name
Test status
Simulation time 11095939801 ps
CPU time 62.74 seconds
Started Mar 19 12:44:45 PM PDT 24
Finished Mar 19 12:45:48 PM PDT 24
Peak memory 200396 kb
Host smart-6bd86da1-f944-4837-ab6b-07306fbf5a71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2010327930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2010327930
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.2694700602
Short name T590
Test name
Test status
Simulation time 43312420847 ps
CPU time 149.73 seconds
Started Mar 19 12:44:51 PM PDT 24
Finished Mar 19 12:47:22 PM PDT 24
Peak memory 200500 kb
Host smart-ad6de8c5-518a-40b3-ba06-4c3663d8ad94
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694700602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2694700602
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.2390426600
Short name T358
Test name
Test status
Simulation time 9356283669 ps
CPU time 65.07 seconds
Started Mar 19 12:44:54 PM PDT 24
Finished Mar 19 12:45:59 PM PDT 24
Peak memory 200496 kb
Host smart-b3bba638-0814-46c0-b7af-7ad0ea79257a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390426600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2390426600
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.2295516864
Short name T144
Test name
Test status
Simulation time 111832643 ps
CPU time 1.22 seconds
Started Mar 19 12:44:53 PM PDT 24
Finished Mar 19 12:44:54 PM PDT 24
Peak memory 200396 kb
Host smart-4e5b7b1d-4a7e-4d43-8d04-f1ec8415b3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295516864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.2295516864
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3804511017
Short name T27
Test name
Test status
Simulation time 61804061213 ps
CPU time 1149.45 seconds
Started Mar 19 12:45:03 PM PDT 24
Finished Mar 19 01:04:13 PM PDT 24
Peak memory 200476 kb
Host smart-2e6eba92-2ecb-47ad-ab5a-3a1d4b2140cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804511017 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3804511017
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.3871605983
Short name T550
Test name
Test status
Simulation time 170246669 ps
CPU time 1.02 seconds
Started Mar 19 12:44:46 PM PDT 24
Finished Mar 19 12:44:47 PM PDT 24
Peak memory 199424 kb
Host smart-ad6d99dd-19db-43d4-8c6c-3aec52c69d91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871605983 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.3871605983
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.657211397
Short name T318
Test name
Test status
Simulation time 330639799079 ps
CPU time 416.16 seconds
Started Mar 19 12:44:59 PM PDT 24
Finished Mar 19 12:51:56 PM PDT 24
Peak memory 200380 kb
Host smart-a3f09b7f-a829-44b1-bb01-6bd6e8949a48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657211397 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.657211397
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2591297499
Short name T298
Test name
Test status
Simulation time 1583508213 ps
CPU time 18.79 seconds
Started Mar 19 12:44:54 PM PDT 24
Finished Mar 19 12:45:13 PM PDT 24
Peak memory 200420 kb
Host smart-40eaac87-43d4-42be-bef4-91ce53f6c05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591297499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2591297499
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/102.hmac_stress_all_with_rand_reset.1059581848
Short name T76
Test name
Test status
Simulation time 51896691492 ps
CPU time 2307.44 seconds
Started Mar 19 12:46:33 PM PDT 24
Finished Mar 19 01:25:01 PM PDT 24
Peak memory 265616 kb
Host smart-f6e822e9-3848-4362-a7bf-aa2cc725a38d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1059581848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.hmac_stress_all_with_rand_reset.1059581848
Directory /workspace/102.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3758382101
Short name T250
Test name
Test status
Simulation time 11395058 ps
CPU time 0.58 seconds
Started Mar 19 12:44:50 PM PDT 24
Finished Mar 19 12:44:51 PM PDT 24
Peak memory 194828 kb
Host smart-32873161-1b0f-484f-9a03-7dceb071b788
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758382101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3758382101
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2138214357
Short name T55
Test name
Test status
Simulation time 1988108986 ps
CPU time 19.07 seconds
Started Mar 19 12:44:45 PM PDT 24
Finished Mar 19 12:45:04 PM PDT 24
Peak memory 224988 kb
Host smart-d41c359b-5bf1-44c8-8f85-46329c782c51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2138214357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2138214357
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.79257328
Short name T305
Test name
Test status
Simulation time 3899748368 ps
CPU time 42.51 seconds
Started Mar 19 12:44:59 PM PDT 24
Finished Mar 19 12:45:42 PM PDT 24
Peak memory 200484 kb
Host smart-7575f654-797f-41e1-89d0-93c0714ac732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79257328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.79257328
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1802613754
Short name T207
Test name
Test status
Simulation time 2622830978 ps
CPU time 141.86 seconds
Started Mar 19 12:45:06 PM PDT 24
Finished Mar 19 12:47:28 PM PDT 24
Peak memory 200552 kb
Host smart-f797932e-8f3c-4973-a00d-7676ec2b9d1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1802613754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1802613754
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1025774959
Short name T412
Test name
Test status
Simulation time 1713839081 ps
CPU time 93.82 seconds
Started Mar 19 12:44:57 PM PDT 24
Finished Mar 19 12:46:31 PM PDT 24
Peak memory 200396 kb
Host smart-587f4b89-ae30-4b47-bba6-fa02692a35cf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025774959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1025774959
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2705173201
Short name T566
Test name
Test status
Simulation time 9578348491 ps
CPU time 127.9 seconds
Started Mar 19 12:44:52 PM PDT 24
Finished Mar 19 12:47:00 PM PDT 24
Peak memory 200468 kb
Host smart-60522f7d-3806-4b1c-83f9-83c74c74d728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705173201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2705173201
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.3973633682
Short name T130
Test name
Test status
Simulation time 163111065 ps
CPU time 5.39 seconds
Started Mar 19 12:44:52 PM PDT 24
Finished Mar 19 12:44:58 PM PDT 24
Peak memory 200192 kb
Host smart-c7321db0-b577-4587-b5de-4ef9f43b61ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973633682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3973633682
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.1442430417
Short name T92
Test name
Test status
Simulation time 25065440678 ps
CPU time 348.99 seconds
Started Mar 19 12:44:50 PM PDT 24
Finished Mar 19 12:50:40 PM PDT 24
Peak memory 229092 kb
Host smart-74111937-8458-48c9-bb69-dd97f317848c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442430417 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1442430417
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.3420167688
Short name T335
Test name
Test status
Simulation time 147488664 ps
CPU time 0.98 seconds
Started Mar 19 12:44:52 PM PDT 24
Finished Mar 19 12:44:53 PM PDT 24
Peak memory 198356 kb
Host smart-61466e92-ec62-4f3d-bdc8-04b9a40b9d19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420167688 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.3420167688
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.790261354
Short name T154
Test name
Test status
Simulation time 28242451206 ps
CPU time 492.58 seconds
Started Mar 19 12:44:55 PM PDT 24
Finished Mar 19 12:53:08 PM PDT 24
Peak memory 200404 kb
Host smart-6f301fc0-e4f8-4c7f-92fa-06099d66313c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790261354 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.790261354
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.431344264
Short name T67
Test name
Test status
Simulation time 13790128354 ps
CPU time 50.07 seconds
Started Mar 19 12:44:58 PM PDT 24
Finished Mar 19 12:45:48 PM PDT 24
Peak memory 200484 kb
Host smart-a635f926-7b24-46f5-855e-30405be95948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431344264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.431344264
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/110.hmac_stress_all_with_rand_reset.2632535741
Short name T523
Test name
Test status
Simulation time 246508334914 ps
CPU time 953.16 seconds
Started Mar 19 12:46:36 PM PDT 24
Finished Mar 19 01:02:30 PM PDT 24
Peak memory 225108 kb
Host smart-b962efd9-ef8b-4c64-ae6e-22e94d4aaeff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2632535741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.hmac_stress_all_with_rand_reset.2632535741
Directory /workspace/110.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/119.hmac_stress_all_with_rand_reset.2682488948
Short name T28
Test name
Test status
Simulation time 62829821140 ps
CPU time 2545.46 seconds
Started Mar 19 12:46:41 PM PDT 24
Finished Mar 19 01:29:07 PM PDT 24
Peak memory 225080 kb
Host smart-2fcb4023-4f8f-456f-a812-7d4b9b218e70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2682488948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.hmac_stress_all_with_rand_reset.2682488948
Directory /workspace/119.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.751298474
Short name T514
Test name
Test status
Simulation time 36179608 ps
CPU time 0.6 seconds
Started Mar 19 12:45:03 PM PDT 24
Finished Mar 19 12:45:04 PM PDT 24
Peak memory 195892 kb
Host smart-a41b979d-e84d-4942-89cc-21f402d07a0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751298474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.751298474
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3506507763
Short name T291
Test name
Test status
Simulation time 11717398036 ps
CPU time 24.97 seconds
Started Mar 19 12:45:02 PM PDT 24
Finished Mar 19 12:45:27 PM PDT 24
Peak memory 208608 kb
Host smart-12791d18-f7e4-4565-a247-916d11ea7c44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3506507763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3506507763
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1718224893
Short name T422
Test name
Test status
Simulation time 195200977 ps
CPU time 9.64 seconds
Started Mar 19 12:44:53 PM PDT 24
Finished Mar 19 12:45:03 PM PDT 24
Peak memory 200372 kb
Host smart-69bca941-6c8d-4a4c-b296-9461ffe34a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718224893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1718224893
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.147327780
Short name T549
Test name
Test status
Simulation time 659234032 ps
CPU time 37.05 seconds
Started Mar 19 12:44:46 PM PDT 24
Finished Mar 19 12:45:24 PM PDT 24
Peak memory 200412 kb
Host smart-ede25c6a-3715-493c-973b-8d6e1c1f1394
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=147327780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.147327780
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1217155350
Short name T300
Test name
Test status
Simulation time 2277675876 ps
CPU time 118.98 seconds
Started Mar 19 12:44:57 PM PDT 24
Finished Mar 19 12:46:56 PM PDT 24
Peak memory 200472 kb
Host smart-614223c7-a3bb-4ea3-bf08-c99ff805f15d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217155350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1217155350
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1691619289
Short name T127
Test name
Test status
Simulation time 14302167577 ps
CPU time 65.74 seconds
Started Mar 19 12:44:51 PM PDT 24
Finished Mar 19 12:45:58 PM PDT 24
Peak memory 200444 kb
Host smart-80725c56-5944-4c90-a34f-fffab07ab6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691619289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1691619289
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.969126430
Short name T223
Test name
Test status
Simulation time 259114137 ps
CPU time 4.5 seconds
Started Mar 19 12:44:52 PM PDT 24
Finished Mar 19 12:44:57 PM PDT 24
Peak memory 200372 kb
Host smart-3924c3e3-5dcd-41d7-ba27-2437f451ab4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969126430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.969126430
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.4086279065
Short name T419
Test name
Test status
Simulation time 1444543612 ps
CPU time 45.56 seconds
Started Mar 19 12:45:04 PM PDT 24
Finished Mar 19 12:45:49 PM PDT 24
Peak memory 200424 kb
Host smart-df616c9d-a5a0-4e9e-8b70-731441585d3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086279065 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.4086279065
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.4137891280
Short name T377
Test name
Test status
Simulation time 290543612 ps
CPU time 1.32 seconds
Started Mar 19 12:45:03 PM PDT 24
Finished Mar 19 12:45:04 PM PDT 24
Peak memory 200364 kb
Host smart-c41b704d-e009-43be-812b-25a2f6c2fc0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137891280 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.4137891280
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.1536803464
Short name T176
Test name
Test status
Simulation time 54876917197 ps
CPU time 492.45 seconds
Started Mar 19 12:44:59 PM PDT 24
Finished Mar 19 12:53:11 PM PDT 24
Peak memory 200440 kb
Host smart-8cede05e-5d25-41c0-a925-49c6e9d83fc4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536803464 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.1536803464
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.209529740
Short name T143
Test name
Test status
Simulation time 6667114063 ps
CPU time 8.39 seconds
Started Mar 19 12:45:01 PM PDT 24
Finished Mar 19 12:45:10 PM PDT 24
Peak memory 200500 kb
Host smart-ea916ccc-c833-4c82-874f-c2e45ba80701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209529740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.209529740
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.593423777
Short name T421
Test name
Test status
Simulation time 22706775 ps
CPU time 0.62 seconds
Started Mar 19 12:45:01 PM PDT 24
Finished Mar 19 12:45:01 PM PDT 24
Peak memory 194848 kb
Host smart-86d86e31-c43d-40db-b539-4f62db87f402
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593423777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.593423777
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3251049724
Short name T167
Test name
Test status
Simulation time 60387757 ps
CPU time 2.71 seconds
Started Mar 19 12:44:57 PM PDT 24
Finished Mar 19 12:45:00 PM PDT 24
Peak memory 200320 kb
Host smart-05679177-350c-4911-9de5-a5bcd18198f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3251049724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3251049724
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1427214703
Short name T113
Test name
Test status
Simulation time 7442581731 ps
CPU time 48.44 seconds
Started Mar 19 12:44:52 PM PDT 24
Finished Mar 19 12:45:41 PM PDT 24
Peak memory 200416 kb
Host smart-e12a36d9-e75f-404b-a5dd-15e71deb6044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427214703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1427214703
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.500185015
Short name T385
Test name
Test status
Simulation time 1950348069 ps
CPU time 29.12 seconds
Started Mar 19 12:45:02 PM PDT 24
Finished Mar 19 12:45:31 PM PDT 24
Peak memory 200428 kb
Host smart-09efb1cb-adb1-462c-a616-42f7aad75102
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=500185015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.500185015
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.843000168
Short name T581
Test name
Test status
Simulation time 117319764920 ps
CPU time 126.28 seconds
Started Mar 19 12:44:55 PM PDT 24
Finished Mar 19 12:47:01 PM PDT 24
Peak memory 200476 kb
Host smart-742acad3-8ab7-413c-b35c-f914d0096fbc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843000168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.843000168
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.3121725572
Short name T194
Test name
Test status
Simulation time 6514980331 ps
CPU time 61.39 seconds
Started Mar 19 12:45:04 PM PDT 24
Finished Mar 19 12:46:05 PM PDT 24
Peak memory 200428 kb
Host smart-2cda23b4-fc7e-4ba4-b10c-6fa091a6a1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121725572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.3121725572
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_stress_all.1322402153
Short name T189
Test name
Test status
Simulation time 16932648328 ps
CPU time 495.43 seconds
Started Mar 19 12:45:07 PM PDT 24
Finished Mar 19 12:53:22 PM PDT 24
Peak memory 200452 kb
Host smart-ed2a427d-e261-49b8-a398-f9b38eb9bfcc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322402153 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1322402153
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.3833133789
Short name T150
Test name
Test status
Simulation time 160866515 ps
CPU time 1.02 seconds
Started Mar 19 12:45:01 PM PDT 24
Finished Mar 19 12:45:03 PM PDT 24
Peak memory 199576 kb
Host smart-bf3969f7-767c-42a8-a28c-172827cb7d1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833133789 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.3833133789
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.2926409961
Short name T237
Test name
Test status
Simulation time 26421468900 ps
CPU time 481.62 seconds
Started Mar 19 12:44:52 PM PDT 24
Finished Mar 19 12:52:54 PM PDT 24
Peak memory 200424 kb
Host smart-fcea642a-2ba8-43b0-a01d-0dfec4746532
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926409961 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.2926409961
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.4160931586
Short name T307
Test name
Test status
Simulation time 4719990511 ps
CPU time 25.05 seconds
Started Mar 19 12:45:06 PM PDT 24
Finished Mar 19 12:45:31 PM PDT 24
Peak memory 200504 kb
Host smart-868db605-74f2-4be2-a626-c5cd23308ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160931586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.4160931586
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.3506640168
Short name T174
Test name
Test status
Simulation time 12758972 ps
CPU time 0.6 seconds
Started Mar 19 12:44:58 PM PDT 24
Finished Mar 19 12:44:59 PM PDT 24
Peak memory 195744 kb
Host smart-eb76f880-bd94-4c98-b62c-b6f8e0136590
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506640168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.3506640168
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1935206163
Short name T255
Test name
Test status
Simulation time 4547405605 ps
CPU time 41.48 seconds
Started Mar 19 12:45:02 PM PDT 24
Finished Mar 19 12:45:44 PM PDT 24
Peak memory 208672 kb
Host smart-2613a10d-e477-4eb8-9cd9-ee236ee23c81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1935206163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1935206163
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.1903178803
Short name T532
Test name
Test status
Simulation time 4657729521 ps
CPU time 50.87 seconds
Started Mar 19 12:45:03 PM PDT 24
Finished Mar 19 12:45:54 PM PDT 24
Peak memory 200452 kb
Host smart-a12a77c6-26ea-420e-9886-e51e4898ac2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903178803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.1903178803
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3991001170
Short name T381
Test name
Test status
Simulation time 8111162295 ps
CPU time 119.07 seconds
Started Mar 19 12:44:59 PM PDT 24
Finished Mar 19 12:46:58 PM PDT 24
Peak memory 200464 kb
Host smart-0c8db7cb-0ede-4b6f-a56c-2c3b129bb835
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3991001170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3991001170
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.1622239933
Short name T586
Test name
Test status
Simulation time 23985524432 ps
CPU time 47.12 seconds
Started Mar 19 12:45:01 PM PDT 24
Finished Mar 19 12:45:49 PM PDT 24
Peak memory 200452 kb
Host smart-9fb6726e-6c35-46cf-bc45-fb985b128253
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622239933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1622239933
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1763022399
Short name T436
Test name
Test status
Simulation time 1829104467 ps
CPU time 34.03 seconds
Started Mar 19 12:45:01 PM PDT 24
Finished Mar 19 12:45:35 PM PDT 24
Peak memory 200384 kb
Host smart-cb8f47ed-3085-48b5-bdaa-649ba194d1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763022399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1763022399
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3758136993
Short name T496
Test name
Test status
Simulation time 184138602 ps
CPU time 5.12 seconds
Started Mar 19 12:45:06 PM PDT 24
Finished Mar 19 12:45:11 PM PDT 24
Peak memory 200372 kb
Host smart-4774df07-7be4-4728-936e-bcec7f0eabd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758136993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3758136993
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.1447682022
Short name T30
Test name
Test status
Simulation time 60558797243 ps
CPU time 1086.93 seconds
Started Mar 19 12:44:58 PM PDT 24
Finished Mar 19 01:03:06 PM PDT 24
Peak memory 213740 kb
Host smart-15a89a3d-1ccb-4c8b-9d91-f157dbcb7974
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447682022 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.1447682022
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_stress_all_with_rand_reset.3556739969
Short name T75
Test name
Test status
Simulation time 22000070614 ps
CPU time 116.47 seconds
Started Mar 19 12:44:58 PM PDT 24
Finished Mar 19 12:46:55 PM PDT 24
Peak memory 208768 kb
Host smart-ab4dd116-c866-4303-b9b6-34054f5c5a90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3556739969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all_with_rand_reset.3556739969
Directory /workspace/14.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.1624013840
Short name T43
Test name
Test status
Simulation time 202676702 ps
CPU time 1.11 seconds
Started Mar 19 12:45:04 PM PDT 24
Finished Mar 19 12:45:05 PM PDT 24
Peak memory 200364 kb
Host smart-fd3f3aa1-d6ea-4d73-a36d-32f779b8a559
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624013840 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.1624013840
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.1427221998
Short name T81
Test name
Test status
Simulation time 15647712749 ps
CPU time 422.39 seconds
Started Mar 19 12:45:04 PM PDT 24
Finished Mar 19 12:52:06 PM PDT 24
Peak memory 200384 kb
Host smart-3891ca59-f3d5-4360-a325-8bf5798b2dec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427221998 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.1427221998
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3772114703
Short name T538
Test name
Test status
Simulation time 3835024573 ps
CPU time 69.84 seconds
Started Mar 19 12:45:05 PM PDT 24
Finished Mar 19 12:46:15 PM PDT 24
Peak memory 200460 kb
Host smart-36d9f068-4587-40db-bb56-0530519b1262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772114703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3772114703
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.3259099849
Short name T424
Test name
Test status
Simulation time 17586349 ps
CPU time 0.61 seconds
Started Mar 19 12:45:06 PM PDT 24
Finished Mar 19 12:45:07 PM PDT 24
Peak memory 195732 kb
Host smart-80435003-e2b6-4470-bed5-142d6a350d7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259099849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3259099849
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3032648336
Short name T78
Test name
Test status
Simulation time 5777568328 ps
CPU time 20.04 seconds
Started Mar 19 12:45:02 PM PDT 24
Finished Mar 19 12:45:23 PM PDT 24
Peak memory 215836 kb
Host smart-33412358-4abb-4955-a843-fa7a7b647cb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3032648336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3032648336
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.363361605
Short name T473
Test name
Test status
Simulation time 3377522625 ps
CPU time 44.61 seconds
Started Mar 19 12:45:04 PM PDT 24
Finished Mar 19 12:45:49 PM PDT 24
Peak memory 200512 kb
Host smart-f8b8e8f0-8825-4251-9b8d-c6997e095208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363361605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.363361605
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.691035759
Short name T323
Test name
Test status
Simulation time 6250852329 ps
CPU time 181.18 seconds
Started Mar 19 12:45:06 PM PDT 24
Finished Mar 19 12:48:07 PM PDT 24
Peak memory 200480 kb
Host smart-d7902c7c-a43b-4d8a-90c8-d455c79321b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=691035759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.691035759
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.1316050646
Short name T427
Test name
Test status
Simulation time 113472140093 ps
CPU time 204.73 seconds
Started Mar 19 12:45:02 PM PDT 24
Finished Mar 19 12:48:27 PM PDT 24
Peak memory 200484 kb
Host smart-b2720bdf-cb38-4ca6-8271-8dbbe54b139f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316050646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1316050646
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3116332115
Short name T408
Test name
Test status
Simulation time 11434683319 ps
CPU time 129.84 seconds
Started Mar 19 12:45:04 PM PDT 24
Finished Mar 19 12:47:14 PM PDT 24
Peak memory 200404 kb
Host smart-94ac526c-245f-4744-a087-1fadd44ddb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116332115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3116332115
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2022090468
Short name T324
Test name
Test status
Simulation time 237121149 ps
CPU time 4.29 seconds
Started Mar 19 12:45:05 PM PDT 24
Finished Mar 19 12:45:10 PM PDT 24
Peak memory 200392 kb
Host smart-1638802c-20a8-43f3-a137-53f16e6d2687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022090468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2022090468
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1089090432
Short name T85
Test name
Test status
Simulation time 113916016345 ps
CPU time 303.8 seconds
Started Mar 19 12:45:07 PM PDT 24
Finished Mar 19 12:50:11 PM PDT 24
Peak memory 200460 kb
Host smart-a71e4242-d24c-4576-8349-2cff2afd46ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089090432 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1089090432
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.324045806
Short name T378
Test name
Test status
Simulation time 64413584 ps
CPU time 1.08 seconds
Started Mar 19 12:45:01 PM PDT 24
Finished Mar 19 12:45:03 PM PDT 24
Peak memory 199776 kb
Host smart-5bacc51e-0dac-4c99-bceb-610b90e32d6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324045806 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_test_hmac_vectors.324045806
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.2029827426
Short name T261
Test name
Test status
Simulation time 104300905929 ps
CPU time 488.81 seconds
Started Mar 19 12:45:09 PM PDT 24
Finished Mar 19 12:53:18 PM PDT 24
Peak memory 200440 kb
Host smart-3cdf0bc6-98e9-4a6f-8ebb-6c7ac265fab5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029827426 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.2029827426
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.931780703
Short name T125
Test name
Test status
Simulation time 4526664594 ps
CPU time 81.8 seconds
Started Mar 19 12:45:05 PM PDT 24
Finished Mar 19 12:46:27 PM PDT 24
Peak memory 200512 kb
Host smart-99d05d22-7cf3-4277-ba80-09051f1fe3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931780703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.931780703
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3340820208
Short name T292
Test name
Test status
Simulation time 46758352 ps
CPU time 0.61 seconds
Started Mar 19 12:45:08 PM PDT 24
Finished Mar 19 12:45:09 PM PDT 24
Peak memory 195884 kb
Host smart-78a81646-bc3a-49aa-91e6-e541e2ed361c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340820208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3340820208
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1735423950
Short name T354
Test name
Test status
Simulation time 9524859236 ps
CPU time 31.03 seconds
Started Mar 19 12:45:06 PM PDT 24
Finished Mar 19 12:45:37 PM PDT 24
Peak memory 216896 kb
Host smart-3779e7c5-0a49-4bc9-8b28-275c88b4c532
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1735423950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1735423950
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.4140552953
Short name T525
Test name
Test status
Simulation time 233949096 ps
CPU time 11.89 seconds
Started Mar 19 12:45:06 PM PDT 24
Finished Mar 19 12:45:18 PM PDT 24
Peak memory 200400 kb
Host smart-39c44cfb-d6d4-4d6f-a414-dc081c028c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140552953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.4140552953
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_error.3475799079
Short name T494
Test name
Test status
Simulation time 7719811229 ps
CPU time 136.93 seconds
Started Mar 19 12:45:12 PM PDT 24
Finished Mar 19 12:47:29 PM PDT 24
Peak memory 200464 kb
Host smart-b5b54be9-ffc1-4cc8-9eea-59112ad2f427
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475799079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3475799079
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2633304366
Short name T386
Test name
Test status
Simulation time 2085860588 ps
CPU time 35.15 seconds
Started Mar 19 12:45:04 PM PDT 24
Finished Mar 19 12:45:40 PM PDT 24
Peak memory 200420 kb
Host smart-b97b82b1-03c1-4f24-9305-fafd4eb12327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633304366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2633304366
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.291396589
Short name T4
Test name
Test status
Simulation time 291145165 ps
CPU time 3.47 seconds
Started Mar 19 12:45:15 PM PDT 24
Finished Mar 19 12:45:18 PM PDT 24
Peak memory 200368 kb
Host smart-b6473d36-0d94-4e25-99a7-e9af6281bbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291396589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.291396589
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.518512672
Short name T51
Test name
Test status
Simulation time 26492077649 ps
CPU time 1298.54 seconds
Started Mar 19 12:45:07 PM PDT 24
Finished Mar 19 01:06:46 PM PDT 24
Peak memory 216936 kb
Host smart-519eeced-26a5-44d9-b4b4-a7cb73ab261b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518512672 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.518512672
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.2073220682
Short name T450
Test name
Test status
Simulation time 100158053 ps
CPU time 1.12 seconds
Started Mar 19 12:45:17 PM PDT 24
Finished Mar 19 12:45:19 PM PDT 24
Peak memory 200040 kb
Host smart-d1796420-1c28-4f7d-8cea-e549e40b30a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073220682 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.2073220682
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.2765110262
Short name T478
Test name
Test status
Simulation time 16544721929 ps
CPU time 454.67 seconds
Started Mar 19 12:45:12 PM PDT 24
Finished Mar 19 12:52:47 PM PDT 24
Peak memory 200436 kb
Host smart-e01dfa76-ec7f-45d2-b73c-fb7348c51746
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765110262 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.2765110262
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2014287919
Short name T370
Test name
Test status
Simulation time 1144829165 ps
CPU time 15.56 seconds
Started Mar 19 12:45:11 PM PDT 24
Finished Mar 19 12:45:27 PM PDT 24
Peak memory 200460 kb
Host smart-2b565fbb-5025-4c13-8920-2568d6b028d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014287919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2014287919
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/169.hmac_stress_all_with_rand_reset.836366860
Short name T72
Test name
Test status
Simulation time 19975832249 ps
CPU time 705.07 seconds
Started Mar 19 12:47:01 PM PDT 24
Finished Mar 19 12:58:46 PM PDT 24
Peak memory 234260 kb
Host smart-93cde7b5-a3c8-4ca2-bd3e-42dbb37d64a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=836366860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.hmac_stress_all_with_rand_reset.836366860
Directory /workspace/169.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3704176805
Short name T210
Test name
Test status
Simulation time 11975049 ps
CPU time 0.57 seconds
Started Mar 19 12:45:18 PM PDT 24
Finished Mar 19 12:45:19 PM PDT 24
Peak memory 194664 kb
Host smart-42383611-24a0-4548-9b32-a3ea28580c0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704176805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3704176805
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2758201334
Short name T578
Test name
Test status
Simulation time 2254838542 ps
CPU time 41.84 seconds
Started Mar 19 12:45:05 PM PDT 24
Finished Mar 19 12:45:47 PM PDT 24
Peak memory 217828 kb
Host smart-6f49f459-4fe0-416a-92d0-9380c7b7e3b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2758201334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2758201334
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2754882321
Short name T337
Test name
Test status
Simulation time 3660190189 ps
CPU time 39.19 seconds
Started Mar 19 12:45:06 PM PDT 24
Finished Mar 19 12:45:45 PM PDT 24
Peak memory 200488 kb
Host smart-8f9b935c-43e1-411f-bbb3-750d0207023e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754882321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2754882321
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2601302074
Short name T148
Test name
Test status
Simulation time 4109331000 ps
CPU time 103.01 seconds
Started Mar 19 12:45:06 PM PDT 24
Finished Mar 19 12:46:49 PM PDT 24
Peak memory 200440 kb
Host smart-e7c2f689-d598-416e-beb8-3706dd9c7d1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2601302074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2601302074
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.249406096
Short name T511
Test name
Test status
Simulation time 49063614936 ps
CPU time 191.96 seconds
Started Mar 19 12:45:08 PM PDT 24
Finished Mar 19 12:48:20 PM PDT 24
Peak memory 200500 kb
Host smart-087eb43c-57bb-4046-92d1-9d6b02de8ab8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249406096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.249406096
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.1468396783
Short name T443
Test name
Test status
Simulation time 241708598 ps
CPU time 5.33 seconds
Started Mar 19 12:45:07 PM PDT 24
Finished Mar 19 12:45:12 PM PDT 24
Peak memory 200416 kb
Host smart-c179267a-699d-459c-9307-5574c2ea72da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468396783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1468396783
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.254206939
Short name T528
Test name
Test status
Simulation time 1684904843 ps
CPU time 6.4 seconds
Started Mar 19 12:45:08 PM PDT 24
Finished Mar 19 12:45:14 PM PDT 24
Peak memory 200464 kb
Host smart-0c30ab3f-3e21-4d54-aaa8-16fca7358f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254206939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.254206939
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2782514301
Short name T277
Test name
Test status
Simulation time 125704356489 ps
CPU time 1422.28 seconds
Started Mar 19 12:45:16 PM PDT 24
Finished Mar 19 01:08:59 PM PDT 24
Peak memory 233276 kb
Host smart-8a57f75d-124a-4166-a92e-f1c4118b1b38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782514301 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2782514301
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.3713542925
Short name T208
Test name
Test status
Simulation time 82670364 ps
CPU time 1.06 seconds
Started Mar 19 12:45:21 PM PDT 24
Finished Mar 19 12:45:22 PM PDT 24
Peak memory 199928 kb
Host smart-ddaf7d75-cd19-4ab5-a3b4-c9b490a45624
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713542925 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.3713542925
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.3502557588
Short name T248
Test name
Test status
Simulation time 222155499210 ps
CPU time 501.38 seconds
Started Mar 19 12:45:21 PM PDT 24
Finished Mar 19 12:53:43 PM PDT 24
Peak memory 200388 kb
Host smart-87f77a87-b55f-4b34-9d77-e3005aa2cf5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502557588 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.3502557588
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3686412455
Short name T372
Test name
Test status
Simulation time 15241893271 ps
CPU time 110.77 seconds
Started Mar 19 12:45:05 PM PDT 24
Finished Mar 19 12:46:56 PM PDT 24
Peak memory 200508 kb
Host smart-0e7efe5b-2d5a-4594-916c-25f8d71b3fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686412455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3686412455
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/177.hmac_stress_all_with_rand_reset.214464666
Short name T11
Test name
Test status
Simulation time 228859450510 ps
CPU time 2305.69 seconds
Started Mar 19 12:46:55 PM PDT 24
Finished Mar 19 01:25:21 PM PDT 24
Peak memory 228120 kb
Host smart-47d2a22b-9b0e-4bc4-b59f-ddb05fd25ad4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=214464666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.hmac_stress_all_with_rand_reset.214464666
Directory /workspace/177.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2685911623
Short name T500
Test name
Test status
Simulation time 66185023 ps
CPU time 0.57 seconds
Started Mar 19 12:45:15 PM PDT 24
Finished Mar 19 12:45:16 PM PDT 24
Peak memory 195892 kb
Host smart-8a7bc8cd-5078-4d98-8097-3be29947b99a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685911623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2685911623
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.4260647333
Short name T585
Test name
Test status
Simulation time 1048902261 ps
CPU time 12.49 seconds
Started Mar 19 12:45:22 PM PDT 24
Finished Mar 19 12:45:35 PM PDT 24
Peak memory 248908 kb
Host smart-13157853-f6dd-488c-9f90-21ac399cec52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4260647333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.4260647333
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3790304962
Short name T263
Test name
Test status
Simulation time 1908629030 ps
CPU time 39.69 seconds
Started Mar 19 12:45:23 PM PDT 24
Finished Mar 19 12:46:08 PM PDT 24
Peak memory 200340 kb
Host smart-1de732e3-024f-4862-8dac-dfa0dc087ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790304962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3790304962
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2155795823
Short name T296
Test name
Test status
Simulation time 2201900359 ps
CPU time 20.8 seconds
Started Mar 19 12:45:18 PM PDT 24
Finished Mar 19 12:45:39 PM PDT 24
Peak memory 200504 kb
Host smart-f303fe3e-a048-4c24-b587-e53bafaab9d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2155795823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2155795823
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.301249067
Short name T531
Test name
Test status
Simulation time 85721887514 ps
CPU time 74.38 seconds
Started Mar 19 12:45:21 PM PDT 24
Finished Mar 19 12:46:35 PM PDT 24
Peak memory 200452 kb
Host smart-a7b78fa1-d1b7-48a8-b64a-314392202e90
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301249067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.301249067
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1991571724
Short name T83
Test name
Test status
Simulation time 4025320569 ps
CPU time 19.12 seconds
Started Mar 19 12:45:19 PM PDT 24
Finished Mar 19 12:45:38 PM PDT 24
Peak memory 200456 kb
Host smart-f31a1625-1a52-4af4-bfae-3b4068e03e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991571724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1991571724
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.817405843
Short name T393
Test name
Test status
Simulation time 85604718 ps
CPU time 1.7 seconds
Started Mar 19 12:45:18 PM PDT 24
Finished Mar 19 12:45:20 PM PDT 24
Peak memory 200380 kb
Host smart-a3291a75-6dec-4ba1-8ddd-e09bd964d33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817405843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.817405843
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.3827681140
Short name T571
Test name
Test status
Simulation time 173735719 ps
CPU time 1.34 seconds
Started Mar 19 12:45:23 PM PDT 24
Finished Mar 19 12:45:25 PM PDT 24
Peak memory 200384 kb
Host smart-3315f6e1-38df-4341-abcf-4a353f2d5347
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827681140 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.3827681140
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.3787727560
Short name T420
Test name
Test status
Simulation time 7436736811 ps
CPU time 425.13 seconds
Started Mar 19 12:45:22 PM PDT 24
Finished Mar 19 12:52:28 PM PDT 24
Peak memory 200380 kb
Host smart-0b9352c7-74a6-4ca4-8b39-75e70919972b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787727560 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.3787727560
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.352441851
Short name T134
Test name
Test status
Simulation time 2273118741 ps
CPU time 32.73 seconds
Started Mar 19 12:45:19 PM PDT 24
Finished Mar 19 12:45:53 PM PDT 24
Peak memory 200420 kb
Host smart-87023b2d-18f0-4071-839d-fd144c6e7506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352441851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.352441851
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.4245294
Short name T227
Test name
Test status
Simulation time 61146912 ps
CPU time 0.58 seconds
Started Mar 19 12:45:21 PM PDT 24
Finished Mar 19 12:45:22 PM PDT 24
Peak memory 195924 kb
Host smart-7298d531-395e-46e5-a7b6-82c592538cfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.4245294
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3323670446
Short name T582
Test name
Test status
Simulation time 11256602486 ps
CPU time 34.78 seconds
Started Mar 19 12:45:18 PM PDT 24
Finished Mar 19 12:45:54 PM PDT 24
Peak memory 208656 kb
Host smart-d534e464-12fb-40fb-a1c1-c9b4f6c861de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3323670446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3323670446
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.3289291392
Short name T516
Test name
Test status
Simulation time 10240962539 ps
CPU time 40.95 seconds
Started Mar 19 12:45:23 PM PDT 24
Finished Mar 19 12:46:04 PM PDT 24
Peak memory 200432 kb
Host smart-240d63cf-0500-4c9b-8b44-61a61ee77c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289291392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.3289291392
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3359149718
Short name T93
Test name
Test status
Simulation time 5110907302 ps
CPU time 74.4 seconds
Started Mar 19 12:45:15 PM PDT 24
Finished Mar 19 12:46:30 PM PDT 24
Peak memory 200496 kb
Host smart-7e46f346-fba9-4926-9226-ee466d477289
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3359149718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3359149718
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2187582524
Short name T526
Test name
Test status
Simulation time 13512566072 ps
CPU time 17.72 seconds
Started Mar 19 12:45:16 PM PDT 24
Finished Mar 19 12:45:34 PM PDT 24
Peak memory 200432 kb
Host smart-1370ae1b-8288-4b28-b99e-704e6491b355
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187582524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2187582524
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.4047220323
Short name T346
Test name
Test status
Simulation time 338259042 ps
CPU time 3.99 seconds
Started Mar 19 12:45:17 PM PDT 24
Finished Mar 19 12:45:21 PM PDT 24
Peak memory 200432 kb
Host smart-2b82f40a-0705-43df-bafe-4178a7ed92cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047220323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.4047220323
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.2239600724
Short name T146
Test name
Test status
Simulation time 693123596 ps
CPU time 3.38 seconds
Started Mar 19 12:45:23 PM PDT 24
Finished Mar 19 12:45:27 PM PDT 24
Peak memory 200416 kb
Host smart-4cea3cc0-4843-44a9-a5fc-c49df604bda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239600724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2239600724
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.307328514
Short name T342
Test name
Test status
Simulation time 165968918688 ps
CPU time 1618.17 seconds
Started Mar 19 12:45:21 PM PDT 24
Finished Mar 19 01:12:20 PM PDT 24
Peak memory 248516 kb
Host smart-14f878c0-c552-479a-bce4-48507c88f73e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307328514 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.307328514
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.2360890658
Short name T139
Test name
Test status
Simulation time 31796344 ps
CPU time 1.2 seconds
Started Mar 19 12:45:14 PM PDT 24
Finished Mar 19 12:45:16 PM PDT 24
Peak memory 200320 kb
Host smart-1dbf9c8f-0111-4296-b475-8b3f76a3704c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360890658 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.2360890658
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.2604532197
Short name T484
Test name
Test status
Simulation time 385259398652 ps
CPU time 406.85 seconds
Started Mar 19 12:45:18 PM PDT 24
Finished Mar 19 12:52:06 PM PDT 24
Peak memory 200376 kb
Host smart-215f2c4f-8fad-4228-981b-9b4e7608a09f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604532197 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.2604532197
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.4008829701
Short name T512
Test name
Test status
Simulation time 10750642558 ps
CPU time 97.54 seconds
Started Mar 19 12:45:27 PM PDT 24
Finished Mar 19 12:47:05 PM PDT 24
Peak memory 200504 kb
Host smart-d5b7d821-b5ad-45a4-a6f1-afdcf528badf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008829701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.4008829701
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2967130500
Short name T409
Test name
Test status
Simulation time 10489158 ps
CPU time 0.56 seconds
Started Mar 19 12:46:14 PM PDT 24
Finished Mar 19 12:46:14 PM PDT 24
Peak memory 194608 kb
Host smart-5cd094eb-6d39-4bd8-b399-d8158a68e5ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967130500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2967130500
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.4232278268
Short name T82
Test name
Test status
Simulation time 5891597027 ps
CPU time 59.3 seconds
Started Mar 19 12:44:39 PM PDT 24
Finished Mar 19 12:45:38 PM PDT 24
Peak memory 233304 kb
Host smart-0a156c56-d99a-4c33-84d8-08c646a06dd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4232278268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.4232278268
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1297833288
Short name T244
Test name
Test status
Simulation time 1213492557 ps
CPU time 20.95 seconds
Started Mar 19 12:44:42 PM PDT 24
Finished Mar 19 12:45:04 PM PDT 24
Peak memory 200372 kb
Host smart-3e53d42f-c89f-41e7-911d-5185d6596eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297833288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1297833288
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3385115459
Short name T357
Test name
Test status
Simulation time 8329300657 ps
CPU time 126.12 seconds
Started Mar 19 12:44:34 PM PDT 24
Finished Mar 19 12:46:40 PM PDT 24
Peak memory 200420 kb
Host smart-2d435a53-3a42-4c40-97cc-a96fda1697f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3385115459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3385115459
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.1912441247
Short name T486
Test name
Test status
Simulation time 113670169 ps
CPU time 2.57 seconds
Started Mar 19 12:44:35 PM PDT 24
Finished Mar 19 12:44:38 PM PDT 24
Peak memory 200204 kb
Host smart-ba0a8fc7-7bec-4d07-bd9e-d46a687ccf8a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912441247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.1912441247
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.2042610852
Short name T191
Test name
Test status
Simulation time 2633437571 ps
CPU time 47.24 seconds
Started Mar 19 12:46:11 PM PDT 24
Finished Mar 19 12:46:59 PM PDT 24
Peak memory 197908 kb
Host smart-015b9000-7a09-4ffe-8c68-9d32df7bf7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042610852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2042610852
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_smoke.174642864
Short name T158
Test name
Test status
Simulation time 265737456 ps
CPU time 2.33 seconds
Started Mar 19 12:44:44 PM PDT 24
Finished Mar 19 12:44:46 PM PDT 24
Peak memory 200364 kb
Host smart-9a533d7f-ba10-4ad9-9199-caa11e47ca6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174642864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.174642864
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.1005752075
Short name T594
Test name
Test status
Simulation time 78499863681 ps
CPU time 1086.48 seconds
Started Mar 19 12:44:50 PM PDT 24
Finished Mar 19 01:02:57 PM PDT 24
Peak memory 233132 kb
Host smart-70bb4e8c-16a8-41c5-91a1-f29d6455ace5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005752075 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.1005752075
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.294308902
Short name T449
Test name
Test status
Simulation time 255991866 ps
CPU time 1.35 seconds
Started Mar 19 12:46:11 PM PDT 24
Finished Mar 19 12:46:13 PM PDT 24
Peak memory 197604 kb
Host smart-c6e59649-8f4d-44ec-85a9-965f5af47a82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294308902 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.hmac_test_hmac_vectors.294308902
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.3187402052
Short name T487
Test name
Test status
Simulation time 15410514586 ps
CPU time 385.18 seconds
Started Mar 19 12:46:13 PM PDT 24
Finished Mar 19 12:52:38 PM PDT 24
Peak memory 200180 kb
Host smart-0a28f801-f9b2-4d3b-8a94-d82a0047b5fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187402052 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.3187402052
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2392009754
Short name T169
Test name
Test status
Simulation time 3225961833 ps
CPU time 76.04 seconds
Started Mar 19 12:45:00 PM PDT 24
Finished Mar 19 12:46:17 PM PDT 24
Peak memory 200396 kb
Host smart-1a7f421d-3a10-4cec-9364-7c004c0056c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392009754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2392009754
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.3725909671
Short name T355
Test name
Test status
Simulation time 36555942 ps
CPU time 0.59 seconds
Started Mar 19 12:45:21 PM PDT 24
Finished Mar 19 12:45:22 PM PDT 24
Peak memory 195936 kb
Host smart-b64b148a-b89a-4128-b8e6-6f8f8c55d320
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725909671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.3725909671
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2475987968
Short name T58
Test name
Test status
Simulation time 991421224 ps
CPU time 35.57 seconds
Started Mar 19 12:45:18 PM PDT 24
Finished Mar 19 12:45:54 PM PDT 24
Peak memory 208608 kb
Host smart-43ee27ca-e6e7-4108-b937-f6a30a22c91f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2475987968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2475987968
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2994768451
Short name T584
Test name
Test status
Simulation time 2221536900 ps
CPU time 47.87 seconds
Started Mar 19 12:45:20 PM PDT 24
Finished Mar 19 12:46:09 PM PDT 24
Peak memory 200500 kb
Host smart-2f3e398d-5631-4de6-9e2e-7001b5097f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994768451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2994768451
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.224921843
Short name T225
Test name
Test status
Simulation time 2614500539 ps
CPU time 55.09 seconds
Started Mar 19 12:45:21 PM PDT 24
Finished Mar 19 12:46:16 PM PDT 24
Peak memory 200428 kb
Host smart-0cf36154-41f7-4e96-ab74-4470eea6178c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=224921843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.224921843
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1365139293
Short name T517
Test name
Test status
Simulation time 14548810 ps
CPU time 0.65 seconds
Started Mar 19 12:45:15 PM PDT 24
Finished Mar 19 12:45:16 PM PDT 24
Peak memory 196808 kb
Host smart-adbeb7cd-de8d-45df-b090-7a36b0a165a0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365139293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1365139293
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.4126424877
Short name T558
Test name
Test status
Simulation time 1184494572 ps
CPU time 37.42 seconds
Started Mar 19 12:45:13 PM PDT 24
Finished Mar 19 12:45:51 PM PDT 24
Peak memory 200404 kb
Host smart-82d4db19-5e5e-4286-96f7-008133a9be45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126424877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.4126424877
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.180632327
Short name T206
Test name
Test status
Simulation time 101129662 ps
CPU time 3.15 seconds
Started Mar 19 12:45:17 PM PDT 24
Finished Mar 19 12:45:20 PM PDT 24
Peak memory 200452 kb
Host smart-9009f03d-f08f-4cf1-82fb-24f437010db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180632327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.180632327
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.1723706007
Short name T462
Test name
Test status
Simulation time 17350600806 ps
CPU time 179.65 seconds
Started Mar 19 12:45:20 PM PDT 24
Finished Mar 19 12:48:20 PM PDT 24
Peak memory 241404 kb
Host smart-1df4f834-ec57-423e-877c-c362c38084eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723706007 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1723706007
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.999676814
Short name T171
Test name
Test status
Simulation time 30398821 ps
CPU time 0.98 seconds
Started Mar 19 12:45:20 PM PDT 24
Finished Mar 19 12:45:21 PM PDT 24
Peak memory 199700 kb
Host smart-51d1d1e4-9d03-4bdb-aa6e-a12e7358173a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999676814 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_hmac_vectors.999676814
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.3557198971
Short name T270
Test name
Test status
Simulation time 7201882472 ps
CPU time 380.08 seconds
Started Mar 19 12:45:19 PM PDT 24
Finished Mar 19 12:51:39 PM PDT 24
Peak memory 200424 kb
Host smart-be5e31b8-f28d-4640-8160-797ad96329e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557198971 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.3557198971
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.741497607
Short name T320
Test name
Test status
Simulation time 7976631043 ps
CPU time 58.33 seconds
Started Mar 19 12:45:21 PM PDT 24
Finished Mar 19 12:46:20 PM PDT 24
Peak memory 200464 kb
Host smart-df406d01-48a6-461a-b155-acd84b99c9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741497607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.741497607
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.4230218005
Short name T434
Test name
Test status
Simulation time 12234133 ps
CPU time 0.58 seconds
Started Mar 19 12:45:22 PM PDT 24
Finished Mar 19 12:45:23 PM PDT 24
Peak memory 194804 kb
Host smart-b3f7fc40-e7a9-4142-a1f0-ae574de003d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230218005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.4230218005
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.33652550
Short name T181
Test name
Test status
Simulation time 1546628395 ps
CPU time 62.47 seconds
Started Mar 19 12:45:19 PM PDT 24
Finished Mar 19 12:46:23 PM PDT 24
Peak memory 217848 kb
Host smart-c22e5832-114b-422d-b32d-5e7500653e01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=33652550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.33652550
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1226393477
Short name T44
Test name
Test status
Simulation time 2630854750 ps
CPU time 30.07 seconds
Started Mar 19 12:45:24 PM PDT 24
Finished Mar 19 12:45:54 PM PDT 24
Peak memory 200460 kb
Host smart-25449a36-2d8a-42bf-8f4f-bc0718333bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226393477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1226393477
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.2752501851
Short name T453
Test name
Test status
Simulation time 26886242703 ps
CPU time 143.58 seconds
Started Mar 19 12:45:21 PM PDT 24
Finished Mar 19 12:47:45 PM PDT 24
Peak memory 200452 kb
Host smart-d5d7293e-f139-4b75-9364-0ae96c5a9d72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2752501851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2752501851
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.69082182
Short name T186
Test name
Test status
Simulation time 1758732721 ps
CPU time 24.41 seconds
Started Mar 19 12:45:27 PM PDT 24
Finished Mar 19 12:45:52 PM PDT 24
Peak memory 200456 kb
Host smart-171edf46-e373-44f3-89d0-273e663ec8da
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69082182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.69082182
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1759036570
Short name T428
Test name
Test status
Simulation time 167285327 ps
CPU time 9.27 seconds
Started Mar 19 12:45:28 PM PDT 24
Finished Mar 19 12:45:37 PM PDT 24
Peak memory 200368 kb
Host smart-03f96692-6e02-45a1-93f7-87f040223791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759036570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1759036570
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.665104813
Short name T236
Test name
Test status
Simulation time 841240797 ps
CPU time 2.66 seconds
Started Mar 19 12:45:20 PM PDT 24
Finished Mar 19 12:45:24 PM PDT 24
Peak memory 200376 kb
Host smart-ed4f7fbd-bc19-4ab8-9f4b-9c4592f25eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665104813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.665104813
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3103759078
Short name T91
Test name
Test status
Simulation time 540201185010 ps
CPU time 1722.4 seconds
Started Mar 19 12:45:21 PM PDT 24
Finished Mar 19 01:14:04 PM PDT 24
Peak memory 232740 kb
Host smart-d301ce68-f0fe-4c22-8b06-43c2d7beeaf3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103759078 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3103759078
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.1905196110
Short name T455
Test name
Test status
Simulation time 160520123 ps
CPU time 1.02 seconds
Started Mar 19 12:45:28 PM PDT 24
Finished Mar 19 12:45:30 PM PDT 24
Peak memory 199188 kb
Host smart-6058a49a-10b6-452f-9827-9c8e80b0a59d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905196110 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.1905196110
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.4284535406
Short name T495
Test name
Test status
Simulation time 380837368279 ps
CPU time 499.17 seconds
Started Mar 19 12:45:20 PM PDT 24
Finished Mar 19 12:53:40 PM PDT 24
Peak memory 200392 kb
Host smart-fb4f189d-db90-4dfa-826c-9542d175054c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284535406 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.4284535406
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.4004070719
Short name T221
Test name
Test status
Simulation time 1353486793 ps
CPU time 23.24 seconds
Started Mar 19 12:45:18 PM PDT 24
Finished Mar 19 12:45:42 PM PDT 24
Peak memory 200448 kb
Host smart-a31f72cd-d06c-47e6-bfcc-ff2884b4e8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004070719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.4004070719
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.943630893
Short name T535
Test name
Test status
Simulation time 24906450 ps
CPU time 0.6 seconds
Started Mar 19 12:45:20 PM PDT 24
Finished Mar 19 12:45:21 PM PDT 24
Peak memory 195900 kb
Host smart-31c32591-6666-4fb0-8bee-af813b57b4b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943630893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.943630893
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.775429994
Short name T402
Test name
Test status
Simulation time 2337271562 ps
CPU time 51.14 seconds
Started Mar 19 12:45:24 PM PDT 24
Finished Mar 19 12:46:15 PM PDT 24
Peak memory 228016 kb
Host smart-3d79bb7c-90f0-4325-901c-030610395279
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=775429994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.775429994
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1721432899
Short name T551
Test name
Test status
Simulation time 1574865393 ps
CPU time 3.28 seconds
Started Mar 19 12:45:25 PM PDT 24
Finished Mar 19 12:45:28 PM PDT 24
Peak memory 200356 kb
Host smart-2966c3d7-761a-4473-8344-928b032e18fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721432899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1721432899
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1857415276
Short name T281
Test name
Test status
Simulation time 7544669273 ps
CPU time 105.04 seconds
Started Mar 19 12:45:26 PM PDT 24
Finished Mar 19 12:47:12 PM PDT 24
Peak memory 200464 kb
Host smart-2067c6cd-eddf-4160-bb17-93f34d65592c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1857415276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1857415276
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.868031032
Short name T276
Test name
Test status
Simulation time 7744280366 ps
CPU time 51.17 seconds
Started Mar 19 12:45:22 PM PDT 24
Finished Mar 19 12:46:13 PM PDT 24
Peak memory 200460 kb
Host smart-573c6dcb-4a33-4ba9-ac45-f19a3f989f8f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868031032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.868031032
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3858930830
Short name T192
Test name
Test status
Simulation time 2351688758 ps
CPU time 23.23 seconds
Started Mar 19 12:45:26 PM PDT 24
Finished Mar 19 12:45:50 PM PDT 24
Peak memory 200508 kb
Host smart-786b70c4-cfc8-432e-87db-5f92d3a0e57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858930830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3858930830
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2964874751
Short name T405
Test name
Test status
Simulation time 2209802412 ps
CPU time 6.39 seconds
Started Mar 19 12:45:26 PM PDT 24
Finished Mar 19 12:45:33 PM PDT 24
Peak memory 200524 kb
Host smart-543a6ebd-5e6f-402c-9604-0a1196b4fd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964874751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2964874751
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.1751116106
Short name T87
Test name
Test status
Simulation time 191636758364 ps
CPU time 1228.55 seconds
Started Mar 19 12:45:26 PM PDT 24
Finished Mar 19 01:05:55 PM PDT 24
Peak memory 200544 kb
Host smart-dde31f90-1e9c-44a2-a8d8-3d5473ead5d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751116106 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1751116106
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.2956488134
Short name T61
Test name
Test status
Simulation time 218651187 ps
CPU time 1.21 seconds
Started Mar 19 12:45:28 PM PDT 24
Finished Mar 19 12:45:30 PM PDT 24
Peak memory 200348 kb
Host smart-c998c63a-415d-45d1-9744-86b2ed0f9f51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956488134 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.2956488134
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.1526221029
Short name T182
Test name
Test status
Simulation time 36388432405 ps
CPU time 440.2 seconds
Started Mar 19 12:45:28 PM PDT 24
Finished Mar 19 12:52:50 PM PDT 24
Peak memory 200424 kb
Host smart-249519c9-cfed-431f-82f1-9553001cdb76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526221029 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.1526221029
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.3201803500
Short name T141
Test name
Test status
Simulation time 13377863822 ps
CPU time 46.97 seconds
Started Mar 19 12:45:28 PM PDT 24
Finished Mar 19 12:46:17 PM PDT 24
Peak memory 200492 kb
Host smart-16df7d94-ced1-4363-92b6-99f18e3dbfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201803500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3201803500
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.1767966178
Short name T26
Test name
Test status
Simulation time 101358365 ps
CPU time 0.59 seconds
Started Mar 19 12:45:18 PM PDT 24
Finished Mar 19 12:45:19 PM PDT 24
Peak memory 195844 kb
Host smart-0e5b6c31-8f78-45de-aa02-084276a2481b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767966178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1767966178
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2041334184
Short name T570
Test name
Test status
Simulation time 369570074 ps
CPU time 3.7 seconds
Started Mar 19 12:45:22 PM PDT 24
Finished Mar 19 12:45:26 PM PDT 24
Peak memory 200352 kb
Host smart-c01b8481-f018-48ad-9e72-7a0266428afb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2041334184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2041334184
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.3354677811
Short name T536
Test name
Test status
Simulation time 4543529465 ps
CPU time 54.79 seconds
Started Mar 19 12:45:25 PM PDT 24
Finished Mar 19 12:46:20 PM PDT 24
Peak memory 200480 kb
Host smart-ee6f078a-80c1-48f9-b7b6-ad1264550f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354677811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3354677811
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1157383898
Short name T284
Test name
Test status
Simulation time 2865891809 ps
CPU time 48.44 seconds
Started Mar 19 12:45:24 PM PDT 24
Finished Mar 19 12:46:12 PM PDT 24
Peak memory 200480 kb
Host smart-48cfc367-ce42-4ee6-bad5-703a53009566
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1157383898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1157383898
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1446508048
Short name T32
Test name
Test status
Simulation time 8926920608 ps
CPU time 120.97 seconds
Started Mar 19 12:45:20 PM PDT 24
Finished Mar 19 12:47:22 PM PDT 24
Peak memory 200452 kb
Host smart-3e417a9b-5c7a-494e-a639-b82a079ba98b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446508048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1446508048
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1695379812
Short name T534
Test name
Test status
Simulation time 448269118 ps
CPU time 9.05 seconds
Started Mar 19 12:45:19 PM PDT 24
Finished Mar 19 12:45:30 PM PDT 24
Peak memory 200376 kb
Host smart-66ca3443-d1c1-4e48-bd34-7cb49034a42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695379812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1695379812
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.901889316
Short name T356
Test name
Test status
Simulation time 745842773 ps
CPU time 1.36 seconds
Started Mar 19 12:45:25 PM PDT 24
Finished Mar 19 12:45:27 PM PDT 24
Peak memory 200400 kb
Host smart-92f187ff-15c3-4b20-b23e-e1a9caf520ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901889316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.901889316
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.973038044
Short name T369
Test name
Test status
Simulation time 378334140682 ps
CPU time 1048.72 seconds
Started Mar 19 12:45:28 PM PDT 24
Finished Mar 19 01:02:58 PM PDT 24
Peak memory 222588 kb
Host smart-a19e867b-7cf5-4c4f-a83e-4bfde1355903
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973038044 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.973038044
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.715661085
Short name T376
Test name
Test status
Simulation time 213603648 ps
CPU time 1.29 seconds
Started Mar 19 12:45:23 PM PDT 24
Finished Mar 19 12:45:24 PM PDT 24
Peak memory 200388 kb
Host smart-71877c5b-6c40-4b88-bf2e-d6e6ea43f3a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715661085 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_hmac_vectors.715661085
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.3936203311
Short name T310
Test name
Test status
Simulation time 50810467006 ps
CPU time 407.99 seconds
Started Mar 19 12:45:27 PM PDT 24
Finished Mar 19 12:52:16 PM PDT 24
Peak memory 200428 kb
Host smart-88373fba-7b9f-4ec7-a9ea-715ccd0beec2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936203311 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.3936203311
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3576081724
Short name T132
Test name
Test status
Simulation time 13235824975 ps
CPU time 94.84 seconds
Started Mar 19 12:45:23 PM PDT 24
Finished Mar 19 12:46:58 PM PDT 24
Peak memory 200464 kb
Host smart-ad909b53-c44c-4e72-b2b1-3a83db16a845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576081724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3576081724
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2276893958
Short name T25
Test name
Test status
Simulation time 11626961 ps
CPU time 0.6 seconds
Started Mar 19 12:45:26 PM PDT 24
Finished Mar 19 12:45:27 PM PDT 24
Peak memory 195560 kb
Host smart-b5a5c7e3-2b98-4f71-b2e0-551d944d5051
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276893958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2276893958
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3932075579
Short name T23
Test name
Test status
Simulation time 303611265 ps
CPU time 11.19 seconds
Started Mar 19 12:45:22 PM PDT 24
Finished Mar 19 12:45:39 PM PDT 24
Peak memory 208572 kb
Host smart-e1f2686a-b1aa-4ebc-898d-537f7dc8e2f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3932075579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3932075579
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2903045826
Short name T220
Test name
Test status
Simulation time 644692234 ps
CPU time 14.27 seconds
Started Mar 19 12:45:25 PM PDT 24
Finished Mar 19 12:45:39 PM PDT 24
Peak memory 200384 kb
Host smart-c44666fa-1bf3-4afa-b674-a362136d88ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903045826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2903045826
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1356698340
Short name T442
Test name
Test status
Simulation time 1278474712 ps
CPU time 9.25 seconds
Started Mar 19 12:45:25 PM PDT 24
Finished Mar 19 12:45:34 PM PDT 24
Peak memory 200380 kb
Host smart-3971b85f-6fc0-4b54-93a9-d31a576b29e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1356698340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1356698340
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2624051507
Short name T326
Test name
Test status
Simulation time 21269894053 ps
CPU time 135.02 seconds
Started Mar 19 12:45:24 PM PDT 24
Finished Mar 19 12:47:39 PM PDT 24
Peak memory 200492 kb
Host smart-7297d034-5fb7-4d33-b6e2-43655120ab8a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624051507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2624051507
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.26691086
Short name T290
Test name
Test status
Simulation time 13489880981 ps
CPU time 88.96 seconds
Started Mar 19 12:45:26 PM PDT 24
Finished Mar 19 12:46:55 PM PDT 24
Peak memory 200544 kb
Host smart-773ae881-2e79-4032-b292-539b013c13d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26691086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.26691086
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1163555483
Short name T239
Test name
Test status
Simulation time 1857877875 ps
CPU time 6.52 seconds
Started Mar 19 12:45:25 PM PDT 24
Finished Mar 19 12:45:32 PM PDT 24
Peak memory 200376 kb
Host smart-0ae1408b-0b7c-457b-8875-f0837ad61d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163555483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1163555483
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.1491924558
Short name T252
Test name
Test status
Simulation time 9405860684 ps
CPU time 50.75 seconds
Started Mar 19 12:45:26 PM PDT 24
Finished Mar 19 12:46:17 PM PDT 24
Peak memory 200484 kb
Host smart-25a3eb10-5b03-467e-8130-dfa054d65c0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491924558 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1491924558
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.2686155250
Short name T341
Test name
Test status
Simulation time 438029035 ps
CPU time 1.02 seconds
Started Mar 19 12:45:28 PM PDT 24
Finished Mar 19 12:45:29 PM PDT 24
Peak memory 199960 kb
Host smart-051e25be-194a-4114-b9e7-d11c34ea48f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686155250 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.2686155250
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.1344079827
Short name T219
Test name
Test status
Simulation time 29067124599 ps
CPU time 516.65 seconds
Started Mar 19 12:45:28 PM PDT 24
Finished Mar 19 12:54:06 PM PDT 24
Peak memory 200444 kb
Host smart-d25b4f0b-c833-4100-b352-217582b4bc30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344079827 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.1344079827
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3974474422
Short name T245
Test name
Test status
Simulation time 5744480386 ps
CPU time 78.1 seconds
Started Mar 19 12:45:23 PM PDT 24
Finished Mar 19 12:46:41 PM PDT 24
Peak memory 200464 kb
Host smart-38920dee-6f0e-4d6a-8603-55c433216307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974474422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3974474422
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.4205581862
Short name T390
Test name
Test status
Simulation time 14725995 ps
CPU time 0.57 seconds
Started Mar 19 12:45:28 PM PDT 24
Finished Mar 19 12:45:29 PM PDT 24
Peak memory 195584 kb
Host smart-8a42a1b8-384c-443a-af9d-211acd7c38fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205581862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.4205581862
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3354965018
Short name T576
Test name
Test status
Simulation time 860337743 ps
CPU time 35.79 seconds
Started Mar 19 12:45:25 PM PDT 24
Finished Mar 19 12:46:01 PM PDT 24
Peak memory 225028 kb
Host smart-367772cd-dea7-4b76-bbc6-499add9f088d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3354965018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3354965018
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1100866778
Short name T556
Test name
Test status
Simulation time 3951198360 ps
CPU time 49.65 seconds
Started Mar 19 12:45:25 PM PDT 24
Finished Mar 19 12:46:15 PM PDT 24
Peak memory 200412 kb
Host smart-3935d1b1-cbc5-41f6-97bb-b813e87f398d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100866778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1100866778
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.2946751575
Short name T545
Test name
Test status
Simulation time 1543933160 ps
CPU time 86.16 seconds
Started Mar 19 12:45:24 PM PDT 24
Finished Mar 19 12:46:51 PM PDT 24
Peak memory 200428 kb
Host smart-178ac6f0-b4f6-4bf0-b72d-4ccb957235e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2946751575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2946751575
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2878477865
Short name T579
Test name
Test status
Simulation time 2082539365 ps
CPU time 115.04 seconds
Started Mar 19 12:45:27 PM PDT 24
Finished Mar 19 12:47:23 PM PDT 24
Peak memory 200404 kb
Host smart-4adca168-5bf8-491f-ad03-4ca1c77df611
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878477865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2878477865
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3865328401
Short name T202
Test name
Test status
Simulation time 3815901134 ps
CPU time 74.74 seconds
Started Mar 19 12:45:33 PM PDT 24
Finished Mar 19 12:46:48 PM PDT 24
Peak memory 200480 kb
Host smart-deacfa87-81be-4629-80c9-2745f839ec78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865328401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3865328401
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2940486450
Short name T490
Test name
Test status
Simulation time 1855302259 ps
CPU time 3.56 seconds
Started Mar 19 12:45:26 PM PDT 24
Finished Mar 19 12:45:30 PM PDT 24
Peak memory 200392 kb
Host smart-d8c6bd65-53e2-4422-8358-baf3d5e2cdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940486450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2940486450
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2976514176
Short name T502
Test name
Test status
Simulation time 666246468185 ps
CPU time 1282.2 seconds
Started Mar 19 12:45:25 PM PDT 24
Finished Mar 19 01:06:47 PM PDT 24
Peak memory 238384 kb
Host smart-2685f8ea-4f04-49e1-9674-c1654faa2e5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976514176 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2976514176
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.2749773448
Short name T425
Test name
Test status
Simulation time 51983779 ps
CPU time 1.02 seconds
Started Mar 19 12:45:26 PM PDT 24
Finished Mar 19 12:45:29 PM PDT 24
Peak memory 199732 kb
Host smart-7006ac56-e3a4-4106-9375-db9eb723f6c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749773448 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.2749773448
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.1919718541
Short name T429
Test name
Test status
Simulation time 86342995955 ps
CPU time 490.27 seconds
Started Mar 19 12:45:29 PM PDT 24
Finished Mar 19 12:53:40 PM PDT 24
Peak memory 200344 kb
Host smart-1e6f4f8f-70f9-4898-8bc2-d63f42194005
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919718541 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.1919718541
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2447249841
Short name T197
Test name
Test status
Simulation time 12451185320 ps
CPU time 64.24 seconds
Started Mar 19 12:45:24 PM PDT 24
Finished Mar 19 12:46:29 PM PDT 24
Peak memory 200440 kb
Host smart-216e7ac2-0afe-400c-af8d-84493ab5c218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447249841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2447249841
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.3458698492
Short name T452
Test name
Test status
Simulation time 15596732 ps
CPU time 0.6 seconds
Started Mar 19 12:45:26 PM PDT 24
Finished Mar 19 12:45:27 PM PDT 24
Peak memory 195952 kb
Host smart-c74a48be-fde4-42d0-80af-5a1bd5c6ab11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458698492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3458698492
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.1238342127
Short name T57
Test name
Test status
Simulation time 565151190 ps
CPU time 4.29 seconds
Started Mar 19 12:45:26 PM PDT 24
Finished Mar 19 12:45:30 PM PDT 24
Peak memory 200340 kb
Host smart-dc373157-1533-4e51-a9a6-ebced7757e70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1238342127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1238342127
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.572490699
Short name T247
Test name
Test status
Simulation time 2632732410 ps
CPU time 28.27 seconds
Started Mar 19 12:45:31 PM PDT 24
Finished Mar 19 12:46:00 PM PDT 24
Peak memory 200500 kb
Host smart-6367f099-5fde-4d4e-8a4a-e08bdd33c6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572490699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.572490699
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3646906856
Short name T383
Test name
Test status
Simulation time 36287460563 ps
CPU time 128.1 seconds
Started Mar 19 12:45:24 PM PDT 24
Finished Mar 19 12:47:33 PM PDT 24
Peak memory 200508 kb
Host smart-d0ba81fe-382b-43a4-a955-6e02808d6bd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3646906856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3646906856
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.2977673366
Short name T295
Test name
Test status
Simulation time 499684763 ps
CPU time 26.71 seconds
Started Mar 19 12:45:35 PM PDT 24
Finished Mar 19 12:46:01 PM PDT 24
Peak memory 200284 kb
Host smart-b5981458-5b0e-4057-a941-2e2346ad9d72
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977673366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2977673366
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2087023416
Short name T344
Test name
Test status
Simulation time 19427553880 ps
CPU time 95.4 seconds
Started Mar 19 12:45:25 PM PDT 24
Finished Mar 19 12:47:01 PM PDT 24
Peak memory 200464 kb
Host smart-968f8e02-6464-4e50-9071-a33e8d93df23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087023416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2087023416
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.1466176008
Short name T297
Test name
Test status
Simulation time 762884163 ps
CPU time 6.28 seconds
Started Mar 19 12:45:30 PM PDT 24
Finished Mar 19 12:45:37 PM PDT 24
Peak memory 200404 kb
Host smart-5e103a9a-8f37-4d55-94dc-8ef7e53ae316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466176008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1466176008
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.2078201457
Short name T212
Test name
Test status
Simulation time 15718126855 ps
CPU time 842.48 seconds
Started Mar 19 12:45:26 PM PDT 24
Finished Mar 19 12:59:30 PM PDT 24
Peak memory 241640 kb
Host smart-6d898bd6-9548-470f-a753-80fdebd167dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078201457 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.2078201457
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.1913175471
Short name T19
Test name
Test status
Simulation time 112738103 ps
CPU time 1.31 seconds
Started Mar 19 12:45:25 PM PDT 24
Finished Mar 19 12:45:27 PM PDT 24
Peak memory 200380 kb
Host smart-2f5e120a-b44c-4431-8683-cfac368f445c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913175471 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.1913175471
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.3055535523
Short name T587
Test name
Test status
Simulation time 107090036912 ps
CPU time 457.21 seconds
Started Mar 19 12:45:25 PM PDT 24
Finished Mar 19 12:53:02 PM PDT 24
Peak memory 200380 kb
Host smart-5b42f6f6-b991-474f-8fb7-35f8d4279a7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055535523 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.3055535523
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2771099205
Short name T416
Test name
Test status
Simulation time 13043149492 ps
CPU time 61.06 seconds
Started Mar 19 12:45:25 PM PDT 24
Finished Mar 19 12:46:27 PM PDT 24
Peak memory 200448 kb
Host smart-e5cbf04f-3db3-4b62-bca1-d458d7369691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771099205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2771099205
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.2409208172
Short name T371
Test name
Test status
Simulation time 48267551 ps
CPU time 0.53 seconds
Started Mar 19 12:45:26 PM PDT 24
Finished Mar 19 12:45:27 PM PDT 24
Peak memory 195812 kb
Host smart-9f8313de-4f0c-4b49-92a4-1935d713e8cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409208172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2409208172
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.248726361
Short name T268
Test name
Test status
Simulation time 3577754622 ps
CPU time 31.9 seconds
Started Mar 19 12:45:23 PM PDT 24
Finished Mar 19 12:45:55 PM PDT 24
Peak memory 233224 kb
Host smart-0cefbfc4-8ce5-482f-b422-f94a6dab16b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=248726361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.248726361
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.236142100
Short name T373
Test name
Test status
Simulation time 1637110326 ps
CPU time 27.38 seconds
Started Mar 19 12:45:26 PM PDT 24
Finished Mar 19 12:45:55 PM PDT 24
Peak memory 200424 kb
Host smart-82ab2084-9564-450d-a63b-e26bff3a3054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236142100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.236142100
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.2665597523
Short name T131
Test name
Test status
Simulation time 1154657378 ps
CPU time 65.15 seconds
Started Mar 19 12:45:31 PM PDT 24
Finished Mar 19 12:46:36 PM PDT 24
Peak memory 200428 kb
Host smart-63c50238-04e3-4373-8516-9babf1156286
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2665597523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.2665597523
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.4254050944
Short name T577
Test name
Test status
Simulation time 1705797674 ps
CPU time 92.75 seconds
Started Mar 19 12:45:24 PM PDT 24
Finished Mar 19 12:46:57 PM PDT 24
Peak memory 200440 kb
Host smart-4b598dcb-711c-4e2b-9c66-9287ff6048fc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254050944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.4254050944
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3366301102
Short name T123
Test name
Test status
Simulation time 1405005651 ps
CPU time 84.52 seconds
Started Mar 19 12:45:35 PM PDT 24
Finished Mar 19 12:46:59 PM PDT 24
Peak memory 200480 kb
Host smart-599b39a9-b59d-46c7-bac6-d22d8f76a149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366301102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3366301102
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.4030205656
Short name T94
Test name
Test status
Simulation time 232853054 ps
CPU time 1.98 seconds
Started Mar 19 12:45:24 PM PDT 24
Finished Mar 19 12:45:26 PM PDT 24
Peak memory 200380 kb
Host smart-2886941b-21b9-46e6-a762-4ebfa0d77d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030205656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.4030205656
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.407554389
Short name T456
Test name
Test status
Simulation time 608731267075 ps
CPU time 2080.63 seconds
Started Mar 19 12:45:25 PM PDT 24
Finished Mar 19 01:20:06 PM PDT 24
Peak memory 243480 kb
Host smart-881bdc69-10f7-40a7-8163-82ebf41b37ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407554389 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.407554389
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.2131770224
Short name T204
Test name
Test status
Simulation time 46556530 ps
CPU time 0.96 seconds
Started Mar 19 12:45:24 PM PDT 24
Finished Mar 19 12:45:25 PM PDT 24
Peak memory 200000 kb
Host smart-084fcc37-bdd5-4513-8d06-37b5d03bb632
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131770224 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.2131770224
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.2782967311
Short name T374
Test name
Test status
Simulation time 8526020196 ps
CPU time 443.68 seconds
Started Mar 19 12:45:24 PM PDT 24
Finished Mar 19 12:52:47 PM PDT 24
Peak memory 200372 kb
Host smart-81b418d1-875f-487a-8f47-7c621b9e045a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782967311 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.2782967311
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1885380199
Short name T379
Test name
Test status
Simulation time 2533428197 ps
CPU time 34.13 seconds
Started Mar 19 12:45:24 PM PDT 24
Finished Mar 19 12:45:58 PM PDT 24
Peak memory 200472 kb
Host smart-429c7e58-ea1f-4184-b35f-4e136b76aed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885380199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1885380199
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.226020044
Short name T328
Test name
Test status
Simulation time 29540562 ps
CPU time 0.6 seconds
Started Mar 19 12:45:29 PM PDT 24
Finished Mar 19 12:45:30 PM PDT 24
Peak memory 194852 kb
Host smart-ed4476b5-0c8d-4e12-819a-ffc0594876be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226020044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.226020044
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.18122696
Short name T228
Test name
Test status
Simulation time 554240828 ps
CPU time 4.95 seconds
Started Mar 19 12:45:24 PM PDT 24
Finished Mar 19 12:45:29 PM PDT 24
Peak memory 200376 kb
Host smart-988b2832-21b1-4457-ba13-7c8b292f45b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=18122696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.18122696
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3379028685
Short name T6
Test name
Test status
Simulation time 2154286183 ps
CPU time 33.19 seconds
Started Mar 19 12:45:25 PM PDT 24
Finished Mar 19 12:45:58 PM PDT 24
Peak memory 200488 kb
Host smart-bca01f41-9288-4cfa-ab32-7ec7e164e069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379028685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3379028685
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.630060703
Short name T145
Test name
Test status
Simulation time 1168122995 ps
CPU time 16.93 seconds
Started Mar 19 12:45:23 PM PDT 24
Finished Mar 19 12:45:40 PM PDT 24
Peak memory 200364 kb
Host smart-aa7e65ea-9084-4f14-961b-cc8d3847195c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=630060703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.630060703
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3063266144
Short name T564
Test name
Test status
Simulation time 7088460217 ps
CPU time 92.16 seconds
Started Mar 19 12:45:35 PM PDT 24
Finished Mar 19 12:47:07 PM PDT 24
Peak memory 200524 kb
Host smart-0577c223-4d55-40c1-a738-69a8f684389d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063266144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3063266144
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1581393845
Short name T319
Test name
Test status
Simulation time 13874979624 ps
CPU time 107.3 seconds
Started Mar 19 12:45:35 PM PDT 24
Finished Mar 19 12:47:22 PM PDT 24
Peak memory 200492 kb
Host smart-402caa56-a1f5-41e0-b310-8ab7b405a694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581393845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1581393845
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3522124765
Short name T330
Test name
Test status
Simulation time 755064133 ps
CPU time 2.52 seconds
Started Mar 19 12:45:25 PM PDT 24
Finished Mar 19 12:45:28 PM PDT 24
Peak memory 200356 kb
Host smart-5f645074-5e19-48cb-9f93-b7f433d5ccb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522124765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3522124765
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3941474263
Short name T593
Test name
Test status
Simulation time 47395852275 ps
CPU time 577.1 seconds
Started Mar 19 12:45:28 PM PDT 24
Finished Mar 19 12:55:06 PM PDT 24
Peak memory 200464 kb
Host smart-1e5a32ce-27c6-4ee7-aeeb-01e5b57a4351
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941474263 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3941474263
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.673376155
Short name T391
Test name
Test status
Simulation time 28623181 ps
CPU time 0.98 seconds
Started Mar 19 12:45:26 PM PDT 24
Finished Mar 19 12:45:27 PM PDT 24
Peak memory 198536 kb
Host smart-41a91bc7-4f1e-4c6d-8637-0d7e5f2e4dd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673376155 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_hmac_vectors.673376155
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.3785162255
Short name T41
Test name
Test status
Simulation time 63247469956 ps
CPU time 504.26 seconds
Started Mar 19 12:45:27 PM PDT 24
Finished Mar 19 12:53:52 PM PDT 24
Peak memory 200388 kb
Host smart-d810ab57-d4e8-4096-ab36-4bc644ba0ff7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785162255 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.3785162255
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.682232065
Short name T445
Test name
Test status
Simulation time 1469368321 ps
CPU time 75 seconds
Started Mar 19 12:45:27 PM PDT 24
Finished Mar 19 12:46:43 PM PDT 24
Peak memory 200392 kb
Host smart-a5dc5fad-ed2a-45a7-82ca-055626930dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682232065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.682232065
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.700137984
Short name T128
Test name
Test status
Simulation time 59932535 ps
CPU time 0.57 seconds
Started Mar 19 12:45:34 PM PDT 24
Finished Mar 19 12:45:34 PM PDT 24
Peak memory 195888 kb
Host smart-9d8e4d78-fd93-4d29-b3a8-72a8c654faa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700137984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.700137984
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.795414053
Short name T572
Test name
Test status
Simulation time 1291711211 ps
CPU time 41.51 seconds
Started Mar 19 12:45:30 PM PDT 24
Finished Mar 19 12:46:13 PM PDT 24
Peak memory 208580 kb
Host smart-57488ec0-21c0-47c2-98f2-2a8834555fcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=795414053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.795414053
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.767161030
Short name T142
Test name
Test status
Simulation time 1542765047 ps
CPU time 23.28 seconds
Started Mar 19 12:45:31 PM PDT 24
Finished Mar 19 12:45:55 PM PDT 24
Peak memory 200388 kb
Host smart-9f13b86a-7f6f-4070-a20f-83980ae8577e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767161030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.767161030
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.693973494
Short name T274
Test name
Test status
Simulation time 4253757616 ps
CPU time 55.33 seconds
Started Mar 19 12:45:22 PM PDT 24
Finished Mar 19 12:46:18 PM PDT 24
Peak memory 200376 kb
Host smart-49ded684-7563-4479-bed5-12d56dee0584
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=693973494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.693973494
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.1214687998
Short name T333
Test name
Test status
Simulation time 7459827072 ps
CPU time 97.5 seconds
Started Mar 19 12:45:29 PM PDT 24
Finished Mar 19 12:47:07 PM PDT 24
Peak memory 200444 kb
Host smart-923de768-cd3b-4cac-b7aa-24bad614c49a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214687998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1214687998
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1185303657
Short name T170
Test name
Test status
Simulation time 6972495057 ps
CPU time 69.41 seconds
Started Mar 19 12:45:26 PM PDT 24
Finished Mar 19 12:46:37 PM PDT 24
Peak memory 200444 kb
Host smart-9fa943be-ac4c-4af7-bbbc-1cbc9b179509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185303657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1185303657
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2230511931
Short name T568
Test name
Test status
Simulation time 145956867 ps
CPU time 2.4 seconds
Started Mar 19 12:45:31 PM PDT 24
Finished Mar 19 12:45:34 PM PDT 24
Peak memory 200384 kb
Host smart-f1f346bd-138f-4d71-998d-13a8e5235f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230511931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2230511931
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.116958125
Short name T79
Test name
Test status
Simulation time 32124380231 ps
CPU time 1698.75 seconds
Started Mar 19 12:45:30 PM PDT 24
Finished Mar 19 01:13:50 PM PDT 24
Peak memory 200452 kb
Host smart-ec42e97c-2b04-4b27-a841-43c24b8eff1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116958125 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.116958125
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.3621965130
Short name T285
Test name
Test status
Simulation time 124151011 ps
CPU time 1.21 seconds
Started Mar 19 12:45:38 PM PDT 24
Finished Mar 19 12:45:40 PM PDT 24
Peak memory 200280 kb
Host smart-ae775922-4fe1-44df-a8a0-efe1a527aebc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621965130 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.3621965130
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.2410029087
Short name T140
Test name
Test status
Simulation time 48437277316 ps
CPU time 400.54 seconds
Started Mar 19 12:45:27 PM PDT 24
Finished Mar 19 12:52:09 PM PDT 24
Peak memory 200384 kb
Host smart-6f76bb61-8e0c-4b11-89ca-cd0956c7dfa7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410029087 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.2410029087
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.3620357990
Short name T156
Test name
Test status
Simulation time 7702420266 ps
CPU time 36.16 seconds
Started Mar 19 12:45:25 PM PDT 24
Finished Mar 19 12:46:01 PM PDT 24
Peak memory 200448 kb
Host smart-520373e1-4227-437f-8c06-03804dafd791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620357990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3620357990
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2018931454
Short name T322
Test name
Test status
Simulation time 45115592 ps
CPU time 0.62 seconds
Started Mar 19 12:46:11 PM PDT 24
Finished Mar 19 12:46:13 PM PDT 24
Peak memory 192988 kb
Host smart-6d92c857-8db4-4bac-869d-4b10991cf95f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018931454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2018931454
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.2558905045
Short name T562
Test name
Test status
Simulation time 17005251482 ps
CPU time 52.42 seconds
Started Mar 19 12:44:53 PM PDT 24
Finished Mar 19 12:45:45 PM PDT 24
Peak memory 229112 kb
Host smart-985137af-e3b3-4211-8c65-78db49cf42dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2558905045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2558905045
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.4160392483
Short name T444
Test name
Test status
Simulation time 2112486898 ps
CPU time 52.44 seconds
Started Mar 19 12:44:36 PM PDT 24
Finished Mar 19 12:45:28 PM PDT 24
Peak memory 200428 kb
Host smart-d4be0962-4ed3-4053-b6a0-894c4a6a62e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160392483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.4160392483
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3365676569
Short name T350
Test name
Test status
Simulation time 1122296586 ps
CPU time 37.77 seconds
Started Mar 19 12:44:34 PM PDT 24
Finished Mar 19 12:45:12 PM PDT 24
Peak memory 200412 kb
Host smart-89ded7e7-1538-4ea6-a527-5a39b3913146
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3365676569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3365676569
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_long_msg.197597626
Short name T147
Test name
Test status
Simulation time 2725756859 ps
CPU time 48.6 seconds
Started Mar 19 12:46:07 PM PDT 24
Finished Mar 19 12:46:56 PM PDT 24
Peak memory 200300 kb
Host smart-519d4cc2-2975-474e-b27c-6a216d390b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197597626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.197597626
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1662966158
Short name T36
Test name
Test status
Simulation time 217368638 ps
CPU time 0.89 seconds
Started Mar 19 12:44:41 PM PDT 24
Finished Mar 19 12:44:42 PM PDT 24
Peak memory 218736 kb
Host smart-0b3234a2-1add-46c6-a257-2aa794764268
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662966158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1662966158
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.1908665676
Short name T180
Test name
Test status
Simulation time 205227751 ps
CPU time 0.97 seconds
Started Mar 19 12:44:38 PM PDT 24
Finished Mar 19 12:44:39 PM PDT 24
Peak memory 200000 kb
Host smart-7b1832eb-3452-417e-a890-e3e03dadc988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908665676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1908665676
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3071696295
Short name T561
Test name
Test status
Simulation time 18761523495 ps
CPU time 898.16 seconds
Started Mar 19 12:46:07 PM PDT 24
Finished Mar 19 01:01:05 PM PDT 24
Peak memory 238524 kb
Host smart-781f440a-7e54-49ad-af39-8df4d1748c73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071696295 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3071696295
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.280485978
Short name T73
Test name
Test status
Simulation time 28144128765 ps
CPU time 1327.25 seconds
Started Mar 19 12:44:40 PM PDT 24
Finished Mar 19 01:06:47 PM PDT 24
Peak memory 233332 kb
Host smart-5684da69-d499-4efb-992c-8febb64cc1de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=280485978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.280485978
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.1237702837
Short name T242
Test name
Test status
Simulation time 75199663 ps
CPU time 1.47 seconds
Started Mar 19 12:44:38 PM PDT 24
Finished Mar 19 12:44:39 PM PDT 24
Peak memory 200384 kb
Host smart-5e30f574-29c9-4f23-b8fa-9438971d9b68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237702837 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.1237702837
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.571940573
Short name T325
Test name
Test status
Simulation time 64773142608 ps
CPU time 407.32 seconds
Started Mar 19 12:44:36 PM PDT 24
Finished Mar 19 12:51:24 PM PDT 24
Peak memory 200388 kb
Host smart-cecea92b-2e38-48b0-99ff-a48184548c68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571940573 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.571940573
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3101943911
Short name T417
Test name
Test status
Simulation time 10777099511 ps
CPU time 72.86 seconds
Started Mar 19 12:44:37 PM PDT 24
Finished Mar 19 12:45:50 PM PDT 24
Peak memory 200432 kb
Host smart-43e3fa8e-0f01-4acd-bc27-ea5170c33e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101943911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3101943911
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1416811289
Short name T471
Test name
Test status
Simulation time 18805687 ps
CPU time 0.57 seconds
Started Mar 19 12:45:30 PM PDT 24
Finished Mar 19 12:45:32 PM PDT 24
Peak memory 195688 kb
Host smart-cf07008f-dcd8-4016-af82-fa9be5b8aec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416811289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1416811289
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1119664531
Short name T226
Test name
Test status
Simulation time 1068928492 ps
CPU time 36.25 seconds
Started Mar 19 12:45:29 PM PDT 24
Finished Mar 19 12:46:07 PM PDT 24
Peak memory 208588 kb
Host smart-47bbb257-00dc-4add-9d6c-ed5266d18ff3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1119664531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1119664531
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.2882775579
Short name T454
Test name
Test status
Simulation time 6097050923 ps
CPU time 49.75 seconds
Started Mar 19 12:45:36 PM PDT 24
Finished Mar 19 12:46:27 PM PDT 24
Peak memory 200480 kb
Host smart-0b63c813-f728-4e24-8eee-0a741d843a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882775579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.2882775579
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.3923672061
Short name T287
Test name
Test status
Simulation time 36681201 ps
CPU time 0.79 seconds
Started Mar 19 12:45:33 PM PDT 24
Finished Mar 19 12:45:34 PM PDT 24
Peak memory 198252 kb
Host smart-f64aa424-cca2-4fb8-b70d-c49e88342faa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3923672061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3923672061
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1849929631
Short name T14
Test name
Test status
Simulation time 1132534603 ps
CPU time 67.11 seconds
Started Mar 19 12:45:32 PM PDT 24
Finished Mar 19 12:46:40 PM PDT 24
Peak memory 200384 kb
Host smart-75d6a7ce-7a80-4725-9891-143dcc52f51c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849929631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1849929631
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2670500350
Short name T273
Test name
Test status
Simulation time 1409784280 ps
CPU time 20.91 seconds
Started Mar 19 12:45:32 PM PDT 24
Finished Mar 19 12:45:53 PM PDT 24
Peak memory 200196 kb
Host smart-1184de25-2b2f-497e-bc13-3cc4d155bbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670500350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2670500350
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2972381379
Short name T497
Test name
Test status
Simulation time 164938809 ps
CPU time 4.55 seconds
Started Mar 19 12:45:28 PM PDT 24
Finished Mar 19 12:45:34 PM PDT 24
Peak memory 200384 kb
Host smart-489a76e9-d1f5-40d4-a9e5-a9b96aab257a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972381379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2972381379
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.2902451536
Short name T394
Test name
Test status
Simulation time 42183705353 ps
CPU time 563.03 seconds
Started Mar 19 12:45:29 PM PDT 24
Finished Mar 19 12:54:53 PM PDT 24
Peak memory 216900 kb
Host smart-f1744236-2344-4a12-a3e9-6fd8fcf3ad2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902451536 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2902451536
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.3799410668
Short name T439
Test name
Test status
Simulation time 198100261 ps
CPU time 1.24 seconds
Started Mar 19 12:45:37 PM PDT 24
Finished Mar 19 12:45:39 PM PDT 24
Peak memory 200432 kb
Host smart-ce22ec04-b4ec-4602-a21c-748f3ff74e00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799410668 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.3799410668
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.2220035911
Short name T311
Test name
Test status
Simulation time 26271269798 ps
CPU time 470.87 seconds
Started Mar 19 12:45:30 PM PDT 24
Finished Mar 19 12:53:21 PM PDT 24
Peak memory 200388 kb
Host smart-ec1981ac-9e4a-4275-83c4-28840d04577a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220035911 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.2220035911
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.1677756290
Short name T518
Test name
Test status
Simulation time 3962307670 ps
CPU time 14.3 seconds
Started Mar 19 12:45:31 PM PDT 24
Finished Mar 19 12:45:46 PM PDT 24
Peak memory 200448 kb
Host smart-1acac48d-d507-4221-8c33-64ee9795ff93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677756290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.1677756290
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.890722805
Short name T157
Test name
Test status
Simulation time 49182318 ps
CPU time 0.59 seconds
Started Mar 19 12:45:31 PM PDT 24
Finished Mar 19 12:45:32 PM PDT 24
Peak memory 195872 kb
Host smart-93775820-6460-4342-a591-3d8e67cdb67f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890722805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.890722805
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3300586588
Short name T397
Test name
Test status
Simulation time 2442637961 ps
CPU time 25.69 seconds
Started Mar 19 12:45:41 PM PDT 24
Finished Mar 19 12:46:07 PM PDT 24
Peak memory 231676 kb
Host smart-86403a02-ba77-4607-bce0-6ede638850e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3300586588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3300586588
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2887765946
Short name T184
Test name
Test status
Simulation time 450330183 ps
CPU time 10.01 seconds
Started Mar 19 12:45:42 PM PDT 24
Finished Mar 19 12:45:52 PM PDT 24
Peak memory 200368 kb
Host smart-47a8c92b-aed1-4549-9d03-279007f56e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887765946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2887765946
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.715231690
Short name T464
Test name
Test status
Simulation time 7305127748 ps
CPU time 32.13 seconds
Started Mar 19 12:45:32 PM PDT 24
Finished Mar 19 12:46:05 PM PDT 24
Peak memory 200440 kb
Host smart-1304a0bc-17f1-4460-96ff-ad86f6d52889
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=715231690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.715231690
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.4075252708
Short name T77
Test name
Test status
Simulation time 134990627204 ps
CPU time 156.6 seconds
Started Mar 19 12:45:29 PM PDT 24
Finished Mar 19 12:48:07 PM PDT 24
Peak memory 200516 kb
Host smart-b10f2be0-5aaf-471e-8d67-90c3b9899266
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075252708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.4075252708
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.2192136763
Short name T503
Test name
Test status
Simulation time 2231752428 ps
CPU time 65.12 seconds
Started Mar 19 12:45:30 PM PDT 24
Finished Mar 19 12:46:36 PM PDT 24
Peak memory 200456 kb
Host smart-b508a101-f2f5-4f22-b0cb-0324551a8a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192136763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.2192136763
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.613781443
Short name T198
Test name
Test status
Simulation time 606912511 ps
CPU time 6.93 seconds
Started Mar 19 12:45:30 PM PDT 24
Finished Mar 19 12:45:37 PM PDT 24
Peak memory 200372 kb
Host smart-71645aa6-39d4-4d3e-84a4-0cdfc8d9c9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613781443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.613781443
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.3261720874
Short name T426
Test name
Test status
Simulation time 4890542720 ps
CPU time 9.23 seconds
Started Mar 19 12:45:45 PM PDT 24
Finished Mar 19 12:45:54 PM PDT 24
Peak memory 200400 kb
Host smart-bceb5d82-0a03-424c-845c-9a06e0bae082
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261720874 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.3261720874
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.1465014393
Short name T257
Test name
Test status
Simulation time 216868546 ps
CPU time 1.03 seconds
Started Mar 19 12:45:39 PM PDT 24
Finished Mar 19 12:45:40 PM PDT 24
Peak memory 198648 kb
Host smart-88b9b020-be09-4b26-a7ed-9b8e58ee8434
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465014393 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.1465014393
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.3098680479
Short name T260
Test name
Test status
Simulation time 31616322680 ps
CPU time 427.53 seconds
Started Mar 19 12:45:30 PM PDT 24
Finished Mar 19 12:52:39 PM PDT 24
Peak memory 200392 kb
Host smart-a72d3269-d78c-4478-a4b0-d20dc928651f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098680479 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.3098680479
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.169238293
Short name T567
Test name
Test status
Simulation time 4278886739 ps
CPU time 63.42 seconds
Started Mar 19 12:45:29 PM PDT 24
Finished Mar 19 12:46:33 PM PDT 24
Peak memory 200496 kb
Host smart-2b3aba8f-d118-4bb3-bff5-c3a04d12fbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169238293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.169238293
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3838347315
Short name T24
Test name
Test status
Simulation time 20367786 ps
CPU time 0.58 seconds
Started Mar 19 12:45:32 PM PDT 24
Finished Mar 19 12:45:32 PM PDT 24
Peak memory 195564 kb
Host smart-58e4f877-74a8-48dd-a545-8a8ef1897dd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838347315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3838347315
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.872892256
Short name T574
Test name
Test status
Simulation time 13042328666 ps
CPU time 25.14 seconds
Started Mar 19 12:45:31 PM PDT 24
Finished Mar 19 12:45:57 PM PDT 24
Peak memory 222976 kb
Host smart-a8c2ab30-62ec-4922-84ca-135770cf6c58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=872892256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.872892256
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1625915856
Short name T205
Test name
Test status
Simulation time 1010894812 ps
CPU time 21.16 seconds
Started Mar 19 12:45:32 PM PDT 24
Finished Mar 19 12:45:53 PM PDT 24
Peak memory 200132 kb
Host smart-d6649ed5-3709-4563-8709-e12fa5755c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625915856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1625915856
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.631239282
Short name T294
Test name
Test status
Simulation time 8218973020 ps
CPU time 122.45 seconds
Started Mar 19 12:45:31 PM PDT 24
Finished Mar 19 12:47:34 PM PDT 24
Peak memory 200460 kb
Host smart-52a0b0b3-6701-4d84-aaac-ccf6a1605888
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=631239282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.631239282
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.10297309
Short name T16
Test name
Test status
Simulation time 3707547664 ps
CPU time 99.93 seconds
Started Mar 19 12:45:30 PM PDT 24
Finished Mar 19 12:47:11 PM PDT 24
Peak memory 200444 kb
Host smart-23171b4e-0bed-44eb-b039-d2889e8e747e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10297309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.10297309
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2013091987
Short name T62
Test name
Test status
Simulation time 1157695763 ps
CPU time 16.78 seconds
Started Mar 19 12:45:30 PM PDT 24
Finished Mar 19 12:45:48 PM PDT 24
Peak memory 200332 kb
Host smart-2839be04-b949-40e9-9780-0a64f80c44fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013091987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2013091987
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2705469177
Short name T345
Test name
Test status
Simulation time 955766374 ps
CPU time 3.81 seconds
Started Mar 19 12:45:32 PM PDT 24
Finished Mar 19 12:45:36 PM PDT 24
Peak memory 200376 kb
Host smart-26783186-eb9a-461a-a79b-39ce6fa4a272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705469177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2705469177
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.1682445598
Short name T133
Test name
Test status
Simulation time 73267499 ps
CPU time 0.98 seconds
Started Mar 19 12:45:37 PM PDT 24
Finished Mar 19 12:45:38 PM PDT 24
Peak memory 199144 kb
Host smart-73446064-2cee-4835-bc0a-3991accefea9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682445598 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.1682445598
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.1986500978
Short name T243
Test name
Test status
Simulation time 7645990915 ps
CPU time 408.33 seconds
Started Mar 19 12:45:31 PM PDT 24
Finished Mar 19 12:52:20 PM PDT 24
Peak memory 200436 kb
Host smart-b954e50d-b4a8-4763-bd9f-24a1a758e78e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986500978 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.1986500978
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1541936113
Short name T97
Test name
Test status
Simulation time 15837211829 ps
CPU time 80.8 seconds
Started Mar 19 12:45:31 PM PDT 24
Finished Mar 19 12:46:52 PM PDT 24
Peak memory 200556 kb
Host smart-fdd82b05-1fbe-4f3b-bde3-aa27c08267f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541936113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1541936113
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.848379360
Short name T403
Test name
Test status
Simulation time 12192273 ps
CPU time 0.57 seconds
Started Mar 19 12:45:37 PM PDT 24
Finished Mar 19 12:45:38 PM PDT 24
Peak memory 195784 kb
Host smart-0dfcc782-ab12-40b6-a3be-cbdd27789c0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848379360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.848379360
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.289308519
Short name T554
Test name
Test status
Simulation time 2067377153 ps
CPU time 63.24 seconds
Started Mar 19 12:45:43 PM PDT 24
Finished Mar 19 12:46:46 PM PDT 24
Peak memory 226044 kb
Host smart-5c80acc9-fe94-43bc-8cd3-032a26909b87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=289308519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.289308519
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.802762098
Short name T137
Test name
Test status
Simulation time 1083022017 ps
CPU time 11 seconds
Started Mar 19 12:45:41 PM PDT 24
Finished Mar 19 12:45:53 PM PDT 24
Peak memory 200428 kb
Host smart-fae4d4b0-705c-4ba5-9c0b-b9ae386b7949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802762098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.802762098
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2439627004
Short name T529
Test name
Test status
Simulation time 9466787427 ps
CPU time 139.02 seconds
Started Mar 19 12:45:41 PM PDT 24
Finished Mar 19 12:48:00 PM PDT 24
Peak memory 200536 kb
Host smart-1a29e9c2-c024-46be-9036-202ec5519377
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2439627004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2439627004
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1958609762
Short name T565
Test name
Test status
Simulation time 2649675445 ps
CPU time 35.84 seconds
Started Mar 19 12:45:41 PM PDT 24
Finished Mar 19 12:46:17 PM PDT 24
Peak memory 200460 kb
Host smart-6da8b79b-ff48-4756-90d4-a59756681d9b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958609762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1958609762
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.2664568416
Short name T404
Test name
Test status
Simulation time 26661925416 ps
CPU time 112.05 seconds
Started Mar 19 12:45:45 PM PDT 24
Finished Mar 19 12:47:38 PM PDT 24
Peak memory 200512 kb
Host smart-d57cd0fd-9e61-46c8-8a66-1682f49155a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664568416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2664568416
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1833141708
Short name T303
Test name
Test status
Simulation time 398783053 ps
CPU time 7.08 seconds
Started Mar 19 12:45:44 PM PDT 24
Finished Mar 19 12:45:51 PM PDT 24
Peak memory 200364 kb
Host smart-83cdda8f-a85d-4f89-b8ea-ba8bed99653d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833141708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1833141708
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3487698633
Short name T362
Test name
Test status
Simulation time 4092620923 ps
CPU time 61.55 seconds
Started Mar 19 12:45:39 PM PDT 24
Finished Mar 19 12:46:41 PM PDT 24
Peak memory 246896 kb
Host smart-5290ce0a-85bd-4a65-ba6e-87185e4303c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487698633 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3487698633
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.1001729002
Short name T327
Test name
Test status
Simulation time 250093506 ps
CPU time 1.23 seconds
Started Mar 19 12:45:36 PM PDT 24
Finished Mar 19 12:45:37 PM PDT 24
Peak memory 200364 kb
Host smart-b231a4a8-e645-4c3e-9ddc-414c1221f444
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001729002 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.1001729002
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.2446958993
Short name T382
Test name
Test status
Simulation time 16623537970 ps
CPU time 436.02 seconds
Started Mar 19 12:45:44 PM PDT 24
Finished Mar 19 12:53:00 PM PDT 24
Peak memory 200436 kb
Host smart-3bc39790-b6cc-4fa3-9fa6-4dc690e05ca0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446958993 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.2446958993
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.1803949436
Short name T60
Test name
Test status
Simulation time 1864476979 ps
CPU time 71.66 seconds
Started Mar 19 12:45:39 PM PDT 24
Finished Mar 19 12:46:51 PM PDT 24
Peak memory 200436 kb
Host smart-7ba1fded-d700-4824-b6c1-0dbaaf9d6d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803949436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1803949436
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.1163412645
Short name T384
Test name
Test status
Simulation time 175463575 ps
CPU time 0.55 seconds
Started Mar 19 12:45:38 PM PDT 24
Finished Mar 19 12:45:39 PM PDT 24
Peak memory 195880 kb
Host smart-d64d65f9-7df3-47b9-a246-6e38719dcfc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163412645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1163412645
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.843300178
Short name T365
Test name
Test status
Simulation time 1715172435 ps
CPU time 57.04 seconds
Started Mar 19 12:45:37 PM PDT 24
Finished Mar 19 12:46:35 PM PDT 24
Peak memory 231396 kb
Host smart-dbe9b62f-e2a0-4217-893b-0ff4ab5b99a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=843300178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.843300178
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.13720214
Short name T279
Test name
Test status
Simulation time 358139683 ps
CPU time 17.36 seconds
Started Mar 19 12:45:39 PM PDT 24
Finished Mar 19 12:45:56 PM PDT 24
Peak memory 200420 kb
Host smart-4d3ffdc5-d902-4e9f-87e5-b58f9854821b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13720214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.13720214
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.2232622599
Short name T138
Test name
Test status
Simulation time 1917950073 ps
CPU time 116.7 seconds
Started Mar 19 12:45:42 PM PDT 24
Finished Mar 19 12:47:39 PM PDT 24
Peak memory 200472 kb
Host smart-875384da-0d8d-4675-97f7-56668780f3b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2232622599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2232622599
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1025697631
Short name T196
Test name
Test status
Simulation time 12276692245 ps
CPU time 170.8 seconds
Started Mar 19 12:45:42 PM PDT 24
Finished Mar 19 12:48:33 PM PDT 24
Peak memory 200436 kb
Host smart-6a8c39c3-aac8-49ad-8679-f638c785df64
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025697631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1025697631
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3789364536
Short name T126
Test name
Test status
Simulation time 109392784 ps
CPU time 6.97 seconds
Started Mar 19 12:45:43 PM PDT 24
Finished Mar 19 12:45:50 PM PDT 24
Peak memory 200360 kb
Host smart-fdbe0085-78c7-4e3e-92c0-6ad3edabf82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789364536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3789364536
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2797741697
Short name T548
Test name
Test status
Simulation time 165154097 ps
CPU time 2.37 seconds
Started Mar 19 12:45:43 PM PDT 24
Finished Mar 19 12:45:46 PM PDT 24
Peak memory 200512 kb
Host smart-8605bdd0-23b1-4d42-82fe-d3b383d5eab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797741697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2797741697
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.2575406271
Short name T522
Test name
Test status
Simulation time 72796423559 ps
CPU time 686 seconds
Started Mar 19 12:45:45 PM PDT 24
Finished Mar 19 12:57:11 PM PDT 24
Peak memory 224980 kb
Host smart-e4703c63-9edc-43af-9533-17f201758ffb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575406271 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2575406271
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.3647176447
Short name T573
Test name
Test status
Simulation time 170923906 ps
CPU time 1.12 seconds
Started Mar 19 12:45:46 PM PDT 24
Finished Mar 19 12:45:48 PM PDT 24
Peak memory 199672 kb
Host smart-dfb1847e-342d-4fec-b624-909f8cae452e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647176447 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.3647176447
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.3080468146
Short name T540
Test name
Test status
Simulation time 28712391489 ps
CPU time 524.39 seconds
Started Mar 19 12:45:44 PM PDT 24
Finished Mar 19 12:54:29 PM PDT 24
Peak memory 200388 kb
Host smart-6606fd64-789a-4dff-b5c7-42197fd7fdee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080468146 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.3080468146
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2427293444
Short name T164
Test name
Test status
Simulation time 29275972750 ps
CPU time 76.07 seconds
Started Mar 19 12:45:37 PM PDT 24
Finished Mar 19 12:46:53 PM PDT 24
Peak memory 200436 kb
Host smart-834c67df-d158-4bc9-b968-245bea6ab5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427293444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2427293444
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2440408049
Short name T347
Test name
Test status
Simulation time 67710444 ps
CPU time 0.64 seconds
Started Mar 19 12:45:43 PM PDT 24
Finished Mar 19 12:45:44 PM PDT 24
Peak memory 195540 kb
Host smart-8b08b94f-284b-419c-b0e9-bcec50c23b6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440408049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2440408049
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.3509810467
Short name T39
Test name
Test status
Simulation time 497008971 ps
CPU time 17.74 seconds
Started Mar 19 12:45:49 PM PDT 24
Finished Mar 19 12:46:07 PM PDT 24
Peak memory 208624 kb
Host smart-fc9f4a56-d5b3-4b5e-a1be-b9af462ae9cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3509810467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3509810467
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2866452480
Short name T275
Test name
Test status
Simulation time 3234751385 ps
CPU time 81.41 seconds
Started Mar 19 12:45:42 PM PDT 24
Finished Mar 19 12:47:03 PM PDT 24
Peak memory 200416 kb
Host smart-e6c7bd86-495e-42f5-a957-b094cece0563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866452480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2866452480
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3908310510
Short name T159
Test name
Test status
Simulation time 4112099348 ps
CPU time 59.33 seconds
Started Mar 19 12:45:40 PM PDT 24
Finished Mar 19 12:46:40 PM PDT 24
Peak memory 200512 kb
Host smart-46346677-b79a-46bc-bc50-440a91d3326a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3908310510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3908310510
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_long_msg.2968320562
Short name T349
Test name
Test status
Simulation time 56573769 ps
CPU time 0.79 seconds
Started Mar 19 12:45:44 PM PDT 24
Finished Mar 19 12:45:45 PM PDT 24
Peak memory 197436 kb
Host smart-e7979e1c-c81e-4f81-9489-232fd5dc93d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968320562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.2968320562
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.3775804222
Short name T203
Test name
Test status
Simulation time 395742261 ps
CPU time 1.53 seconds
Started Mar 19 12:45:35 PM PDT 24
Finished Mar 19 12:45:37 PM PDT 24
Peak memory 200328 kb
Host smart-b0d9c248-3ac8-4870-9828-1706023cde67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775804222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3775804222
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.798197149
Short name T541
Test name
Test status
Simulation time 38113521251 ps
CPU time 503.13 seconds
Started Mar 19 12:45:36 PM PDT 24
Finished Mar 19 12:54:00 PM PDT 24
Peak memory 233280 kb
Host smart-23ed869c-fb10-4e97-841d-893412d8b042
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798197149 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.798197149
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.1037113169
Short name T505
Test name
Test status
Simulation time 61978758 ps
CPU time 1.24 seconds
Started Mar 19 12:45:38 PM PDT 24
Finished Mar 19 12:45:40 PM PDT 24
Peak memory 200364 kb
Host smart-f6c1df81-ce6a-47af-a954-2494f4a5b5d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037113169 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.1037113169
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.2492154781
Short name T288
Test name
Test status
Simulation time 219373615060 ps
CPU time 565.32 seconds
Started Mar 19 12:45:45 PM PDT 24
Finished Mar 19 12:55:10 PM PDT 24
Peak memory 200384 kb
Host smart-30b6c745-2f05-4346-9525-a632c848a5c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492154781 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.2492154781
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.3783603554
Short name T190
Test name
Test status
Simulation time 18106859606 ps
CPU time 70.91 seconds
Started Mar 19 12:45:49 PM PDT 24
Finished Mar 19 12:47:00 PM PDT 24
Peak memory 200484 kb
Host smart-41235c6e-359b-4c57-bb24-11725a51e21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783603554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3783603554
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1457648695
Short name T438
Test name
Test status
Simulation time 14090948 ps
CPU time 0.6 seconds
Started Mar 19 12:45:43 PM PDT 24
Finished Mar 19 12:45:44 PM PDT 24
Peak memory 195884 kb
Host smart-dab0fd77-baec-4ef6-b979-1eb7015c559e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457648695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1457648695
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.309801274
Short name T54
Test name
Test status
Simulation time 3137027126 ps
CPU time 29.34 seconds
Started Mar 19 12:45:45 PM PDT 24
Finished Mar 19 12:46:14 PM PDT 24
Peak memory 239348 kb
Host smart-2918be7d-2ec5-4102-a728-0ecc11b45b87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=309801274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.309801274
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.194173164
Short name T332
Test name
Test status
Simulation time 4360876113 ps
CPU time 55.59 seconds
Started Mar 19 12:45:42 PM PDT 24
Finished Mar 19 12:46:38 PM PDT 24
Peak memory 200480 kb
Host smart-10ddf1f2-967e-439f-be8f-e5f63d042386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194173164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.194173164
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2010863857
Short name T499
Test name
Test status
Simulation time 2068316703 ps
CPU time 117.74 seconds
Started Mar 19 12:45:42 PM PDT 24
Finished Mar 19 12:47:40 PM PDT 24
Peak memory 200400 kb
Host smart-610ecfde-a1e2-49b5-9274-51912cf7263b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2010863857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2010863857
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.45302596
Short name T40
Test name
Test status
Simulation time 12155098044 ps
CPU time 72.92 seconds
Started Mar 19 12:45:52 PM PDT 24
Finished Mar 19 12:47:05 PM PDT 24
Peak memory 200452 kb
Host smart-84c31be6-f17a-4234-857d-1c14952515ac
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45302596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.45302596
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3118438520
Short name T480
Test name
Test status
Simulation time 7498335033 ps
CPU time 51.1 seconds
Started Mar 19 12:45:46 PM PDT 24
Finished Mar 19 12:46:37 PM PDT 24
Peak memory 200432 kb
Host smart-22d85f89-d6c6-4e63-8576-e83326e6613f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118438520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3118438520
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2988190287
Short name T246
Test name
Test status
Simulation time 358332954 ps
CPU time 5.55 seconds
Started Mar 19 12:45:41 PM PDT 24
Finished Mar 19 12:45:47 PM PDT 24
Peak memory 200392 kb
Host smart-7662302a-502b-4dce-a024-0af93210b769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988190287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2988190287
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.2935797250
Short name T447
Test name
Test status
Simulation time 61913144352 ps
CPU time 2799.65 seconds
Started Mar 19 12:45:45 PM PDT 24
Finished Mar 19 01:32:25 PM PDT 24
Peak memory 200416 kb
Host smart-52d02338-bea2-40a8-816b-060aed9bb2e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935797250 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2935797250
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.1632971882
Short name T466
Test name
Test status
Simulation time 181681175 ps
CPU time 0.99 seconds
Started Mar 19 12:45:43 PM PDT 24
Finished Mar 19 12:45:44 PM PDT 24
Peak memory 199652 kb
Host smart-cb203974-c865-44f7-8ced-b95197309a59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632971882 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.1632971882
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.107690791
Short name T530
Test name
Test status
Simulation time 181122760357 ps
CPU time 568.22 seconds
Started Mar 19 12:45:45 PM PDT 24
Finished Mar 19 12:55:13 PM PDT 24
Peak memory 200400 kb
Host smart-4e18d3cc-ccf8-4e57-9f74-dc1527c1fcc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107690791 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.107690791
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1374871080
Short name T183
Test name
Test status
Simulation time 5675100215 ps
CPU time 82.38 seconds
Started Mar 19 12:45:44 PM PDT 24
Finished Mar 19 12:47:06 PM PDT 24
Peak memory 200460 kb
Host smart-6b652fac-bb2a-4e02-989c-b3c3789f70f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374871080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1374871080
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.2981763354
Short name T483
Test name
Test status
Simulation time 11700238 ps
CPU time 0.63 seconds
Started Mar 19 12:45:50 PM PDT 24
Finished Mar 19 12:45:51 PM PDT 24
Peak memory 195752 kb
Host smart-dca228aa-67b8-4f44-ae62-3b8af252cec5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981763354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2981763354
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1937403542
Short name T459
Test name
Test status
Simulation time 2595745189 ps
CPU time 49.18 seconds
Started Mar 19 12:45:47 PM PDT 24
Finished Mar 19 12:46:37 PM PDT 24
Peak memory 216488 kb
Host smart-a6cf20e8-6863-4b99-8f21-bb40ea016123
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1937403542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1937403542
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1301080671
Short name T437
Test name
Test status
Simulation time 4271256607 ps
CPU time 31.97 seconds
Started Mar 19 12:45:44 PM PDT 24
Finished Mar 19 12:46:16 PM PDT 24
Peak memory 200428 kb
Host smart-167dcd3f-c817-4d5a-b263-1b8c8f3b67ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301080671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1301080671
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3610491930
Short name T498
Test name
Test status
Simulation time 1641152588 ps
CPU time 91.43 seconds
Started Mar 19 12:45:41 PM PDT 24
Finished Mar 19 12:47:13 PM PDT 24
Peak memory 200404 kb
Host smart-c9b4e825-6a06-4a5c-b847-51774608af55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3610491930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3610491930
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.103241972
Short name T52
Test name
Test status
Simulation time 105135968632 ps
CPU time 167.07 seconds
Started Mar 19 12:45:44 PM PDT 24
Finished Mar 19 12:48:31 PM PDT 24
Peak memory 200464 kb
Host smart-23718c05-d250-4a58-889b-eb6216bef9ee
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103241972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.103241972
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1379402939
Short name T395
Test name
Test status
Simulation time 18104042779 ps
CPU time 84.47 seconds
Started Mar 19 12:45:52 PM PDT 24
Finished Mar 19 12:47:16 PM PDT 24
Peak memory 200448 kb
Host smart-f56f702b-728f-41eb-9a7f-0f0d080aa24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379402939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1379402939
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.4188807906
Short name T48
Test name
Test status
Simulation time 215189017 ps
CPU time 3.92 seconds
Started Mar 19 12:45:45 PM PDT 24
Finished Mar 19 12:45:49 PM PDT 24
Peak memory 200380 kb
Host smart-81666d7c-f67e-4a96-8128-adf154936d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188807906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.4188807906
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2100619355
Short name T555
Test name
Test status
Simulation time 20674543562 ps
CPU time 1103.34 seconds
Started Mar 19 12:45:55 PM PDT 24
Finished Mar 19 01:04:18 PM PDT 24
Peak memory 200456 kb
Host smart-5f811292-e8d6-4297-863a-27a999c0e85b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100619355 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2100619355
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.72715434
Short name T1
Test name
Test status
Simulation time 106930155 ps
CPU time 1.24 seconds
Started Mar 19 12:45:57 PM PDT 24
Finished Mar 19 12:45:58 PM PDT 24
Peak memory 200268 kb
Host smart-b1bdaf73-59e0-4b38-9f51-d41498012026
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72715434 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 37.hmac_test_hmac_vectors.72715434
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.306451454
Short name T306
Test name
Test status
Simulation time 7328991025 ps
CPU time 410.18 seconds
Started Mar 19 12:45:59 PM PDT 24
Finished Mar 19 12:52:49 PM PDT 24
Peak memory 200400 kb
Host smart-5d93c8c3-6ff1-4fb1-bf0e-f254ab746c96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306451454 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.306451454
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3282152352
Short name T458
Test name
Test status
Simulation time 26482844414 ps
CPU time 66.83 seconds
Started Mar 19 12:45:47 PM PDT 24
Finished Mar 19 12:46:54 PM PDT 24
Peak memory 200412 kb
Host smart-d96036bf-bfa7-4a68-9a41-3464ec2d48cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282152352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3282152352
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3433053922
Short name T317
Test name
Test status
Simulation time 14209461 ps
CPU time 0.56 seconds
Started Mar 19 12:45:47 PM PDT 24
Finished Mar 19 12:45:48 PM PDT 24
Peak memory 195964 kb
Host smart-66fb54c7-ed76-4fa4-9111-1786f2a13e2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433053922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3433053922
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.705308561
Short name T472
Test name
Test status
Simulation time 11655606278 ps
CPU time 59.12 seconds
Started Mar 19 12:45:47 PM PDT 24
Finished Mar 19 12:46:46 PM PDT 24
Peak memory 241456 kb
Host smart-7d3deacd-e157-4d7f-9d13-321b2baebfa0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=705308561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.705308561
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3602805251
Short name T506
Test name
Test status
Simulation time 814107333 ps
CPU time 17.66 seconds
Started Mar 19 12:45:55 PM PDT 24
Finished Mar 19 12:46:13 PM PDT 24
Peak memory 200440 kb
Host smart-8b0b9032-0e58-44fc-ad90-44510f9f4f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602805251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3602805251
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.4054948759
Short name T352
Test name
Test status
Simulation time 200201274 ps
CPU time 5.05 seconds
Started Mar 19 12:45:57 PM PDT 24
Finished Mar 19 12:46:02 PM PDT 24
Peak memory 200484 kb
Host smart-f1461922-7c92-4c18-a110-ecbd27617177
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4054948759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.4054948759
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.577442847
Short name T17
Test name
Test status
Simulation time 4507330779 ps
CPU time 67.28 seconds
Started Mar 19 12:45:48 PM PDT 24
Finished Mar 19 12:46:56 PM PDT 24
Peak memory 200500 kb
Host smart-d53d54e9-551c-4533-8390-7962d8733bf7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577442847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.577442847
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3996682864
Short name T467
Test name
Test status
Simulation time 3704316009 ps
CPU time 52.88 seconds
Started Mar 19 12:45:53 PM PDT 24
Finished Mar 19 12:46:46 PM PDT 24
Peak memory 200444 kb
Host smart-adc6776c-0790-4af5-bdba-f9228b926f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996682864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3996682864
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1036482847
Short name T235
Test name
Test status
Simulation time 475396087 ps
CPU time 4.29 seconds
Started Mar 19 12:45:49 PM PDT 24
Finished Mar 19 12:45:54 PM PDT 24
Peak memory 200372 kb
Host smart-3b8dc0de-8330-4cfd-b4a4-991a738447f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036482847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1036482847
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3892693991
Short name T122
Test name
Test status
Simulation time 17337505009 ps
CPU time 457.83 seconds
Started Mar 19 12:45:48 PM PDT 24
Finished Mar 19 12:53:26 PM PDT 24
Peak memory 200452 kb
Host smart-1cdaa987-9c40-4f9e-bb95-8f8837cc582c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892693991 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3892693991
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.2055275039
Short name T475
Test name
Test status
Simulation time 27338039 ps
CPU time 0.98 seconds
Started Mar 19 12:45:56 PM PDT 24
Finished Mar 19 12:45:58 PM PDT 24
Peak memory 198840 kb
Host smart-1a9e58f2-5c45-44d3-a169-8f53412465b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055275039 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.2055275039
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.554630968
Short name T588
Test name
Test status
Simulation time 81362447419 ps
CPU time 554.58 seconds
Started Mar 19 12:45:58 PM PDT 24
Finished Mar 19 12:55:13 PM PDT 24
Peak memory 200480 kb
Host smart-fd43226c-171b-47c3-9738-e467a307c146
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554630968 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.554630968
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.3799458745
Short name T166
Test name
Test status
Simulation time 268853621 ps
CPU time 10.89 seconds
Started Mar 19 12:45:50 PM PDT 24
Finished Mar 19 12:46:01 PM PDT 24
Peak memory 200376 kb
Host smart-47750a5b-1358-4c6c-b4cf-a03b608cb4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799458745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.3799458745
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.675231143
Short name T251
Test name
Test status
Simulation time 89996908 ps
CPU time 0.59 seconds
Started Mar 19 12:45:53 PM PDT 24
Finished Mar 19 12:45:54 PM PDT 24
Peak memory 195920 kb
Host smart-eb6f8925-b751-4b55-8332-f099a549e41c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675231143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.675231143
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1720384316
Short name T451
Test name
Test status
Simulation time 3155361595 ps
CPU time 58.89 seconds
Started Mar 19 12:45:58 PM PDT 24
Finished Mar 19 12:46:58 PM PDT 24
Peak memory 233216 kb
Host smart-c792beb6-b325-4470-a6f3-4a7ae9c53d41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1720384316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1720384316
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3266718586
Short name T265
Test name
Test status
Simulation time 1291259317 ps
CPU time 64.21 seconds
Started Mar 19 12:45:59 PM PDT 24
Finished Mar 19 12:47:04 PM PDT 24
Peak memory 200356 kb
Host smart-38f6b1d9-c915-42a7-973a-195cbc687e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266718586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3266718586
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.4231195171
Short name T476
Test name
Test status
Simulation time 2048877322 ps
CPU time 121.09 seconds
Started Mar 19 12:45:59 PM PDT 24
Finished Mar 19 12:48:01 PM PDT 24
Peak memory 200384 kb
Host smart-490bfeb5-37e6-439e-a84d-a2a359f2e5a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231195171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.4231195171
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.2045430951
Short name T510
Test name
Test status
Simulation time 14097595354 ps
CPU time 59.97 seconds
Started Mar 19 12:45:54 PM PDT 24
Finished Mar 19 12:46:54 PM PDT 24
Peak memory 200508 kb
Host smart-289d1788-28d6-4939-8fe5-abbf2e539bfc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045430951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.2045430951
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3137900056
Short name T360
Test name
Test status
Simulation time 5087346886 ps
CPU time 74.73 seconds
Started Mar 19 12:45:57 PM PDT 24
Finished Mar 19 12:47:13 PM PDT 24
Peak memory 200460 kb
Host smart-28256da4-61ee-4760-a6b3-843cd159b611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137900056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3137900056
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2603585187
Short name T331
Test name
Test status
Simulation time 96622130 ps
CPU time 2.75 seconds
Started Mar 19 12:45:55 PM PDT 24
Finished Mar 19 12:45:58 PM PDT 24
Peak memory 200436 kb
Host smart-75fac0dc-e6ef-4018-99b9-b73992899ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603585187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2603585187
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.84967227
Short name T89
Test name
Test status
Simulation time 413766109206 ps
CPU time 1312.63 seconds
Started Mar 19 12:45:53 PM PDT 24
Finished Mar 19 01:07:46 PM PDT 24
Peak memory 200460 kb
Host smart-638f1522-d74d-4735-9432-675041532146
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84967227 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.84967227
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.3300016913
Short name T149
Test name
Test status
Simulation time 32401311 ps
CPU time 1.25 seconds
Started Mar 19 12:45:55 PM PDT 24
Finished Mar 19 12:45:56 PM PDT 24
Peak memory 200420 kb
Host smart-d7c077ae-c328-40f6-983a-a6f33a34b7c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300016913 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.3300016913
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.1978706224
Short name T162
Test name
Test status
Simulation time 168457944493 ps
CPU time 517.32 seconds
Started Mar 19 12:45:58 PM PDT 24
Finished Mar 19 12:54:35 PM PDT 24
Peak memory 200396 kb
Host smart-8d52dac6-97f5-4825-ae0a-b91f298a92e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978706224 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.1978706224
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.772261500
Short name T520
Test name
Test status
Simulation time 16035782416 ps
CPU time 70.68 seconds
Started Mar 19 12:45:54 PM PDT 24
Finished Mar 19 12:47:05 PM PDT 24
Peak memory 200492 kb
Host smart-b74b1ae5-51cf-4b2e-b9c4-7ad5f02da507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772261500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.772261500
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3850559187
Short name T283
Test name
Test status
Simulation time 12813047 ps
CPU time 0.57 seconds
Started Mar 19 12:44:46 PM PDT 24
Finished Mar 19 12:44:47 PM PDT 24
Peak memory 195832 kb
Host smart-b0cd3293-fa03-457a-bbf9-336e9124cc62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850559187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3850559187
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.4086406983
Short name T479
Test name
Test status
Simulation time 1392133742 ps
CPU time 48.65 seconds
Started Mar 19 12:44:41 PM PDT 24
Finished Mar 19 12:45:30 PM PDT 24
Peak memory 209488 kb
Host smart-ad4d35ac-e8eb-4186-8651-fe10bd9bd52a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4086406983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.4086406983
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3916107586
Short name T589
Test name
Test status
Simulation time 1009697988 ps
CPU time 49.24 seconds
Started Mar 19 12:44:48 PM PDT 24
Finished Mar 19 12:45:37 PM PDT 24
Peak memory 200364 kb
Host smart-c0175a5c-34a6-4a98-851a-c74c82c04fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916107586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3916107586
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.4038458009
Short name T168
Test name
Test status
Simulation time 27721869589 ps
CPU time 113.69 seconds
Started Mar 19 12:44:41 PM PDT 24
Finished Mar 19 12:46:35 PM PDT 24
Peak memory 200348 kb
Host smart-83e96c96-af58-4e1d-93de-7ab8d03781fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4038458009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.4038458009
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2510193954
Short name T13
Test name
Test status
Simulation time 11159530769 ps
CPU time 185.52 seconds
Started Mar 19 12:46:11 PM PDT 24
Finished Mar 19 12:49:17 PM PDT 24
Peak memory 197708 kb
Host smart-dcc307dd-ec77-4575-b9ce-ef94b5c98100
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510193954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2510193954
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1038123848
Short name T299
Test name
Test status
Simulation time 656539327 ps
CPU time 35.52 seconds
Started Mar 19 12:46:11 PM PDT 24
Finished Mar 19 12:46:47 PM PDT 24
Peak memory 197636 kb
Host smart-2161d56e-4f25-4a8c-b215-f5ce81355644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038123848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1038123848
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.55791465
Short name T37
Test name
Test status
Simulation time 63933634 ps
CPU time 0.86 seconds
Started Mar 19 12:44:52 PM PDT 24
Finished Mar 19 12:44:53 PM PDT 24
Peak memory 218800 kb
Host smart-8e418849-71ae-4092-9bfa-55d18c420ffe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55791465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.55791465
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.252114900
Short name T45
Test name
Test status
Simulation time 2587730248 ps
CPU time 5.45 seconds
Started Mar 19 12:46:21 PM PDT 24
Finished Mar 19 12:46:26 PM PDT 24
Peak memory 200244 kb
Host smart-c5a3fb40-256e-423a-baab-f29ce39d0ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252114900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.252114900
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2928005682
Short name T266
Test name
Test status
Simulation time 164272670379 ps
CPU time 1520.62 seconds
Started Mar 19 12:44:50 PM PDT 24
Finished Mar 19 01:10:11 PM PDT 24
Peak memory 216920 kb
Host smart-0ece37de-1293-447d-b785-48d3fa347020
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928005682 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2928005682
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.1977929036
Short name T155
Test name
Test status
Simulation time 33237032 ps
CPU time 1.24 seconds
Started Mar 19 12:44:49 PM PDT 24
Finished Mar 19 12:44:51 PM PDT 24
Peak memory 200316 kb
Host smart-9f14567c-b829-452c-9bc0-8566e049bbfa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977929036 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.1977929036
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.445271952
Short name T238
Test name
Test status
Simulation time 126015457256 ps
CPU time 565.7 seconds
Started Mar 19 12:44:42 PM PDT 24
Finished Mar 19 12:54:08 PM PDT 24
Peak memory 200404 kb
Host smart-6a776680-b207-4913-b6db-43a067ccd510
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445271952 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.445271952
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2600072250
Short name T302
Test name
Test status
Simulation time 5048659384 ps
CPU time 71.55 seconds
Started Mar 19 12:44:42 PM PDT 24
Finished Mar 19 12:45:54 PM PDT 24
Peak memory 200432 kb
Host smart-bb9d5ee5-d34f-4272-8593-a6628dec70d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600072250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2600072250
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3114991283
Short name T407
Test name
Test status
Simulation time 14807695 ps
CPU time 0.62 seconds
Started Mar 19 12:45:58 PM PDT 24
Finished Mar 19 12:45:59 PM PDT 24
Peak memory 195908 kb
Host smart-8a6a8abe-f25b-4178-8a53-74d9c1e296c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114991283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3114991283
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.2060420314
Short name T435
Test name
Test status
Simulation time 1450816954 ps
CPU time 57.51 seconds
Started Mar 19 12:46:02 PM PDT 24
Finished Mar 19 12:47:00 PM PDT 24
Peak memory 241352 kb
Host smart-f393256a-d3d3-4f2e-9a48-bfa720948b17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2060420314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2060420314
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.425560129
Short name T304
Test name
Test status
Simulation time 2345719235 ps
CPU time 54.71 seconds
Started Mar 19 12:46:01 PM PDT 24
Finished Mar 19 12:46:56 PM PDT 24
Peak memory 200432 kb
Host smart-68f7cdad-fcb7-4f41-b9f7-91b320e99fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425560129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.425560129
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3921960214
Short name T280
Test name
Test status
Simulation time 1396406216 ps
CPU time 77.77 seconds
Started Mar 19 12:45:56 PM PDT 24
Finished Mar 19 12:47:13 PM PDT 24
Peak memory 200384 kb
Host smart-9feccaaf-c916-4741-bfbc-09897e245000
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3921960214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3921960214
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2474129752
Short name T527
Test name
Test status
Simulation time 43500068816 ps
CPU time 201.43 seconds
Started Mar 19 12:46:02 PM PDT 24
Finished Mar 19 12:49:24 PM PDT 24
Peak memory 200448 kb
Host smart-b4c450d2-dcb5-4ee6-8eab-414a3a4e96a0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474129752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2474129752
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3782493671
Short name T224
Test name
Test status
Simulation time 10618430982 ps
CPU time 56.99 seconds
Started Mar 19 12:45:55 PM PDT 24
Finished Mar 19 12:46:52 PM PDT 24
Peak memory 200512 kb
Host smart-8bd2a4f5-f125-4b9a-97af-5ffc2cd5be59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782493671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3782493671
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1994877039
Short name T441
Test name
Test status
Simulation time 125645382 ps
CPU time 3.88 seconds
Started Mar 19 12:45:53 PM PDT 24
Finished Mar 19 12:45:57 PM PDT 24
Peak memory 200448 kb
Host smart-e456b60b-b2ad-4c66-83a0-e42366b624a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994877039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1994877039
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.298090884
Short name T114
Test name
Test status
Simulation time 44755690226 ps
CPU time 223.41 seconds
Started Mar 19 12:46:00 PM PDT 24
Finished Mar 19 12:49:44 PM PDT 24
Peak memory 233156 kb
Host smart-ad42efd5-cc4d-4c36-826f-b0047036fcd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298090884 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.298090884
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.3954504337
Short name T124
Test name
Test status
Simulation time 61257349 ps
CPU time 1.3 seconds
Started Mar 19 12:45:58 PM PDT 24
Finished Mar 19 12:46:00 PM PDT 24
Peak memory 200408 kb
Host smart-8b49103f-426e-4afa-ae92-a24b60e6be4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954504337 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.3954504337
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.3036597703
Short name T380
Test name
Test status
Simulation time 8367261230 ps
CPU time 454.11 seconds
Started Mar 19 12:46:04 PM PDT 24
Finished Mar 19 12:53:39 PM PDT 24
Peak memory 200360 kb
Host smart-d6ef625f-3e77-4a1f-ba24-37793264b992
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036597703 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.3036597703
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.32135099
Short name T152
Test name
Test status
Simulation time 1854909620 ps
CPU time 83.21 seconds
Started Mar 19 12:45:59 PM PDT 24
Finished Mar 19 12:47:22 PM PDT 24
Peak memory 200384 kb
Host smart-0877d8f4-8893-4a6b-931f-e3e6f4958e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32135099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.32135099
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1422550555
Short name T493
Test name
Test status
Simulation time 43750474 ps
CPU time 0.58 seconds
Started Mar 19 12:46:02 PM PDT 24
Finished Mar 19 12:46:03 PM PDT 24
Peak memory 195752 kb
Host smart-1e9bd6f3-637c-4b8f-844b-d4e7468e13cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422550555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1422550555
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2782083525
Short name T56
Test name
Test status
Simulation time 3196402945 ps
CPU time 27.07 seconds
Started Mar 19 12:45:59 PM PDT 24
Finished Mar 19 12:46:27 PM PDT 24
Peak memory 200444 kb
Host smart-37038375-52d8-4743-a342-62b2e5fb3c64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2782083525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2782083525
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3615201268
Short name T230
Test name
Test status
Simulation time 1156214903 ps
CPU time 12.44 seconds
Started Mar 19 12:46:01 PM PDT 24
Finished Mar 19 12:46:13 PM PDT 24
Peak memory 200384 kb
Host smart-890e73b3-3c06-4c4a-9046-fc1ab6ddfde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615201268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3615201268
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.3054608040
Short name T136
Test name
Test status
Simulation time 3315844980 ps
CPU time 96 seconds
Started Mar 19 12:45:59 PM PDT 24
Finished Mar 19 12:47:36 PM PDT 24
Peak memory 200436 kb
Host smart-5b8fdd38-c110-428e-89f5-66281fe928ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3054608040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.3054608040
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3444433882
Short name T31
Test name
Test status
Simulation time 9433943560 ps
CPU time 137.49 seconds
Started Mar 19 12:46:01 PM PDT 24
Finished Mar 19 12:48:19 PM PDT 24
Peak memory 200500 kb
Host smart-ad2d6f37-ab01-4ff1-a01f-8327ea1f760d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444433882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3444433882
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.795890321
Short name T400
Test name
Test status
Simulation time 9073143437 ps
CPU time 45.92 seconds
Started Mar 19 12:46:04 PM PDT 24
Finished Mar 19 12:46:50 PM PDT 24
Peak memory 200432 kb
Host smart-2cc86675-f40e-4f89-b6b1-60f3faec24a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795890321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.795890321
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1001734399
Short name T343
Test name
Test status
Simulation time 312935030 ps
CPU time 3.91 seconds
Started Mar 19 12:46:02 PM PDT 24
Finished Mar 19 12:46:07 PM PDT 24
Peak memory 200352 kb
Host smart-486c48d9-3e46-440d-b0ce-fbadae3b83f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001734399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1001734399
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1016282853
Short name T90
Test name
Test status
Simulation time 129801472377 ps
CPU time 891.12 seconds
Started Mar 19 12:46:03 PM PDT 24
Finished Mar 19 01:00:54 PM PDT 24
Peak memory 216928 kb
Host smart-53f42d85-8a0f-427e-8c3f-2bda1449ab16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016282853 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1016282853
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.2405480212
Short name T309
Test name
Test status
Simulation time 292325785 ps
CPU time 1.36 seconds
Started Mar 19 12:46:01 PM PDT 24
Finished Mar 19 12:46:02 PM PDT 24
Peak memory 199368 kb
Host smart-60bb7546-4e00-44f4-94f5-c073fc672682
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405480212 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.2405480212
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.940197571
Short name T249
Test name
Test status
Simulation time 8825439777 ps
CPU time 490.77 seconds
Started Mar 19 12:46:05 PM PDT 24
Finished Mar 19 12:54:16 PM PDT 24
Peak memory 200484 kb
Host smart-e34b0e53-419c-4711-b6d8-b679a56be964
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940197571 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.940197571
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.4178013866
Short name T46
Test name
Test status
Simulation time 41977840235 ps
CPU time 100.25 seconds
Started Mar 19 12:45:59 PM PDT 24
Finished Mar 19 12:47:40 PM PDT 24
Peak memory 200480 kb
Host smart-dd730feb-024a-477f-b8a5-559b52f6a829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178013866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.4178013866
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3142878465
Short name T213
Test name
Test status
Simulation time 46223801 ps
CPU time 0.57 seconds
Started Mar 19 12:46:03 PM PDT 24
Finished Mar 19 12:46:04 PM PDT 24
Peak memory 194832 kb
Host smart-614813f5-284d-49c4-9588-6c084eb034f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142878465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3142878465
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2033188442
Short name T364
Test name
Test status
Simulation time 1453949099 ps
CPU time 48.11 seconds
Started Mar 19 12:45:59 PM PDT 24
Finished Mar 19 12:46:47 PM PDT 24
Peak memory 218808 kb
Host smart-03e7467d-effa-4ff2-9086-654eb7c562a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2033188442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2033188442
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.546076777
Short name T321
Test name
Test status
Simulation time 6045327382 ps
CPU time 28.79 seconds
Started Mar 19 12:46:10 PM PDT 24
Finished Mar 19 12:46:39 PM PDT 24
Peak memory 200464 kb
Host smart-4980090b-d4a1-44a6-a626-271d0c94d971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546076777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.546076777
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.535769068
Short name T546
Test name
Test status
Simulation time 4154443935 ps
CPU time 121.89 seconds
Started Mar 19 12:46:00 PM PDT 24
Finished Mar 19 12:48:02 PM PDT 24
Peak memory 200444 kb
Host smart-91c62ad5-8fa4-4593-9eca-1b3ecedd0bae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=535769068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.535769068
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2707871633
Short name T413
Test name
Test status
Simulation time 1583318054 ps
CPU time 84.52 seconds
Started Mar 19 12:46:04 PM PDT 24
Finished Mar 19 12:47:29 PM PDT 24
Peak memory 200376 kb
Host smart-e1fa64b1-3a20-442c-8c30-398bcbcdae02
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707871633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2707871633
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2859887996
Short name T258
Test name
Test status
Simulation time 3498883201 ps
CPU time 17.47 seconds
Started Mar 19 12:46:05 PM PDT 24
Finished Mar 19 12:46:23 PM PDT 24
Peak memory 200432 kb
Host smart-bb07bcb1-a743-47de-9897-8918c5865bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859887996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2859887996
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3633810206
Short name T312
Test name
Test status
Simulation time 439507082 ps
CPU time 6.51 seconds
Started Mar 19 12:46:05 PM PDT 24
Finished Mar 19 12:46:12 PM PDT 24
Peak memory 200372 kb
Host smart-8a0b40c6-78b9-4db6-b569-18014e8491d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633810206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3633810206
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3566603752
Short name T361
Test name
Test status
Simulation time 148449420863 ps
CPU time 575.42 seconds
Started Mar 19 12:46:09 PM PDT 24
Finished Mar 19 12:55:45 PM PDT 24
Peak memory 231336 kb
Host smart-dfd41412-9984-450c-8deb-df69df69b488
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566603752 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3566603752
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.1197266439
Short name T161
Test name
Test status
Simulation time 729617832 ps
CPU time 1.33 seconds
Started Mar 19 12:46:05 PM PDT 24
Finished Mar 19 12:46:07 PM PDT 24
Peak memory 200256 kb
Host smart-ceb9430a-50ca-4f6a-a6f4-a3cc63f3074d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197266439 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.1197266439
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.2156749715
Short name T363
Test name
Test status
Simulation time 72076562074 ps
CPU time 396.19 seconds
Started Mar 19 12:46:04 PM PDT 24
Finished Mar 19 12:52:40 PM PDT 24
Peak memory 200376 kb
Host smart-cb2d29a9-d6a6-4a1a-8faf-b43fd7829def
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156749715 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.2156749715
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.4053947871
Short name T533
Test name
Test status
Simulation time 1623622444 ps
CPU time 62.04 seconds
Started Mar 19 12:46:06 PM PDT 24
Finished Mar 19 12:47:08 PM PDT 24
Peak memory 200428 kb
Host smart-e7f6448b-d686-4481-bd3d-b09cca1e30e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053947871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.4053947871
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1176068288
Short name T199
Test name
Test status
Simulation time 41695413 ps
CPU time 0.59 seconds
Started Mar 19 12:46:11 PM PDT 24
Finished Mar 19 12:46:12 PM PDT 24
Peak memory 194852 kb
Host smart-2553c570-94cd-4aa9-8014-323ea4074607
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176068288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1176068288
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1994910428
Short name T53
Test name
Test status
Simulation time 1675225094 ps
CPU time 15.07 seconds
Started Mar 19 12:46:10 PM PDT 24
Finished Mar 19 12:46:25 PM PDT 24
Peak memory 215964 kb
Host smart-f110d750-ce4a-49ff-ae78-34bc8117e8b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1994910428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1994910428
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3928492092
Short name T415
Test name
Test status
Simulation time 3453214159 ps
CPU time 24.81 seconds
Started Mar 19 12:46:07 PM PDT 24
Finished Mar 19 12:46:32 PM PDT 24
Peak memory 200436 kb
Host smart-6b8c0fb6-328d-46a3-988f-b8558ad41444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928492092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3928492092
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.633678127
Short name T151
Test name
Test status
Simulation time 1644364608 ps
CPU time 102.29 seconds
Started Mar 19 12:46:04 PM PDT 24
Finished Mar 19 12:47:47 PM PDT 24
Peak memory 200492 kb
Host smart-39c46a1b-98f7-446d-a920-594e3634cb3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=633678127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.633678127
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.772342919
Short name T193
Test name
Test status
Simulation time 5830915444 ps
CPU time 104.02 seconds
Started Mar 19 12:46:05 PM PDT 24
Finished Mar 19 12:47:49 PM PDT 24
Peak memory 200444 kb
Host smart-80c62c93-ff10-4d76-9ae2-544545247a60
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772342919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.772342919
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.315612791
Short name T414
Test name
Test status
Simulation time 16379399199 ps
CPU time 33.03 seconds
Started Mar 19 12:46:02 PM PDT 24
Finished Mar 19 12:46:35 PM PDT 24
Peak memory 200452 kb
Host smart-ebc52e2e-6026-4b8c-9a62-87cf1e413b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315612791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.315612791
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.1677228210
Short name T165
Test name
Test status
Simulation time 684456064 ps
CPU time 3.93 seconds
Started Mar 19 12:46:04 PM PDT 24
Finished Mar 19 12:46:08 PM PDT 24
Peak memory 200360 kb
Host smart-e155b598-f84d-4071-a32d-f48f03c2ec03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677228210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1677228210
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.3245954632
Short name T88
Test name
Test status
Simulation time 13181323080 ps
CPU time 55.73 seconds
Started Mar 19 12:46:10 PM PDT 24
Finished Mar 19 12:47:06 PM PDT 24
Peak memory 200516 kb
Host smart-591cf50f-ee7b-4f1b-bf90-beea565d6db5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245954632 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3245954632
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.857306255
Short name T95
Test name
Test status
Simulation time 32383460 ps
CPU time 1.11 seconds
Started Mar 19 12:46:08 PM PDT 24
Finished Mar 19 12:46:09 PM PDT 24
Peak memory 199856 kb
Host smart-a5491286-e148-4851-a14f-074d5661f558
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857306255 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_hmac_vectors.857306255
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.3907991625
Short name T218
Test name
Test status
Simulation time 14851068718 ps
CPU time 395.93 seconds
Started Mar 19 12:46:04 PM PDT 24
Finished Mar 19 12:52:41 PM PDT 24
Peak memory 200352 kb
Host smart-68481d5a-84ad-4338-b208-ba751adcd652
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907991625 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.3907991625
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2824429422
Short name T446
Test name
Test status
Simulation time 743193113 ps
CPU time 22.32 seconds
Started Mar 19 12:46:06 PM PDT 24
Finished Mar 19 12:46:28 PM PDT 24
Peak memory 200356 kb
Host smart-a9858a75-2e7a-4260-a51e-dac830d8cfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824429422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2824429422
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1471061645
Short name T129
Test name
Test status
Simulation time 60209577 ps
CPU time 0.59 seconds
Started Mar 19 12:46:05 PM PDT 24
Finished Mar 19 12:46:06 PM PDT 24
Peak memory 195532 kb
Host smart-4a13f6d1-09d0-4946-9985-8052e9ce9da4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471061645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1471061645
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.4009166973
Short name T163
Test name
Test status
Simulation time 4669517103 ps
CPU time 41.64 seconds
Started Mar 19 12:46:05 PM PDT 24
Finished Mar 19 12:46:47 PM PDT 24
Peak memory 221856 kb
Host smart-0e4bc4e6-a957-4785-a154-fc27c5e6bcc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4009166973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.4009166973
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.466438124
Short name T313
Test name
Test status
Simulation time 4248918606 ps
CPU time 36.63 seconds
Started Mar 19 12:46:05 PM PDT 24
Finished Mar 19 12:46:42 PM PDT 24
Peak memory 200424 kb
Host smart-a59cbc88-9124-4227-8a2c-b6a8deca9478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466438124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.466438124
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1734146197
Short name T513
Test name
Test status
Simulation time 2388993110 ps
CPU time 41.35 seconds
Started Mar 19 12:46:11 PM PDT 24
Finished Mar 19 12:46:52 PM PDT 24
Peak memory 200448 kb
Host smart-d1bb0a58-ddff-4d7a-a4c6-92ab28d6a33a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1734146197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1734146197
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1328334210
Short name T460
Test name
Test status
Simulation time 11962948790 ps
CPU time 119.97 seconds
Started Mar 19 12:46:07 PM PDT 24
Finished Mar 19 12:48:07 PM PDT 24
Peak memory 200544 kb
Host smart-f68c1b3a-45bb-4aab-921a-876fa164af41
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328334210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1328334210
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2634558107
Short name T187
Test name
Test status
Simulation time 927056068 ps
CPU time 28.23 seconds
Started Mar 19 12:46:06 PM PDT 24
Finished Mar 19 12:46:34 PM PDT 24
Peak memory 200428 kb
Host smart-dcf3b9ba-29e2-47ee-88f2-1cc261ac2cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634558107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2634558107
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.1545857173
Short name T289
Test name
Test status
Simulation time 65350771 ps
CPU time 1.05 seconds
Started Mar 19 12:46:10 PM PDT 24
Finished Mar 19 12:46:11 PM PDT 24
Peak memory 199128 kb
Host smart-b07ad50d-2ca7-4c66-9337-74dddc3d37fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545857173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1545857173
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2516038254
Short name T49
Test name
Test status
Simulation time 127860032394 ps
CPU time 1775.87 seconds
Started Mar 19 12:46:08 PM PDT 24
Finished Mar 19 01:15:45 PM PDT 24
Peak memory 208700 kb
Host smart-a97e112a-1b95-4415-aeb8-2d83c00768a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516038254 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2516038254
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.1359431627
Short name T214
Test name
Test status
Simulation time 108766988 ps
CPU time 1.13 seconds
Started Mar 19 12:46:07 PM PDT 24
Finished Mar 19 12:46:08 PM PDT 24
Peak memory 200328 kb
Host smart-80342ca1-d449-4594-ac53-30b34d09bde3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359431627 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.1359431627
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.1032786627
Short name T178
Test name
Test status
Simulation time 57191539347 ps
CPU time 491.62 seconds
Started Mar 19 12:46:07 PM PDT 24
Finished Mar 19 12:54:18 PM PDT 24
Peak memory 200468 kb
Host smart-1f87529c-91b0-4f93-b855-b5d9075af4c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032786627 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.1032786627
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.152173096
Short name T468
Test name
Test status
Simulation time 38135714820 ps
CPU time 74.17 seconds
Started Mar 19 12:46:05 PM PDT 24
Finished Mar 19 12:47:19 PM PDT 24
Peak memory 200412 kb
Host smart-7264ac7a-ae6a-4372-89b7-12355c84eba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152173096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.152173096
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2585210240
Short name T278
Test name
Test status
Simulation time 27497667 ps
CPU time 0.56 seconds
Started Mar 19 12:46:11 PM PDT 24
Finished Mar 19 12:46:12 PM PDT 24
Peak memory 195972 kb
Host smart-d354b8a0-e3be-4592-a3de-e0596745ed43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585210240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2585210240
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.550154240
Short name T552
Test name
Test status
Simulation time 1296807233 ps
CPU time 8.81 seconds
Started Mar 19 12:46:06 PM PDT 24
Finished Mar 19 12:46:15 PM PDT 24
Peak memory 208688 kb
Host smart-16f0bd2b-0f01-4d7f-a0c6-8606d90caeb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=550154240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.550154240
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3066824628
Short name T271
Test name
Test status
Simulation time 10497859139 ps
CPU time 41.52 seconds
Started Mar 19 12:46:09 PM PDT 24
Finished Mar 19 12:46:50 PM PDT 24
Peak memory 200432 kb
Host smart-d64df72c-7b39-4a08-942d-5b0b6dc4734e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066824628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3066824628
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.709815970
Short name T367
Test name
Test status
Simulation time 2736908170 ps
CPU time 159.1 seconds
Started Mar 19 12:46:04 PM PDT 24
Finished Mar 19 12:48:44 PM PDT 24
Peak memory 200388 kb
Host smart-b0bdca1b-6476-4686-8443-4b08c0fccb91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=709815970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.709815970
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1144406529
Short name T521
Test name
Test status
Simulation time 13932210326 ps
CPU time 131.22 seconds
Started Mar 19 12:46:05 PM PDT 24
Finished Mar 19 12:48:17 PM PDT 24
Peak memory 200512 kb
Host smart-54594bfa-7b74-4622-a219-a9d0f1b70b5a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144406529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1144406529
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1257715578
Short name T501
Test name
Test status
Simulation time 2131648936 ps
CPU time 108.16 seconds
Started Mar 19 12:46:04 PM PDT 24
Finished Mar 19 12:47:52 PM PDT 24
Peak memory 200444 kb
Host smart-3be447ba-b4cf-4ff5-a361-a7e9d2e1ddb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257715578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1257715578
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.430802797
Short name T461
Test name
Test status
Simulation time 668543406 ps
CPU time 2.95 seconds
Started Mar 19 12:46:10 PM PDT 24
Finished Mar 19 12:46:13 PM PDT 24
Peak memory 200348 kb
Host smart-716dfa5c-13a9-4183-988f-4b3e29b84cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430802797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.430802797
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.1531211323
Short name T401
Test name
Test status
Simulation time 36210538419 ps
CPU time 456.15 seconds
Started Mar 19 12:46:06 PM PDT 24
Finished Mar 19 12:53:42 PM PDT 24
Peak memory 241464 kb
Host smart-bfe16af0-316d-4809-8d36-ae910a4d0a46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531211323 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1531211323
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.345489991
Short name T233
Test name
Test status
Simulation time 32966194 ps
CPU time 1.19 seconds
Started Mar 19 12:46:06 PM PDT 24
Finished Mar 19 12:46:07 PM PDT 24
Peak memory 200100 kb
Host smart-026ced76-aea1-4f08-921f-a94a435e39a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345489991 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_hmac_vectors.345489991
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.2478056455
Short name T469
Test name
Test status
Simulation time 29846327499 ps
CPU time 419.77 seconds
Started Mar 19 12:46:07 PM PDT 24
Finished Mar 19 12:53:06 PM PDT 24
Peak memory 200376 kb
Host smart-97645c04-43f9-44c1-9fd4-3fbe185e8f54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478056455 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.2478056455
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.2294701220
Short name T488
Test name
Test status
Simulation time 816411423 ps
CPU time 35.98 seconds
Started Mar 19 12:46:07 PM PDT 24
Finished Mar 19 12:46:43 PM PDT 24
Peak memory 200380 kb
Host smart-6b7b0811-4538-4362-a467-7872b1f48b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294701220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2294701220
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3427936998
Short name T353
Test name
Test status
Simulation time 37674835 ps
CPU time 0.58 seconds
Started Mar 19 12:46:10 PM PDT 24
Finished Mar 19 12:46:11 PM PDT 24
Peak memory 195828 kb
Host smart-3dc4abcf-41fe-4a15-9574-07caf410413f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427936998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3427936998
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.2725901906
Short name T563
Test name
Test status
Simulation time 2854518713 ps
CPU time 24.79 seconds
Started Mar 19 12:46:10 PM PDT 24
Finished Mar 19 12:46:35 PM PDT 24
Peak memory 208624 kb
Host smart-5f6fc60b-e972-4582-a491-3c818286fd44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2725901906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2725901906
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.4155119728
Short name T491
Test name
Test status
Simulation time 2570530535 ps
CPU time 53.18 seconds
Started Mar 19 12:46:10 PM PDT 24
Finished Mar 19 12:47:03 PM PDT 24
Peak memory 200444 kb
Host smart-12a68733-1d1e-4a69-b6e3-ee58706112a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155119728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.4155119728
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.1904804453
Short name T188
Test name
Test status
Simulation time 4023024012 ps
CPU time 119.22 seconds
Started Mar 19 12:46:12 PM PDT 24
Finished Mar 19 12:48:11 PM PDT 24
Peak memory 200488 kb
Host smart-c5cc7d04-d7de-44e8-b4bb-ad22090a6cf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1904804453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1904804453
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.778988743
Short name T398
Test name
Test status
Simulation time 14733781534 ps
CPU time 144.79 seconds
Started Mar 19 12:46:12 PM PDT 24
Finished Mar 19 12:48:37 PM PDT 24
Peak memory 200468 kb
Host smart-981c4fc1-b40c-474d-a496-99f0f2636777
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778988743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.778988743
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.3965874153
Short name T179
Test name
Test status
Simulation time 2266193265 ps
CPU time 103.11 seconds
Started Mar 19 12:46:09 PM PDT 24
Finished Mar 19 12:47:52 PM PDT 24
Peak memory 200512 kb
Host smart-9e5ac43d-e061-4a64-86fd-5e5d1cab8f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965874153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.3965874153
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.332049090
Short name T316
Test name
Test status
Simulation time 154011920 ps
CPU time 5.01 seconds
Started Mar 19 12:46:11 PM PDT 24
Finished Mar 19 12:46:16 PM PDT 24
Peak memory 200432 kb
Host smart-0e84e096-31e4-4260-8e05-4e31161466ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332049090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.332049090
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2904813032
Short name T411
Test name
Test status
Simulation time 30598091184 ps
CPU time 152.94 seconds
Started Mar 19 12:46:13 PM PDT 24
Finished Mar 19 12:48:46 PM PDT 24
Peak memory 241492 kb
Host smart-4bbc72c9-e09b-4a49-bfe1-4b322286b249
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904813032 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2904813032
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.1026955375
Short name T366
Test name
Test status
Simulation time 28470414 ps
CPU time 1.08 seconds
Started Mar 19 12:46:12 PM PDT 24
Finished Mar 19 12:46:13 PM PDT 24
Peak memory 198716 kb
Host smart-7dbdbb51-8397-4de2-ba12-b77211df5a09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026955375 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.1026955375
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.643624160
Short name T504
Test name
Test status
Simulation time 27184488624 ps
CPU time 484.97 seconds
Started Mar 19 12:46:09 PM PDT 24
Finished Mar 19 12:54:15 PM PDT 24
Peak memory 200456 kb
Host smart-43bae5c7-e6f5-4607-8968-3825f67deec0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643624160 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.643624160
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.3645217092
Short name T121
Test name
Test status
Simulation time 23811025878 ps
CPU time 87.81 seconds
Started Mar 19 12:46:10 PM PDT 24
Finished Mar 19 12:47:38 PM PDT 24
Peak memory 200452 kb
Host smart-fe910d75-4343-4b11-a2dc-0ff4c59305b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645217092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.3645217092
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3059760522
Short name T84
Test name
Test status
Simulation time 14566800 ps
CPU time 0.6 seconds
Started Mar 19 12:46:16 PM PDT 24
Finished Mar 19 12:46:16 PM PDT 24
Peak memory 195888 kb
Host smart-ea643d7e-eed9-432e-81a9-06e3e3c8167a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059760522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3059760522
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2051960343
Short name T440
Test name
Test status
Simulation time 208492560 ps
CPU time 8.31 seconds
Started Mar 19 12:46:11 PM PDT 24
Finished Mar 19 12:46:20 PM PDT 24
Peak memory 216624 kb
Host smart-d96f1147-dc13-43c1-b99e-60a12ae9124b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2051960343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2051960343
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.637038169
Short name T229
Test name
Test status
Simulation time 8134732150 ps
CPU time 42.83 seconds
Started Mar 19 12:46:12 PM PDT 24
Finished Mar 19 12:46:55 PM PDT 24
Peak memory 200432 kb
Host smart-7487e7fd-eb1a-4577-89ae-638d68355be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637038169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.637038169
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2953678923
Short name T256
Test name
Test status
Simulation time 2927986325 ps
CPU time 84.91 seconds
Started Mar 19 12:46:12 PM PDT 24
Finished Mar 19 12:47:37 PM PDT 24
Peak memory 200512 kb
Host smart-3b3bcd32-e065-4f42-8c9e-4c4ebb6af858
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2953678923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2953678923
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2679056897
Short name T272
Test name
Test status
Simulation time 1079850690 ps
CPU time 60.4 seconds
Started Mar 19 12:46:12 PM PDT 24
Finished Mar 19 12:47:12 PM PDT 24
Peak memory 200448 kb
Host smart-3d038b71-657c-4eea-b7d0-9ff35dbffa55
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679056897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2679056897
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.2965295506
Short name T492
Test name
Test status
Simulation time 259919748 ps
CPU time 2.25 seconds
Started Mar 19 12:46:11 PM PDT 24
Finished Mar 19 12:46:13 PM PDT 24
Peak memory 200412 kb
Host smart-b71c5818-2a6f-4011-ade4-42272f0cd7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965295506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2965295506
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2874462446
Short name T96
Test name
Test status
Simulation time 327676145 ps
CPU time 5.78 seconds
Started Mar 19 12:46:12 PM PDT 24
Finished Mar 19 12:46:18 PM PDT 24
Peak memory 200384 kb
Host smart-1dac7744-a62d-47de-a0a8-bfacc8bcd0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874462446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2874462446
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.181193007
Short name T301
Test name
Test status
Simulation time 138953518074 ps
CPU time 603.66 seconds
Started Mar 19 12:46:17 PM PDT 24
Finished Mar 19 12:56:21 PM PDT 24
Peak memory 200528 kb
Host smart-84ee6092-845b-4c96-9d82-376df280b81d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181193007 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.181193007
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.2769245178
Short name T418
Test name
Test status
Simulation time 171272327 ps
CPU time 1.05 seconds
Started Mar 19 12:46:17 PM PDT 24
Finished Mar 19 12:46:18 PM PDT 24
Peak memory 199220 kb
Host smart-9364c799-d6db-456e-b601-8ebd380a59d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769245178 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.2769245178
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.3116570580
Short name T544
Test name
Test status
Simulation time 50939261902 ps
CPU time 510.16 seconds
Started Mar 19 12:46:11 PM PDT 24
Finished Mar 19 12:54:42 PM PDT 24
Peak memory 200412 kb
Host smart-43ba2436-4718-4a76-b43f-4792c709cf18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116570580 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.3116570580
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.664279488
Short name T508
Test name
Test status
Simulation time 518967055 ps
CPU time 16.04 seconds
Started Mar 19 12:46:12 PM PDT 24
Finished Mar 19 12:46:28 PM PDT 24
Peak memory 200456 kb
Host smart-8540c4b1-1847-4e8b-89a7-c243ca44e980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664279488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.664279488
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.814524863
Short name T410
Test name
Test status
Simulation time 19235247 ps
CPU time 0.58 seconds
Started Mar 19 12:46:17 PM PDT 24
Finished Mar 19 12:46:18 PM PDT 24
Peak memory 194680 kb
Host smart-4e2d7d9c-d0b1-4f5d-86d6-c5731ed42757
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814524863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.814524863
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.3408754110
Short name T539
Test name
Test status
Simulation time 306902844 ps
CPU time 5.88 seconds
Started Mar 19 12:46:16 PM PDT 24
Finished Mar 19 12:46:22 PM PDT 24
Peak memory 208600 kb
Host smart-e34eac89-db09-414b-bf0e-cbf1f56ffb39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3408754110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3408754110
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.2015151542
Short name T406
Test name
Test status
Simulation time 3458642504 ps
CPU time 80.18 seconds
Started Mar 19 12:46:19 PM PDT 24
Finished Mar 19 12:47:39 PM PDT 24
Peak memory 200448 kb
Host smart-567f3228-dace-4ece-84dc-cc7cca39ce27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015151542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2015151542
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.1568419289
Short name T359
Test name
Test status
Simulation time 488624529 ps
CPU time 14.43 seconds
Started Mar 19 12:46:18 PM PDT 24
Finished Mar 19 12:46:32 PM PDT 24
Peak memory 200452 kb
Host smart-fc390473-b125-4f63-8358-cceaaad96ab9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1568419289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1568419289
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1782384862
Short name T42
Test name
Test status
Simulation time 25368434004 ps
CPU time 97.79 seconds
Started Mar 19 12:46:15 PM PDT 24
Finished Mar 19 12:47:53 PM PDT 24
Peak memory 200464 kb
Host smart-057e41a4-e37e-490e-849e-ba32b745cc38
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782384862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1782384862
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1635431424
Short name T234
Test name
Test status
Simulation time 1005452972 ps
CPU time 19.72 seconds
Started Mar 19 12:46:19 PM PDT 24
Finished Mar 19 12:46:38 PM PDT 24
Peak memory 200428 kb
Host smart-dc4fdb19-7051-424f-acd1-02ef3ddf414e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635431424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1635431424
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3026600216
Short name T338
Test name
Test status
Simulation time 768178705 ps
CPU time 3.1 seconds
Started Mar 19 12:46:15 PM PDT 24
Finished Mar 19 12:46:19 PM PDT 24
Peak memory 200384 kb
Host smart-a14d723f-5983-4819-85a8-b6515997a8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026600216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3026600216
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.1829317935
Short name T336
Test name
Test status
Simulation time 45200140 ps
CPU time 1.07 seconds
Started Mar 19 12:46:15 PM PDT 24
Finished Mar 19 12:46:17 PM PDT 24
Peak memory 199560 kb
Host smart-d1407bd0-411c-4d01-8b18-a7dac7072860
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829317935 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.1829317935
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.706039184
Short name T314
Test name
Test status
Simulation time 27500170656 ps
CPU time 411.38 seconds
Started Mar 19 12:46:16 PM PDT 24
Finished Mar 19 12:53:08 PM PDT 24
Peak memory 200400 kb
Host smart-776ecf15-1052-48dc-8d05-1df9da707c0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706039184 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.706039184
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1197687502
Short name T329
Test name
Test status
Simulation time 217669128 ps
CPU time 8.45 seconds
Started Mar 19 12:46:16 PM PDT 24
Finished Mar 19 12:46:24 PM PDT 24
Peak memory 200396 kb
Host smart-94d8a89e-b85f-4064-afca-5b4b998201a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197687502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1197687502
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3775976039
Short name T507
Test name
Test status
Simulation time 14230094 ps
CPU time 0.57 seconds
Started Mar 19 12:46:24 PM PDT 24
Finished Mar 19 12:46:25 PM PDT 24
Peak memory 194840 kb
Host smart-08eee7c4-1b66-41ee-a1c4-c8c1fa539b79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775976039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3775976039
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1874830744
Short name T474
Test name
Test status
Simulation time 7670795500 ps
CPU time 42.36 seconds
Started Mar 19 12:46:15 PM PDT 24
Finished Mar 19 12:46:58 PM PDT 24
Peak memory 233208 kb
Host smart-42dd4a04-4376-4e6f-8852-a70760e24281
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1874830744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1874830744
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1882009063
Short name T232
Test name
Test status
Simulation time 642541833 ps
CPU time 8.11 seconds
Started Mar 19 12:46:17 PM PDT 24
Finished Mar 19 12:46:25 PM PDT 24
Peak memory 200356 kb
Host smart-8e496b72-2c76-43a7-a29c-93b187319ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882009063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1882009063
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.488353213
Short name T547
Test name
Test status
Simulation time 2281282656 ps
CPU time 40.99 seconds
Started Mar 19 12:46:16 PM PDT 24
Finished Mar 19 12:46:57 PM PDT 24
Peak memory 200480 kb
Host smart-b38819e8-ef1c-4467-9688-e29f4b52394f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=488353213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.488353213
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3033498120
Short name T18
Test name
Test status
Simulation time 3575946443 ps
CPU time 95.37 seconds
Started Mar 19 12:46:15 PM PDT 24
Finished Mar 19 12:47:51 PM PDT 24
Peak memory 200432 kb
Host smart-cbe1d8c4-464c-4c66-b20a-0e2ad01a38dd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033498120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3033498120
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.3615851091
Short name T368
Test name
Test status
Simulation time 6190790803 ps
CPU time 85.52 seconds
Started Mar 19 12:46:18 PM PDT 24
Finished Mar 19 12:47:44 PM PDT 24
Peak memory 200488 kb
Host smart-5372b77f-3a53-4ba2-83fb-74c09e747412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615851091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3615851091
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.4153557524
Short name T217
Test name
Test status
Simulation time 196488436 ps
CPU time 3.34 seconds
Started Mar 19 12:46:15 PM PDT 24
Finished Mar 19 12:46:19 PM PDT 24
Peak memory 200404 kb
Host smart-b15742c4-5116-4f84-887d-9c9a23bb6eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153557524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.4153557524
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.3581010117
Short name T430
Test name
Test status
Simulation time 579598734 ps
CPU time 27.61 seconds
Started Mar 19 12:46:14 PM PDT 24
Finished Mar 19 12:46:42 PM PDT 24
Peak memory 208580 kb
Host smart-34360f2b-aca2-403c-bf75-79c1a96bbca9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581010117 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.3581010117
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.805719113
Short name T2
Test name
Test status
Simulation time 120917232 ps
CPU time 1.01 seconds
Started Mar 19 12:46:18 PM PDT 24
Finished Mar 19 12:46:19 PM PDT 24
Peak memory 199396 kb
Host smart-bbdf1ab0-1ef0-48f0-8f7c-798800779784
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805719113 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_hmac_vectors.805719113
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.121657373
Short name T389
Test name
Test status
Simulation time 29809538274 ps
CPU time 511.4 seconds
Started Mar 19 12:46:17 PM PDT 24
Finished Mar 19 12:54:49 PM PDT 24
Peak memory 200424 kb
Host smart-9b310707-9b02-45ff-b2c9-36e9b0f75006
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121657373 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.121657373
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.2067194049
Short name T267
Test name
Test status
Simulation time 1910534542 ps
CPU time 73.88 seconds
Started Mar 19 12:46:15 PM PDT 24
Finished Mar 19 12:47:29 PM PDT 24
Peak memory 200412 kb
Host smart-a22e5cad-6bc1-473d-937a-ad9e3900fc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067194049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.2067194049
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.3230894988
Short name T580
Test name
Test status
Simulation time 14749078 ps
CPU time 0.57 seconds
Started Mar 19 12:44:43 PM PDT 24
Finished Mar 19 12:44:44 PM PDT 24
Peak memory 195764 kb
Host smart-2e1487ab-b4e5-4053-84f3-b453dbb7b040
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230894988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3230894988
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2029903423
Short name T20
Test name
Test status
Simulation time 1687278127 ps
CPU time 63.46 seconds
Started Mar 19 12:44:41 PM PDT 24
Finished Mar 19 12:45:45 PM PDT 24
Peak memory 225112 kb
Host smart-681281f8-e076-4d61-852d-748f9cdfbe92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2029903423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2029903423
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3836670041
Short name T463
Test name
Test status
Simulation time 968544741 ps
CPU time 46.93 seconds
Started Mar 19 12:44:54 PM PDT 24
Finished Mar 19 12:45:41 PM PDT 24
Peak memory 200400 kb
Host smart-daf019f5-3ae1-4914-b86c-e326eb09dcd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836670041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3836670041
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2679115996
Short name T63
Test name
Test status
Simulation time 2656373745 ps
CPU time 121.86 seconds
Started Mar 19 12:44:46 PM PDT 24
Finished Mar 19 12:46:48 PM PDT 24
Peak memory 200440 kb
Host smart-8f4fa37a-0e32-409b-9ab3-d9cd7bb2164c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2679115996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2679115996
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.3366089318
Short name T431
Test name
Test status
Simulation time 22411679751 ps
CPU time 76.25 seconds
Started Mar 19 12:44:42 PM PDT 24
Finished Mar 19 12:45:58 PM PDT 24
Peak memory 200420 kb
Host smart-b39cd6d2-11d2-4a9c-927e-a95b2f833d1b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366089318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3366089318
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.1273265677
Short name T569
Test name
Test status
Simulation time 5849433367 ps
CPU time 39.71 seconds
Started Mar 19 12:44:40 PM PDT 24
Finished Mar 19 12:45:19 PM PDT 24
Peak memory 200436 kb
Host smart-dc7ee327-9f34-4671-a8a3-a3e64e6a711b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273265677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1273265677
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.304781741
Short name T315
Test name
Test status
Simulation time 359424045 ps
CPU time 4.77 seconds
Started Mar 19 12:44:49 PM PDT 24
Finished Mar 19 12:44:54 PM PDT 24
Peak memory 200380 kb
Host smart-6aa20621-868f-4c8a-9366-8f90e2b5bfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304781741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.304781741
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.558680398
Short name T560
Test name
Test status
Simulation time 15008726939 ps
CPU time 78.09 seconds
Started Mar 19 12:44:53 PM PDT 24
Finished Mar 19 12:46:11 PM PDT 24
Peak memory 229276 kb
Host smart-04677c6c-9560-44ff-94ab-3332d336675a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558680398 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.558680398
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.2396423538
Short name T241
Test name
Test status
Simulation time 222062318 ps
CPU time 1.02 seconds
Started Mar 19 12:44:42 PM PDT 24
Finished Mar 19 12:44:43 PM PDT 24
Peak memory 200076 kb
Host smart-14f17251-7a06-44c7-8c33-6b1ca5d7898d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396423538 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.2396423538
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.2571802964
Short name T80
Test name
Test status
Simulation time 17276426263 ps
CPU time 440.36 seconds
Started Mar 19 12:44:41 PM PDT 24
Finished Mar 19 12:52:02 PM PDT 24
Peak memory 200396 kb
Host smart-700e6fb3-3533-40c3-9ee1-50e920070071
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571802964 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.2571802964
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3705201915
Short name T200
Test name
Test status
Simulation time 17356062156 ps
CPU time 85.52 seconds
Started Mar 19 12:44:43 PM PDT 24
Finished Mar 19 12:46:08 PM PDT 24
Peak memory 200452 kb
Host smart-4553c3e9-2d5f-455d-b523-850ec692f343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705201915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3705201915
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/56.hmac_stress_all_with_rand_reset.2008970221
Short name T10
Test name
Test status
Simulation time 16416796734 ps
CPU time 83.73 seconds
Started Mar 19 12:46:22 PM PDT 24
Finished Mar 19 12:47:46 PM PDT 24
Peak memory 216428 kb
Host smart-b003a67a-9201-4453-9237-e42e2a6c47d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2008970221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.hmac_stress_all_with_rand_reset.2008970221
Directory /workspace/56.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1666432529
Short name T240
Test name
Test status
Simulation time 16356004 ps
CPU time 0.57 seconds
Started Mar 19 12:44:44 PM PDT 24
Finished Mar 19 12:44:45 PM PDT 24
Peak memory 194796 kb
Host smart-8a9b8f9e-93f6-4d36-9391-24bd3cdf8363
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666432529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1666432529
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.4059162899
Short name T175
Test name
Test status
Simulation time 1022981469 ps
CPU time 6.38 seconds
Started Mar 19 12:44:42 PM PDT 24
Finished Mar 19 12:44:49 PM PDT 24
Peak memory 216512 kb
Host smart-146c63c7-fa57-4ce5-be92-015a39c1ab81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4059162899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.4059162899
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3364356642
Short name T524
Test name
Test status
Simulation time 961294614 ps
CPU time 7.68 seconds
Started Mar 19 12:44:42 PM PDT 24
Finished Mar 19 12:44:50 PM PDT 24
Peak memory 200276 kb
Host smart-b4631eb0-1fdf-4540-ac87-ee6c5b80071f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364356642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3364356642
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1275357407
Short name T457
Test name
Test status
Simulation time 945032506 ps
CPU time 54.52 seconds
Started Mar 19 12:44:41 PM PDT 24
Finished Mar 19 12:45:36 PM PDT 24
Peak memory 200388 kb
Host smart-76836808-5cf8-49f5-87ee-e6b7b8bbfd66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1275357407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1275357407
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.339745538
Short name T481
Test name
Test status
Simulation time 5545719320 ps
CPU time 36.23 seconds
Started Mar 19 12:44:54 PM PDT 24
Finished Mar 19 12:45:31 PM PDT 24
Peak memory 200492 kb
Host smart-f82ea935-a956-4ea9-a672-d11bc5f9883d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339745538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.339745538
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.2633620480
Short name T515
Test name
Test status
Simulation time 4365982897 ps
CPU time 53.56 seconds
Started Mar 19 12:44:40 PM PDT 24
Finished Mar 19 12:45:34 PM PDT 24
Peak memory 200484 kb
Host smart-ac9f8f24-e267-4a09-b790-dfc02088a9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633620480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2633620480
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.676680578
Short name T583
Test name
Test status
Simulation time 201077168 ps
CPU time 1.19 seconds
Started Mar 19 12:44:47 PM PDT 24
Finished Mar 19 12:44:48 PM PDT 24
Peak memory 200364 kb
Host smart-39aefa00-f7ca-4eb8-9b6d-2d99f3c5051c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676680578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.676680578
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.321929113
Short name T86
Test name
Test status
Simulation time 27333656864 ps
CPU time 79.95 seconds
Started Mar 19 12:44:49 PM PDT 24
Finished Mar 19 12:46:09 PM PDT 24
Peak memory 226640 kb
Host smart-1a0910db-3549-437f-9621-5788eddc7ab7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321929113 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.321929113
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.3610719185
Short name T482
Test name
Test status
Simulation time 52819145 ps
CPU time 1.27 seconds
Started Mar 19 12:44:39 PM PDT 24
Finished Mar 19 12:44:41 PM PDT 24
Peak memory 200484 kb
Host smart-bf2aeb64-02e3-4d8b-89bc-3ac350e30465
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610719185 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.3610719185
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.1159599185
Short name T308
Test name
Test status
Simulation time 100727226597 ps
CPU time 452.61 seconds
Started Mar 19 12:44:43 PM PDT 24
Finished Mar 19 12:52:15 PM PDT 24
Peak memory 200392 kb
Host smart-88d30bd7-d2e8-4eff-a49e-f45ce555b1a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159599185 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.1159599185
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1966206368
Short name T340
Test name
Test status
Simulation time 1247716284 ps
CPU time 5.26 seconds
Started Mar 19 12:44:43 PM PDT 24
Finished Mar 19 12:44:48 PM PDT 24
Peak memory 200424 kb
Host smart-fac42bcd-e3bc-41d5-83a1-19e5ab671099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966206368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1966206368
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.1553216671
Short name T160
Test name
Test status
Simulation time 14207847 ps
CPU time 0.55 seconds
Started Mar 19 12:44:41 PM PDT 24
Finished Mar 19 12:44:41 PM PDT 24
Peak memory 194852 kb
Host smart-6330a5a8-28df-47d1-9099-ba5cd59280fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553216671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1553216671
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2549822
Short name T448
Test name
Test status
Simulation time 3914208750 ps
CPU time 34.66 seconds
Started Mar 19 12:44:49 PM PDT 24
Finished Mar 19 12:45:25 PM PDT 24
Peak memory 216404 kb
Host smart-e0061fa2-cd1a-4788-ab53-c02b09863f3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2549822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2549822
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2618838285
Short name T388
Test name
Test status
Simulation time 831839919 ps
CPU time 42.95 seconds
Started Mar 19 12:44:42 PM PDT 24
Finished Mar 19 12:45:26 PM PDT 24
Peak memory 200384 kb
Host smart-69d44a62-c200-432d-aa8d-dbdf160ed1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618838285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2618838285
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.3189799643
Short name T215
Test name
Test status
Simulation time 6130586041 ps
CPU time 81.16 seconds
Started Mar 19 12:44:54 PM PDT 24
Finished Mar 19 12:46:15 PM PDT 24
Peak memory 200428 kb
Host smart-d3310058-780d-44f6-adee-193a38a8440c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3189799643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3189799643
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1234954704
Short name T286
Test name
Test status
Simulation time 10042918011 ps
CPU time 26.65 seconds
Started Mar 19 12:44:42 PM PDT 24
Finished Mar 19 12:45:09 PM PDT 24
Peak memory 200460 kb
Host smart-8aca025d-59d3-405e-9b21-b2dd64990b4a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234954704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1234954704
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2316508613
Short name T209
Test name
Test status
Simulation time 204562642 ps
CPU time 11.15 seconds
Started Mar 19 12:44:52 PM PDT 24
Finished Mar 19 12:45:04 PM PDT 24
Peak memory 200368 kb
Host smart-b7d4ef72-3f91-44c4-af9f-dab594cf4db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316508613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2316508613
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.4258366182
Short name T519
Test name
Test status
Simulation time 246469692 ps
CPU time 3.87 seconds
Started Mar 19 12:44:57 PM PDT 24
Finished Mar 19 12:45:01 PM PDT 24
Peak memory 200372 kb
Host smart-13b4926a-50c7-4ef9-be66-2ed33232583f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258366182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.4258366182
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.2482280271
Short name T591
Test name
Test status
Simulation time 85792545114 ps
CPU time 1681.07 seconds
Started Mar 19 12:44:58 PM PDT 24
Finished Mar 19 01:12:59 PM PDT 24
Peak memory 200516 kb
Host smart-4157b71f-f48a-4f94-aa03-1bf5128083f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482280271 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.2482280271
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.3690113697
Short name T351
Test name
Test status
Simulation time 34504794 ps
CPU time 1.25 seconds
Started Mar 19 12:44:39 PM PDT 24
Finished Mar 19 12:44:41 PM PDT 24
Peak memory 200396 kb
Host smart-96080159-7ef5-43de-8e35-9ac741fa812d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690113697 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.3690113697
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.3093945523
Short name T3
Test name
Test status
Simulation time 33682416149 ps
CPU time 453.05 seconds
Started Mar 19 12:45:04 PM PDT 24
Finished Mar 19 12:52:37 PM PDT 24
Peak memory 200440 kb
Host smart-d5f79b60-a52d-4fb2-bab7-efacdc3c38da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093945523 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.3093945523
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.800978041
Short name T231
Test name
Test status
Simulation time 3419790997 ps
CPU time 84.43 seconds
Started Mar 19 12:45:02 PM PDT 24
Finished Mar 19 12:46:27 PM PDT 24
Peak memory 200444 kb
Host smart-0bfe8853-6d54-423c-a612-d9a233a48ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800978041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.800978041
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.214445014
Short name T387
Test name
Test status
Simulation time 43339603 ps
CPU time 0.59 seconds
Started Mar 19 12:44:49 PM PDT 24
Finished Mar 19 12:44:51 PM PDT 24
Peak memory 195848 kb
Host smart-7ce6e4ac-e6bb-4c67-886a-4c44b7e8346c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214445014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.214445014
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1472829683
Short name T485
Test name
Test status
Simulation time 1482722037 ps
CPU time 53.42 seconds
Started Mar 19 12:44:52 PM PDT 24
Finished Mar 19 12:45:46 PM PDT 24
Peak memory 224900 kb
Host smart-d2cce9a1-728f-4027-8cf7-9e3f02046234
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1472829683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1472829683
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.89575254
Short name T153
Test name
Test status
Simulation time 23680679542 ps
CPU time 30.66 seconds
Started Mar 19 12:44:40 PM PDT 24
Finished Mar 19 12:45:11 PM PDT 24
Peak memory 200504 kb
Host smart-4358fe57-fe7b-4a15-8b62-245b8674525f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89575254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.89575254
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3599116429
Short name T553
Test name
Test status
Simulation time 2892643704 ps
CPU time 165.56 seconds
Started Mar 19 12:44:43 PM PDT 24
Finished Mar 19 12:47:28 PM PDT 24
Peak memory 200464 kb
Host smart-52b823d4-2781-4789-976a-540a94c105d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3599116429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3599116429
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.2785372301
Short name T557
Test name
Test status
Simulation time 105688478334 ps
CPU time 143.57 seconds
Started Mar 19 12:44:49 PM PDT 24
Finished Mar 19 12:47:13 PM PDT 24
Peak memory 200500 kb
Host smart-590538e0-7143-4d9d-9b80-7f6010b1625e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785372301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2785372301
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.533949378
Short name T211
Test name
Test status
Simulation time 2013583074 ps
CPU time 109.48 seconds
Started Mar 19 12:44:52 PM PDT 24
Finished Mar 19 12:46:42 PM PDT 24
Peak memory 200376 kb
Host smart-e53cd893-c9ce-4cc7-affe-d9273b397db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533949378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.533949378
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.249966653
Short name T470
Test name
Test status
Simulation time 1679098974 ps
CPU time 4.52 seconds
Started Mar 19 12:44:47 PM PDT 24
Finished Mar 19 12:44:51 PM PDT 24
Peak memory 200420 kb
Host smart-8d7e73a6-9c11-48da-aabf-3cf508782dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249966653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.249966653
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.247512332
Short name T433
Test name
Test status
Simulation time 109166045485 ps
CPU time 1429.24 seconds
Started Mar 19 12:44:50 PM PDT 24
Finished Mar 19 01:08:40 PM PDT 24
Peak memory 200488 kb
Host smart-fdb2e870-b67f-4fa7-86c0-55f0c6318cee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247512332 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.247512332
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.3110104086
Short name T339
Test name
Test status
Simulation time 123339741 ps
CPU time 1.01 seconds
Started Mar 19 12:44:41 PM PDT 24
Finished Mar 19 12:44:42 PM PDT 24
Peak memory 200192 kb
Host smart-3adc8e6d-5ba1-46c8-b84e-cef55cfd78bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110104086 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.3110104086
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.3488495568
Short name T172
Test name
Test status
Simulation time 14282457818 ps
CPU time 398.79 seconds
Started Mar 19 12:44:52 PM PDT 24
Finished Mar 19 12:51:31 PM PDT 24
Peak memory 200364 kb
Host smart-2e902fd0-1f67-4735-be8a-7a65f274df0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488495568 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.3488495568
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.3392617259
Short name T559
Test name
Test status
Simulation time 2035829017 ps
CPU time 16.12 seconds
Started Mar 19 12:44:42 PM PDT 24
Finished Mar 19 12:44:58 PM PDT 24
Peak memory 200432 kb
Host smart-bc500be4-6207-47a7-82d5-3871a06f8958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392617259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3392617259
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/83.hmac_stress_all_with_rand_reset.3263060877
Short name T74
Test name
Test status
Simulation time 361666779321 ps
CPU time 3307.39 seconds
Started Mar 19 12:46:34 PM PDT 24
Finished Mar 19 01:41:42 PM PDT 24
Peak memory 265760 kb
Host smart-2d7eaae6-7a45-4678-8247-8e680ffbc204
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3263060877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.hmac_stress_all_with_rand_reset.3263060877
Directory /workspace/83.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3531479608
Short name T396
Test name
Test status
Simulation time 89868337 ps
CPU time 0.64 seconds
Started Mar 19 12:44:53 PM PDT 24
Finished Mar 19 12:44:54 PM PDT 24
Peak memory 195948 kb
Host smart-68ecd3b9-d9fa-4ce4-9769-546c927c65f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531479608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3531479608
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.525327622
Short name T542
Test name
Test status
Simulation time 3143511574 ps
CPU time 25.62 seconds
Started Mar 19 12:44:51 PM PDT 24
Finished Mar 19 12:45:18 PM PDT 24
Peak memory 216668 kb
Host smart-b9500afa-a9a6-4650-a623-34dd60c7392c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=525327622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.525327622
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.222413973
Short name T334
Test name
Test status
Simulation time 1837733626 ps
CPU time 16.65 seconds
Started Mar 19 12:44:53 PM PDT 24
Finished Mar 19 12:45:10 PM PDT 24
Peak memory 200344 kb
Host smart-7dd6d381-d888-4567-ac33-1827cbfdadc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222413973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.222413973
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1503087981
Short name T222
Test name
Test status
Simulation time 5940963498 ps
CPU time 92 seconds
Started Mar 19 12:44:55 PM PDT 24
Finished Mar 19 12:46:27 PM PDT 24
Peak memory 200476 kb
Host smart-44a2389b-d983-4fa2-9a7a-a76d44e62743
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1503087981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1503087981
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.928028415
Short name T543
Test name
Test status
Simulation time 9003394590 ps
CPU time 130.12 seconds
Started Mar 19 12:44:47 PM PDT 24
Finished Mar 19 12:46:57 PM PDT 24
Peak memory 200456 kb
Host smart-7ab5f54b-86dd-433f-b556-b6a64b7549b3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928028415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.928028415
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3598509874
Short name T477
Test name
Test status
Simulation time 3233231610 ps
CPU time 46.36 seconds
Started Mar 19 12:44:52 PM PDT 24
Finished Mar 19 12:45:38 PM PDT 24
Peak memory 200480 kb
Host smart-070febaf-3ab2-4c86-ac77-6087b61b2798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598509874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3598509874
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2385597237
Short name T465
Test name
Test status
Simulation time 112378175 ps
CPU time 3.54 seconds
Started Mar 19 12:44:50 PM PDT 24
Finished Mar 19 12:44:54 PM PDT 24
Peak memory 200364 kb
Host smart-c867e33d-cb21-4512-b33b-94cf2024ce37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385597237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2385597237
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.500634053
Short name T399
Test name
Test status
Simulation time 23435808747 ps
CPU time 95.8 seconds
Started Mar 19 12:44:55 PM PDT 24
Finished Mar 19 12:46:31 PM PDT 24
Peak memory 200520 kb
Host smart-1caf1b76-d072-4cd2-b332-e9ac220fea34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500634053 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.500634053
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.1537148404
Short name T253
Test name
Test status
Simulation time 248972369 ps
CPU time 1.25 seconds
Started Mar 19 12:44:49 PM PDT 24
Finished Mar 19 12:44:50 PM PDT 24
Peak memory 200168 kb
Host smart-e9e7b101-a0e8-4955-ba97-1a6999133dd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537148404 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.1537148404
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.3695264667
Short name T185
Test name
Test status
Simulation time 8281424103 ps
CPU time 489.55 seconds
Started Mar 19 12:45:01 PM PDT 24
Finished Mar 19 12:53:11 PM PDT 24
Peak memory 200468 kb
Host smart-4daa13ba-749b-4e1a-b896-fd73f302a208
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695264667 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.3695264667
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.4149764110
Short name T264
Test name
Test status
Simulation time 1233088101 ps
CPU time 54.16 seconds
Started Mar 19 12:44:51 PM PDT 24
Finished Mar 19 12:45:45 PM PDT 24
Peak memory 200404 kb
Host smart-fbf5e07a-f8a7-4075-86ba-5aec9ba6833e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149764110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.4149764110
Directory /workspace/9.hmac_wipe_secret/latest
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