Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	13257902	1			T1	43022		T2	31		T3	8361
all_values[1]	13257902	1			T1	43022		T2	31		T3	8361
all_values[2]	13257902	1			T1	43022		T2	31		T3	8361

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

106282

1

T1

2867

T3

332

T4

9

auto[1]

39667424

1

T1

126199

T2

93

T3

24751

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37645334

1

T1

103202

T2

89

T3

25046

auto[1]

2128372

1

T1

25864

T2

4

T3

37

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	40729	1			T1	2863		T3	330		T11	15
all_values[0]	auto[0]	auto[1]	528	1			T1	2		T3	2		T11	2
all_values[0]	auto[1]	auto[0]	13170583	1			T1	40023		T2	27		T3	7994
all_values[0]	auto[1]	auto[1]	46062	1			T1	134		T2	4		T3	35
all_values[1]	auto[0]	auto[0]	35041	1			T1	2		T4	9		T23	1643
all_values[1]	auto[0]	auto[1]	213	1			T11	1		T13	3		T42	2
all_values[1]	auto[1]	auto[0]	13222160	1			T1	43020		T2	31		T3	8361
all_values[1]	auto[1]	auto[1]	488	1			T11	5		T12	35		T13	3
all_values[2]	auto[0]	auto[0]	21228	1			T25	1284		T11	20		T15	2
all_values[2]	auto[0]	auto[1]	8543	1			T13	3		T42	2		T5	6
all_values[2]	auto[1]	auto[0]	11155593	1			T1	17294		T2	31		T3	8361
all_values[2]	auto[1]	auto[1]	2072538	1			T1	25728		T4	19486		T14	10534