Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	13257902	1			T1	43022		T2	31		T3	8361
all_pins[1]	13257902	1			T1	43022		T2	31		T3	8361
all_pins[2]	13257902	1			T1	43022		T2	31		T3	8361

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	37653305	1			T1	103201		T2	89		T3	25048
values[0x1]	2120401	1			T1	25865		T2	4		T3	35
transitions[0x0=>0x1]	2120226	1			T1	25865		T2	4		T3	35
transitions[0x1=>0x0]	2120245	1			T1	25865		T2	4		T3	35

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	13210559	1			T1	42885		T2	27		T3	8326
all_pins[0]	values[0x1]	47343	1			T1	137		T2	4		T3	35
all_pins[0]	transitions[0x0=>0x1]	47272	1			T1	137		T2	4		T3	35
all_pins[0]	transitions[0x1=>0x0]	2072486	1			T1	25728		T4	19486		T14	10534
all_pins[1]	values[0x0]	13257382	1			T1	43022		T2	31		T3	8361
all_pins[1]	values[0x1]	520	1			T11	5		T12	35		T13	3
all_pins[1]	transitions[0x0=>0x1]	461	1			T11	5		T12	35		T13	2
all_pins[1]	transitions[0x1=>0x0]	47284	1			T1	137		T2	4		T3	35
all_pins[2]	values[0x0]	11185364	1			T1	17294		T2	31		T3	8361
all_pins[2]	values[0x1]	2072538	1			T1	25728		T4	19486		T14	10534
all_pins[2]	transitions[0x0=>0x1]	2072493	1			T1	25728		T4	19486		T14	10534
all_pins[2]	transitions[0x1=>0x0]	475	1			T11	5		T12	35		T13	3