Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 981 1 T11 4 T13 17 T42 10
all_values[1] 981 1 T11 4 T13 17 T42 10
all_values[2] 981 1 T11 4 T13 17 T42 10


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1468 1 T11 4 T13 21 T42 11
auto[1] 1475 1 T11 8 T13 30 T42 19


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1073 1 T11 7 T13 22 T42 15
auto[1] 1870 1 T11 5 T13 29 T42 15


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1699 1 T11 8 T13 31 T42 17
auto[1] 1244 1 T11 4 T13 20 T42 13


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 192 1 T13 5 T42 1 T5 4
all_values[0] auto[0] auto[0] auto[1] 93 1 T41 1 T5 3 T6 1
all_values[0] auto[0] auto[1] auto[0] 175 1 T11 1 T13 5 T42 6
all_values[0] auto[0] auto[1] auto[1] 94 1 T103 1 T6 1 T104 4
all_values[0] auto[1] auto[0] auto[1] 203 1 T11 1 T13 4 T42 3
all_values[0] auto[1] auto[1] auto[1] 224 1 T11 2 T13 3 T5 6
all_values[1] auto[0] auto[0] auto[0] 159 1 T13 2 T42 2 T41 1
all_values[1] auto[0] auto[0] auto[1] 114 1 T13 1 T41 1 T5 3
all_values[1] auto[0] auto[1] auto[0] 163 1 T11 2 T13 4 T42 2
all_values[1] auto[0] auto[1] auto[1] 135 1 T11 1 T13 4 T42 1
all_values[1] auto[1] auto[0] auto[1] 216 1 T11 1 T13 2 T42 2
all_values[1] auto[1] auto[1] auto[1] 194 1 T13 4 T42 3 T41 1
all_values[2] auto[0] auto[0] auto[0] 208 1 T11 2 T13 4 T42 2
all_values[2] auto[0] auto[0] auto[1] 87 1 T13 1 T5 1 T6 2
all_values[2] auto[0] auto[1] auto[0] 176 1 T11 2 T13 2 T42 2
all_values[2] auto[0] auto[1] auto[1] 103 1 T13 3 T42 1 T5 2
all_values[2] auto[1] auto[0] auto[1] 196 1 T13 2 T42 1 T41 1
all_values[2] auto[1] auto[1] auto[1] 211 1 T13 5 T42 4 T5 7


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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