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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.78 92.80 85.98 100.00 78.95 88.15 99.49 69.08


Total test records in report: 731
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T538 /workspace/coverage/default/28.hmac_smoke.2193806148 Mar 21 01:03:57 PM PDT 24 Mar 21 01:04:10 PM PDT 24 454336899 ps
T539 /workspace/coverage/default/11.hmac_alert_test.3366784281 Mar 21 01:03:51 PM PDT 24 Mar 21 01:03:53 PM PDT 24 21613162 ps
T540 /workspace/coverage/default/45.hmac_error.377317794 Mar 21 01:04:48 PM PDT 24 Mar 21 01:06:04 PM PDT 24 5491137348 ps
T541 /workspace/coverage/default/61.hmac_stress_all_with_rand_reset.1324412669 Mar 21 01:05:06 PM PDT 24 Mar 21 01:22:36 PM PDT 24 128826383269 ps
T542 /workspace/coverage/default/31.hmac_test_hmac_vectors.4213156806 Mar 21 01:04:15 PM PDT 24 Mar 21 01:04:22 PM PDT 24 70712170 ps
T543 /workspace/coverage/default/18.hmac_datapath_stress.1961781927 Mar 21 01:04:00 PM PDT 24 Mar 21 01:04:24 PM PDT 24 1831651064 ps
T544 /workspace/coverage/default/28.hmac_error.1882381094 Mar 21 01:04:33 PM PDT 24 Mar 21 01:04:59 PM PDT 24 4042307747 ps
T545 /workspace/coverage/default/35.hmac_back_pressure.1250852544 Mar 21 01:04:34 PM PDT 24 Mar 21 01:05:33 PM PDT 24 1555599818 ps
T546 /workspace/coverage/default/13.hmac_error.3433777901 Mar 21 01:04:00 PM PDT 24 Mar 21 01:05:07 PM PDT 24 21152149108 ps
T547 /workspace/coverage/default/44.hmac_alert_test.2289407788 Mar 21 01:04:49 PM PDT 24 Mar 21 01:04:50 PM PDT 24 31495236 ps
T548 /workspace/coverage/default/29.hmac_long_msg.3731500153 Mar 21 01:04:21 PM PDT 24 Mar 21 01:05:46 PM PDT 24 2699822721 ps
T549 /workspace/coverage/default/38.hmac_long_msg.137950365 Mar 21 01:04:32 PM PDT 24 Mar 21 01:04:43 PM PDT 24 702937503 ps
T550 /workspace/coverage/default/43.hmac_alert_test.447360433 Mar 21 01:04:46 PM PDT 24 Mar 21 01:04:47 PM PDT 24 13454435 ps
T551 /workspace/coverage/default/0.hmac_alert_test.3366043 Mar 21 01:03:33 PM PDT 24 Mar 21 01:03:34 PM PDT 24 14644802 ps
T552 /workspace/coverage/default/13.hmac_long_msg.1301962311 Mar 21 01:03:57 PM PDT 24 Mar 21 01:05:11 PM PDT 24 1280370222 ps
T553 /workspace/coverage/default/48.hmac_burst_wr.927650631 Mar 21 01:04:59 PM PDT 24 Mar 21 01:05:27 PM PDT 24 1675059399 ps
T554 /workspace/coverage/default/1.hmac_burst_wr.1451883198 Mar 21 01:03:45 PM PDT 24 Mar 21 01:04:10 PM PDT 24 1596424972 ps
T555 /workspace/coverage/default/18.hmac_smoke.2538357626 Mar 21 01:03:58 PM PDT 24 Mar 21 01:04:11 PM PDT 24 98650624 ps
T556 /workspace/coverage/default/19.hmac_long_msg.789493709 Mar 21 01:03:58 PM PDT 24 Mar 21 01:05:10 PM PDT 24 12704259015 ps
T557 /workspace/coverage/default/12.hmac_back_pressure.1099651984 Mar 21 01:03:52 PM PDT 24 Mar 21 01:04:07 PM PDT 24 826688577 ps
T558 /workspace/coverage/default/36.hmac_test_hmac_vectors.92780041 Mar 21 01:04:28 PM PDT 24 Mar 21 01:04:30 PM PDT 24 33508475 ps
T559 /workspace/coverage/default/15.hmac_test_hmac_vectors.3758713679 Mar 21 01:04:01 PM PDT 24 Mar 21 01:04:02 PM PDT 24 51592033 ps
T560 /workspace/coverage/default/1.hmac_back_pressure.2084634306 Mar 21 01:03:42 PM PDT 24 Mar 21 01:04:28 PM PDT 24 2612310157 ps
T561 /workspace/coverage/default/30.hmac_test_sha_vectors.2751587111 Mar 21 01:04:25 PM PDT 24 Mar 21 01:11:46 PM PDT 24 35169831606 ps
T77 /workspace/coverage/default/0.hmac_stress_all.2941893380 Mar 21 01:03:41 PM PDT 24 Mar 21 01:12:41 PM PDT 24 42665513918 ps
T562 /workspace/coverage/default/30.hmac_error.790000393 Mar 21 01:04:27 PM PDT 24 Mar 21 01:08:05 PM PDT 24 16451720476 ps
T563 /workspace/coverage/default/27.hmac_datapath_stress.3503411823 Mar 21 01:04:01 PM PDT 24 Mar 21 01:04:49 PM PDT 24 3442918800 ps
T564 /workspace/coverage/default/44.hmac_smoke.1025755854 Mar 21 01:04:47 PM PDT 24 Mar 21 01:04:48 PM PDT 24 82680318 ps
T565 /workspace/coverage/default/12.hmac_test_hmac_vectors.1694094646 Mar 21 01:03:48 PM PDT 24 Mar 21 01:03:51 PM PDT 24 58964087 ps
T566 /workspace/coverage/default/46.hmac_datapath_stress.2437673034 Mar 21 01:04:50 PM PDT 24 Mar 21 01:05:38 PM PDT 24 830252925 ps
T567 /workspace/coverage/default/20.hmac_error.1919927763 Mar 21 01:03:58 PM PDT 24 Mar 21 01:07:08 PM PDT 24 15176648113 ps
T568 /workspace/coverage/default/13.hmac_alert_test.2615451677 Mar 21 01:04:01 PM PDT 24 Mar 21 01:04:08 PM PDT 24 16675709 ps
T569 /workspace/coverage/default/20.hmac_back_pressure.1973145423 Mar 21 01:04:15 PM PDT 24 Mar 21 01:04:56 PM PDT 24 1032957891 ps
T570 /workspace/coverage/default/0.hmac_test_sha_vectors.3565951262 Mar 21 01:03:33 PM PDT 24 Mar 21 01:10:25 PM PDT 24 15416911289 ps
T571 /workspace/coverage/default/15.hmac_back_pressure.2696014437 Mar 21 01:03:59 PM PDT 24 Mar 21 01:04:40 PM PDT 24 1313203104 ps
T572 /workspace/coverage/default/40.hmac_wipe_secret.2220280359 Mar 21 01:04:42 PM PDT 24 Mar 21 01:05:03 PM PDT 24 14065861591 ps
T573 /workspace/coverage/default/13.hmac_back_pressure.3729642417 Mar 21 01:03:51 PM PDT 24 Mar 21 01:04:45 PM PDT 24 10386386495 ps
T574 /workspace/coverage/default/37.hmac_smoke.1037934245 Mar 21 01:04:30 PM PDT 24 Mar 21 01:04:32 PM PDT 24 87696289 ps
T575 /workspace/coverage/default/49.hmac_wipe_secret.1708338736 Mar 21 01:05:05 PM PDT 24 Mar 21 01:05:55 PM PDT 24 27217928677 ps
T576 /workspace/coverage/default/48.hmac_smoke.896332462 Mar 21 01:04:58 PM PDT 24 Mar 21 01:05:01 PM PDT 24 836615632 ps
T577 /workspace/coverage/default/44.hmac_back_pressure.2692764122 Mar 21 01:04:48 PM PDT 24 Mar 21 01:04:50 PM PDT 24 81601395 ps
T578 /workspace/coverage/default/37.hmac_error.1471173537 Mar 21 01:04:37 PM PDT 24 Mar 21 01:05:13 PM PDT 24 4150895922 ps
T579 /workspace/coverage/default/15.hmac_burst_wr.2496366726 Mar 21 01:04:10 PM PDT 24 Mar 21 01:04:37 PM PDT 24 1911997055 ps
T30 /workspace/coverage/default/4.hmac_sec_cm.784187443 Mar 21 01:03:35 PM PDT 24 Mar 21 01:03:37 PM PDT 24 69477516 ps
T580 /workspace/coverage/default/172.hmac_stress_all_with_rand_reset.1111803923 Mar 21 01:05:22 PM PDT 24 Mar 21 01:25:10 PM PDT 24 75104457195 ps
T581 /workspace/coverage/default/30.hmac_back_pressure.483289948 Mar 21 01:04:25 PM PDT 24 Mar 21 01:04:56 PM PDT 24 7287615171 ps
T582 /workspace/coverage/default/38.hmac_stress_all.3227171281 Mar 21 01:04:33 PM PDT 24 Mar 21 01:16:27 PM PDT 24 12831810387 ps
T583 /workspace/coverage/default/19.hmac_burst_wr.2556642065 Mar 21 01:03:50 PM PDT 24 Mar 21 01:04:27 PM PDT 24 2928448422 ps
T584 /workspace/coverage/default/8.hmac_alert_test.1237016740 Mar 21 01:03:47 PM PDT 24 Mar 21 01:03:49 PM PDT 24 34154768 ps
T585 /workspace/coverage/default/36.hmac_datapath_stress.3865766351 Mar 21 01:04:28 PM PDT 24 Mar 21 01:06:04 PM PDT 24 1569867490 ps
T586 /workspace/coverage/default/2.hmac_burst_wr.3876205067 Mar 21 01:03:36 PM PDT 24 Mar 21 01:04:09 PM PDT 24 1671211659 ps
T587 /workspace/coverage/default/24.hmac_back_pressure.1162037084 Mar 21 01:04:00 PM PDT 24 Mar 21 01:04:20 PM PDT 24 3096129992 ps
T588 /workspace/coverage/default/41.hmac_smoke.4264825118 Mar 21 01:04:39 PM PDT 24 Mar 21 01:04:42 PM PDT 24 24866532 ps
T589 /workspace/coverage/default/49.hmac_back_pressure.4040813923 Mar 21 01:04:56 PM PDT 24 Mar 21 01:05:43 PM PDT 24 4797497805 ps
T590 /workspace/coverage/default/32.hmac_burst_wr.4192621029 Mar 21 01:04:30 PM PDT 24 Mar 21 01:05:12 PM PDT 24 4965132216 ps
T591 /workspace/coverage/default/21.hmac_burst_wr.2822416902 Mar 21 01:03:59 PM PDT 24 Mar 21 01:04:25 PM PDT 24 2169436102 ps
T592 /workspace/coverage/default/18.hmac_test_sha_vectors.2797996993 Mar 21 01:03:58 PM PDT 24 Mar 21 01:12:09 PM PDT 24 8593260292 ps
T593 /workspace/coverage/default/5.hmac_stress_all.1146235794 Mar 21 01:03:36 PM PDT 24 Mar 21 01:07:28 PM PDT 24 5164908479 ps
T594 /workspace/coverage/default/27.hmac_burst_wr.2983777599 Mar 21 01:03:58 PM PDT 24 Mar 21 01:05:06 PM PDT 24 5325333316 ps
T595 /workspace/coverage/default/48.hmac_wipe_secret.3464006397 Mar 21 01:04:57 PM PDT 24 Mar 21 01:06:00 PM PDT 24 3437202445 ps
T596 /workspace/coverage/default/39.hmac_error.1339050894 Mar 21 01:04:38 PM PDT 24 Mar 21 01:05:41 PM PDT 24 6581308424 ps
T597 /workspace/coverage/default/43.hmac_error.3834467505 Mar 21 01:04:46 PM PDT 24 Mar 21 01:07:24 PM PDT 24 7093198318 ps
T598 /workspace/coverage/default/49.hmac_burst_wr.3287618746 Mar 21 01:05:06 PM PDT 24 Mar 21 01:05:33 PM PDT 24 6324500073 ps
T599 /workspace/coverage/default/32.hmac_wipe_secret.846711994 Mar 21 01:04:30 PM PDT 24 Mar 21 01:05:05 PM PDT 24 660411855 ps
T600 /workspace/coverage/default/47.hmac_stress_all.2352559000 Mar 21 01:04:58 PM PDT 24 Mar 21 01:18:41 PM PDT 24 16039778055 ps
T601 /workspace/coverage/default/31.hmac_smoke.2820560190 Mar 21 01:04:14 PM PDT 24 Mar 21 01:04:18 PM PDT 24 775107059 ps
T58 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1557913560 Mar 21 01:01:19 PM PDT 24 Mar 21 01:01:24 PM PDT 24 271561152 ps
T61 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3214517445 Mar 21 01:01:12 PM PDT 24 Mar 21 01:01:15 PM PDT 24 131595308 ps
T62 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.14199574 Mar 21 01:01:12 PM PDT 24 Mar 21 01:01:15 PM PDT 24 133362527 ps
T602 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1986624214 Mar 21 01:01:29 PM PDT 24 Mar 21 01:05:19 PM PDT 24 61644480668 ps
T59 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3258290417 Mar 21 01:01:13 PM PDT 24 Mar 21 01:01:17 PM PDT 24 122351787 ps
T60 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3595475413 Mar 21 01:01:21 PM PDT 24 Mar 21 01:01:24 PM PDT 24 335063998 ps
T603 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2196997143 Mar 21 01:01:14 PM PDT 24 Mar 21 01:01:17 PM PDT 24 48283554 ps
T604 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3377293207 Mar 21 01:01:13 PM PDT 24 Mar 21 01:01:15 PM PDT 24 224515907 ps
T95 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.4031489750 Mar 21 01:01:14 PM PDT 24 Mar 21 01:01:15 PM PDT 24 77660866 ps
T605 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2661552505 Mar 21 01:01:19 PM PDT 24 Mar 21 01:01:19 PM PDT 24 20505925 ps
T606 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2561381954 Mar 21 01:01:19 PM PDT 24 Mar 21 01:01:20 PM PDT 24 41130828 ps
T607 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1176223466 Mar 21 01:01:14 PM PDT 24 Mar 21 01:01:16 PM PDT 24 64637377 ps
T608 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1907702174 Mar 21 01:01:21 PM PDT 24 Mar 21 01:01:25 PM PDT 24 218691682 ps
T609 /workspace/coverage/cover_reg_top/12.hmac_intr_test.84731792 Mar 21 01:01:40 PM PDT 24 Mar 21 01:01:41 PM PDT 24 15039281 ps
T610 /workspace/coverage/cover_reg_top/30.hmac_intr_test.4038203962 Mar 21 01:01:23 PM PDT 24 Mar 21 01:01:24 PM PDT 24 83284426 ps
T611 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.271734301 Mar 21 01:01:18 PM PDT 24 Mar 21 01:01:19 PM PDT 24 25952506 ps
T612 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3952696187 Mar 21 01:01:13 PM PDT 24 Mar 21 01:01:16 PM PDT 24 88745450 ps
T613 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2531133737 Mar 21 01:01:23 PM PDT 24 Mar 21 01:01:25 PM PDT 24 68072397 ps
T614 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4278147926 Mar 21 01:01:24 PM PDT 24 Mar 21 01:01:26 PM PDT 24 508433967 ps
T615 /workspace/coverage/cover_reg_top/28.hmac_intr_test.4158550760 Mar 21 01:01:25 PM PDT 24 Mar 21 01:01:26 PM PDT 24 15413837 ps
T86 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3659345699 Mar 21 01:01:14 PM PDT 24 Mar 21 01:01:15 PM PDT 24 43322131 ps
T105 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2201559157 Mar 21 01:01:16 PM PDT 24 Mar 21 01:01:18 PM PDT 24 337716734 ps
T616 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3189690600 Mar 21 01:01:17 PM PDT 24 Mar 21 01:03:38 PM PDT 24 81516927624 ps
T617 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1712293797 Mar 21 01:01:20 PM PDT 24 Mar 21 01:01:21 PM PDT 24 47706695 ps
T87 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1276641453 Mar 21 01:01:26 PM PDT 24 Mar 21 01:01:27 PM PDT 24 275676730 ps
T88 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2654297584 Mar 21 01:01:13 PM PDT 24 Mar 21 01:01:19 PM PDT 24 737549352 ps
T618 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.245821160 Mar 21 01:01:16 PM PDT 24 Mar 21 01:01:18 PM PDT 24 131053657 ps
T619 /workspace/coverage/cover_reg_top/8.hmac_intr_test.36817341 Mar 21 01:01:18 PM PDT 24 Mar 21 01:01:18 PM PDT 24 43201993 ps
T620 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1113461037 Mar 21 01:01:21 PM PDT 24 Mar 21 01:01:22 PM PDT 24 12186629 ps
T112 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1795147619 Mar 21 01:01:09 PM PDT 24 Mar 21 01:01:11 PM PDT 24 297794908 ps
T621 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2207315496 Mar 21 01:01:24 PM PDT 24 Mar 21 01:01:25 PM PDT 24 43417083 ps
T622 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3306959661 Mar 21 01:01:21 PM PDT 24 Mar 21 01:01:23 PM PDT 24 47404970 ps
T106 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1082363344 Mar 21 01:01:18 PM PDT 24 Mar 21 01:01:22 PM PDT 24 776647021 ps
T623 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1266873917 Mar 21 01:01:12 PM PDT 24 Mar 21 01:01:14 PM PDT 24 114560507 ps
T624 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3647208259 Mar 21 01:01:13 PM PDT 24 Mar 21 01:01:17 PM PDT 24 58649023 ps
T109 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3173867483 Mar 21 01:01:45 PM PDT 24 Mar 21 01:01:49 PM PDT 24 428891835 ps
T89 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3594954593 Mar 21 01:01:19 PM PDT 24 Mar 21 01:01:20 PM PDT 24 126557920 ps
T625 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3052490031 Mar 21 01:01:18 PM PDT 24 Mar 21 01:01:19 PM PDT 24 107226744 ps
T626 /workspace/coverage/cover_reg_top/39.hmac_intr_test.2803466512 Mar 21 01:01:44 PM PDT 24 Mar 21 01:01:45 PM PDT 24 56666346 ps
T90 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1100313725 Mar 21 01:01:13 PM PDT 24 Mar 21 01:01:16 PM PDT 24 58771712 ps
T627 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.973812403 Mar 21 01:01:21 PM PDT 24 Mar 21 01:01:25 PM PDT 24 398128873 ps
T628 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3198248075 Mar 21 01:01:42 PM PDT 24 Mar 21 01:01:42 PM PDT 24 11910285 ps
T629 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1098238499 Mar 21 01:01:11 PM PDT 24 Mar 21 01:01:26 PM PDT 24 20878313167 ps
T91 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1986923475 Mar 21 01:01:11 PM PDT 24 Mar 21 01:01:15 PM PDT 24 79243651 ps
T630 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2673587920 Mar 21 01:01:45 PM PDT 24 Mar 21 01:01:46 PM PDT 24 38097051 ps
T631 /workspace/coverage/cover_reg_top/26.hmac_intr_test.4266251656 Mar 21 01:01:46 PM PDT 24 Mar 21 01:01:47 PM PDT 24 28734237 ps
T632 /workspace/coverage/cover_reg_top/7.hmac_intr_test.3842477272 Mar 21 01:01:19 PM PDT 24 Mar 21 01:01:20 PM PDT 24 12476775 ps
T633 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1291387085 Mar 21 01:01:09 PM PDT 24 Mar 21 01:26:55 PM PDT 24 1257606955626 ps
T92 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3975649206 Mar 21 01:01:27 PM PDT 24 Mar 21 01:01:28 PM PDT 24 49375744 ps
T93 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.949247670 Mar 21 01:01:25 PM PDT 24 Mar 21 01:01:27 PM PDT 24 48470758 ps
T634 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3572016667 Mar 21 01:01:14 PM PDT 24 Mar 21 01:01:30 PM PDT 24 1053129983 ps
T635 /workspace/coverage/cover_reg_top/27.hmac_intr_test.613945232 Mar 21 01:01:24 PM PDT 24 Mar 21 01:01:25 PM PDT 24 58132193 ps
T636 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1926944170 Mar 21 01:01:45 PM PDT 24 Mar 21 01:01:46 PM PDT 24 31435189 ps
T637 /workspace/coverage/cover_reg_top/42.hmac_intr_test.631512801 Mar 21 01:01:46 PM PDT 24 Mar 21 01:01:46 PM PDT 24 48040592 ps
T638 /workspace/coverage/cover_reg_top/5.hmac_intr_test.516615643 Mar 21 01:01:22 PM PDT 24 Mar 21 01:01:24 PM PDT 24 30790154 ps
T94 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2546022271 Mar 21 01:01:20 PM PDT 24 Mar 21 01:01:21 PM PDT 24 19429102 ps
T639 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.522342860 Mar 21 01:01:29 PM PDT 24 Mar 21 01:01:31 PM PDT 24 92080888 ps
T96 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.948473881 Mar 21 01:01:10 PM PDT 24 Mar 21 01:01:16 PM PDT 24 351393311 ps
T640 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1744372590 Mar 21 01:01:17 PM PDT 24 Mar 21 01:01:19 PM PDT 24 80876614 ps
T97 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1552794217 Mar 21 01:01:13 PM PDT 24 Mar 21 01:01:15 PM PDT 24 217270726 ps
T641 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1835798359 Mar 21 01:01:17 PM PDT 24 Mar 21 01:01:18 PM PDT 24 316801114 ps
T642 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1848073979 Mar 21 01:01:13 PM PDT 24 Mar 21 01:01:15 PM PDT 24 220387023 ps
T643 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2132290403 Mar 21 01:01:13 PM PDT 24 Mar 21 01:01:14 PM PDT 24 39963141 ps
T644 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3459131579 Mar 21 01:01:17 PM PDT 24 Mar 21 01:01:18 PM PDT 24 25273201 ps
T645 /workspace/coverage/cover_reg_top/17.hmac_intr_test.2485429511 Mar 21 01:01:26 PM PDT 24 Mar 21 01:01:26 PM PDT 24 29642756 ps
T646 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2442613793 Mar 21 01:01:38 PM PDT 24 Mar 21 01:01:40 PM PDT 24 117807930 ps
T98 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3720697257 Mar 21 01:01:13 PM PDT 24 Mar 21 01:01:23 PM PDT 24 1468859531 ps
T113 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2047692878 Mar 21 01:01:29 PM PDT 24 Mar 21 01:01:33 PM PDT 24 755109694 ps
T647 /workspace/coverage/cover_reg_top/38.hmac_intr_test.1329444891 Mar 21 01:01:31 PM PDT 24 Mar 21 01:01:32 PM PDT 24 106551673 ps
T648 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1435344209 Mar 21 01:01:38 PM PDT 24 Mar 21 01:01:46 PM PDT 24 299061068 ps
T649 /workspace/coverage/cover_reg_top/35.hmac_intr_test.3830679598 Mar 21 01:01:46 PM PDT 24 Mar 21 01:01:46 PM PDT 24 25341461 ps
T99 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.260736514 Mar 21 01:01:18 PM PDT 24 Mar 21 01:01:19 PM PDT 24 33548444 ps
T650 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3565929846 Mar 21 01:01:09 PM PDT 24 Mar 21 01:01:10 PM PDT 24 58731774 ps
T651 /workspace/coverage/cover_reg_top/32.hmac_intr_test.4124414447 Mar 21 01:01:44 PM PDT 24 Mar 21 01:01:45 PM PDT 24 17057299 ps
T652 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.91182211 Mar 21 01:01:37 PM PDT 24 Mar 21 01:01:40 PM PDT 24 142077111 ps
T653 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.305282103 Mar 21 01:01:13 PM PDT 24 Mar 21 01:01:15 PM PDT 24 174488128 ps
T654 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1886616452 Mar 21 01:01:18 PM PDT 24 Mar 21 01:01:19 PM PDT 24 55829612 ps
T655 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2893052975 Mar 21 01:01:16 PM PDT 24 Mar 21 01:01:17 PM PDT 24 52302590 ps
T656 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3569076876 Mar 21 01:01:40 PM PDT 24 Mar 21 01:01:41 PM PDT 24 165748450 ps
T657 /workspace/coverage/cover_reg_top/19.hmac_intr_test.4134884919 Mar 21 01:01:21 PM PDT 24 Mar 21 01:01:22 PM PDT 24 16995858 ps
T658 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3078704862 Mar 21 01:01:17 PM PDT 24 Mar 21 01:01:19 PM PDT 24 61096494 ps
T116 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3162300357 Mar 21 01:01:23 PM PDT 24 Mar 21 01:01:27 PM PDT 24 346153922 ps
T659 /workspace/coverage/cover_reg_top/3.hmac_intr_test.962901231 Mar 21 01:01:25 PM PDT 24 Mar 21 01:01:26 PM PDT 24 131364590 ps
T660 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1472581695 Mar 21 01:01:09 PM PDT 24 Mar 21 01:01:10 PM PDT 24 44069861 ps
T661 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1525801678 Mar 21 01:01:19 PM PDT 24 Mar 21 01:01:20 PM PDT 24 39047024 ps
T662 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1639400593 Mar 21 01:01:10 PM PDT 24 Mar 21 01:01:10 PM PDT 24 55152934 ps
T663 /workspace/coverage/cover_reg_top/9.hmac_intr_test.1832427791 Mar 21 01:01:12 PM PDT 24 Mar 21 01:01:14 PM PDT 24 39225607 ps
T664 /workspace/coverage/cover_reg_top/6.hmac_intr_test.2648972402 Mar 21 01:01:24 PM PDT 24 Mar 21 01:01:24 PM PDT 24 15222039 ps
T665 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2179616384 Mar 21 01:01:17 PM PDT 24 Mar 21 01:01:18 PM PDT 24 31326257 ps
T666 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1340934705 Mar 21 01:01:21 PM PDT 24 Mar 21 01:01:24 PM PDT 24 341048640 ps
T110 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2556330471 Mar 21 01:01:17 PM PDT 24 Mar 21 01:01:20 PM PDT 24 654203526 ps
T667 /workspace/coverage/cover_reg_top/47.hmac_intr_test.3198097720 Mar 21 01:01:25 PM PDT 24 Mar 21 01:01:26 PM PDT 24 22653177 ps
T668 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2686378680 Mar 21 01:01:14 PM PDT 24 Mar 21 01:01:15 PM PDT 24 232040789 ps
T669 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3821125571 Mar 21 01:01:16 PM PDT 24 Mar 21 01:01:18 PM PDT 24 269532331 ps
T670 /workspace/coverage/cover_reg_top/14.hmac_intr_test.4041641855 Mar 21 01:01:26 PM PDT 24 Mar 21 01:01:27 PM PDT 24 25955838 ps
T671 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3571810280 Mar 21 01:01:13 PM PDT 24 Mar 21 01:01:16 PM PDT 24 155321918 ps
T672 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.679357848 Mar 21 01:01:14 PM PDT 24 Mar 21 01:01:16 PM PDT 24 840581222 ps
T673 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.604637366 Mar 21 01:01:20 PM PDT 24 Mar 21 01:01:22 PM PDT 24 46742354 ps
T117 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3271193592 Mar 21 01:01:22 PM PDT 24 Mar 21 01:01:25 PM PDT 24 104636806 ps
T674 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2245440189 Mar 21 01:01:44 PM PDT 24 Mar 21 01:01:45 PM PDT 24 56875703 ps
T675 /workspace/coverage/cover_reg_top/40.hmac_intr_test.32978126 Mar 21 01:01:43 PM PDT 24 Mar 21 01:01:44 PM PDT 24 130124502 ps
T676 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3861257466 Mar 21 01:01:19 PM PDT 24 Mar 21 01:01:20 PM PDT 24 96295895 ps
T677 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2240949448 Mar 21 01:01:42 PM PDT 24 Mar 21 01:01:45 PM PDT 24 215585515 ps
T678 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1812071960 Mar 21 01:01:26 PM PDT 24 Mar 21 01:01:28 PM PDT 24 122398742 ps
T107 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1546209672 Mar 21 01:01:12 PM PDT 24 Mar 21 01:01:17 PM PDT 24 1139729268 ps
T679 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3986023011 Mar 21 01:01:13 PM PDT 24 Mar 21 01:01:15 PM PDT 24 32902816 ps
T680 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1604298400 Mar 21 01:01:45 PM PDT 24 Mar 21 01:01:46 PM PDT 24 186505008 ps
T681 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2882635644 Mar 21 01:01:18 PM PDT 24 Mar 21 01:01:19 PM PDT 24 32760135 ps
T682 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2489514421 Mar 21 01:01:13 PM PDT 24 Mar 21 01:01:23 PM PDT 24 209341611 ps
T683 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1452106658 Mar 21 01:01:12 PM PDT 24 Mar 21 01:01:16 PM PDT 24 59243335 ps
T684 /workspace/coverage/cover_reg_top/2.hmac_intr_test.630770890 Mar 21 01:01:08 PM PDT 24 Mar 21 01:01:08 PM PDT 24 31315753 ps
T685 /workspace/coverage/cover_reg_top/36.hmac_intr_test.184393996 Mar 21 01:01:35 PM PDT 24 Mar 21 01:01:36 PM PDT 24 19631065 ps
T114 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1011649705 Mar 21 01:01:24 PM PDT 24 Mar 21 01:01:28 PM PDT 24 326029887 ps
T100 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2349554884 Mar 21 01:01:12 PM PDT 24 Mar 21 01:01:24 PM PDT 24 1091408397 ps
T686 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2212796788 Mar 21 01:01:09 PM PDT 24 Mar 21 01:01:12 PM PDT 24 169684239 ps
T108 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3534507191 Mar 21 01:01:21 PM PDT 24 Mar 21 01:01:24 PM PDT 24 200880640 ps
T118 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.4188687729 Mar 21 01:01:14 PM PDT 24 Mar 21 01:01:16 PM PDT 24 98786583 ps
T687 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2200242505 Mar 21 01:01:15 PM PDT 24 Mar 21 01:01:19 PM PDT 24 600633531 ps
T688 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.4000249379 Mar 21 01:01:17 PM PDT 24 Mar 21 01:01:18 PM PDT 24 87048049 ps
T689 /workspace/coverage/cover_reg_top/29.hmac_intr_test.3316632261 Mar 21 01:01:20 PM PDT 24 Mar 21 01:01:21 PM PDT 24 35509067 ps
T690 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3875459596 Mar 21 01:01:23 PM PDT 24 Mar 21 01:01:24 PM PDT 24 58927387 ps
T691 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2679223812 Mar 21 01:01:25 PM PDT 24 Mar 21 01:01:26 PM PDT 24 29772470 ps
T692 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3778150079 Mar 21 01:01:16 PM PDT 24 Mar 21 01:01:18 PM PDT 24 66888290 ps
T693 /workspace/coverage/cover_reg_top/22.hmac_intr_test.904673562 Mar 21 01:01:20 PM PDT 24 Mar 21 01:01:20 PM PDT 24 27075741 ps
T101 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1319403271 Mar 21 01:01:16 PM PDT 24 Mar 21 01:01:21 PM PDT 24 210289853 ps
T694 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1116985718 Mar 21 01:01:42 PM PDT 24 Mar 21 01:01:43 PM PDT 24 16756212 ps
T695 /workspace/coverage/cover_reg_top/41.hmac_intr_test.3970763899 Mar 21 01:01:31 PM PDT 24 Mar 21 01:01:31 PM PDT 24 15169483 ps
T696 /workspace/coverage/cover_reg_top/25.hmac_intr_test.108853713 Mar 21 01:01:42 PM PDT 24 Mar 21 01:01:42 PM PDT 24 87529944 ps
T697 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.35770784 Mar 21 01:01:23 PM PDT 24 Mar 21 01:01:27 PM PDT 24 365099907 ps
T698 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.59169329 Mar 21 01:01:17 PM PDT 24 Mar 21 01:01:19 PM PDT 24 40623379 ps
T699 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.716651726 Mar 21 01:01:18 PM PDT 24 Mar 21 01:01:19 PM PDT 24 12902506 ps
T700 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.814296339 Mar 21 01:01:45 PM PDT 24 Mar 21 01:01:46 PM PDT 24 17041701 ps
T115 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3376959144 Mar 21 01:01:28 PM PDT 24 Mar 21 01:01:31 PM PDT 24 735887684 ps
T701 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.374045995 Mar 21 01:01:15 PM PDT 24 Mar 21 01:01:16 PM PDT 24 108539307 ps
T702 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.427438738 Mar 21 01:01:12 PM PDT 24 Mar 21 01:01:14 PM PDT 24 407442746 ps
T703 /workspace/coverage/cover_reg_top/4.hmac_intr_test.3309964572 Mar 21 01:01:08 PM PDT 24 Mar 21 01:01:09 PM PDT 24 22724607 ps
T704 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1734112228 Mar 21 01:01:18 PM PDT 24 Mar 21 01:01:20 PM PDT 24 61272522 ps
T705 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2453833856 Mar 21 01:01:20 PM PDT 24 Mar 21 01:01:23 PM PDT 24 88371480 ps
T706 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.334441848 Mar 21 01:01:13 PM PDT 24 Mar 21 01:01:14 PM PDT 24 78000347 ps
T707 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1853457997 Mar 21 01:01:31 PM PDT 24 Mar 21 01:01:32 PM PDT 24 17357395 ps
T708 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.4113545078 Mar 21 01:01:13 PM PDT 24 Mar 21 01:01:15 PM PDT 24 87732508 ps
T111 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.4065475846 Mar 21 01:01:16 PM PDT 24 Mar 21 01:01:21 PM PDT 24 576053795 ps
T709 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.518975754 Mar 21 01:01:16 PM PDT 24 Mar 21 01:01:17 PM PDT 24 38215168 ps
T710 /workspace/coverage/cover_reg_top/24.hmac_intr_test.2681343970 Mar 21 01:01:24 PM PDT 24 Mar 21 01:01:26 PM PDT 24 19254049 ps
T711 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1751384098 Mar 21 01:01:13 PM PDT 24 Mar 21 01:01:17 PM PDT 24 136757528 ps
T712 /workspace/coverage/cover_reg_top/31.hmac_intr_test.4207622512 Mar 21 01:01:25 PM PDT 24 Mar 21 01:01:26 PM PDT 24 14454044 ps
T713 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4286700563 Mar 21 01:01:28 PM PDT 24 Mar 21 01:01:31 PM PDT 24 87005166 ps
T714 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.707667224 Mar 21 01:01:21 PM PDT 24 Mar 21 01:04:03 PM PDT 24 45039800791 ps
T715 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.4090738195 Mar 21 01:01:42 PM PDT 24 Mar 21 01:01:47 PM PDT 24 227482276 ps
T716 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2469999077 Mar 21 01:01:20 PM PDT 24 Mar 21 01:01:24 PM PDT 24 163316380 ps
T717 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2711659074 Mar 21 01:01:26 PM PDT 24 Mar 21 01:01:27 PM PDT 24 41220167 ps
T718 /workspace/coverage/cover_reg_top/48.hmac_intr_test.2786548440 Mar 21 01:01:43 PM PDT 24 Mar 21 01:01:44 PM PDT 24 20207816 ps
T719 /workspace/coverage/cover_reg_top/11.hmac_intr_test.3560754527 Mar 21 01:01:26 PM PDT 24 Mar 21 01:01:26 PM PDT 24 57349616 ps
T720 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3413047326 Mar 21 01:01:19 PM PDT 24 Mar 21 01:01:20 PM PDT 24 126998262 ps
T721 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3365981505 Mar 21 01:01:26 PM PDT 24 Mar 21 01:01:27 PM PDT 24 38073278 ps
T722 /workspace/coverage/cover_reg_top/0.hmac_intr_test.881538401 Mar 21 01:01:09 PM PDT 24 Mar 21 01:01:10 PM PDT 24 42463820 ps
T723 /workspace/coverage/cover_reg_top/34.hmac_intr_test.758494187 Mar 21 01:01:26 PM PDT 24 Mar 21 01:01:27 PM PDT 24 40111127 ps
T724 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2678016974 Mar 21 01:01:17 PM PDT 24 Mar 21 01:01:21 PM PDT 24 188305592 ps
T725 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3952382367 Mar 21 01:01:26 PM PDT 24 Mar 21 01:01:27 PM PDT 24 14678166 ps
T726 /workspace/coverage/cover_reg_top/20.hmac_intr_test.97419811 Mar 21 01:01:29 PM PDT 24 Mar 21 01:01:29 PM PDT 24 49542716 ps
T727 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3494716231 Mar 21 01:01:17 PM PDT 24 Mar 21 01:05:19 PM PDT 24 47925142705 ps
T728 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.678513135 Mar 21 01:01:11 PM PDT 24 Mar 21 01:01:12 PM PDT 24 231392432 ps
T729 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3009419961 Mar 21 01:01:18 PM PDT 24 Mar 21 01:01:20 PM PDT 24 113394164 ps
T730 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2732917800 Mar 21 01:01:12 PM PDT 24 Mar 21 01:01:19 PM PDT 24 118918624 ps
T731 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.223196063 Mar 21 01:01:11 PM PDT 24 Mar 21 01:01:13 PM PDT 24 61071410 ps

Test location /workspace/coverage/default/14.hmac_stress_all.3877591124
Short name T1
Test name
Test status
Simulation time 25765056548 ps
CPU time 360.61 seconds
Started Mar 21 01:04:00 PM PDT 24
Finished Mar 21 01:10:01 PM PDT 24
Peak memory 249396 kb
Host smart-326b498b-fe42-4ec9-9212-b8fd4a7a3ec6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877591124 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3877591124
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/55.hmac_stress_all_with_rand_reset.2261183686
Short name T12
Test name
Test status
Simulation time 92091003194 ps
CPU time 603.85 seconds
Started Mar 21 01:05:06 PM PDT 24
Finished Mar 21 01:15:11 PM PDT 24
Peak memory 257840 kb
Host smart-2ee835cd-a531-4777-a487-5a42e294737f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2261183686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.hmac_stress_all_with_rand_reset.2261183686
Directory /workspace/55.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.hmac_stress_all_with_rand_reset.1964851333
Short name T6
Test name
Test status
Simulation time 104432088708 ps
CPU time 2075.37 seconds
Started Mar 21 01:04:23 PM PDT 24
Finished Mar 21 01:38:59 PM PDT 24
Peak memory 225216 kb
Host smart-07e402c4-d764-4a23-8597-c9f8432ae6e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1964851333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all_with_rand_reset.1964851333
Directory /workspace/33.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/105.hmac_stress_all_with_rand_reset.1982495975
Short name T8
Test name
Test status
Simulation time 203848889530 ps
CPU time 2573.1 seconds
Started Mar 21 01:05:16 PM PDT 24
Finished Mar 21 01:48:09 PM PDT 24
Peak memory 266120 kb
Host smart-9b865600-1d0c-490d-a337-e925b5c4df97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1982495975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.hmac_stress_all_with_rand_reset.1982495975
Directory /workspace/105.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3083908773
Short name T28
Test name
Test status
Simulation time 127672624 ps
CPU time 0.83 seconds
Started Mar 21 01:03:34 PM PDT 24
Finished Mar 21 01:03:35 PM PDT 24
Peak memory 218720 kb
Host smart-ec8b6257-7b3c-4123-acd4-5e948778cd4b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083908773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3083908773
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1557913560
Short name T58
Test name
Test status
Simulation time 271561152 ps
CPU time 4.65 seconds
Started Mar 21 01:01:19 PM PDT 24
Finished Mar 21 01:01:24 PM PDT 24
Peak memory 199932 kb
Host smart-2484e793-b802-46ee-a9d8-aa3f5f2b1c5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557913560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1557913560
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/188.hmac_stress_all_with_rand_reset.2330533002
Short name T10
Test name
Test status
Simulation time 115558480354 ps
CPU time 3191.12 seconds
Started Mar 21 01:05:33 PM PDT 24
Finished Mar 21 01:58:45 PM PDT 24
Peak memory 252896 kb
Host smart-adb17af3-002b-40b4-acef-b3b445201b5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2330533002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.hmac_stress_all_with_rand_reset.2330533002
Directory /workspace/188.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.hmac_alert_test.868301775
Short name T16
Test name
Test status
Simulation time 13444647 ps
CPU time 0.59 seconds
Started Mar 21 01:03:50 PM PDT 24
Finished Mar 21 01:03:53 PM PDT 24
Peak memory 195564 kb
Host smart-55d9db5e-e88b-4d9f-9195-9591fff05e3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868301775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.868301775
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1986923475
Short name T91
Test name
Test status
Simulation time 79243651 ps
CPU time 1.02 seconds
Started Mar 21 01:01:11 PM PDT 24
Finished Mar 21 01:01:15 PM PDT 24
Peak memory 199048 kb
Host smart-3198e61c-e5f9-4bde-a0e1-987a294906fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986923475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1986923475
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/default/25.hmac_stress_all.130920254
Short name T11
Test name
Test status
Simulation time 94614286144 ps
CPU time 1677.9 seconds
Started Mar 21 01:04:00 PM PDT 24
Finished Mar 21 01:31:58 PM PDT 24
Peak memory 208660 kb
Host smart-0b491e8a-6bf9-446a-ac6a-80a4bb4fb1b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130920254 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.130920254
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_stress_all.26802502
Short name T43
Test name
Test status
Simulation time 44907532358 ps
CPU time 628.22 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:14:26 PM PDT 24
Peak memory 200416 kb
Host smart-6a19e03e-a8e8-47ab-8a9e-1f5c27d6abc1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26802502 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.26802502
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3376959144
Short name T115
Test name
Test status
Simulation time 735887684 ps
CPU time 3.08 seconds
Started Mar 21 01:01:28 PM PDT 24
Finished Mar 21 01:01:31 PM PDT 24
Peak memory 199936 kb
Host smart-6f6b531a-5e61-4983-9404-ebc93e2dd109
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376959144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3376959144
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.4090738195
Short name T715
Test name
Test status
Simulation time 227482276 ps
CPU time 4.65 seconds
Started Mar 21 01:01:42 PM PDT 24
Finished Mar 21 01:01:47 PM PDT 24
Peak memory 199944 kb
Host smart-8d8040fd-d1ac-46ee-afbe-11e50dbf1737
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090738195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.4090738195
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3534507191
Short name T108
Test name
Test status
Simulation time 200880640 ps
CPU time 2.08 seconds
Started Mar 21 01:01:21 PM PDT 24
Finished Mar 21 01:01:24 PM PDT 24
Peak memory 200076 kb
Host smart-a55671f9-2291-45ec-b197-cbeed22e386d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534507191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3534507191
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1047622532
Short name T41
Test name
Test status
Simulation time 60895819862 ps
CPU time 988.14 seconds
Started Mar 21 01:03:37 PM PDT 24
Finished Mar 21 01:20:06 PM PDT 24
Peak memory 200436 kb
Host smart-63b2671a-9670-45e5-9ccb-ae6f82761055
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047622532 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1047622532
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1319403271
Short name T101
Test name
Test status
Simulation time 210289853 ps
CPU time 5.46 seconds
Started Mar 21 01:01:16 PM PDT 24
Finished Mar 21 01:01:21 PM PDT 24
Peak memory 198924 kb
Host smart-8196e697-879b-438b-835b-136b8e9145b6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319403271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1319403271
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3720697257
Short name T98
Test name
Test status
Simulation time 1468859531 ps
CPU time 9.9 seconds
Started Mar 21 01:01:13 PM PDT 24
Finished Mar 21 01:01:23 PM PDT 24
Peak memory 199020 kb
Host smart-edfd6ab7-ad33-40cd-bb94-03502563b9c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720697257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3720697257
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3565929846
Short name T650
Test name
Test status
Simulation time 58731774 ps
CPU time 1.59 seconds
Started Mar 21 01:01:09 PM PDT 24
Finished Mar 21 01:01:10 PM PDT 24
Peak memory 200020 kb
Host smart-91e678b4-8733-46f9-8339-b26b1ee56a8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565929846 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.3565929846
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.4031489750
Short name T95
Test name
Test status
Simulation time 77660866 ps
CPU time 0.86 seconds
Started Mar 21 01:01:14 PM PDT 24
Finished Mar 21 01:01:15 PM PDT 24
Peak memory 199228 kb
Host smart-f398a830-81d4-482e-acdd-c82e75b8b92a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031489750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.4031489750
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.881538401
Short name T722
Test name
Test status
Simulation time 42463820 ps
CPU time 0.68 seconds
Started Mar 21 01:01:09 PM PDT 24
Finished Mar 21 01:01:10 PM PDT 24
Peak memory 194608 kb
Host smart-2f50b3d5-5d08-4c75-98f0-1d510fd7f447
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881538401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.881538401
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.679357848
Short name T672
Test name
Test status
Simulation time 840581222 ps
CPU time 2.12 seconds
Started Mar 21 01:01:14 PM PDT 24
Finished Mar 21 01:01:16 PM PDT 24
Peak memory 199712 kb
Host smart-f89f45f4-ce9e-4ea5-ade0-9082c5fc4e3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679357848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_
outstanding.679357848
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.223196063
Short name T731
Test name
Test status
Simulation time 61071410 ps
CPU time 1.6 seconds
Started Mar 21 01:01:11 PM PDT 24
Finished Mar 21 01:01:13 PM PDT 24
Peak memory 200080 kb
Host smart-fcdec553-e04e-46d9-98ce-73cb3a465ace
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223196063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.223196063
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1795147619
Short name T112
Test name
Test status
Simulation time 297794908 ps
CPU time 1.89 seconds
Started Mar 21 01:01:09 PM PDT 24
Finished Mar 21 01:01:11 PM PDT 24
Peak memory 200108 kb
Host smart-a5802479-a88d-4421-b914-cb181fe20573
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795147619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1795147619
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1100313725
Short name T90
Test name
Test status
Simulation time 58771712 ps
CPU time 3.1 seconds
Started Mar 21 01:01:13 PM PDT 24
Finished Mar 21 01:01:16 PM PDT 24
Peak memory 199660 kb
Host smart-318dbdad-9428-47c4-88f0-fe2ec36efa5c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100313725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1100313725
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2489514421
Short name T682
Test name
Test status
Simulation time 209341611 ps
CPU time 9.8 seconds
Started Mar 21 01:01:13 PM PDT 24
Finished Mar 21 01:01:23 PM PDT 24
Peak memory 199864 kb
Host smart-071ca156-05c8-4ed0-b404-305848f6dbc2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489514421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2489514421
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1552794217
Short name T97
Test name
Test status
Simulation time 217270726 ps
CPU time 0.99 seconds
Started Mar 21 01:01:13 PM PDT 24
Finished Mar 21 01:01:15 PM PDT 24
Peak memory 199640 kb
Host smart-b693a90a-d356-4e74-9f37-f4cdf625a706
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552794217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1552794217
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2212796788
Short name T686
Test name
Test status
Simulation time 169684239 ps
CPU time 2.7 seconds
Started Mar 21 01:01:09 PM PDT 24
Finished Mar 21 01:01:12 PM PDT 24
Peak memory 200012 kb
Host smart-4a5eb747-662f-4232-83d8-2cc928becba5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212796788 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2212796788
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1639400593
Short name T662
Test name
Test status
Simulation time 55152934 ps
CPU time 0.69 seconds
Started Mar 21 01:01:10 PM PDT 24
Finished Mar 21 01:01:10 PM PDT 24
Peak memory 197488 kb
Host smart-0d61a7b1-6e96-426c-aaf6-e9449989fc41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639400593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1639400593
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1472581695
Short name T660
Test name
Test status
Simulation time 44069861 ps
CPU time 0.64 seconds
Started Mar 21 01:01:09 PM PDT 24
Finished Mar 21 01:01:10 PM PDT 24
Peak memory 194692 kb
Host smart-55c1379b-b089-4a47-a95d-a0522786325a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472581695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1472581695
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3952696187
Short name T612
Test name
Test status
Simulation time 88745450 ps
CPU time 2.17 seconds
Started Mar 21 01:01:13 PM PDT 24
Finished Mar 21 01:01:16 PM PDT 24
Peak memory 199848 kb
Host smart-fcc052b0-49de-410e-9f4c-8dfd09c7b638
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952696187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.3952696187
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1176223466
Short name T607
Test name
Test status
Simulation time 64637377 ps
CPU time 1.63 seconds
Started Mar 21 01:01:14 PM PDT 24
Finished Mar 21 01:01:16 PM PDT 24
Peak memory 200068 kb
Host smart-814cfb47-fe99-4b14-b2a9-8ca7d64a3038
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176223466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1176223466
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3173867483
Short name T109
Test name
Test status
Simulation time 428891835 ps
CPU time 4.21 seconds
Started Mar 21 01:01:45 PM PDT 24
Finished Mar 21 01:01:49 PM PDT 24
Peak memory 200012 kb
Host smart-08fb5557-e111-470b-86b0-4f0f6e901fc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173867483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3173867483
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2453833856
Short name T705
Test name
Test status
Simulation time 88371480 ps
CPU time 2.56 seconds
Started Mar 21 01:01:20 PM PDT 24
Finished Mar 21 01:01:23 PM PDT 24
Peak memory 200096 kb
Host smart-089fcfeb-ab90-4409-8895-551a8aa27c61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453833856 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2453833856
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.14199574
Short name T62
Test name
Test status
Simulation time 133362527 ps
CPU time 0.84 seconds
Started Mar 21 01:01:12 PM PDT 24
Finished Mar 21 01:01:15 PM PDT 24
Peak memory 199156 kb
Host smart-f72b90ea-078a-4590-9708-475cfdccaf4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14199574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.14199574
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1113461037
Short name T620
Test name
Test status
Simulation time 12186629 ps
CPU time 0.59 seconds
Started Mar 21 01:01:21 PM PDT 24
Finished Mar 21 01:01:22 PM PDT 24
Peak memory 194840 kb
Host smart-6d67efbf-ba8a-418f-933a-23ae1c76731a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113461037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1113461037
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3778150079
Short name T692
Test name
Test status
Simulation time 66888290 ps
CPU time 1.02 seconds
Started Mar 21 01:01:16 PM PDT 24
Finished Mar 21 01:01:18 PM PDT 24
Peak memory 198924 kb
Host smart-57988634-a47a-4acf-a5ba-3d675b2f9162
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778150079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.3778150079
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.4113545078
Short name T708
Test name
Test status
Simulation time 87732508 ps
CPU time 2.01 seconds
Started Mar 21 01:01:13 PM PDT 24
Finished Mar 21 01:01:15 PM PDT 24
Peak memory 200096 kb
Host smart-a83a1b6e-2c11-4124-9760-fb94ca93da37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113545078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.4113545078
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1525801678
Short name T661
Test name
Test status
Simulation time 39047024 ps
CPU time 1.21 seconds
Started Mar 21 01:01:19 PM PDT 24
Finished Mar 21 01:01:20 PM PDT 24
Peak memory 199796 kb
Host smart-eeb803c0-39e0-4295-84cc-c437fa862cd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525801678 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1525801678
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3594954593
Short name T89
Test name
Test status
Simulation time 126557920 ps
CPU time 0.94 seconds
Started Mar 21 01:01:19 PM PDT 24
Finished Mar 21 01:01:20 PM PDT 24
Peak memory 198992 kb
Host smart-7b1203f2-e713-44a7-93db-917e73a09481
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594954593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3594954593
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.3560754527
Short name T719
Test name
Test status
Simulation time 57349616 ps
CPU time 0.6 seconds
Started Mar 21 01:01:26 PM PDT 24
Finished Mar 21 01:01:26 PM PDT 24
Peak memory 194596 kb
Host smart-aa780e0a-79e9-4fad-b4ac-78da080fd25e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560754527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3560754527
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3986023011
Short name T679
Test name
Test status
Simulation time 32902816 ps
CPU time 1.56 seconds
Started Mar 21 01:01:13 PM PDT 24
Finished Mar 21 01:01:15 PM PDT 24
Peak memory 199580 kb
Host smart-099eea9b-089f-45a7-96f0-ac769b05cf95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986023011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3986023011
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4286700563
Short name T713
Test name
Test status
Simulation time 87005166 ps
CPU time 2.57 seconds
Started Mar 21 01:01:28 PM PDT 24
Finished Mar 21 01:01:31 PM PDT 24
Peak memory 200060 kb
Host smart-51eaeab9-f31c-489a-8c2e-1ffec5b1a259
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286700563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.4286700563
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3189690600
Short name T616
Test name
Test status
Simulation time 81516927624 ps
CPU time 140.37 seconds
Started Mar 21 01:01:17 PM PDT 24
Finished Mar 21 01:03:38 PM PDT 24
Peak memory 215604 kb
Host smart-25e99e72-ca1f-46b4-8b75-6716d37bf76c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189690600 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.3189690600
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3413047326
Short name T720
Test name
Test status
Simulation time 126998262 ps
CPU time 0.96 seconds
Started Mar 21 01:01:19 PM PDT 24
Finished Mar 21 01:01:20 PM PDT 24
Peak memory 199724 kb
Host smart-b034266a-1479-4655-8f0d-7a59c054826a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413047326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3413047326
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.84731792
Short name T609
Test name
Test status
Simulation time 15039281 ps
CPU time 0.63 seconds
Started Mar 21 01:01:40 PM PDT 24
Finished Mar 21 01:01:41 PM PDT 24
Peak memory 194480 kb
Host smart-4da71d0e-83ed-4ad7-8121-8165543d590a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84731792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.84731792
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1712293797
Short name T617
Test name
Test status
Simulation time 47706695 ps
CPU time 1.07 seconds
Started Mar 21 01:01:20 PM PDT 24
Finished Mar 21 01:01:21 PM PDT 24
Peak memory 199592 kb
Host smart-bb8c35c8-de3c-44b7-919a-28e7a2d247a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712293797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1712293797
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.91182211
Short name T652
Test name
Test status
Simulation time 142077111 ps
CPU time 2.81 seconds
Started Mar 21 01:01:37 PM PDT 24
Finished Mar 21 01:01:40 PM PDT 24
Peak memory 199968 kb
Host smart-977a246c-3ae8-4bcd-88e9-90ae540d6c53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91182211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.91182211
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1734112228
Short name T704
Test name
Test status
Simulation time 61272522 ps
CPU time 1.11 seconds
Started Mar 21 01:01:18 PM PDT 24
Finished Mar 21 01:01:20 PM PDT 24
Peak memory 199872 kb
Host smart-5257c97e-7cd6-4de7-b7cb-880805dc3800
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734112228 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1734112228
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2893052975
Short name T655
Test name
Test status
Simulation time 52302590 ps
CPU time 0.91 seconds
Started Mar 21 01:01:16 PM PDT 24
Finished Mar 21 01:01:17 PM PDT 24
Peak memory 199152 kb
Host smart-f97aa92d-05da-4da0-9a7e-c0c72d8a5092
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893052975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2893052975
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2679223812
Short name T691
Test name
Test status
Simulation time 29772470 ps
CPU time 0.62 seconds
Started Mar 21 01:01:25 PM PDT 24
Finished Mar 21 01:01:26 PM PDT 24
Peak memory 194736 kb
Host smart-d786dbee-aa03-492c-8847-0399824e2405
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679223812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2679223812
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2442613793
Short name T646
Test name
Test status
Simulation time 117807930 ps
CPU time 1.22 seconds
Started Mar 21 01:01:38 PM PDT 24
Finished Mar 21 01:01:40 PM PDT 24
Peak memory 198052 kb
Host smart-bcdd3bb5-a7eb-4ff5-ab76-3791759c6638
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442613793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2442613793
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1435344209
Short name T648
Test name
Test status
Simulation time 299061068 ps
CPU time 2.52 seconds
Started Mar 21 01:01:38 PM PDT 24
Finished Mar 21 01:01:46 PM PDT 24
Peak memory 199964 kb
Host smart-258ce988-8d0b-4208-9cd2-6cc3151813f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435344209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1435344209
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1604298400
Short name T680
Test name
Test status
Simulation time 186505008 ps
CPU time 1.03 seconds
Started Mar 21 01:01:45 PM PDT 24
Finished Mar 21 01:01:46 PM PDT 24
Peak memory 199752 kb
Host smart-33dd5b5c-3a43-4bee-8ead-691cb12a5698
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604298400 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1604298400
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.814296339
Short name T700
Test name
Test status
Simulation time 17041701 ps
CPU time 0.78 seconds
Started Mar 21 01:01:45 PM PDT 24
Finished Mar 21 01:01:46 PM PDT 24
Peak memory 199072 kb
Host smart-3f853385-4629-434f-9ba6-b1807223d46f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814296339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.814296339
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.4041641855
Short name T670
Test name
Test status
Simulation time 25955838 ps
CPU time 0.59 seconds
Started Mar 21 01:01:26 PM PDT 24
Finished Mar 21 01:01:27 PM PDT 24
Peak memory 194732 kb
Host smart-4d5f8157-252c-4090-80a1-bc1bf564588b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041641855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.4041641855
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2196997143
Short name T603
Test name
Test status
Simulation time 48283554 ps
CPU time 2.18 seconds
Started Mar 21 01:01:14 PM PDT 24
Finished Mar 21 01:01:17 PM PDT 24
Peak memory 199776 kb
Host smart-cd5257ee-76a6-4134-9698-2826fd3ca96e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196997143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2196997143
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3647208259
Short name T624
Test name
Test status
Simulation time 58649023 ps
CPU time 3.45 seconds
Started Mar 21 01:01:13 PM PDT 24
Finished Mar 21 01:01:17 PM PDT 24
Peak memory 200056 kb
Host smart-d261ef4f-69f1-49d2-aa06-5e0cb5ecf6f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647208259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3647208259
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1082363344
Short name T106
Test name
Test status
Simulation time 776647021 ps
CPU time 4.01 seconds
Started Mar 21 01:01:18 PM PDT 24
Finished Mar 21 01:01:22 PM PDT 24
Peak memory 199964 kb
Host smart-95b808ac-2dc3-40b5-9b1f-c3e5f99b67b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082363344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1082363344
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3377293207
Short name T604
Test name
Test status
Simulation time 224515907 ps
CPU time 2.28 seconds
Started Mar 21 01:01:13 PM PDT 24
Finished Mar 21 01:01:15 PM PDT 24
Peak memory 199992 kb
Host smart-342ecb9f-e2a2-47b5-967f-e0d8b01ba949
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377293207 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.3377293207
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.949247670
Short name T93
Test name
Test status
Simulation time 48470758 ps
CPU time 0.89 seconds
Started Mar 21 01:01:25 PM PDT 24
Finished Mar 21 01:01:27 PM PDT 24
Peak memory 199412 kb
Host smart-64af0bad-b42d-4cbf-bee3-5ff1ec9d13d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949247670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.949247670
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2132290403
Short name T643
Test name
Test status
Simulation time 39963141 ps
CPU time 0.57 seconds
Started Mar 21 01:01:13 PM PDT 24
Finished Mar 21 01:01:14 PM PDT 24
Peak memory 194772 kb
Host smart-f5ba7770-331b-4218-a578-1204586c4857
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132290403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2132290403
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3875459596
Short name T690
Test name
Test status
Simulation time 58927387 ps
CPU time 1.16 seconds
Started Mar 21 01:01:23 PM PDT 24
Finished Mar 21 01:01:24 PM PDT 24
Peak memory 199668 kb
Host smart-cb9d8a45-73ba-430c-8b88-10fad4037e02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875459596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3875459596
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1907702174
Short name T608
Test name
Test status
Simulation time 218691682 ps
CPU time 3.35 seconds
Started Mar 21 01:01:21 PM PDT 24
Finished Mar 21 01:01:25 PM PDT 24
Peak memory 200020 kb
Host smart-3d921d8c-379a-4bcc-b967-bc06a96e8812
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907702174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1907702174
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1011649705
Short name T114
Test name
Test status
Simulation time 326029887 ps
CPU time 4.43 seconds
Started Mar 21 01:01:24 PM PDT 24
Finished Mar 21 01:01:28 PM PDT 24
Peak memory 199928 kb
Host smart-6ca4c863-5699-4038-ad49-76607f864e43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011649705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1011649705
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3494716231
Short name T727
Test name
Test status
Simulation time 47925142705 ps
CPU time 241.32 seconds
Started Mar 21 01:01:17 PM PDT 24
Finished Mar 21 01:05:19 PM PDT 24
Peak memory 209404 kb
Host smart-dea05568-d82e-44d4-861c-1305f45e37b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494716231 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3494716231
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1926944170
Short name T636
Test name
Test status
Simulation time 31435189 ps
CPU time 0.98 seconds
Started Mar 21 01:01:45 PM PDT 24
Finished Mar 21 01:01:46 PM PDT 24
Peak memory 199424 kb
Host smart-58f61065-5855-4356-a2aa-98abbff27c6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926944170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1926944170
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3459131579
Short name T644
Test name
Test status
Simulation time 25273201 ps
CPU time 0.57 seconds
Started Mar 21 01:01:17 PM PDT 24
Finished Mar 21 01:01:18 PM PDT 24
Peak memory 194412 kb
Host smart-0b883a8b-91ec-4fc4-b25a-4570d5082463
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459131579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3459131579
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3078704862
Short name T658
Test name
Test status
Simulation time 61096494 ps
CPU time 1.6 seconds
Started Mar 21 01:01:17 PM PDT 24
Finished Mar 21 01:01:19 PM PDT 24
Peak memory 200072 kb
Host smart-9a9eae5d-7e54-4edf-b6ed-9750ec8e0350
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078704862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3078704862
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2469999077
Short name T716
Test name
Test status
Simulation time 163316380 ps
CPU time 3.11 seconds
Started Mar 21 01:01:20 PM PDT 24
Finished Mar 21 01:01:24 PM PDT 24
Peak memory 200020 kb
Host smart-8697c6b7-eaa6-42fe-88ff-2a25e402433a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469999077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2469999077
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2556330471
Short name T110
Test name
Test status
Simulation time 654203526 ps
CPU time 2.99 seconds
Started Mar 21 01:01:17 PM PDT 24
Finished Mar 21 01:01:20 PM PDT 24
Peak memory 199932 kb
Host smart-1c1347e1-d098-4a7f-b648-4fc8a3aef320
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556330471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2556330471
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.245821160
Short name T618
Test name
Test status
Simulation time 131053657 ps
CPU time 1.17 seconds
Started Mar 21 01:01:16 PM PDT 24
Finished Mar 21 01:01:18 PM PDT 24
Peak memory 199692 kb
Host smart-0633c8d2-5c8f-4502-ad1b-63d98ba60da4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245821160 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.245821160
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1835798359
Short name T641
Test name
Test status
Simulation time 316801114 ps
CPU time 0.68 seconds
Started Mar 21 01:01:17 PM PDT 24
Finished Mar 21 01:01:18 PM PDT 24
Peak memory 197188 kb
Host smart-f691a6eb-c1a3-4e0e-bf9a-dbf6ea611b20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835798359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1835798359
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2485429511
Short name T645
Test name
Test status
Simulation time 29642756 ps
CPU time 0.59 seconds
Started Mar 21 01:01:26 PM PDT 24
Finished Mar 21 01:01:26 PM PDT 24
Peak memory 194528 kb
Host smart-c8464c14-31ec-4d2a-86be-a488c0fae36c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485429511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2485429511
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4278147926
Short name T614
Test name
Test status
Simulation time 508433967 ps
CPU time 1.63 seconds
Started Mar 21 01:01:24 PM PDT 24
Finished Mar 21 01:01:26 PM PDT 24
Peak memory 199516 kb
Host smart-ee7b6f15-cb54-4428-8602-f47d68dcbafb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278147926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.4278147926
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.59169329
Short name T698
Test name
Test status
Simulation time 40623379 ps
CPU time 1.8 seconds
Started Mar 21 01:01:17 PM PDT 24
Finished Mar 21 01:01:19 PM PDT 24
Peak memory 199980 kb
Host smart-c59453a6-6011-414a-97bc-0c03813becbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59169329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.59169329
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3595475413
Short name T60
Test name
Test status
Simulation time 335063998 ps
CPU time 1.92 seconds
Started Mar 21 01:01:21 PM PDT 24
Finished Mar 21 01:01:24 PM PDT 24
Peak memory 199940 kb
Host smart-9e003ce2-0761-4772-be91-c6bd7a15dff6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595475413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3595475413
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1812071960
Short name T678
Test name
Test status
Simulation time 122398742 ps
CPU time 2.18 seconds
Started Mar 21 01:01:26 PM PDT 24
Finished Mar 21 01:01:28 PM PDT 24
Peak memory 199992 kb
Host smart-56673c9f-6b68-41d7-9797-21a6e328c6a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812071960 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1812071960
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.260736514
Short name T99
Test name
Test status
Simulation time 33548444 ps
CPU time 0.86 seconds
Started Mar 21 01:01:18 PM PDT 24
Finished Mar 21 01:01:19 PM PDT 24
Peak memory 199304 kb
Host smart-7ce7afba-3068-4148-812a-9a1763f7aeb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260736514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.260736514
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2882635644
Short name T681
Test name
Test status
Simulation time 32760135 ps
CPU time 0.57 seconds
Started Mar 21 01:01:18 PM PDT 24
Finished Mar 21 01:01:19 PM PDT 24
Peak memory 194464 kb
Host smart-5c9c1139-c3bb-4363-bddf-a49f2f674b9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882635644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2882635644
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3306959661
Short name T622
Test name
Test status
Simulation time 47404970 ps
CPU time 1.84 seconds
Started Mar 21 01:01:21 PM PDT 24
Finished Mar 21 01:01:23 PM PDT 24
Peak memory 200048 kb
Host smart-628792bf-5326-4dee-bb2c-3604f69c60a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306959661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3306959661
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.271734301
Short name T611
Test name
Test status
Simulation time 25952506 ps
CPU time 1.43 seconds
Started Mar 21 01:01:18 PM PDT 24
Finished Mar 21 01:01:19 PM PDT 24
Peak memory 199996 kb
Host smart-76eacb98-8486-4dbb-b942-703be2256644
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271734301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.271734301
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2047692878
Short name T113
Test name
Test status
Simulation time 755109694 ps
CPU time 3.24 seconds
Started Mar 21 01:01:29 PM PDT 24
Finished Mar 21 01:01:33 PM PDT 24
Peak memory 199940 kb
Host smart-9615d48f-bc52-40d6-abe8-a3f18070e957
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047692878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2047692878
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3365981505
Short name T721
Test name
Test status
Simulation time 38073278 ps
CPU time 1.16 seconds
Started Mar 21 01:01:26 PM PDT 24
Finished Mar 21 01:01:27 PM PDT 24
Peak memory 199800 kb
Host smart-bc7b8ac4-f80f-4509-ba3a-187a0f2a32cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365981505 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3365981505
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1886616452
Short name T654
Test name
Test status
Simulation time 55829612 ps
CPU time 0.8 seconds
Started Mar 21 01:01:18 PM PDT 24
Finished Mar 21 01:01:19 PM PDT 24
Peak memory 199028 kb
Host smart-ffb5b6a4-fb49-4d3e-a6ab-491f4beec926
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886616452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1886616452
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.4134884919
Short name T657
Test name
Test status
Simulation time 16995858 ps
CPU time 0.61 seconds
Started Mar 21 01:01:21 PM PDT 24
Finished Mar 21 01:01:22 PM PDT 24
Peak memory 194544 kb
Host smart-720b8f7e-74b0-43ad-ae8e-7b9d53d06389
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134884919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.4134884919
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2240949448
Short name T677
Test name
Test status
Simulation time 215585515 ps
CPU time 2.29 seconds
Started Mar 21 01:01:42 PM PDT 24
Finished Mar 21 01:01:45 PM PDT 24
Peak memory 199920 kb
Host smart-9fb3830d-7202-46b2-a07c-a6afad43d933
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240949448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.2240949448
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.973812403
Short name T627
Test name
Test status
Simulation time 398128873 ps
CPU time 4.35 seconds
Started Mar 21 01:01:21 PM PDT 24
Finished Mar 21 01:01:25 PM PDT 24
Peak memory 199972 kb
Host smart-5ec1baf5-836a-4609-ac0f-4d84e81aa3c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973812403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.973812403
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.35770784
Short name T697
Test name
Test status
Simulation time 365099907 ps
CPU time 3.14 seconds
Started Mar 21 01:01:23 PM PDT 24
Finished Mar 21 01:01:27 PM PDT 24
Peak memory 199932 kb
Host smart-d757700b-3e9e-4139-986e-340ebbafa8b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35770784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.35770784
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.948473881
Short name T96
Test name
Test status
Simulation time 351393311 ps
CPU time 5.28 seconds
Started Mar 21 01:01:10 PM PDT 24
Finished Mar 21 01:01:16 PM PDT 24
Peak memory 199904 kb
Host smart-3fae5138-a4b2-494a-b652-a2f65e3d3445
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948473881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.948473881
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3572016667
Short name T634
Test name
Test status
Simulation time 1053129983 ps
CPU time 15.94 seconds
Started Mar 21 01:01:14 PM PDT 24
Finished Mar 21 01:01:30 PM PDT 24
Peak memory 198944 kb
Host smart-f483fff7-a98c-42c8-8a82-30a6e7dad191
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572016667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3572016667
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.518975754
Short name T709
Test name
Test status
Simulation time 38215168 ps
CPU time 0.93 seconds
Started Mar 21 01:01:16 PM PDT 24
Finished Mar 21 01:01:17 PM PDT 24
Peak memory 199108 kb
Host smart-da237aa2-74fc-45e5-ab33-72767f2356dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518975754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.518975754
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3214517445
Short name T61
Test name
Test status
Simulation time 131595308 ps
CPU time 2.32 seconds
Started Mar 21 01:01:12 PM PDT 24
Finished Mar 21 01:01:15 PM PDT 24
Peak memory 200028 kb
Host smart-8e50856a-4d04-4897-b2cb-e110ab78ea12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214517445 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3214517445
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2179616384
Short name T665
Test name
Test status
Simulation time 31326257 ps
CPU time 0.9 seconds
Started Mar 21 01:01:17 PM PDT 24
Finished Mar 21 01:01:18 PM PDT 24
Peak memory 199020 kb
Host smart-b5268e91-3eb4-4027-9c12-3fd42ec5ef08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179616384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2179616384
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.630770890
Short name T684
Test name
Test status
Simulation time 31315753 ps
CPU time 0.57 seconds
Started Mar 21 01:01:08 PM PDT 24
Finished Mar 21 01:01:08 PM PDT 24
Peak memory 194544 kb
Host smart-08d5c9e9-523a-4db1-9b68-fdaba73bceed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630770890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.630770890
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1266873917
Short name T623
Test name
Test status
Simulation time 114560507 ps
CPU time 2.35 seconds
Started Mar 21 01:01:12 PM PDT 24
Finished Mar 21 01:01:14 PM PDT 24
Peak memory 199892 kb
Host smart-68934b6e-da17-48c3-885a-320484e04042
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266873917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1266873917
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1848073979
Short name T642
Test name
Test status
Simulation time 220387023 ps
CPU time 1.3 seconds
Started Mar 21 01:01:13 PM PDT 24
Finished Mar 21 01:01:15 PM PDT 24
Peak memory 200044 kb
Host smart-0dd21168-07ef-496b-96ff-33acd2bfe229
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848073979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1848073979
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2201559157
Short name T105
Test name
Test status
Simulation time 337716734 ps
CPU time 1.72 seconds
Started Mar 21 01:01:16 PM PDT 24
Finished Mar 21 01:01:18 PM PDT 24
Peak memory 199932 kb
Host smart-e5bdc0ca-209b-4001-8057-256a1fce28ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201559157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2201559157
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.97419811
Short name T726
Test name
Test status
Simulation time 49542716 ps
CPU time 0.55 seconds
Started Mar 21 01:01:29 PM PDT 24
Finished Mar 21 01:01:29 PM PDT 24
Peak memory 194488 kb
Host smart-e3324cb1-e332-46c7-9af9-81642602cda1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97419811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.97419811
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1853457997
Short name T707
Test name
Test status
Simulation time 17357395 ps
CPU time 0.6 seconds
Started Mar 21 01:01:31 PM PDT 24
Finished Mar 21 01:01:32 PM PDT 24
Peak memory 194708 kb
Host smart-20e1bf43-2ea6-4d10-ace9-8ab29efc3d3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853457997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1853457997
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.904673562
Short name T693
Test name
Test status
Simulation time 27075741 ps
CPU time 0.55 seconds
Started Mar 21 01:01:20 PM PDT 24
Finished Mar 21 01:01:20 PM PDT 24
Peak memory 194472 kb
Host smart-0920005f-4968-4a72-b18a-d18b0c5f0b58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904673562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.904673562
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2711659074
Short name T717
Test name
Test status
Simulation time 41220167 ps
CPU time 0.57 seconds
Started Mar 21 01:01:26 PM PDT 24
Finished Mar 21 01:01:27 PM PDT 24
Peak memory 194776 kb
Host smart-75092f84-d66e-451c-81be-27ff7f91dc9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711659074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2711659074
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2681343970
Short name T710
Test name
Test status
Simulation time 19254049 ps
CPU time 0.61 seconds
Started Mar 21 01:01:24 PM PDT 24
Finished Mar 21 01:01:26 PM PDT 24
Peak memory 194544 kb
Host smart-681ce2fa-9fd3-4a8a-b7da-24c766c363f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681343970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2681343970
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.108853713
Short name T696
Test name
Test status
Simulation time 87529944 ps
CPU time 0.63 seconds
Started Mar 21 01:01:42 PM PDT 24
Finished Mar 21 01:01:42 PM PDT 24
Peak memory 194448 kb
Host smart-f86c0811-5757-4728-9740-2d241c465b21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108853713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.108853713
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.4266251656
Short name T631
Test name
Test status
Simulation time 28734237 ps
CPU time 0.62 seconds
Started Mar 21 01:01:46 PM PDT 24
Finished Mar 21 01:01:47 PM PDT 24
Peak memory 194736 kb
Host smart-bfd4ab72-45d8-45ba-b18c-2c3bdf30054c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266251656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.4266251656
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.613945232
Short name T635
Test name
Test status
Simulation time 58132193 ps
CPU time 0.59 seconds
Started Mar 21 01:01:24 PM PDT 24
Finished Mar 21 01:01:25 PM PDT 24
Peak memory 194548 kb
Host smart-4b6fe361-d9ac-49e4-b1f0-97cd17fc71a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613945232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.613945232
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.4158550760
Short name T615
Test name
Test status
Simulation time 15413837 ps
CPU time 0.62 seconds
Started Mar 21 01:01:25 PM PDT 24
Finished Mar 21 01:01:26 PM PDT 24
Peak memory 194552 kb
Host smart-88dba4f5-5f55-4695-817a-6bdfa98669c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158550760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.4158550760
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3316632261
Short name T689
Test name
Test status
Simulation time 35509067 ps
CPU time 0.61 seconds
Started Mar 21 01:01:20 PM PDT 24
Finished Mar 21 01:01:21 PM PDT 24
Peak memory 194548 kb
Host smart-f6cd3a7d-c2ae-4cce-bedc-051b872f8afb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316632261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3316632261
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1452106658
Short name T683
Test name
Test status
Simulation time 59243335 ps
CPU time 3.01 seconds
Started Mar 21 01:01:12 PM PDT 24
Finished Mar 21 01:01:16 PM PDT 24
Peak memory 198912 kb
Host smart-3b36ab98-1be5-4a0a-a4eb-db43e7a4081b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452106658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1452106658
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1098238499
Short name T629
Test name
Test status
Simulation time 20878313167 ps
CPU time 15.28 seconds
Started Mar 21 01:01:11 PM PDT 24
Finished Mar 21 01:01:26 PM PDT 24
Peak memory 199220 kb
Host smart-5c934f4d-0a3a-4292-a9b7-9c4af64bb194
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098238499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1098238499
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.334441848
Short name T706
Test name
Test status
Simulation time 78000347 ps
CPU time 0.99 seconds
Started Mar 21 01:01:13 PM PDT 24
Finished Mar 21 01:01:14 PM PDT 24
Peak memory 199140 kb
Host smart-a2baa639-64e4-450c-a26b-dd1b93e4e308
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334441848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.334441848
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2207315496
Short name T621
Test name
Test status
Simulation time 43417083 ps
CPU time 1.34 seconds
Started Mar 21 01:01:24 PM PDT 24
Finished Mar 21 01:01:25 PM PDT 24
Peak memory 199984 kb
Host smart-c5215edd-54e6-450f-82b2-167143e8da42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207315496 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2207315496
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.678513135
Short name T728
Test name
Test status
Simulation time 231392432 ps
CPU time 0.79 seconds
Started Mar 21 01:01:11 PM PDT 24
Finished Mar 21 01:01:12 PM PDT 24
Peak memory 199744 kb
Host smart-057abd65-5e72-4fd4-818a-3ca413926a5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678513135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.678513135
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.962901231
Short name T659
Test name
Test status
Simulation time 131364590 ps
CPU time 0.61 seconds
Started Mar 21 01:01:25 PM PDT 24
Finished Mar 21 01:01:26 PM PDT 24
Peak memory 194552 kb
Host smart-959054ec-e9b6-4e84-93aa-1fcfee7c0ec2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962901231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.962901231
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.305282103
Short name T653
Test name
Test status
Simulation time 174488128 ps
CPU time 1.16 seconds
Started Mar 21 01:01:13 PM PDT 24
Finished Mar 21 01:01:15 PM PDT 24
Peak memory 198724 kb
Host smart-ffb9e4bf-214c-47bf-b293-b88fd67cc29b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305282103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.305282103
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2732917800
Short name T730
Test name
Test status
Simulation time 118918624 ps
CPU time 2.18 seconds
Started Mar 21 01:01:12 PM PDT 24
Finished Mar 21 01:01:19 PM PDT 24
Peak memory 199964 kb
Host smart-e86e7aab-5e04-4e36-9a61-268bab6a0272
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732917800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2732917800
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1546209672
Short name T107
Test name
Test status
Simulation time 1139729268 ps
CPU time 3.85 seconds
Started Mar 21 01:01:12 PM PDT 24
Finished Mar 21 01:01:17 PM PDT 24
Peak memory 199948 kb
Host smart-9dd66b02-1550-4463-9c93-859ae450d0a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546209672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1546209672
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.4038203962
Short name T610
Test name
Test status
Simulation time 83284426 ps
CPU time 0.62 seconds
Started Mar 21 01:01:23 PM PDT 24
Finished Mar 21 01:01:24 PM PDT 24
Peak memory 194656 kb
Host smart-e5b8b36f-8663-4e2b-aa14-eb3c314c3f43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038203962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.4038203962
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.4207622512
Short name T712
Test name
Test status
Simulation time 14454044 ps
CPU time 0.59 seconds
Started Mar 21 01:01:25 PM PDT 24
Finished Mar 21 01:01:26 PM PDT 24
Peak memory 194488 kb
Host smart-372c9ff8-3e13-48c8-96b6-de26bbd8e305
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207622512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.4207622512
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.4124414447
Short name T651
Test name
Test status
Simulation time 17057299 ps
CPU time 0.59 seconds
Started Mar 21 01:01:44 PM PDT 24
Finished Mar 21 01:01:45 PM PDT 24
Peak memory 194800 kb
Host smart-8427225e-d6d8-417b-8de3-a28d99782fff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124414447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.4124414447
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2561381954
Short name T606
Test name
Test status
Simulation time 41130828 ps
CPU time 0.56 seconds
Started Mar 21 01:01:19 PM PDT 24
Finished Mar 21 01:01:20 PM PDT 24
Peak memory 194488 kb
Host smart-7383751c-7464-4055-b730-d01c30a2c8f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561381954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2561381954
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.758494187
Short name T723
Test name
Test status
Simulation time 40111127 ps
CPU time 0.6 seconds
Started Mar 21 01:01:26 PM PDT 24
Finished Mar 21 01:01:27 PM PDT 24
Peak memory 194484 kb
Host smart-6ec46277-b0d3-4ea3-bda4-0d0f9e305cae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758494187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.758494187
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.3830679598
Short name T649
Test name
Test status
Simulation time 25341461 ps
CPU time 0.57 seconds
Started Mar 21 01:01:46 PM PDT 24
Finished Mar 21 01:01:46 PM PDT 24
Peak memory 194756 kb
Host smart-07584328-91a9-479b-8035-d131b972e9a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830679598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3830679598
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.184393996
Short name T685
Test name
Test status
Simulation time 19631065 ps
CPU time 0.66 seconds
Started Mar 21 01:01:35 PM PDT 24
Finished Mar 21 01:01:36 PM PDT 24
Peak memory 194500 kb
Host smart-c9fda77f-71f6-493d-883f-e59687ab9538
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184393996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.184393996
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2673587920
Short name T630
Test name
Test status
Simulation time 38097051 ps
CPU time 0.58 seconds
Started Mar 21 01:01:45 PM PDT 24
Finished Mar 21 01:01:46 PM PDT 24
Peak memory 194556 kb
Host smart-7fdaae4f-ea1a-4fd8-93fa-5adc87ce655a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673587920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2673587920
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.1329444891
Short name T647
Test name
Test status
Simulation time 106551673 ps
CPU time 0.61 seconds
Started Mar 21 01:01:31 PM PDT 24
Finished Mar 21 01:01:32 PM PDT 24
Peak memory 194708 kb
Host smart-b1919153-fe97-46f2-8eac-addd68944b52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329444891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1329444891
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.2803466512
Short name T626
Test name
Test status
Simulation time 56666346 ps
CPU time 0.57 seconds
Started Mar 21 01:01:44 PM PDT 24
Finished Mar 21 01:01:45 PM PDT 24
Peak memory 194416 kb
Host smart-3102a95f-4314-4ae6-baaf-04c825979070
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803466512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.2803466512
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2654297584
Short name T88
Test name
Test status
Simulation time 737549352 ps
CPU time 6.13 seconds
Started Mar 21 01:01:13 PM PDT 24
Finished Mar 21 01:01:19 PM PDT 24
Peak memory 199120 kb
Host smart-61a31ad8-82ed-450e-8a27-062205dad936
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654297584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2654297584
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2349554884
Short name T100
Test name
Test status
Simulation time 1091408397 ps
CPU time 11.52 seconds
Started Mar 21 01:01:12 PM PDT 24
Finished Mar 21 01:01:24 PM PDT 24
Peak memory 199924 kb
Host smart-5b7f2f22-0a0e-4a5c-b954-7c3b24e23fa8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349554884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2349554884
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2245440189
Short name T674
Test name
Test status
Simulation time 56875703 ps
CPU time 0.88 seconds
Started Mar 21 01:01:44 PM PDT 24
Finished Mar 21 01:01:45 PM PDT 24
Peak memory 198380 kb
Host smart-a2e11a28-e750-45a2-a7b8-3791d5c28444
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245440189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2245440189
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1291387085
Short name T633
Test name
Test status
Simulation time 1257606955626 ps
CPU time 1545.86 seconds
Started Mar 21 01:01:09 PM PDT 24
Finished Mar 21 01:26:55 PM PDT 24
Peak memory 220740 kb
Host smart-5fe9b04f-7b2f-4117-a6b7-ce01ec009550
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291387085 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1291387085
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2546022271
Short name T94
Test name
Test status
Simulation time 19429102 ps
CPU time 0.93 seconds
Started Mar 21 01:01:20 PM PDT 24
Finished Mar 21 01:01:21 PM PDT 24
Peak memory 199736 kb
Host smart-8296e837-c370-49d2-9771-d081bbd6275a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546022271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2546022271
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3309964572
Short name T703
Test name
Test status
Simulation time 22724607 ps
CPU time 0.55 seconds
Started Mar 21 01:01:08 PM PDT 24
Finished Mar 21 01:01:09 PM PDT 24
Peak memory 194436 kb
Host smart-599f1b0f-0e0e-4180-87ce-050f8f985fef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309964572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3309964572
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3571810280
Short name T671
Test name
Test status
Simulation time 155321918 ps
CPU time 2.54 seconds
Started Mar 21 01:01:13 PM PDT 24
Finished Mar 21 01:01:16 PM PDT 24
Peak memory 199884 kb
Host smart-6af1e6ef-5374-44ce-bfd6-381f83e6af7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571810280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3571810280
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2678016974
Short name T724
Test name
Test status
Simulation time 188305592 ps
CPU time 4.21 seconds
Started Mar 21 01:01:17 PM PDT 24
Finished Mar 21 01:01:21 PM PDT 24
Peak memory 199992 kb
Host smart-a2a73de3-4ee9-4584-94ce-d4474b48f1f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678016974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.2678016974
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3258290417
Short name T59
Test name
Test status
Simulation time 122351787 ps
CPU time 3.89 seconds
Started Mar 21 01:01:13 PM PDT 24
Finished Mar 21 01:01:17 PM PDT 24
Peak memory 200016 kb
Host smart-acf0e84e-5588-4d22-a834-619188386109
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258290417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3258290417
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.32978126
Short name T675
Test name
Test status
Simulation time 130124502 ps
CPU time 0.59 seconds
Started Mar 21 01:01:43 PM PDT 24
Finished Mar 21 01:01:44 PM PDT 24
Peak memory 194524 kb
Host smart-51f08671-4fb0-43f4-9b3a-65204006efe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32978126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.32978126
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.3970763899
Short name T695
Test name
Test status
Simulation time 15169483 ps
CPU time 0.66 seconds
Started Mar 21 01:01:31 PM PDT 24
Finished Mar 21 01:01:31 PM PDT 24
Peak memory 194712 kb
Host smart-bc2cb1ff-16b9-4b95-aa13-56c07dbb2282
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970763899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3970763899
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.631512801
Short name T637
Test name
Test status
Simulation time 48040592 ps
CPU time 0.6 seconds
Started Mar 21 01:01:46 PM PDT 24
Finished Mar 21 01:01:46 PM PDT 24
Peak memory 194552 kb
Host smart-8097bef9-da1d-4ccf-b217-c3d21e41e404
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631512801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.631512801
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3198248075
Short name T628
Test name
Test status
Simulation time 11910285 ps
CPU time 0.56 seconds
Started Mar 21 01:01:42 PM PDT 24
Finished Mar 21 01:01:42 PM PDT 24
Peak memory 194492 kb
Host smart-58ca0e12-d095-426a-9dec-35314a301141
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198248075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3198248075
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3569076876
Short name T656
Test name
Test status
Simulation time 165748450 ps
CPU time 0.61 seconds
Started Mar 21 01:01:40 PM PDT 24
Finished Mar 21 01:01:41 PM PDT 24
Peak memory 194720 kb
Host smart-a17e8dc1-600d-4370-9672-22eb649e4cb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569076876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3569076876
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1116985718
Short name T694
Test name
Test status
Simulation time 16756212 ps
CPU time 0.57 seconds
Started Mar 21 01:01:42 PM PDT 24
Finished Mar 21 01:01:43 PM PDT 24
Peak memory 194456 kb
Host smart-52ab9ce6-0352-4a69-9c08-4e6b36d2c3b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116985718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1116985718
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3952382367
Short name T725
Test name
Test status
Simulation time 14678166 ps
CPU time 0.69 seconds
Started Mar 21 01:01:26 PM PDT 24
Finished Mar 21 01:01:27 PM PDT 24
Peak memory 194548 kb
Host smart-446f77bc-b3f0-48dd-9fcb-f9b8a9be9009
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952382367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3952382367
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3198097720
Short name T667
Test name
Test status
Simulation time 22653177 ps
CPU time 0.57 seconds
Started Mar 21 01:01:25 PM PDT 24
Finished Mar 21 01:01:26 PM PDT 24
Peak memory 194484 kb
Host smart-404cb645-e5c4-4422-9465-2cd7045cec29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198097720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3198097720
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2786548440
Short name T718
Test name
Test status
Simulation time 20207816 ps
CPU time 0.61 seconds
Started Mar 21 01:01:43 PM PDT 24
Finished Mar 21 01:01:44 PM PDT 24
Peak memory 194448 kb
Host smart-3e6ef8c1-f3f2-4cba-bdda-113a867ee48b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786548440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2786548440
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2661552505
Short name T605
Test name
Test status
Simulation time 20505925 ps
CPU time 0.59 seconds
Started Mar 21 01:01:19 PM PDT 24
Finished Mar 21 01:01:19 PM PDT 24
Peak memory 194728 kb
Host smart-a7b10e3a-a27c-4aa4-8677-c2fec10edaca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661552505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2661552505
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3861257466
Short name T676
Test name
Test status
Simulation time 96295895 ps
CPU time 1.1 seconds
Started Mar 21 01:01:19 PM PDT 24
Finished Mar 21 01:01:20 PM PDT 24
Peak memory 199820 kb
Host smart-0b32440d-233b-4f2f-bfb2-46661b6701a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861257466 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3861257466
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.374045995
Short name T701
Test name
Test status
Simulation time 108539307 ps
CPU time 0.8 seconds
Started Mar 21 01:01:15 PM PDT 24
Finished Mar 21 01:01:16 PM PDT 24
Peak memory 198720 kb
Host smart-9de501f0-7f73-4e72-8165-d188895ce824
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374045995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.374045995
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.516615643
Short name T638
Test name
Test status
Simulation time 30790154 ps
CPU time 0.6 seconds
Started Mar 21 01:01:22 PM PDT 24
Finished Mar 21 01:01:24 PM PDT 24
Peak memory 194468 kb
Host smart-2765329d-523c-4b34-94ce-2795992eaa0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516615643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.516615643
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.604637366
Short name T673
Test name
Test status
Simulation time 46742354 ps
CPU time 2.16 seconds
Started Mar 21 01:01:20 PM PDT 24
Finished Mar 21 01:01:22 PM PDT 24
Peak memory 199660 kb
Host smart-7fe3b3c5-b290-49c2-9db9-8c97701247e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604637366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_
outstanding.604637366
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2531133737
Short name T613
Test name
Test status
Simulation time 68072397 ps
CPU time 1.7 seconds
Started Mar 21 01:01:23 PM PDT 24
Finished Mar 21 01:01:25 PM PDT 24
Peak memory 199968 kb
Host smart-f9848c3c-d272-4282-9d43-a172d8a5e818
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531133737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.2531133737
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3162300357
Short name T116
Test name
Test status
Simulation time 346153922 ps
CPU time 4.37 seconds
Started Mar 21 01:01:23 PM PDT 24
Finished Mar 21 01:01:27 PM PDT 24
Peak memory 199952 kb
Host smart-a2fd0caa-54e3-4532-81a7-58bd406118df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162300357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3162300357
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3821125571
Short name T669
Test name
Test status
Simulation time 269532331 ps
CPU time 1.83 seconds
Started Mar 21 01:01:16 PM PDT 24
Finished Mar 21 01:01:18 PM PDT 24
Peak memory 200056 kb
Host smart-0eb83b27-9bf4-416f-a58f-8def7c4181eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821125571 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3821125571
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3975649206
Short name T92
Test name
Test status
Simulation time 49375744 ps
CPU time 0.86 seconds
Started Mar 21 01:01:27 PM PDT 24
Finished Mar 21 01:01:28 PM PDT 24
Peak memory 199260 kb
Host smart-ca0e332c-9048-4067-9efb-bacdeeb1c0fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975649206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3975649206
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2648972402
Short name T664
Test name
Test status
Simulation time 15222039 ps
CPU time 0.61 seconds
Started Mar 21 01:01:24 PM PDT 24
Finished Mar 21 01:01:24 PM PDT 24
Peak memory 194568 kb
Host smart-6ab96102-fd11-4cfb-a465-93d4b32c1bbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648972402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2648972402
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.4000249379
Short name T688
Test name
Test status
Simulation time 87048049 ps
CPU time 1.08 seconds
Started Mar 21 01:01:17 PM PDT 24
Finished Mar 21 01:01:18 PM PDT 24
Peak memory 199492 kb
Host smart-9e87fc1e-bb33-4b45-b268-21c973c3c150
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000249379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.4000249379
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1751384098
Short name T711
Test name
Test status
Simulation time 136757528 ps
CPU time 3.9 seconds
Started Mar 21 01:01:13 PM PDT 24
Finished Mar 21 01:01:17 PM PDT 24
Peak memory 200072 kb
Host smart-636dfcbc-630c-4f2a-839b-6918f4483a57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751384098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1751384098
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1340934705
Short name T666
Test name
Test status
Simulation time 341048640 ps
CPU time 2.98 seconds
Started Mar 21 01:01:21 PM PDT 24
Finished Mar 21 01:01:24 PM PDT 24
Peak memory 199952 kb
Host smart-07d14260-1e26-4a0b-a66f-91cb933a2cea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340934705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1340934705
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.707667224
Short name T714
Test name
Test status
Simulation time 45039800791 ps
CPU time 161.59 seconds
Started Mar 21 01:01:21 PM PDT 24
Finished Mar 21 01:04:03 PM PDT 24
Peak memory 216568 kb
Host smart-6fe396eb-b270-4ded-9a5d-7d6ea0264e99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707667224 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.707667224
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3659345699
Short name T86
Test name
Test status
Simulation time 43322131 ps
CPU time 0.94 seconds
Started Mar 21 01:01:14 PM PDT 24
Finished Mar 21 01:01:15 PM PDT 24
Peak memory 199240 kb
Host smart-ddae6635-6f1a-418b-87ec-e6efa7ab9836
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659345699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3659345699
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.3842477272
Short name T632
Test name
Test status
Simulation time 12476775 ps
CPU time 0.6 seconds
Started Mar 21 01:01:19 PM PDT 24
Finished Mar 21 01:01:20 PM PDT 24
Peak memory 194716 kb
Host smart-34a7d02f-6854-496a-be8a-8ff3a2715f54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842477272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3842477272
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3052490031
Short name T625
Test name
Test status
Simulation time 107226744 ps
CPU time 1.17 seconds
Started Mar 21 01:01:18 PM PDT 24
Finished Mar 21 01:01:19 PM PDT 24
Peak memory 198328 kb
Host smart-c7a1c8fb-0601-454a-ba8e-c32416c012ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052490031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3052490031
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.427438738
Short name T702
Test name
Test status
Simulation time 407442746 ps
CPU time 1.97 seconds
Started Mar 21 01:01:12 PM PDT 24
Finished Mar 21 01:01:14 PM PDT 24
Peak memory 199968 kb
Host smart-8bc217a4-8a4c-4f85-b223-e29a04140d92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427438738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.427438738
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3271193592
Short name T117
Test name
Test status
Simulation time 104636806 ps
CPU time 1.84 seconds
Started Mar 21 01:01:22 PM PDT 24
Finished Mar 21 01:01:25 PM PDT 24
Peak memory 199912 kb
Host smart-ad6f07e9-23ab-4587-a9ec-91de46d39453
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271193592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3271193592
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3009419961
Short name T729
Test name
Test status
Simulation time 113394164 ps
CPU time 1.77 seconds
Started Mar 21 01:01:18 PM PDT 24
Finished Mar 21 01:01:20 PM PDT 24
Peak memory 200116 kb
Host smart-fd7711b0-fd0f-4968-8bbc-e01d6680d99e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009419961 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3009419961
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1276641453
Short name T87
Test name
Test status
Simulation time 275676730 ps
CPU time 0.87 seconds
Started Mar 21 01:01:26 PM PDT 24
Finished Mar 21 01:01:27 PM PDT 24
Peak memory 199036 kb
Host smart-96df1c2f-f360-442e-9292-6b8fec35ade8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276641453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1276641453
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.36817341
Short name T619
Test name
Test status
Simulation time 43201993 ps
CPU time 0.55 seconds
Started Mar 21 01:01:18 PM PDT 24
Finished Mar 21 01:01:18 PM PDT 24
Peak memory 194552 kb
Host smart-103edca6-6c18-4a6c-8402-4183adf3c9bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36817341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.36817341
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.522342860
Short name T639
Test name
Test status
Simulation time 92080888 ps
CPU time 1.74 seconds
Started Mar 21 01:01:29 PM PDT 24
Finished Mar 21 01:01:31 PM PDT 24
Peak memory 199604 kb
Host smart-3c61bff5-d1d2-4f84-a670-e2ec69468640
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522342860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_
outstanding.522342860
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2686378680
Short name T668
Test name
Test status
Simulation time 232040789 ps
CPU time 1.53 seconds
Started Mar 21 01:01:14 PM PDT 24
Finished Mar 21 01:01:15 PM PDT 24
Peak memory 199972 kb
Host smart-34e650e2-3d9c-45f3-b316-bd65c49b7ef9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686378680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2686378680
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.4065475846
Short name T111
Test name
Test status
Simulation time 576053795 ps
CPU time 4.09 seconds
Started Mar 21 01:01:16 PM PDT 24
Finished Mar 21 01:01:21 PM PDT 24
Peak memory 199948 kb
Host smart-c0cc9c1d-7d06-4395-b52a-43daf8f91b15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065475846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.4065475846
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1986624214
Short name T602
Test name
Test status
Simulation time 61644480668 ps
CPU time 230.09 seconds
Started Mar 21 01:01:29 PM PDT 24
Finished Mar 21 01:05:19 PM PDT 24
Peak memory 216496 kb
Host smart-f9d446d0-b24b-41b3-b51e-72c2b07968a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986624214 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1986624214
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.716651726
Short name T699
Test name
Test status
Simulation time 12902506 ps
CPU time 0.68 seconds
Started Mar 21 01:01:18 PM PDT 24
Finished Mar 21 01:01:19 PM PDT 24
Peak memory 197576 kb
Host smart-c63cf818-244b-4e10-b05d-8785290d2d3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716651726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.716651726
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1832427791
Short name T663
Test name
Test status
Simulation time 39225607 ps
CPU time 0.59 seconds
Started Mar 21 01:01:12 PM PDT 24
Finished Mar 21 01:01:14 PM PDT 24
Peak memory 194440 kb
Host smart-e7ad84c3-c96e-42f1-ba43-384f50db99bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832427791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1832427791
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1744372590
Short name T640
Test name
Test status
Simulation time 80876614 ps
CPU time 1.1 seconds
Started Mar 21 01:01:17 PM PDT 24
Finished Mar 21 01:01:19 PM PDT 24
Peak memory 199900 kb
Host smart-db7fdc43-3fac-4f55-9224-0588c4b6491d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744372590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.1744372590
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2200242505
Short name T687
Test name
Test status
Simulation time 600633531 ps
CPU time 3.4 seconds
Started Mar 21 01:01:15 PM PDT 24
Finished Mar 21 01:01:19 PM PDT 24
Peak memory 199988 kb
Host smart-7ece8c9b-c299-41fc-ae8a-2f19c1f134c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200242505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2200242505
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.4188687729
Short name T118
Test name
Test status
Simulation time 98786583 ps
CPU time 1.82 seconds
Started Mar 21 01:01:14 PM PDT 24
Finished Mar 21 01:01:16 PM PDT 24
Peak memory 200004 kb
Host smart-72000610-e743-46f3-b306-216ebbe180fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188687729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.4188687729
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3366043
Short name T551
Test name
Test status
Simulation time 14644802 ps
CPU time 0.65 seconds
Started Mar 21 01:03:33 PM PDT 24
Finished Mar 21 01:03:34 PM PDT 24
Peak memory 195812 kb
Host smart-f026435d-a998-4981-858c-d2a23959ee3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3366043
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.5093105
Short name T309
Test name
Test status
Simulation time 4631772020 ps
CPU time 44.45 seconds
Started Mar 21 01:03:34 PM PDT 24
Finished Mar 21 01:04:19 PM PDT 24
Peak memory 221932 kb
Host smart-9ecb55f2-8850-44f9-848b-86e7aba52b2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=5093105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.5093105
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3632375083
Short name T80
Test name
Test status
Simulation time 1896216791 ps
CPU time 38.28 seconds
Started Mar 21 01:03:36 PM PDT 24
Finished Mar 21 01:04:15 PM PDT 24
Peak memory 200412 kb
Host smart-b19f915e-3250-429d-bb05-7b189efd21d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632375083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3632375083
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.757988977
Short name T85
Test name
Test status
Simulation time 1217555497 ps
CPU time 75.6 seconds
Started Mar 21 01:03:35 PM PDT 24
Finished Mar 21 01:04:51 PM PDT 24
Peak memory 200336 kb
Host smart-2a6c5fe7-ee45-4ac2-8967-79d024b02292
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=757988977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.757988977
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2530694258
Short name T265
Test name
Test status
Simulation time 60055578946 ps
CPU time 197.32 seconds
Started Mar 21 01:03:42 PM PDT 24
Finished Mar 21 01:06:59 PM PDT 24
Peak memory 200408 kb
Host smart-5c05546a-3126-4d8b-8cdf-714a11684db9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530694258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2530694258
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1457185222
Short name T153
Test name
Test status
Simulation time 7617417340 ps
CPU time 114.33 seconds
Started Mar 21 01:03:34 PM PDT 24
Finished Mar 21 01:05:29 PM PDT 24
Peak memory 200372 kb
Host smart-26e8dc5d-1ec6-4656-b41d-7bc36736d9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457185222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1457185222
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.2103489098
Short name T188
Test name
Test status
Simulation time 763743479 ps
CPU time 6.17 seconds
Started Mar 21 01:03:42 PM PDT 24
Finished Mar 21 01:03:48 PM PDT 24
Peak memory 200276 kb
Host smart-8e61f596-4758-4036-9e51-81d1c1d4f79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103489098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2103489098
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2941893380
Short name T77
Test name
Test status
Simulation time 42665513918 ps
CPU time 539.19 seconds
Started Mar 21 01:03:41 PM PDT 24
Finished Mar 21 01:12:41 PM PDT 24
Peak memory 208644 kb
Host smart-b0dd61cd-65d5-4bf6-80dc-c595d1c6792c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941893380 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2941893380
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.3713874708
Short name T314
Test name
Test status
Simulation time 60555341 ps
CPU time 1.08 seconds
Started Mar 21 01:03:34 PM PDT 24
Finished Mar 21 01:03:36 PM PDT 24
Peak memory 199184 kb
Host smart-196541dd-70bf-4355-931a-2fc18abc04fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713874708 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.3713874708
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.3565951262
Short name T570
Test name
Test status
Simulation time 15416911289 ps
CPU time 411.38 seconds
Started Mar 21 01:03:33 PM PDT 24
Finished Mar 21 01:10:25 PM PDT 24
Peak memory 200356 kb
Host smart-f4f6cae9-e01b-4cb3-9ac4-65e531b41c86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565951262 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.3565951262
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.2699102892
Short name T148
Test name
Test status
Simulation time 5891787665 ps
CPU time 86.36 seconds
Started Mar 21 01:03:39 PM PDT 24
Finished Mar 21 01:05:06 PM PDT 24
Peak memory 200428 kb
Host smart-4d48014e-1a26-4b0d-b266-d54c555483c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699102892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.2699102892
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3583548341
Short name T154
Test name
Test status
Simulation time 23676153 ps
CPU time 0.59 seconds
Started Mar 21 01:03:34 PM PDT 24
Finished Mar 21 01:03:36 PM PDT 24
Peak memory 194672 kb
Host smart-18771ee8-e1f7-4301-8b63-5dfeaad69ab4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583548341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3583548341
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.2084634306
Short name T560
Test name
Test status
Simulation time 2612310157 ps
CPU time 45.92 seconds
Started Mar 21 01:03:42 PM PDT 24
Finished Mar 21 01:04:28 PM PDT 24
Peak memory 233056 kb
Host smart-5a5d3fc4-20ba-4abe-82dd-0fd65260fd02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2084634306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.2084634306
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.1451883198
Short name T554
Test name
Test status
Simulation time 1596424972 ps
CPU time 25.29 seconds
Started Mar 21 01:03:45 PM PDT 24
Finished Mar 21 01:04:10 PM PDT 24
Peak memory 200432 kb
Host smart-66e70f13-d8cc-4a1b-b6ff-f5a7625f34d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451883198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1451883198
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3079866663
Short name T380
Test name
Test status
Simulation time 3757516271 ps
CPU time 113.12 seconds
Started Mar 21 01:03:32 PM PDT 24
Finished Mar 21 01:05:25 PM PDT 24
Peak memory 200432 kb
Host smart-5e155b2d-ff3c-4f80-806b-d841019824d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3079866663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3079866663
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.1626376838
Short name T444
Test name
Test status
Simulation time 18458998641 ps
CPU time 168.81 seconds
Started Mar 21 01:03:34 PM PDT 24
Finished Mar 21 01:06:23 PM PDT 24
Peak memory 200452 kb
Host smart-6620bdd8-1450-4ac6-be73-cf70c1fbc193
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626376838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1626376838
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.3912597831
Short name T252
Test name
Test status
Simulation time 34142402067 ps
CPU time 71.3 seconds
Started Mar 21 01:03:34 PM PDT 24
Finished Mar 21 01:04:46 PM PDT 24
Peak memory 200312 kb
Host smart-4d1aca40-01c0-4d70-bd04-2a514428fc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912597831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3912597831
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.2141328956
Short name T26
Test name
Test status
Simulation time 120961634 ps
CPU time 0.92 seconds
Started Mar 21 01:03:33 PM PDT 24
Finished Mar 21 01:03:34 PM PDT 24
Peak memory 218704 kb
Host smart-32c1ec7b-780d-4b35-b4ab-03364874bb1e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141328956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2141328956
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.1504632658
Short name T236
Test name
Test status
Simulation time 330755479 ps
CPU time 4.29 seconds
Started Mar 21 01:03:32 PM PDT 24
Finished Mar 21 01:03:36 PM PDT 24
Peak memory 200376 kb
Host smart-7d67629a-50e2-4ee9-a143-3ff645ab0244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504632658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1504632658
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3983189061
Short name T525
Test name
Test status
Simulation time 98721741978 ps
CPU time 891.96 seconds
Started Mar 21 01:03:36 PM PDT 24
Finished Mar 21 01:18:29 PM PDT 24
Peak memory 237260 kb
Host smart-677c260f-544b-48af-8b01-572d0efbb50c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983189061 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3983189061
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.469237057
Short name T2
Test name
Test status
Simulation time 102702939 ps
CPU time 1.02 seconds
Started Mar 21 01:03:34 PM PDT 24
Finished Mar 21 01:03:36 PM PDT 24
Peak memory 199084 kb
Host smart-9f0cd62f-b6c6-4b85-a87b-24947d740850
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469237057 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_hmac_vectors.469237057
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.3139398470
Short name T398
Test name
Test status
Simulation time 204923573489 ps
CPU time 461.05 seconds
Started Mar 21 01:03:42 PM PDT 24
Finished Mar 21 01:11:24 PM PDT 24
Peak memory 200320 kb
Host smart-41a24cdd-4a1b-453c-af68-cd77cda4598d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139398470 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.3139398470
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1898486175
Short name T68
Test name
Test status
Simulation time 23358306234 ps
CPU time 77.55 seconds
Started Mar 21 01:03:34 PM PDT 24
Finished Mar 21 01:04:53 PM PDT 24
Peak memory 200372 kb
Host smart-5e90db67-9950-4df8-b13f-7645e709015f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898486175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1898486175
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.4185812678
Short name T484
Test name
Test status
Simulation time 7728111877 ps
CPU time 20.91 seconds
Started Mar 21 01:03:51 PM PDT 24
Finished Mar 21 01:04:14 PM PDT 24
Peak memory 221964 kb
Host smart-7f4b014b-8743-4fbd-80f7-af0a0d7406ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4185812678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.4185812678
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.1230360138
Short name T421
Test name
Test status
Simulation time 2369912556 ps
CPU time 61.18 seconds
Started Mar 21 01:03:48 PM PDT 24
Finished Mar 21 01:04:50 PM PDT 24
Peak memory 200464 kb
Host smart-6a802f67-3ea7-456d-a1f0-7b940c33a7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230360138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1230360138
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.369336511
Short name T125
Test name
Test status
Simulation time 3587601479 ps
CPU time 50.58 seconds
Started Mar 21 01:03:51 PM PDT 24
Finished Mar 21 01:04:44 PM PDT 24
Peak memory 200404 kb
Host smart-146bfccd-b6b1-4b3b-b230-2220252c73ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=369336511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.369336511
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.2610240553
Short name T438
Test name
Test status
Simulation time 2424529192 ps
CPU time 24.84 seconds
Started Mar 21 01:03:42 PM PDT 24
Finished Mar 21 01:04:08 PM PDT 24
Peak memory 200512 kb
Host smart-6764284c-e6a7-4898-879c-b453f78ed660
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610240553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2610240553
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3122434602
Short name T244
Test name
Test status
Simulation time 8761055375 ps
CPU time 82.62 seconds
Started Mar 21 01:03:46 PM PDT 24
Finished Mar 21 01:05:09 PM PDT 24
Peak memory 200400 kb
Host smart-8ce4778a-2fc8-4060-b42a-dbfc2cd4f199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122434602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3122434602
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.3313711365
Short name T24
Test name
Test status
Simulation time 835499628 ps
CPU time 6.27 seconds
Started Mar 21 01:03:51 PM PDT 24
Finished Mar 21 01:03:59 PM PDT 24
Peak memory 200296 kb
Host smart-d6aa68ca-03e4-4685-8ae7-08cca29c97b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313711365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3313711365
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.732045843
Short name T260
Test name
Test status
Simulation time 87271626184 ps
CPU time 1166.71 seconds
Started Mar 21 01:03:54 PM PDT 24
Finished Mar 21 01:23:21 PM PDT 24
Peak memory 200444 kb
Host smart-80e0a40b-abe6-4474-bb5f-496beef1decc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732045843 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.732045843
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.281695738
Short name T204
Test name
Test status
Simulation time 52021316 ps
CPU time 1 seconds
Started Mar 21 01:03:52 PM PDT 24
Finished Mar 21 01:03:54 PM PDT 24
Peak memory 199744 kb
Host smart-8e90a601-be0d-4fa2-9375-caf9586b292f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281695738 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.hmac_test_hmac_vectors.281695738
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.3018581146
Short name T396
Test name
Test status
Simulation time 117809389996 ps
CPU time 537.59 seconds
Started Mar 21 01:03:54 PM PDT 24
Finished Mar 21 01:12:52 PM PDT 24
Peak memory 200392 kb
Host smart-c9cfde2a-970f-4cb4-aebb-49b6b1256ad5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018581146 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.3018581146
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.247072427
Short name T445
Test name
Test status
Simulation time 2429276067 ps
CPU time 35.22 seconds
Started Mar 21 01:03:53 PM PDT 24
Finished Mar 21 01:04:28 PM PDT 24
Peak memory 200388 kb
Host smart-f2a811f5-cb5d-4edb-9952-51da7acc7744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247072427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.247072427
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/102.hmac_stress_all_with_rand_reset.2037527122
Short name T63
Test name
Test status
Simulation time 101257485173 ps
CPU time 1784.27 seconds
Started Mar 21 01:05:16 PM PDT 24
Finished Mar 21 01:35:00 PM PDT 24
Peak memory 243380 kb
Host smart-31dde623-64da-4b52-b759-b27700b9a963
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2037527122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.hmac_stress_all_with_rand_reset.2037527122
Directory /workspace/102.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3366784281
Short name T539
Test name
Test status
Simulation time 21613162 ps
CPU time 0.58 seconds
Started Mar 21 01:03:51 PM PDT 24
Finished Mar 21 01:03:53 PM PDT 24
Peak memory 195960 kb
Host smart-301a0df1-4905-42e1-93ed-2264c78f52fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366784281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3366784281
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.769460653
Short name T184
Test name
Test status
Simulation time 1274622685 ps
CPU time 47.6 seconds
Started Mar 21 01:03:43 PM PDT 24
Finished Mar 21 01:04:30 PM PDT 24
Peak memory 232988 kb
Host smart-8b82a008-c356-4e9d-a72b-6309200bb8d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=769460653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.769460653
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.1993180738
Short name T248
Test name
Test status
Simulation time 860020310 ps
CPU time 44.1 seconds
Started Mar 21 01:03:54 PM PDT 24
Finished Mar 21 01:04:39 PM PDT 24
Peak memory 200340 kb
Host smart-3a9cce63-9419-4a5e-8d09-a449413d014d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993180738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1993180738
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1037850614
Short name T134
Test name
Test status
Simulation time 734880785 ps
CPU time 39.03 seconds
Started Mar 21 01:03:55 PM PDT 24
Finished Mar 21 01:04:35 PM PDT 24
Peak memory 200428 kb
Host smart-d8389971-8895-4a83-8b01-84806e85b511
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1037850614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1037850614
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1915543916
Short name T472
Test name
Test status
Simulation time 16719025156 ps
CPU time 159.5 seconds
Started Mar 21 01:03:51 PM PDT 24
Finished Mar 21 01:06:32 PM PDT 24
Peak memory 200484 kb
Host smart-f30ac4b6-ebac-4ec7-9682-d04aef754ed0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915543916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1915543916
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1098608335
Short name T478
Test name
Test status
Simulation time 794203063 ps
CPU time 42.97 seconds
Started Mar 21 01:03:57 PM PDT 24
Finished Mar 21 01:04:41 PM PDT 24
Peak memory 200292 kb
Host smart-a66afa77-28e0-4434-8451-91e47d83857d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098608335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1098608335
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1270455140
Short name T130
Test name
Test status
Simulation time 1561951942 ps
CPU time 5.88 seconds
Started Mar 21 01:03:55 PM PDT 24
Finished Mar 21 01:04:01 PM PDT 24
Peak memory 200376 kb
Host smart-c5e3ac64-dfb6-462d-ba67-15058c80520f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270455140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1270455140
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.1049364068
Short name T263
Test name
Test status
Simulation time 46671693627 ps
CPU time 941.92 seconds
Started Mar 21 01:03:56 PM PDT 24
Finished Mar 21 01:19:38 PM PDT 24
Peak memory 213984 kb
Host smart-3f8afbc2-f913-4d5d-9841-b28402f02d4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049364068 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1049364068
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.3803819894
Short name T287
Test name
Test status
Simulation time 214682516 ps
CPU time 1.33 seconds
Started Mar 21 01:04:01 PM PDT 24
Finished Mar 21 01:04:02 PM PDT 24
Peak memory 199984 kb
Host smart-c4efc4ab-5963-43a9-8b6c-fcfaf3724c45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803819894 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.3803819894
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.3286470248
Short name T471
Test name
Test status
Simulation time 111126834993 ps
CPU time 498.13 seconds
Started Mar 21 01:03:48 PM PDT 24
Finished Mar 21 01:12:08 PM PDT 24
Peak memory 200448 kb
Host smart-6270c5bb-0d4a-41e2-b67c-87b84d68633d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286470248 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.3286470248
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.1807661779
Short name T268
Test name
Test status
Simulation time 9252355536 ps
CPU time 41.39 seconds
Started Mar 21 01:03:55 PM PDT 24
Finished Mar 21 01:04:37 PM PDT 24
Peak memory 200404 kb
Host smart-932cf031-5584-410f-a28f-3aa492d3acf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807661779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1807661779
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1082627209
Short name T221
Test name
Test status
Simulation time 48286421 ps
CPU time 0.58 seconds
Started Mar 21 01:03:50 PM PDT 24
Finished Mar 21 01:03:53 PM PDT 24
Peak memory 195964 kb
Host smart-e4d98d8f-7e84-4387-8d46-8ceb7170a68b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082627209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1082627209
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1099651984
Short name T557
Test name
Test status
Simulation time 826688577 ps
CPU time 14.43 seconds
Started Mar 21 01:03:52 PM PDT 24
Finished Mar 21 01:04:07 PM PDT 24
Peak memory 208524 kb
Host smart-07518a2f-7ae5-49a3-a6e9-0e24ca85c549
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1099651984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1099651984
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2958819089
Short name T201
Test name
Test status
Simulation time 4938334491 ps
CPU time 46.61 seconds
Started Mar 21 01:03:54 PM PDT 24
Finished Mar 21 01:04:41 PM PDT 24
Peak memory 200460 kb
Host smart-0fb6621a-8118-45eb-b174-3b2e0384318f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958819089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2958819089
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.685321084
Short name T532
Test name
Test status
Simulation time 666710660 ps
CPU time 9.65 seconds
Started Mar 21 01:03:47 PM PDT 24
Finished Mar 21 01:03:58 PM PDT 24
Peak memory 200404 kb
Host smart-1510a62b-4e09-4d6e-862b-2d0051b3f874
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=685321084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.685321084
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2984571899
Short name T179
Test name
Test status
Simulation time 4959023250 ps
CPU time 67.86 seconds
Started Mar 21 01:03:44 PM PDT 24
Finished Mar 21 01:04:52 PM PDT 24
Peak memory 200536 kb
Host smart-ed497f40-2a40-4e1b-b325-309f0f1f6349
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984571899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2984571899
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3989032590
Short name T190
Test name
Test status
Simulation time 2840543041 ps
CPU time 77.88 seconds
Started Mar 21 01:03:51 PM PDT 24
Finished Mar 21 01:05:11 PM PDT 24
Peak memory 200416 kb
Host smart-feb5264d-4a5c-430a-9ea6-a7ceb12f0a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989032590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3989032590
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3937295988
Short name T70
Test name
Test status
Simulation time 600734915 ps
CPU time 3.47 seconds
Started Mar 21 01:03:51 PM PDT 24
Finished Mar 21 01:03:56 PM PDT 24
Peak memory 200340 kb
Host smart-0e9ef893-1762-4949-a098-f7ce651d8fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937295988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3937295988
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1469904080
Short name T483
Test name
Test status
Simulation time 1123850845 ps
CPU time 53.33 seconds
Started Mar 21 01:03:50 PM PDT 24
Finished Mar 21 01:04:46 PM PDT 24
Peak memory 200464 kb
Host smart-2fcef114-8bab-4526-8d2e-a3b2c11ebabf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469904080 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1469904080
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.1694094646
Short name T565
Test name
Test status
Simulation time 58964087 ps
CPU time 1.21 seconds
Started Mar 21 01:03:48 PM PDT 24
Finished Mar 21 01:03:51 PM PDT 24
Peak memory 200332 kb
Host smart-e2f597db-3f78-4279-b5d3-6c0d5c03f4fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694094646 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.1694094646
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.574477088
Short name T341
Test name
Test status
Simulation time 27053177093 ps
CPU time 499.48 seconds
Started Mar 21 01:03:50 PM PDT 24
Finished Mar 21 01:12:12 PM PDT 24
Peak memory 200428 kb
Host smart-a97d9866-dfae-460b-a804-78991ce57718
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574477088 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.574477088
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.69994225
Short name T446
Test name
Test status
Simulation time 2647480188 ps
CPU time 20.04 seconds
Started Mar 21 01:03:48 PM PDT 24
Finished Mar 21 01:04:10 PM PDT 24
Peak memory 200348 kb
Host smart-54225b7c-4b4f-4c1d-9b32-0200bded4a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69994225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.69994225
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2615451677
Short name T568
Test name
Test status
Simulation time 16675709 ps
CPU time 0.6 seconds
Started Mar 21 01:04:01 PM PDT 24
Finished Mar 21 01:04:08 PM PDT 24
Peak memory 195880 kb
Host smart-f7ffc946-7173-4099-bcc0-9b754e0a400a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615451677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2615451677
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3729642417
Short name T573
Test name
Test status
Simulation time 10386386495 ps
CPU time 52.41 seconds
Started Mar 21 01:03:51 PM PDT 24
Finished Mar 21 01:04:45 PM PDT 24
Peak memory 208688 kb
Host smart-1826021b-2326-491e-8a2b-4365f2a7855d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3729642417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3729642417
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1941451056
Short name T197
Test name
Test status
Simulation time 1827858590 ps
CPU time 14 seconds
Started Mar 21 01:03:50 PM PDT 24
Finished Mar 21 01:04:07 PM PDT 24
Peak memory 200304 kb
Host smart-3f630507-c950-4e56-89bb-8bfb8c257abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941451056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1941451056
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2957028013
Short name T448
Test name
Test status
Simulation time 1820363420 ps
CPU time 14.44 seconds
Started Mar 21 01:03:49 PM PDT 24
Finished Mar 21 01:04:04 PM PDT 24
Peak memory 200368 kb
Host smart-562a37ed-4f68-4399-9a8f-4a3ee8602cbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2957028013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2957028013
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.3433777901
Short name T546
Test name
Test status
Simulation time 21152149108 ps
CPU time 67.58 seconds
Started Mar 21 01:04:00 PM PDT 24
Finished Mar 21 01:05:07 PM PDT 24
Peak memory 200432 kb
Host smart-394420d8-72b5-447a-ac51-4d970dd7e025
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433777901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3433777901
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1301962311
Short name T552
Test name
Test status
Simulation time 1280370222 ps
CPU time 73.36 seconds
Started Mar 21 01:03:57 PM PDT 24
Finished Mar 21 01:05:11 PM PDT 24
Peak memory 200316 kb
Host smart-3707ad2f-03c0-496e-a03c-afa7bd90613c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301962311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1301962311
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2811569158
Short name T537
Test name
Test status
Simulation time 206910031 ps
CPU time 6.54 seconds
Started Mar 21 01:03:51 PM PDT 24
Finished Mar 21 01:03:59 PM PDT 24
Peak memory 200296 kb
Host smart-4729e608-3320-4232-b03a-4b1c59c1a8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811569158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2811569158
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.3968183186
Short name T215
Test name
Test status
Simulation time 9982191447 ps
CPU time 567.12 seconds
Started Mar 21 01:03:53 PM PDT 24
Finished Mar 21 01:13:20 PM PDT 24
Peak memory 200488 kb
Host smart-16ff433a-76db-4835-8e04-460d1247205d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968183186 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3968183186
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.3994761730
Short name T312
Test name
Test status
Simulation time 48803254 ps
CPU time 1.08 seconds
Started Mar 21 01:04:01 PM PDT 24
Finished Mar 21 01:04:02 PM PDT 24
Peak memory 198636 kb
Host smart-56f09605-fe42-4000-a04f-8a969b71d364
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994761730 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.3994761730
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.4202071560
Short name T520
Test name
Test status
Simulation time 7819015826 ps
CPU time 459.57 seconds
Started Mar 21 01:03:47 PM PDT 24
Finished Mar 21 01:11:27 PM PDT 24
Peak memory 200360 kb
Host smart-ec021c06-a910-41c2-88b5-628c56bcfab1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202071560 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.4202071560
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.656909796
Short name T198
Test name
Test status
Simulation time 3708521763 ps
CPU time 40.75 seconds
Started Mar 21 01:03:53 PM PDT 24
Finished Mar 21 01:04:34 PM PDT 24
Peak memory 200504 kb
Host smart-d1ab111d-432b-427a-9ed0-67269a616c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656909796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.656909796
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/132.hmac_stress_all_with_rand_reset.4245342623
Short name T64
Test name
Test status
Simulation time 54889550025 ps
CPU time 709.63 seconds
Started Mar 21 01:05:16 PM PDT 24
Finished Mar 21 01:17:06 PM PDT 24
Peak memory 241496 kb
Host smart-3e3885a6-e2cd-41f3-b408-51ed1662136a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4245342623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.hmac_stress_all_with_rand_reset.4245342623
Directory /workspace/132.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/136.hmac_stress_all_with_rand_reset.4171558033
Short name T13
Test name
Test status
Simulation time 59379496538 ps
CPU time 828.34 seconds
Started Mar 21 01:05:15 PM PDT 24
Finished Mar 21 01:19:03 PM PDT 24
Peak memory 216872 kb
Host smart-e542b5ac-989f-42b6-901c-164322004f96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4171558033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.hmac_stress_all_with_rand_reset.4171558033
Directory /workspace/136.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1475476789
Short name T523
Test name
Test status
Simulation time 12352086 ps
CPU time 0.57 seconds
Started Mar 21 01:03:54 PM PDT 24
Finished Mar 21 01:03:55 PM PDT 24
Peak memory 194808 kb
Host smart-ea447041-5718-419f-ab71-cc14339c4775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475476789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1475476789
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.743092203
Short name T367
Test name
Test status
Simulation time 943935248 ps
CPU time 35.77 seconds
Started Mar 21 01:03:55 PM PDT 24
Finished Mar 21 01:04:31 PM PDT 24
Peak memory 225576 kb
Host smart-37dce4bf-d3ff-40fc-a3f3-9ac1ae0abda6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=743092203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.743092203
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2650763505
Short name T186
Test name
Test status
Simulation time 1087413794 ps
CPU time 4.3 seconds
Started Mar 21 01:03:54 PM PDT 24
Finished Mar 21 01:03:58 PM PDT 24
Peak memory 200312 kb
Host smart-5d63c29f-d513-4c67-856e-bce23783a7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650763505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2650763505
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.2281600826
Short name T412
Test name
Test status
Simulation time 22825165548 ps
CPU time 90.58 seconds
Started Mar 21 01:03:59 PM PDT 24
Finished Mar 21 01:05:35 PM PDT 24
Peak memory 200432 kb
Host smart-5ccaf695-40b6-4625-83fd-5c293c89925b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2281600826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2281600826
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.1265916087
Short name T206
Test name
Test status
Simulation time 28482301069 ps
CPU time 103.91 seconds
Started Mar 21 01:03:51 PM PDT 24
Finished Mar 21 01:05:37 PM PDT 24
Peak memory 200572 kb
Host smart-2edf04b3-96c6-49aa-8667-4c5796eb812e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265916087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1265916087
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.901909368
Short name T261
Test name
Test status
Simulation time 427020997 ps
CPU time 5.86 seconds
Started Mar 21 01:03:59 PM PDT 24
Finished Mar 21 01:04:05 PM PDT 24
Peak memory 200368 kb
Host smart-e56bfd6a-65e4-4efc-85fe-adf7b9175ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901909368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.901909368
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3798502651
Short name T512
Test name
Test status
Simulation time 319771791 ps
CPU time 1.62 seconds
Started Mar 21 01:04:00 PM PDT 24
Finished Mar 21 01:04:02 PM PDT 24
Peak memory 200344 kb
Host smart-bca55456-e372-432d-8bd2-bf9040674ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798502651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3798502651
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all_with_rand_reset.4134531967
Short name T9
Test name
Test status
Simulation time 26406268806 ps
CPU time 1242.16 seconds
Started Mar 21 01:03:55 PM PDT 24
Finished Mar 21 01:24:37 PM PDT 24
Peak memory 216936 kb
Host smart-25886acd-e492-46b4-8221-e43bab9c6726
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4134531967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all_with_rand_reset.4134531967
Directory /workspace/14.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.2165665801
Short name T326
Test name
Test status
Simulation time 92312887 ps
CPU time 1.07 seconds
Started Mar 21 01:03:57 PM PDT 24
Finished Mar 21 01:03:59 PM PDT 24
Peak memory 199200 kb
Host smart-b179122b-1bec-44d2-9a56-455b952d30a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165665801 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.2165665801
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.3716139896
Short name T403
Test name
Test status
Simulation time 138550924889 ps
CPU time 523.94 seconds
Started Mar 21 01:03:57 PM PDT 24
Finished Mar 21 01:12:42 PM PDT 24
Peak memory 200344 kb
Host smart-ab99d9c6-c296-446c-9151-f73cd8f81ee9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716139896 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.3716139896
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3643664434
Short name T238
Test name
Test status
Simulation time 3992043205 ps
CPU time 49.21 seconds
Started Mar 21 01:03:54 PM PDT 24
Finished Mar 21 01:04:43 PM PDT 24
Peak memory 200400 kb
Host smart-4d03466d-2710-4f86-b0ce-785e02b657fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643664434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3643664434
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.726584814
Short name T413
Test name
Test status
Simulation time 14173985 ps
CPU time 0.6 seconds
Started Mar 21 01:03:57 PM PDT 24
Finished Mar 21 01:03:59 PM PDT 24
Peak memory 195788 kb
Host smart-e88b54e2-38f4-488a-9ef5-4bda4ee0272a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726584814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.726584814
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.2696014437
Short name T571
Test name
Test status
Simulation time 1313203104 ps
CPU time 40.34 seconds
Started Mar 21 01:03:59 PM PDT 24
Finished Mar 21 01:04:40 PM PDT 24
Peak memory 210496 kb
Host smart-811254ec-0418-4167-8db0-cd03c3e0691f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2696014437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2696014437
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2496366726
Short name T579
Test name
Test status
Simulation time 1911997055 ps
CPU time 26.62 seconds
Started Mar 21 01:04:10 PM PDT 24
Finished Mar 21 01:04:37 PM PDT 24
Peak memory 200344 kb
Host smart-bda0f166-8291-4d60-8fc3-a132f5fcd969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496366726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2496366726
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1720637002
Short name T212
Test name
Test status
Simulation time 3637570823 ps
CPU time 62.98 seconds
Started Mar 21 01:03:51 PM PDT 24
Finished Mar 21 01:04:56 PM PDT 24
Peak memory 200420 kb
Host smart-8e829e8c-8ee1-4118-bf60-814a30652414
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1720637002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1720637002
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2470647832
Short name T338
Test name
Test status
Simulation time 5647375688 ps
CPU time 156.59 seconds
Started Mar 21 01:03:53 PM PDT 24
Finished Mar 21 01:06:30 PM PDT 24
Peak memory 200444 kb
Host smart-c2b9ab23-5674-4cca-ade5-65377a03b765
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470647832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2470647832
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2612023607
Short name T429
Test name
Test status
Simulation time 8138612526 ps
CPU time 63.76 seconds
Started Mar 21 01:03:59 PM PDT 24
Finished Mar 21 01:05:03 PM PDT 24
Peak memory 200400 kb
Host smart-23050bf2-b6da-458f-8626-0ca25b548423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612023607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2612023607
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2287689189
Short name T78
Test name
Test status
Simulation time 358004776 ps
CPU time 6.42 seconds
Started Mar 21 01:03:54 PM PDT 24
Finished Mar 21 01:04:00 PM PDT 24
Peak memory 200452 kb
Host smart-e1d0034e-01c7-442a-b6a4-0e6ea26a4e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287689189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2287689189
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.2500559858
Short name T33
Test name
Test status
Simulation time 82603269071 ps
CPU time 1160.69 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:23:19 PM PDT 24
Peak memory 200508 kb
Host smart-7264e280-c8eb-4034-a519-e0f9fda77c2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500559858 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2500559858
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.3758713679
Short name T559
Test name
Test status
Simulation time 51592033 ps
CPU time 0.99 seconds
Started Mar 21 01:04:01 PM PDT 24
Finished Mar 21 01:04:02 PM PDT 24
Peak memory 199508 kb
Host smart-3a669813-870b-4299-8d78-af9b13a5c150
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758713679 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.3758713679
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.3667434309
Short name T321
Test name
Test status
Simulation time 7934029231 ps
CPU time 448.72 seconds
Started Mar 21 01:03:56 PM PDT 24
Finished Mar 21 01:11:25 PM PDT 24
Peak memory 200420 kb
Host smart-a9e7522d-0486-4457-be76-8f42a06e419a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667434309 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.3667434309
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3811067682
Short name T440
Test name
Test status
Simulation time 1773378621 ps
CPU time 40.13 seconds
Started Mar 21 01:03:54 PM PDT 24
Finished Mar 21 01:04:34 PM PDT 24
Peak memory 200340 kb
Host smart-57831e79-24b1-478a-957b-ab3d5d92af35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811067682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3811067682
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/152.hmac_stress_all_with_rand_reset.3076190735
Short name T5
Test name
Test status
Simulation time 26002466370 ps
CPU time 1179.41 seconds
Started Mar 21 01:05:24 PM PDT 24
Finished Mar 21 01:25:03 PM PDT 24
Peak memory 247576 kb
Host smart-82bd8f9f-6c26-4a94-be7d-531747e49d8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3076190735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.hmac_stress_all_with_rand_reset.3076190735
Directory /workspace/152.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3545832985
Short name T165
Test name
Test status
Simulation time 14508635 ps
CPU time 0.58 seconds
Started Mar 21 01:03:57 PM PDT 24
Finished Mar 21 01:03:58 PM PDT 24
Peak memory 195836 kb
Host smart-d45b53ef-7f0a-4fc1-94bc-13fd24f5cc65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545832985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3545832985
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1290563512
Short name T219
Test name
Test status
Simulation time 1827189831 ps
CPU time 34.58 seconds
Started Mar 21 01:04:00 PM PDT 24
Finished Mar 21 01:04:35 PM PDT 24
Peak memory 200348 kb
Host smart-64273001-5781-4b99-8050-d77aa3ae1c4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1290563512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1290563512
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1429540880
Short name T174
Test name
Test status
Simulation time 7366191032 ps
CPU time 26.27 seconds
Started Mar 21 01:03:50 PM PDT 24
Finished Mar 21 01:04:19 PM PDT 24
Peak memory 200472 kb
Host smart-3e3002e3-b3ff-4c21-86e0-ca23d9301fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429540880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1429540880
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.4233365236
Short name T467
Test name
Test status
Simulation time 4653711259 ps
CPU time 145.18 seconds
Started Mar 21 01:03:57 PM PDT 24
Finished Mar 21 01:06:23 PM PDT 24
Peak memory 200396 kb
Host smart-475faae6-740f-474c-ae81-ad0620b27a82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4233365236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.4233365236
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.1174186494
Short name T22
Test name
Test status
Simulation time 57819546963 ps
CPU time 175.6 seconds
Started Mar 21 01:03:43 PM PDT 24
Finished Mar 21 01:06:39 PM PDT 24
Peak memory 200536 kb
Host smart-b787c24f-fe12-44b9-a213-deb4ba77b17e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174186494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1174186494
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.287258199
Short name T132
Test name
Test status
Simulation time 21314936235 ps
CPU time 102.29 seconds
Started Mar 21 01:04:00 PM PDT 24
Finished Mar 21 01:05:43 PM PDT 24
Peak memory 200436 kb
Host smart-9a40700c-c520-4a05-ac1a-2d74ed980ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287258199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.287258199
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.161126500
Short name T377
Test name
Test status
Simulation time 1388050073 ps
CPU time 6.32 seconds
Started Mar 21 01:04:00 PM PDT 24
Finished Mar 21 01:04:07 PM PDT 24
Peak memory 200488 kb
Host smart-47f3c66b-008b-4bf2-9aeb-61dd7f9137a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161126500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.161126500
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.2363034035
Short name T335
Test name
Test status
Simulation time 78586760360 ps
CPU time 1010.32 seconds
Started Mar 21 01:03:57 PM PDT 24
Finished Mar 21 01:20:48 PM PDT 24
Peak memory 241428 kb
Host smart-3a8fd797-7d9e-4c0b-8f87-6d53133d354b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363034035 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2363034035
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.2855929614
Short name T40
Test name
Test status
Simulation time 205244040 ps
CPU time 1.19 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:04:00 PM PDT 24
Peak memory 200356 kb
Host smart-a8c66cd2-7304-4a8e-83f1-0ee779e10c23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855929614 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.2855929614
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.3295249364
Short name T171
Test name
Test status
Simulation time 301396232283 ps
CPU time 501.1 seconds
Started Mar 21 01:03:51 PM PDT 24
Finished Mar 21 01:12:14 PM PDT 24
Peak memory 200368 kb
Host smart-e6500898-bbc3-4c82-affc-5e634c9cd22f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295249364 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.3295249364
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.974879794
Short name T441
Test name
Test status
Simulation time 2044021129 ps
CPU time 47.81 seconds
Started Mar 21 01:03:44 PM PDT 24
Finished Mar 21 01:04:32 PM PDT 24
Peak memory 200480 kb
Host smart-17a97598-c651-40ae-8f06-92e3f3d25666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974879794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.974879794
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1747736783
Short name T513
Test name
Test status
Simulation time 14279827 ps
CPU time 0.58 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:03:59 PM PDT 24
Peak memory 195800 kb
Host smart-7a9924d6-b6e1-4bcc-a232-9c1efa33179d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747736783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1747736783
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.241741529
Short name T292
Test name
Test status
Simulation time 1421703336 ps
CPU time 52.13 seconds
Started Mar 21 01:03:48 PM PDT 24
Finished Mar 21 01:04:41 PM PDT 24
Peak memory 209516 kb
Host smart-a053f4bf-bf79-48ce-a690-3b36e54f3ce3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=241741529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.241741529
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3137047428
Short name T517
Test name
Test status
Simulation time 978684402 ps
CPU time 3.99 seconds
Started Mar 21 01:03:57 PM PDT 24
Finished Mar 21 01:04:02 PM PDT 24
Peak memory 200328 kb
Host smart-66fc1323-24cf-4df5-9f28-fe830300a83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137047428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3137047428
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.1523382250
Short name T504
Test name
Test status
Simulation time 5842305108 ps
CPU time 37.97 seconds
Started Mar 21 01:03:59 PM PDT 24
Finished Mar 21 01:04:37 PM PDT 24
Peak memory 200404 kb
Host smart-0207a72c-e26e-4f00-8599-20e8adab7484
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1523382250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1523382250
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1239130905
Short name T122
Test name
Test status
Simulation time 3444476515 ps
CPU time 59.45 seconds
Started Mar 21 01:03:49 PM PDT 24
Finished Mar 21 01:04:50 PM PDT 24
Peak memory 200412 kb
Host smart-ca822200-f263-4ca0-a280-2b100f9c7372
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239130905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1239130905
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.4122610524
Short name T407
Test name
Test status
Simulation time 3962523017 ps
CPU time 82.14 seconds
Started Mar 21 01:03:50 PM PDT 24
Finished Mar 21 01:05:15 PM PDT 24
Peak memory 200536 kb
Host smart-03f834a0-f09d-4101-a730-9e3942e8a0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122610524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.4122610524
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3123872240
Short name T495
Test name
Test status
Simulation time 215823176 ps
CPU time 3.51 seconds
Started Mar 21 01:04:00 PM PDT 24
Finished Mar 21 01:04:04 PM PDT 24
Peak memory 200336 kb
Host smart-f968a617-4d54-47d7-bfa0-6948dc988186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123872240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3123872240
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.70002882
Short name T103
Test name
Test status
Simulation time 5712398916 ps
CPU time 48.09 seconds
Started Mar 21 01:03:57 PM PDT 24
Finished Mar 21 01:04:46 PM PDT 24
Peak memory 200492 kb
Host smart-fbfe0d24-7493-427d-b96f-7c148f601d14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70002882 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.70002882
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.3046999082
Short name T332
Test name
Test status
Simulation time 195421113 ps
CPU time 0.96 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:04:01 PM PDT 24
Peak memory 198784 kb
Host smart-d737298d-aa07-4f7b-8574-9208158a8ae5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046999082 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.3046999082
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.2928787323
Short name T482
Test name
Test status
Simulation time 36675938459 ps
CPU time 519.74 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:12:38 PM PDT 24
Peak memory 200412 kb
Host smart-07ca3f80-24c6-4c32-91d2-2a2f4a709214
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928787323 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.2928787323
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3373723728
Short name T256
Test name
Test status
Simulation time 7652738335 ps
CPU time 26.7 seconds
Started Mar 21 01:04:16 PM PDT 24
Finished Mar 21 01:04:47 PM PDT 24
Peak memory 200520 kb
Host smart-43aaad64-165d-4b10-b798-69fb3bb9c1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373723728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3373723728
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/172.hmac_stress_all_with_rand_reset.1111803923
Short name T580
Test name
Test status
Simulation time 75104457195 ps
CPU time 1187.95 seconds
Started Mar 21 01:05:22 PM PDT 24
Finished Mar 21 01:25:10 PM PDT 24
Peak memory 249620 kb
Host smart-f64b78ec-7c00-4f4b-b7cd-7b0905069708
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1111803923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.hmac_stress_all_with_rand_reset.1111803923
Directory /workspace/172.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2414660499
Short name T449
Test name
Test status
Simulation time 13737103 ps
CPU time 0.61 seconds
Started Mar 21 01:03:51 PM PDT 24
Finished Mar 21 01:03:53 PM PDT 24
Peak memory 195448 kb
Host smart-ea81cd07-660a-499d-8576-c1a4768e0d7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414660499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2414660499
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1371846236
Short name T395
Test name
Test status
Simulation time 4867267927 ps
CPU time 44.76 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:04:43 PM PDT 24
Peak memory 227332 kb
Host smart-8610acf7-240f-439d-afc7-86ac8d290cc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1371846236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1371846236
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1739372394
Short name T425
Test name
Test status
Simulation time 2758748580 ps
CPU time 7.94 seconds
Started Mar 21 01:03:55 PM PDT 24
Finished Mar 21 01:04:04 PM PDT 24
Peak memory 200456 kb
Host smart-6b769e09-3bfe-4625-bc30-6f12a9b48ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739372394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1739372394
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1961781927
Short name T543
Test name
Test status
Simulation time 1831651064 ps
CPU time 24.13 seconds
Started Mar 21 01:04:00 PM PDT 24
Finished Mar 21 01:04:24 PM PDT 24
Peak memory 200440 kb
Host smart-258d6d95-60d6-4724-8668-636a6776983d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1961781927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1961781927
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.1162062967
Short name T158
Test name
Test status
Simulation time 13574190103 ps
CPU time 55.54 seconds
Started Mar 21 01:03:56 PM PDT 24
Finished Mar 21 01:04:52 PM PDT 24
Peak memory 200408 kb
Host smart-6673ee73-8aa8-4782-a09d-3313158bd8a4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162062967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1162062967
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.2790995131
Short name T381
Test name
Test status
Simulation time 3692051920 ps
CPU time 107.87 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:05:51 PM PDT 24
Peak memory 200408 kb
Host smart-d04a212a-6211-43f1-a7ea-4ff6b434efca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790995131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2790995131
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2538357626
Short name T555
Test name
Test status
Simulation time 98650624 ps
CPU time 3.14 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:04:11 PM PDT 24
Peak memory 200432 kb
Host smart-1ea3d594-39e4-4d4a-8a3e-b120c9d261c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538357626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2538357626
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3217589176
Short name T507
Test name
Test status
Simulation time 4126166205 ps
CPU time 74.29 seconds
Started Mar 21 01:03:59 PM PDT 24
Finished Mar 21 01:05:13 PM PDT 24
Peak memory 212680 kb
Host smart-d5172b6a-7acf-4c65-be16-6be06032b51d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217589176 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3217589176
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.3707838707
Short name T317
Test name
Test status
Simulation time 55451814 ps
CPU time 1.09 seconds
Started Mar 21 01:04:13 PM PDT 24
Finished Mar 21 01:04:15 PM PDT 24
Peak memory 199568 kb
Host smart-9821963b-7607-4224-a886-265cccc58810
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707838707 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.3707838707
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.2797996993
Short name T592
Test name
Test status
Simulation time 8593260292 ps
CPU time 485.73 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:12:09 PM PDT 24
Peak memory 200352 kb
Host smart-f6f368ae-c54c-4fc5-b518-c9a69b7a2b81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797996993 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.2797996993
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.17521865
Short name T390
Test name
Test status
Simulation time 59882391 ps
CPU time 0.72 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:03:59 PM PDT 24
Peak memory 197292 kb
Host smart-0a030c1e-533b-406f-bcd7-32eaf99f3bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17521865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.17521865
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2326536407
Short name T536
Test name
Test status
Simulation time 21764808 ps
CPU time 0.55 seconds
Started Mar 21 01:03:57 PM PDT 24
Finished Mar 21 01:03:59 PM PDT 24
Peak memory 195844 kb
Host smart-9df1144e-d580-4174-ab49-92219fc439d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326536407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2326536407
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.1198229227
Short name T516
Test name
Test status
Simulation time 13685443732 ps
CPU time 36.54 seconds
Started Mar 21 01:03:57 PM PDT 24
Finished Mar 21 01:04:35 PM PDT 24
Peak memory 226092 kb
Host smart-5ce3683a-797a-4efa-a44c-7c621b5fe729
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1198229227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.1198229227
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2556642065
Short name T583
Test name
Test status
Simulation time 2928448422 ps
CPU time 34.78 seconds
Started Mar 21 01:03:50 PM PDT 24
Finished Mar 21 01:04:27 PM PDT 24
Peak memory 200416 kb
Host smart-1d8f3afd-8361-4754-bf9a-0ddca996751d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556642065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2556642065
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1396748468
Short name T223
Test name
Test status
Simulation time 260653455 ps
CPU time 15.69 seconds
Started Mar 21 01:03:57 PM PDT 24
Finished Mar 21 01:04:14 PM PDT 24
Peak memory 199944 kb
Host smart-9823bfce-fe8f-48e0-ab37-bfbcc4a43f06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1396748468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1396748468
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2747436612
Short name T20
Test name
Test status
Simulation time 42338353920 ps
CPU time 87.58 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:05:26 PM PDT 24
Peak memory 200404 kb
Host smart-2b8db5b7-d0e0-4ddf-8d8b-a77dbb514ad4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747436612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2747436612
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.789493709
Short name T556
Test name
Test status
Simulation time 12704259015 ps
CPU time 70.87 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:05:10 PM PDT 24
Peak memory 200448 kb
Host smart-ca37cefc-92cc-4e8b-a851-57ba93125dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789493709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.789493709
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.530740070
Short name T205
Test name
Test status
Simulation time 305680542 ps
CPU time 6.09 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:04:04 PM PDT 24
Peak memory 200404 kb
Host smart-ffdb9854-6899-4b8f-a285-12e3f58b86b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530740070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.530740070
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.2294851546
Short name T74
Test name
Test status
Simulation time 264891386208 ps
CPU time 755.86 seconds
Started Mar 21 01:04:12 PM PDT 24
Finished Mar 21 01:16:50 PM PDT 24
Peak memory 200500 kb
Host smart-c107332e-d6c5-48b3-a0a5-5ba0cfe71951
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294851546 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2294851546
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.630377416
Short name T427
Test name
Test status
Simulation time 43708399 ps
CPU time 1.1 seconds
Started Mar 21 01:03:57 PM PDT 24
Finished Mar 21 01:03:59 PM PDT 24
Peak memory 199368 kb
Host smart-ce84ea92-58f2-4ed4-9ae5-9785c246258e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630377416 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_hmac_vectors.630377416
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.4240121676
Short name T331
Test name
Test status
Simulation time 54869125931 ps
CPU time 528.23 seconds
Started Mar 21 01:03:59 PM PDT 24
Finished Mar 21 01:12:57 PM PDT 24
Peak memory 200352 kb
Host smart-2fc374f0-f2db-483c-b30a-ed4be7a30d48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240121676 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.4240121676
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3909821866
Short name T257
Test name
Test status
Simulation time 1003901356 ps
CPU time 44.12 seconds
Started Mar 21 01:03:57 PM PDT 24
Finished Mar 21 01:04:42 PM PDT 24
Peak memory 200344 kb
Host smart-948253eb-c40e-4601-8877-0742fe060b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909821866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3909821866
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2195544746
Short name T529
Test name
Test status
Simulation time 21444695 ps
CPU time 0.6 seconds
Started Mar 21 01:03:32 PM PDT 24
Finished Mar 21 01:03:33 PM PDT 24
Peak memory 195964 kb
Host smart-efcaf26b-7f55-44bf-8720-d29016e26fc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195544746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2195544746
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.4097825367
Short name T404
Test name
Test status
Simulation time 760262222 ps
CPU time 25.8 seconds
Started Mar 21 01:03:32 PM PDT 24
Finished Mar 21 01:03:58 PM PDT 24
Peak memory 208640 kb
Host smart-067a2f7f-daf9-44ae-8e58-3d0d08368e7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4097825367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.4097825367
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3876205067
Short name T586
Test name
Test status
Simulation time 1671211659 ps
CPU time 32.85 seconds
Started Mar 21 01:03:36 PM PDT 24
Finished Mar 21 01:04:09 PM PDT 24
Peak memory 200296 kb
Host smart-d24573c8-4d5e-4179-8353-a5399a1885e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876205067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3876205067
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3631558205
Short name T35
Test name
Test status
Simulation time 11420678995 ps
CPU time 101.49 seconds
Started Mar 21 01:03:41 PM PDT 24
Finished Mar 21 01:05:22 PM PDT 24
Peak memory 200424 kb
Host smart-12d2289f-45b7-4ca0-a14d-bd133b8dec71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3631558205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3631558205
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.2956016487
Short name T347
Test name
Test status
Simulation time 1847716014 ps
CPU time 24.25 seconds
Started Mar 21 01:03:40 PM PDT 24
Finished Mar 21 01:04:05 PM PDT 24
Peak memory 200404 kb
Host smart-4516c6bb-177a-49af-bf8d-1978f0495500
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956016487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2956016487
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.404741532
Short name T139
Test name
Test status
Simulation time 678068514 ps
CPU time 4.64 seconds
Started Mar 21 01:03:34 PM PDT 24
Finished Mar 21 01:03:40 PM PDT 24
Peak memory 200336 kb
Host smart-08716291-d076-4d9c-8b5e-a0f2f7ae8a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404741532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.404741532
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.44254303
Short name T29
Test name
Test status
Simulation time 172418952 ps
CPU time 0.98 seconds
Started Mar 21 01:03:36 PM PDT 24
Finished Mar 21 01:03:38 PM PDT 24
Peak memory 219728 kb
Host smart-5e4c07ac-0515-487c-a756-9313630ce0cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44254303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.44254303
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.73262110
Short name T406
Test name
Test status
Simulation time 821170145 ps
CPU time 6.32 seconds
Started Mar 21 01:03:42 PM PDT 24
Finished Mar 21 01:03:49 PM PDT 24
Peak memory 200400 kb
Host smart-fe7cec79-87f4-4413-aa1d-11bef2f1f113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73262110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.73262110
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3726339374
Short name T365
Test name
Test status
Simulation time 14915554649 ps
CPU time 289.16 seconds
Started Mar 21 01:03:35 PM PDT 24
Finished Mar 21 01:08:25 PM PDT 24
Peak memory 200568 kb
Host smart-6046c4b1-876c-4257-8812-c7bae175380b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726339374 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3726339374
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.3274633131
Short name T181
Test name
Test status
Simulation time 28499465 ps
CPU time 1.02 seconds
Started Mar 21 01:03:36 PM PDT 24
Finished Mar 21 01:03:38 PM PDT 24
Peak memory 200068 kb
Host smart-fc1fdaaf-5260-4611-9603-d7b8feb7c23d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274633131 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.3274633131
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.3628722302
Short name T159
Test name
Test status
Simulation time 8671119177 ps
CPU time 459.35 seconds
Started Mar 21 01:03:32 PM PDT 24
Finished Mar 21 01:11:11 PM PDT 24
Peak memory 200364 kb
Host smart-3dc379f5-2598-4d17-bf6f-11646822a125
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628722302 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.3628722302
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.859005714
Short name T56
Test name
Test status
Simulation time 10360353365 ps
CPU time 48.06 seconds
Started Mar 21 01:03:44 PM PDT 24
Finished Mar 21 01:04:33 PM PDT 24
Peak memory 200432 kb
Host smart-a5896591-4e77-44ce-b788-251309c2dca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859005714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.859005714
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2675272226
Short name T477
Test name
Test status
Simulation time 21434765 ps
CPU time 0.6 seconds
Started Mar 21 01:03:59 PM PDT 24
Finished Mar 21 01:04:00 PM PDT 24
Peak memory 195924 kb
Host smart-76613127-ee0c-48c8-8dc9-e70f8a46bb22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675272226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2675272226
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1973145423
Short name T569
Test name
Test status
Simulation time 1032957891 ps
CPU time 35.87 seconds
Started Mar 21 01:04:15 PM PDT 24
Finished Mar 21 01:04:56 PM PDT 24
Peak memory 208588 kb
Host smart-16224ce4-54aa-44ab-a2c3-3042db4a1369
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1973145423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1973145423
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.1371176880
Short name T399
Test name
Test status
Simulation time 2720011268 ps
CPU time 26.26 seconds
Started Mar 21 01:04:00 PM PDT 24
Finished Mar 21 01:04:26 PM PDT 24
Peak memory 200404 kb
Host smart-29e16f84-09c4-444a-950a-c82400594754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371176880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1371176880
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1464728832
Short name T149
Test name
Test status
Simulation time 1556762971 ps
CPU time 24.26 seconds
Started Mar 21 01:03:56 PM PDT 24
Finished Mar 21 01:04:26 PM PDT 24
Peak memory 200344 kb
Host smart-3f7b7e68-0865-4345-9317-8f82503789a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1464728832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1464728832
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1919927763
Short name T567
Test name
Test status
Simulation time 15176648113 ps
CPU time 188.24 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:07:08 PM PDT 24
Peak memory 200476 kb
Host smart-f8baa2bd-803e-4911-9912-f1ea69299d9e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919927763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1919927763
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1605742362
Short name T192
Test name
Test status
Simulation time 3913878626 ps
CPU time 51.36 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:04:49 PM PDT 24
Peak memory 200444 kb
Host smart-a0aae7af-1343-46c0-9a43-cd05269efaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605742362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1605742362
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1041037342
Short name T235
Test name
Test status
Simulation time 28359270 ps
CPU time 1.11 seconds
Started Mar 21 01:03:57 PM PDT 24
Finished Mar 21 01:03:59 PM PDT 24
Peak memory 200380 kb
Host smart-a51644e8-2996-471d-90a4-d0d0315294f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041037342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1041037342
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.1617957870
Short name T400
Test name
Test status
Simulation time 108938656 ps
CPU time 1.22 seconds
Started Mar 21 01:04:15 PM PDT 24
Finished Mar 21 01:04:20 PM PDT 24
Peak memory 200244 kb
Host smart-27d9cc4a-52a8-4e6b-9c87-38659d4f7150
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617957870 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.1617957870
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.2034282108
Short name T127
Test name
Test status
Simulation time 29308587851 ps
CPU time 516.99 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:12:35 PM PDT 24
Peak memory 200332 kb
Host smart-1f5bc880-5bac-406f-baaa-e9b9692b1549
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034282108 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.2034282108
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3955699475
Short name T299
Test name
Test status
Simulation time 1725733803 ps
CPU time 8.47 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:04:11 PM PDT 24
Peak memory 200316 kb
Host smart-96886ecc-98aa-4a35-8e92-fada4df95f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955699475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3955699475
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3953706704
Short name T307
Test name
Test status
Simulation time 21616630 ps
CPU time 0.6 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:03:59 PM PDT 24
Peak memory 195812 kb
Host smart-142d92f5-1dbd-42ff-ab7d-6dcd49b168f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953706704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3953706704
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.158833317
Short name T410
Test name
Test status
Simulation time 4461051563 ps
CPU time 41.34 seconds
Started Mar 21 01:04:15 PM PDT 24
Finished Mar 21 01:05:02 PM PDT 24
Peak memory 225004 kb
Host smart-7429606a-b459-466c-96ad-481ecc67892c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=158833317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.158833317
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2822416902
Short name T591
Test name
Test status
Simulation time 2169436102 ps
CPU time 25.61 seconds
Started Mar 21 01:03:59 PM PDT 24
Finished Mar 21 01:04:25 PM PDT 24
Peak memory 200412 kb
Host smart-9a239cd8-733b-4840-ba9a-cec24ea444d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822416902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2822416902
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.3832621981
Short name T191
Test name
Test status
Simulation time 1942397802 ps
CPU time 58.68 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:05:02 PM PDT 24
Peak memory 200344 kb
Host smart-793cfac3-13d8-4175-9a06-77bbc23bad42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3832621981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3832621981
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.2993261192
Short name T462
Test name
Test status
Simulation time 372687168 ps
CPU time 19.9 seconds
Started Mar 21 01:04:00 PM PDT 24
Finished Mar 21 01:04:20 PM PDT 24
Peak memory 200372 kb
Host smart-fa42477f-0a14-4889-8e29-83431cd0b1f5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993261192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2993261192
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.367908100
Short name T464
Test name
Test status
Simulation time 1126231907 ps
CPU time 12.95 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:04:12 PM PDT 24
Peak memory 200436 kb
Host smart-9a5f5cf4-2653-4b10-ab4d-3c136cc444cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367908100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.367908100
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3592227259
Short name T510
Test name
Test status
Simulation time 581820781 ps
CPU time 4.9 seconds
Started Mar 21 01:04:00 PM PDT 24
Finished Mar 21 01:04:05 PM PDT 24
Peak memory 200356 kb
Host smart-cf1d6645-5829-427c-8b3a-2c7e4c2c831f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592227259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3592227259
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.80841715
Short name T356
Test name
Test status
Simulation time 58550201053 ps
CPU time 1674.35 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:31:54 PM PDT 24
Peak memory 200424 kb
Host smart-38a856ae-d1be-4958-b4e9-4d2855d9ea57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80841715 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.80841715
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.1138401403
Short name T164
Test name
Test status
Simulation time 41114604 ps
CPU time 1.01 seconds
Started Mar 21 01:04:01 PM PDT 24
Finished Mar 21 01:04:02 PM PDT 24
Peak memory 199456 kb
Host smart-9cb67784-9bcc-4f1c-bee0-572c6cb1a925
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138401403 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.1138401403
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.2003556138
Short name T419
Test name
Test status
Simulation time 37596388542 ps
CPU time 461.94 seconds
Started Mar 21 01:03:59 PM PDT 24
Finished Mar 21 01:11:41 PM PDT 24
Peak memory 200328 kb
Host smart-279f22fb-57f2-4aaf-8cfe-1fb1d4e1b08e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003556138 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.2003556138
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2753584428
Short name T178
Test name
Test status
Simulation time 24410478338 ps
CPU time 80.47 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:05:19 PM PDT 24
Peak memory 200468 kb
Host smart-2bae957d-b82f-4c9e-bd46-e43995301415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753584428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2753584428
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.644285695
Short name T18
Test name
Test status
Simulation time 27573602 ps
CPU time 0.55 seconds
Started Mar 21 01:04:05 PM PDT 24
Finished Mar 21 01:04:06 PM PDT 24
Peak memory 194756 kb
Host smart-62033cfa-e607-4c07-af5b-d56c0e24c3b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644285695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.644285695
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2428132561
Short name T394
Test name
Test status
Simulation time 3304132410 ps
CPU time 13 seconds
Started Mar 21 01:04:03 PM PDT 24
Finished Mar 21 01:04:16 PM PDT 24
Peak memory 216740 kb
Host smart-13b05a26-7a12-442a-b2c8-edd8a1078adf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2428132561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2428132561
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.527134800
Short name T269
Test name
Test status
Simulation time 1477488220 ps
CPU time 39.09 seconds
Started Mar 21 01:04:02 PM PDT 24
Finished Mar 21 01:04:41 PM PDT 24
Peak memory 200580 kb
Host smart-0ad10dd4-a214-49df-b730-2713f0258b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527134800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.527134800
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.4021282067
Short name T340
Test name
Test status
Simulation time 6817436739 ps
CPU time 74.82 seconds
Started Mar 21 01:04:02 PM PDT 24
Finished Mar 21 01:05:17 PM PDT 24
Peak memory 200668 kb
Host smart-7dcfbb90-59f3-4807-ae0a-1a7e686d53aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4021282067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.4021282067
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.662418429
Short name T416
Test name
Test status
Simulation time 2428231252 ps
CPU time 27.91 seconds
Started Mar 21 01:04:14 PM PDT 24
Finished Mar 21 01:04:43 PM PDT 24
Peak memory 200332 kb
Host smart-3a887b4f-fea0-4e20-baf2-ba3136988617
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662418429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.662418429
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.4087497447
Short name T142
Test name
Test status
Simulation time 94707787 ps
CPU time 2.9 seconds
Started Mar 21 01:04:01 PM PDT 24
Finished Mar 21 01:04:04 PM PDT 24
Peak memory 200548 kb
Host smart-b4596dfa-50df-4493-be3c-e5651e731a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087497447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.4087497447
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.364265529
Short name T345
Test name
Test status
Simulation time 421903209 ps
CPU time 3.44 seconds
Started Mar 21 01:04:02 PM PDT 24
Finished Mar 21 01:04:06 PM PDT 24
Peak memory 200632 kb
Host smart-73c7cca3-b82b-4ddf-804b-b5a6b3e6578b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364265529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.364265529
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.4056834702
Short name T73
Test name
Test status
Simulation time 312454099019 ps
CPU time 902.82 seconds
Started Mar 21 01:04:05 PM PDT 24
Finished Mar 21 01:19:08 PM PDT 24
Peak memory 233152 kb
Host smart-511d2073-7663-4de0-b518-80bb4f30e596
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056834702 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.4056834702
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.3466631593
Short name T522
Test name
Test status
Simulation time 113123450 ps
CPU time 1.23 seconds
Started Mar 21 01:04:02 PM PDT 24
Finished Mar 21 01:04:04 PM PDT 24
Peak memory 200624 kb
Host smart-3c5f2c8e-b256-4962-94dd-df8d33fd0e19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466631593 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.3466631593
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.311659790
Short name T519
Test name
Test status
Simulation time 44311537358 ps
CPU time 532.72 seconds
Started Mar 21 01:04:05 PM PDT 24
Finished Mar 21 01:12:58 PM PDT 24
Peak memory 200344 kb
Host smart-46432263-306b-419c-aaea-c2c28ad471ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311659790 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.311659790
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.3628359147
Short name T355
Test name
Test status
Simulation time 369684063 ps
CPU time 5.9 seconds
Started Mar 21 01:04:00 PM PDT 24
Finished Mar 21 01:04:06 PM PDT 24
Peak memory 200260 kb
Host smart-e37975ff-8425-4da8-8024-5cd32de84b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628359147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3628359147
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.4266098910
Short name T146
Test name
Test status
Simulation time 14158891 ps
CPU time 0.6 seconds
Started Mar 21 01:04:01 PM PDT 24
Finished Mar 21 01:04:08 PM PDT 24
Peak memory 195904 kb
Host smart-38117f3b-b716-4190-9368-6ae706d5ae0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266098910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.4266098910
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2412013047
Short name T415
Test name
Test status
Simulation time 5687241126 ps
CPU time 48.33 seconds
Started Mar 21 01:04:00 PM PDT 24
Finished Mar 21 01:04:49 PM PDT 24
Peak memory 208592 kb
Host smart-828ba996-87d9-46a2-af0d-f8c705cd85f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2412013047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2412013047
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1341690384
Short name T474
Test name
Test status
Simulation time 6943411058 ps
CPU time 58.52 seconds
Started Mar 21 01:04:05 PM PDT 24
Finished Mar 21 01:05:04 PM PDT 24
Peak memory 200408 kb
Host smart-8dc299c8-4db6-4918-a00e-d2cce7938130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341690384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1341690384
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1145854373
Short name T334
Test name
Test status
Simulation time 181420459 ps
CPU time 10.94 seconds
Started Mar 21 01:04:00 PM PDT 24
Finished Mar 21 01:04:11 PM PDT 24
Peak memory 200352 kb
Host smart-2338a60a-33b8-4c73-ad00-983931f87bf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1145854373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1145854373
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.719692339
Short name T274
Test name
Test status
Simulation time 6589877296 ps
CPU time 180.61 seconds
Started Mar 21 01:04:01 PM PDT 24
Finished Mar 21 01:07:02 PM PDT 24
Peak memory 200424 kb
Host smart-687b933f-11e0-46d2-997b-3b6968de7e11
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719692339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.719692339
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1412645706
Short name T199
Test name
Test status
Simulation time 38296576665 ps
CPU time 130.15 seconds
Started Mar 21 01:03:51 PM PDT 24
Finished Mar 21 01:06:11 PM PDT 24
Peak memory 200540 kb
Host smart-bf4c8eda-28d1-4ef2-933c-e6ebc2fe5bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412645706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1412645706
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2953038041
Short name T65
Test name
Test status
Simulation time 1400338547 ps
CPU time 5.64 seconds
Started Mar 21 01:04:07 PM PDT 24
Finished Mar 21 01:04:13 PM PDT 24
Peak memory 200352 kb
Host smart-6cae5689-1ee2-486c-a610-320b37685230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953038041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2953038041
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.961063950
Short name T442
Test name
Test status
Simulation time 4088944920 ps
CPU time 80.47 seconds
Started Mar 21 01:03:53 PM PDT 24
Finished Mar 21 01:05:14 PM PDT 24
Peak memory 200380 kb
Host smart-adbca09c-1db0-49c1-8a5d-a48afcac4742
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961063950 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.961063950
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.222768361
Short name T81
Test name
Test status
Simulation time 31833459 ps
CPU time 1.24 seconds
Started Mar 21 01:04:06 PM PDT 24
Finished Mar 21 01:04:08 PM PDT 24
Peak memory 200360 kb
Host smart-61ae7e04-e8fc-48ca-a6ce-b56ed00285be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222768361 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_hmac_vectors.222768361
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.1338164605
Short name T84
Test name
Test status
Simulation time 116695260184 ps
CPU time 522.11 seconds
Started Mar 21 01:04:05 PM PDT 24
Finished Mar 21 01:12:48 PM PDT 24
Peak memory 200328 kb
Host smart-2a6571b3-bd63-46cf-a15c-76b9dce61f36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338164605 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.1338164605
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2739747858
Short name T392
Test name
Test status
Simulation time 23012950633 ps
CPU time 91.44 seconds
Started Mar 21 01:04:06 PM PDT 24
Finished Mar 21 01:05:39 PM PDT 24
Peak memory 200404 kb
Host smart-348e0a2a-e1ef-40b7-a808-22df29dbd9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739747858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2739747858
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3040557566
Short name T336
Test name
Test status
Simulation time 17738595 ps
CPU time 0.58 seconds
Started Mar 21 01:04:01 PM PDT 24
Finished Mar 21 01:04:01 PM PDT 24
Peak memory 195544 kb
Host smart-e052fe90-ff62-4177-a48d-4f8c7edba875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040557566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3040557566
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1162037084
Short name T587
Test name
Test status
Simulation time 3096129992 ps
CPU time 18.98 seconds
Started Mar 21 01:04:00 PM PDT 24
Finished Mar 21 01:04:20 PM PDT 24
Peak memory 217924 kb
Host smart-0da67e86-7bc6-4075-beaf-da68d490df22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1162037084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1162037084
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1925571989
Short name T346
Test name
Test status
Simulation time 1000149086 ps
CPU time 9.56 seconds
Started Mar 21 01:04:01 PM PDT 24
Finished Mar 21 01:04:10 PM PDT 24
Peak memory 200328 kb
Host smart-06268e18-0e4e-44d7-83cd-c02bdaeb3123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925571989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1925571989
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1464390872
Short name T177
Test name
Test status
Simulation time 2376598878 ps
CPU time 34.65 seconds
Started Mar 21 01:04:07 PM PDT 24
Finished Mar 21 01:04:42 PM PDT 24
Peak memory 200396 kb
Host smart-b3623416-cec0-4e39-bd1a-5b16e0f7652c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1464390872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1464390872
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2087335836
Short name T281
Test name
Test status
Simulation time 2142354880 ps
CPU time 117.3 seconds
Started Mar 21 01:04:27 PM PDT 24
Finished Mar 21 01:06:24 PM PDT 24
Peak memory 200468 kb
Host smart-4f1ca05e-ab8d-4a4d-9a84-3638128ef0a8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087335836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2087335836
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.3004070077
Short name T217
Test name
Test status
Simulation time 3083883460 ps
CPU time 12.1 seconds
Started Mar 21 01:04:04 PM PDT 24
Finished Mar 21 01:04:16 PM PDT 24
Peak memory 200376 kb
Host smart-1a8a1ec3-64b3-4886-a6e8-181c9096990b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004070077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3004070077
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2876993498
Short name T304
Test name
Test status
Simulation time 424793394 ps
CPU time 6.29 seconds
Started Mar 21 01:03:59 PM PDT 24
Finished Mar 21 01:04:06 PM PDT 24
Peak memory 200312 kb
Host smart-2340306e-fcc7-431f-a588-8ba9ddd03998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876993498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2876993498
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.363749705
Short name T514
Test name
Test status
Simulation time 41515691221 ps
CPU time 1268.96 seconds
Started Mar 21 01:04:28 PM PDT 24
Finished Mar 21 01:25:37 PM PDT 24
Peak memory 225096 kb
Host smart-c1bd2e0b-5516-4509-883f-5a8c0b74e1ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363749705 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.363749705
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.3855045962
Short name T499
Test name
Test status
Simulation time 28819153 ps
CPU time 1.07 seconds
Started Mar 21 01:04:08 PM PDT 24
Finished Mar 21 01:04:09 PM PDT 24
Peak memory 199592 kb
Host smart-1edca01c-47ed-428c-bd31-69b66f9911bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855045962 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.3855045962
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.1155546586
Short name T37
Test name
Test status
Simulation time 102285096048 ps
CPU time 437.36 seconds
Started Mar 21 01:04:02 PM PDT 24
Finished Mar 21 01:11:19 PM PDT 24
Peak memory 200376 kb
Host smart-073ecdd7-3755-4833-a8cd-a6f24de2615a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155546586 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.1155546586
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.1165627894
Short name T124
Test name
Test status
Simulation time 568744419 ps
CPU time 6.32 seconds
Started Mar 21 01:04:22 PM PDT 24
Finished Mar 21 01:04:29 PM PDT 24
Peak memory 200404 kb
Host smart-790463d1-c3b1-48a1-9d08-190861998b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165627894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1165627894
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3603075243
Short name T350
Test name
Test status
Simulation time 13305725 ps
CPU time 0.56 seconds
Started Mar 21 01:03:59 PM PDT 24
Finished Mar 21 01:03:59 PM PDT 24
Peak memory 195752 kb
Host smart-bc757f0f-0eb4-4814-aacf-73a143adb8f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603075243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3603075243
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.4020834472
Short name T382
Test name
Test status
Simulation time 918534582 ps
CPU time 36.9 seconds
Started Mar 21 01:04:14 PM PDT 24
Finished Mar 21 01:04:51 PM PDT 24
Peak memory 249328 kb
Host smart-5770be1f-705e-43cb-94a7-0ae57a4f47a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4020834472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.4020834472
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.26798861
Short name T383
Test name
Test status
Simulation time 2656920912 ps
CPU time 13.87 seconds
Started Mar 21 01:04:17 PM PDT 24
Finished Mar 21 01:04:35 PM PDT 24
Peak memory 200368 kb
Host smart-639c5dd9-e910-4e86-be81-003626056abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26798861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.26798861
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.4234494453
Short name T452
Test name
Test status
Simulation time 732891631 ps
CPU time 42.81 seconds
Started Mar 21 01:04:27 PM PDT 24
Finished Mar 21 01:05:10 PM PDT 24
Peak memory 200428 kb
Host smart-965634c2-c1ac-47f6-8935-0f1ed7c67beb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4234494453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.4234494453
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.339666164
Short name T251
Test name
Test status
Simulation time 19567611080 ps
CPU time 63.41 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:05:02 PM PDT 24
Peak memory 200424 kb
Host smart-a5c5611d-25ff-4ec5-8115-f7c8f1f7ec6d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339666164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.339666164
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3257957783
Short name T322
Test name
Test status
Simulation time 875967310 ps
CPU time 28.02 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:04:28 PM PDT 24
Peak memory 200388 kb
Host smart-4617a6be-0cfc-4f4e-a4fc-e7bf6526b884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257957783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3257957783
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2948149489
Short name T497
Test name
Test status
Simulation time 143268552 ps
CPU time 4.41 seconds
Started Mar 21 01:03:59 PM PDT 24
Finished Mar 21 01:04:04 PM PDT 24
Peak memory 200360 kb
Host smart-91abb24e-ec29-4c21-8911-3b56c1eb6b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948149489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2948149489
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.1745290571
Short name T166
Test name
Test status
Simulation time 113554620 ps
CPU time 1.2 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:03:59 PM PDT 24
Peak memory 200104 kb
Host smart-2e14c2ce-2b89-4b39-972f-1823f4cfd7b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745290571 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.1745290571
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.3443030776
Short name T211
Test name
Test status
Simulation time 177438031250 ps
CPU time 431 seconds
Started Mar 21 01:04:01 PM PDT 24
Finished Mar 21 01:11:12 PM PDT 24
Peak memory 200404 kb
Host smart-4c54134d-091c-4d2b-970b-0317444cc1fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443030776 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.3443030776
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2782089742
Short name T348
Test name
Test status
Simulation time 10460970656 ps
CPU time 85.07 seconds
Started Mar 21 01:03:59 PM PDT 24
Finished Mar 21 01:05:25 PM PDT 24
Peak memory 200488 kb
Host smart-15f5f313-2e5c-4243-8e49-38594b2fe867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782089742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2782089742
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.3346049837
Short name T193
Test name
Test status
Simulation time 35367736 ps
CPU time 0.59 seconds
Started Mar 21 01:04:22 PM PDT 24
Finished Mar 21 01:04:23 PM PDT 24
Peak memory 195716 kb
Host smart-572a8abd-9661-4e9f-a97c-501dec39fbd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346049837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3346049837
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2528614436
Short name T486
Test name
Test status
Simulation time 2503075288 ps
CPU time 21.73 seconds
Started Mar 21 01:03:59 PM PDT 24
Finished Mar 21 01:04:21 PM PDT 24
Peak memory 208604 kb
Host smart-5bfa6deb-fbdd-462e-be19-a4114cf90352
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2528614436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2528614436
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.3271793324
Short name T318
Test name
Test status
Simulation time 1562773707 ps
CPU time 11.49 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:04:10 PM PDT 24
Peak memory 200380 kb
Host smart-ada04d5e-0a63-461a-8ec7-2f9cf91a044d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271793324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.3271793324
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.102657386
Short name T313
Test name
Test status
Simulation time 815867071 ps
CPU time 47.99 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:04:46 PM PDT 24
Peak memory 200356 kb
Host smart-c9118b89-9867-42e9-a367-f4c6e4e5c800
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=102657386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.102657386
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3704695900
Short name T226
Test name
Test status
Simulation time 4750971380 ps
CPU time 59.57 seconds
Started Mar 21 01:04:07 PM PDT 24
Finished Mar 21 01:05:07 PM PDT 24
Peak memory 200440 kb
Host smart-54cc0f7a-888c-4075-8ad5-999839d00b1b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704695900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3704695900
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2428001332
Short name T343
Test name
Test status
Simulation time 3564980797 ps
CPU time 66.23 seconds
Started Mar 21 01:04:10 PM PDT 24
Finished Mar 21 01:05:17 PM PDT 24
Peak memory 200420 kb
Host smart-28982fa1-b97b-4c69-98cf-ea1deab04c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428001332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2428001332
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.1184540105
Short name T141
Test name
Test status
Simulation time 105310620 ps
CPU time 1.66 seconds
Started Mar 21 01:04:20 PM PDT 24
Finished Mar 21 01:04:23 PM PDT 24
Peak memory 200436 kb
Host smart-2c466b06-564e-4d08-9fe5-0144d6c414a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184540105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1184540105
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.4223290431
Short name T450
Test name
Test status
Simulation time 34135188271 ps
CPU time 522.42 seconds
Started Mar 21 01:04:02 PM PDT 24
Finished Mar 21 01:12:45 PM PDT 24
Peak memory 200692 kb
Host smart-da6b3a6c-15ea-4bc4-af63-bc1dfc51bb9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223290431 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.4223290431
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.568486444
Short name T160
Test name
Test status
Simulation time 104343925 ps
CPU time 1.09 seconds
Started Mar 21 01:04:20 PM PDT 24
Finished Mar 21 01:04:22 PM PDT 24
Peak memory 199816 kb
Host smart-c0ab9f3d-1ac2-4946-b94a-3f7264478ae8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568486444 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_hmac_vectors.568486444
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.1630198061
Short name T144
Test name
Test status
Simulation time 28061086772 ps
CPU time 407.61 seconds
Started Mar 21 01:04:10 PM PDT 24
Finished Mar 21 01:10:59 PM PDT 24
Peak memory 200332 kb
Host smart-5e41938d-7f96-4176-b665-369155edb668
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630198061 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.1630198061
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.1121240479
Short name T357
Test name
Test status
Simulation time 837712818 ps
CPU time 15.89 seconds
Started Mar 21 01:04:10 PM PDT 24
Finished Mar 21 01:04:27 PM PDT 24
Peak memory 200408 kb
Host smart-9715f0f7-abc6-42ca-95a7-93f89a2ff4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121240479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1121240479
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.4126982015
Short name T276
Test name
Test status
Simulation time 40828309 ps
CPU time 0.58 seconds
Started Mar 21 01:04:23 PM PDT 24
Finished Mar 21 01:04:24 PM PDT 24
Peak memory 195852 kb
Host smart-a7d027c3-5fae-4d16-885d-258e7e0bb20e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126982015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.4126982015
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1681165045
Short name T234
Test name
Test status
Simulation time 1652877600 ps
CPU time 69.5 seconds
Started Mar 21 01:04:15 PM PDT 24
Finished Mar 21 01:05:31 PM PDT 24
Peak memory 229912 kb
Host smart-9d0bb8a3-56b6-41b2-84e8-20eadeb4824d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1681165045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1681165045
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.2983777599
Short name T594
Test name
Test status
Simulation time 5325333316 ps
CPU time 68.05 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:05:06 PM PDT 24
Peak memory 200384 kb
Host smart-b3c4af4f-0975-4dc0-a5f6-994ceb39783b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983777599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2983777599
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3503411823
Short name T563
Test name
Test status
Simulation time 3442918800 ps
CPU time 47.99 seconds
Started Mar 21 01:04:01 PM PDT 24
Finished Mar 21 01:04:49 PM PDT 24
Peak memory 200484 kb
Host smart-d3cb95f2-40e4-49ed-95ad-2fd1ea60354a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3503411823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3503411823
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.4053530985
Short name T289
Test name
Test status
Simulation time 973905480 ps
CPU time 27.01 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:04:25 PM PDT 24
Peak memory 200396 kb
Host smart-9a9817af-d34c-4948-96c9-b1fdbe69bde4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053530985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.4053530985
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.964539809
Short name T259
Test name
Test status
Simulation time 6460726857 ps
CPU time 68.53 seconds
Started Mar 21 01:04:23 PM PDT 24
Finished Mar 21 01:05:32 PM PDT 24
Peak memory 200408 kb
Host smart-98677377-cf5b-406b-a15f-cef674ed6a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964539809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.964539809
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2272528175
Short name T163
Test name
Test status
Simulation time 89929836 ps
CPU time 1.79 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:04:00 PM PDT 24
Peak memory 200404 kb
Host smart-69deb71b-4da3-4897-a995-c83e02d48568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272528175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2272528175
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.4156571277
Short name T409
Test name
Test status
Simulation time 116317177754 ps
CPU time 1617.86 seconds
Started Mar 21 01:04:09 PM PDT 24
Finished Mar 21 01:31:07 PM PDT 24
Peak memory 216020 kb
Host smart-ae63c6d8-aeb5-4872-950e-51cab392cf5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156571277 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.4156571277
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.2596352063
Short name T194
Test name
Test status
Simulation time 365086764 ps
CPU time 1.29 seconds
Started Mar 21 01:04:21 PM PDT 24
Finished Mar 21 01:04:24 PM PDT 24
Peak memory 200216 kb
Host smart-915288d4-db85-4281-b867-6e0413d1275f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596352063 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.2596352063
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.198964309
Short name T316
Test name
Test status
Simulation time 112927629197 ps
CPU time 493.89 seconds
Started Mar 21 01:04:24 PM PDT 24
Finished Mar 21 01:12:38 PM PDT 24
Peak memory 200472 kb
Host smart-7f660209-15ff-4cfc-814a-a0453c794ad0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198964309 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.198964309
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.2969026378
Short name T167
Test name
Test status
Simulation time 2204031866 ps
CPU time 42.62 seconds
Started Mar 21 01:04:00 PM PDT 24
Finished Mar 21 01:04:43 PM PDT 24
Peak memory 200384 kb
Host smart-1f4d3b66-f46c-42b6-bfb7-1dae5b9c4c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969026378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2969026378
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2044736347
Short name T480
Test name
Test status
Simulation time 15042473 ps
CPU time 0.58 seconds
Started Mar 21 01:04:07 PM PDT 24
Finished Mar 21 01:04:08 PM PDT 24
Peak memory 195900 kb
Host smart-4382018d-678b-441b-a320-0f4955444915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044736347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2044736347
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3495622176
Short name T508
Test name
Test status
Simulation time 20463111854 ps
CPU time 41.74 seconds
Started Mar 21 01:04:23 PM PDT 24
Finished Mar 21 01:05:05 PM PDT 24
Peak memory 216832 kb
Host smart-a891ea25-3a1b-40c4-a9ed-eb5cfd86a7e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3495622176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3495622176
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1699814486
Short name T437
Test name
Test status
Simulation time 1167821851 ps
CPU time 8.75 seconds
Started Mar 21 01:04:01 PM PDT 24
Finished Mar 21 01:04:10 PM PDT 24
Peak memory 200316 kb
Host smart-1ce36177-96ef-4fc7-8a4f-49d379b97221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699814486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1699814486
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.1705977257
Short name T454
Test name
Test status
Simulation time 8332574598 ps
CPU time 129.06 seconds
Started Mar 21 01:04:05 PM PDT 24
Finished Mar 21 01:06:14 PM PDT 24
Peak memory 200492 kb
Host smart-405d93cf-fcdf-441e-9079-350f6c1e8e75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1705977257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1705977257
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1882381094
Short name T544
Test name
Test status
Simulation time 4042307747 ps
CPU time 25.66 seconds
Started Mar 21 01:04:33 PM PDT 24
Finished Mar 21 01:04:59 PM PDT 24
Peak memory 200304 kb
Host smart-5f1f454a-c0c4-41c8-aea9-20646d7a5888
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882381094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1882381094
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2634893609
Short name T431
Test name
Test status
Simulation time 3562659827 ps
CPU time 103.06 seconds
Started Mar 21 01:03:59 PM PDT 24
Finished Mar 21 01:05:43 PM PDT 24
Peak memory 200416 kb
Host smart-038fc744-87c7-4ad6-83a0-4140f4f96009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634893609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2634893609
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.2193806148
Short name T538
Test name
Test status
Simulation time 454336899 ps
CPU time 7.09 seconds
Started Mar 21 01:03:57 PM PDT 24
Finished Mar 21 01:04:10 PM PDT 24
Peak memory 200432 kb
Host smart-f8a2e8af-5970-4483-a968-813a60ad47dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193806148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2193806148
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.524882790
Short name T282
Test name
Test status
Simulation time 84589506594 ps
CPU time 818.78 seconds
Started Mar 21 01:04:15 PM PDT 24
Finished Mar 21 01:17:59 PM PDT 24
Peak memory 236868 kb
Host smart-541a5ca0-d3bc-4428-8399-294f266fe2c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524882790 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.524882790
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.493920133
Short name T133
Test name
Test status
Simulation time 75046607 ps
CPU time 1.01 seconds
Started Mar 21 01:04:00 PM PDT 24
Finished Mar 21 01:04:01 PM PDT 24
Peak memory 198312 kb
Host smart-b3dc2967-b02b-4b75-a9aa-1d578fe1a392
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493920133 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_hmac_vectors.493920133
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.1832338316
Short name T168
Test name
Test status
Simulation time 8112250598 ps
CPU time 467.31 seconds
Started Mar 21 01:03:59 PM PDT 24
Finished Mar 21 01:11:47 PM PDT 24
Peak memory 200380 kb
Host smart-80e151da-d5ed-4b3d-a5a2-2b32ed4a1a8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832338316 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.1832338316
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.4156336572
Short name T447
Test name
Test status
Simulation time 1976621851 ps
CPU time 58.32 seconds
Started Mar 21 01:04:00 PM PDT 24
Finished Mar 21 01:04:59 PM PDT 24
Peak memory 200324 kb
Host smart-fc5bd68c-e125-468d-ab06-f2a0a26f92ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156336572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.4156336572
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1750627838
Short name T439
Test name
Test status
Simulation time 129054010 ps
CPU time 0.56 seconds
Started Mar 21 01:04:17 PM PDT 24
Finished Mar 21 01:04:22 PM PDT 24
Peak memory 195624 kb
Host smart-05bbc691-b88b-49a7-afcc-2e69e676395d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750627838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1750627838
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1232156924
Short name T511
Test name
Test status
Simulation time 2132243939 ps
CPU time 38.79 seconds
Started Mar 21 01:04:24 PM PDT 24
Finished Mar 21 01:05:03 PM PDT 24
Peak memory 222636 kb
Host smart-a1af3d0d-abb7-4398-92cd-14f7120f98ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1232156924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1232156924
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2884627393
Short name T330
Test name
Test status
Simulation time 3778751195 ps
CPU time 18.88 seconds
Started Mar 21 01:04:17 PM PDT 24
Finished Mar 21 01:04:40 PM PDT 24
Peak memory 200488 kb
Host smart-e6a40748-51f0-4ee0-9974-3c910f59e558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884627393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2884627393
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.2302691117
Short name T320
Test name
Test status
Simulation time 5101490376 ps
CPU time 74.56 seconds
Started Mar 21 01:04:22 PM PDT 24
Finished Mar 21 01:05:37 PM PDT 24
Peak memory 200488 kb
Host smart-bf371db1-2ebf-435c-90de-26c18feb46f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2302691117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2302691117
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.1043771186
Short name T524
Test name
Test status
Simulation time 2833934492 ps
CPU time 174.8 seconds
Started Mar 21 01:04:34 PM PDT 24
Finished Mar 21 01:07:29 PM PDT 24
Peak memory 200464 kb
Host smart-71603c06-89b2-4c7f-9199-a64ccc832426
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043771186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1043771186
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.3731500153
Short name T548
Test name
Test status
Simulation time 2699822721 ps
CPU time 84 seconds
Started Mar 21 01:04:21 PM PDT 24
Finished Mar 21 01:05:46 PM PDT 24
Peak memory 200504 kb
Host smart-ba735d36-0adf-4ded-aedf-84c4b971f0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731500153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3731500153
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.3869722650
Short name T455
Test name
Test status
Simulation time 500087903 ps
CPU time 6.42 seconds
Started Mar 21 01:03:57 PM PDT 24
Finished Mar 21 01:04:04 PM PDT 24
Peak memory 200376 kb
Host smart-bd64805f-70d2-48a0-a211-259388eb7b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869722650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.3869722650
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.3369087152
Short name T405
Test name
Test status
Simulation time 251404551132 ps
CPU time 1101.2 seconds
Started Mar 21 01:04:24 PM PDT 24
Finished Mar 21 01:22:46 PM PDT 24
Peak memory 216824 kb
Host smart-96c7a173-8b1b-4a52-8561-7f647fe07a02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369087152 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3369087152
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.825112068
Short name T411
Test name
Test status
Simulation time 55137752 ps
CPU time 1.07 seconds
Started Mar 21 01:04:23 PM PDT 24
Finished Mar 21 01:04:24 PM PDT 24
Peak memory 199524 kb
Host smart-9df095b2-966b-4a2b-a7e6-8385ee0336fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825112068 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_hmac_vectors.825112068
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.2283241422
Short name T534
Test name
Test status
Simulation time 29627995968 ps
CPU time 535.53 seconds
Started Mar 21 01:04:20 PM PDT 24
Finished Mar 21 01:13:17 PM PDT 24
Peak memory 200296 kb
Host smart-04b88924-3d34-4ccb-8884-66bb7286300c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283241422 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.2283241422
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.3016662626
Short name T185
Test name
Test status
Simulation time 2457746879 ps
CPU time 33.32 seconds
Started Mar 21 01:04:19 PM PDT 24
Finished Mar 21 01:04:54 PM PDT 24
Peak memory 200184 kb
Host smart-c8df6b2d-1e9f-490e-8222-4001fa48f20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016662626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3016662626
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.988916498
Short name T52
Test name
Test status
Simulation time 40638737 ps
CPU time 0.61 seconds
Started Mar 21 01:03:32 PM PDT 24
Finished Mar 21 01:03:33 PM PDT 24
Peak memory 195788 kb
Host smart-bf39df72-5a9a-4e08-a07c-848e072303c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988916498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.988916498
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3570028799
Short name T49
Test name
Test status
Simulation time 607591689 ps
CPU time 11.51 seconds
Started Mar 21 01:03:35 PM PDT 24
Finished Mar 21 01:03:47 PM PDT 24
Peak memory 208600 kb
Host smart-e4b7a876-aede-4f5e-8ebc-c2addc2c4c6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3570028799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3570028799
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.4097781936
Short name T491
Test name
Test status
Simulation time 2003639756 ps
CPU time 41.1 seconds
Started Mar 21 01:03:32 PM PDT 24
Finished Mar 21 01:04:13 PM PDT 24
Peak memory 200412 kb
Host smart-e64d2d02-51cb-4940-8a75-c8e3b14f6cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097781936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.4097781936
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.58341470
Short name T180
Test name
Test status
Simulation time 1712781862 ps
CPU time 101.95 seconds
Started Mar 21 01:03:35 PM PDT 24
Finished Mar 21 01:05:17 PM PDT 24
Peak memory 200460 kb
Host smart-3aaceb9d-7190-4a1d-8daa-dbb73ab7bb98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58341470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.58341470
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2677693620
Short name T227
Test name
Test status
Simulation time 130008600240 ps
CPU time 191.38 seconds
Started Mar 21 01:03:33 PM PDT 24
Finished Mar 21 01:06:45 PM PDT 24
Peak memory 200380 kb
Host smart-732a6d84-5d09-4e11-8e49-6648cbc56836
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677693620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2677693620
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3332510445
Short name T135
Test name
Test status
Simulation time 1118226480 ps
CPU time 16.88 seconds
Started Mar 21 01:03:32 PM PDT 24
Finished Mar 21 01:03:50 PM PDT 24
Peak memory 200340 kb
Host smart-42fa4377-1967-4196-8983-6a5ee28edf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332510445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3332510445
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3554125020
Short name T27
Test name
Test status
Simulation time 118215742 ps
CPU time 0.97 seconds
Started Mar 21 01:03:32 PM PDT 24
Finished Mar 21 01:03:34 PM PDT 24
Peak memory 218800 kb
Host smart-cdb2b219-1f25-4234-a24e-84b1e834408c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554125020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3554125020
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3873339565
Short name T389
Test name
Test status
Simulation time 230662152 ps
CPU time 3.78 seconds
Started Mar 21 01:03:33 PM PDT 24
Finished Mar 21 01:03:37 PM PDT 24
Peak memory 200388 kb
Host smart-25e0ed28-fa71-4f07-afa7-058e4b743eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873339565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3873339565
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.1126898217
Short name T214
Test name
Test status
Simulation time 190006227 ps
CPU time 1.23 seconds
Started Mar 21 01:03:32 PM PDT 24
Finished Mar 21 01:03:34 PM PDT 24
Peak memory 200344 kb
Host smart-a2fd0618-3e5e-4e48-ba57-19d22fbe1611
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126898217 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.1126898217
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.790891570
Short name T374
Test name
Test status
Simulation time 8718131653 ps
CPU time 473.56 seconds
Started Mar 21 01:03:36 PM PDT 24
Finished Mar 21 01:11:31 PM PDT 24
Peak memory 200344 kb
Host smart-ebccd85e-75ff-4fa1-bb2c-777849639a8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790891570 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.790891570
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3381999981
Short name T145
Test name
Test status
Simulation time 290976851 ps
CPU time 4.76 seconds
Started Mar 21 01:03:45 PM PDT 24
Finished Mar 21 01:03:50 PM PDT 24
Peak memory 200396 kb
Host smart-e6b0d280-6ed6-4644-9064-0bd85ed67eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381999981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3381999981
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.176812507
Short name T128
Test name
Test status
Simulation time 139612575 ps
CPU time 0.58 seconds
Started Mar 21 01:04:30 PM PDT 24
Finished Mar 21 01:04:32 PM PDT 24
Peak memory 194768 kb
Host smart-bc20187f-4629-4e55-b7f1-f02bc6cbb2c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176812507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.176812507
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.483289948
Short name T581
Test name
Test status
Simulation time 7287615171 ps
CPU time 31.19 seconds
Started Mar 21 01:04:25 PM PDT 24
Finished Mar 21 01:04:56 PM PDT 24
Peak memory 208616 kb
Host smart-2b9e9d6c-b648-4709-b9bf-49ca5fa1d5aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=483289948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.483289948
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.603044706
Short name T66
Test name
Test status
Simulation time 3122523137 ps
CPU time 47.86 seconds
Started Mar 21 01:04:20 PM PDT 24
Finished Mar 21 01:05:10 PM PDT 24
Peak memory 200452 kb
Host smart-1f5fd3fd-4ab0-4035-b3b2-6c6d2f612b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603044706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.603044706
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2412984427
Short name T453
Test name
Test status
Simulation time 8049327554 ps
CPU time 121.87 seconds
Started Mar 21 01:04:22 PM PDT 24
Finished Mar 21 01:06:24 PM PDT 24
Peak memory 200504 kb
Host smart-f47fb958-f20a-436d-8fec-09fe08545040
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2412984427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2412984427
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.790000393
Short name T562
Test name
Test status
Simulation time 16451720476 ps
CPU time 217.82 seconds
Started Mar 21 01:04:27 PM PDT 24
Finished Mar 21 01:08:05 PM PDT 24
Peak memory 200484 kb
Host smart-4071fe4a-2298-4149-b3d3-c16af7a71d85
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790000393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.790000393
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3444034522
Short name T385
Test name
Test status
Simulation time 29382956591 ps
CPU time 102.93 seconds
Started Mar 21 01:04:28 PM PDT 24
Finished Mar 21 01:06:11 PM PDT 24
Peak memory 200564 kb
Host smart-77f42f61-47a2-4cb9-890c-566940d022f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444034522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3444034522
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.805210347
Short name T136
Test name
Test status
Simulation time 421656328 ps
CPU time 3.8 seconds
Started Mar 21 01:03:59 PM PDT 24
Finished Mar 21 01:04:03 PM PDT 24
Peak memory 200344 kb
Host smart-19632089-59b8-4509-8e79-0ea3236d612f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805210347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.805210347
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.427334313
Short name T71
Test name
Test status
Simulation time 217182532626 ps
CPU time 735.8 seconds
Started Mar 21 01:04:18 PM PDT 24
Finished Mar 21 01:16:37 PM PDT 24
Peak memory 218912 kb
Host smart-00de9c5c-5cd9-439e-98f3-6ff5cdff9a77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427334313 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.427334313
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.4266368098
Short name T315
Test name
Test status
Simulation time 115197611 ps
CPU time 1.21 seconds
Started Mar 21 01:04:24 PM PDT 24
Finished Mar 21 01:04:25 PM PDT 24
Peak memory 200396 kb
Host smart-40359d24-2694-4a8e-86f8-66fd85e884bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266368098 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.4266368098
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.2751587111
Short name T561
Test name
Test status
Simulation time 35169831606 ps
CPU time 441.78 seconds
Started Mar 21 01:04:25 PM PDT 24
Finished Mar 21 01:11:46 PM PDT 24
Peak memory 200360 kb
Host smart-131b8738-52bc-4106-aeb8-2d4c2708ed89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751587111 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.2751587111
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.5238873
Short name T196
Test name
Test status
Simulation time 1415496549 ps
CPU time 17.93 seconds
Started Mar 21 01:04:09 PM PDT 24
Finished Mar 21 01:04:27 PM PDT 24
Peak memory 200416 kb
Host smart-2ad5e140-17d6-4be1-8c80-ab731530c62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5238873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.5238873
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3209168184
Short name T435
Test name
Test status
Simulation time 26309736 ps
CPU time 0.6 seconds
Started Mar 21 01:04:18 PM PDT 24
Finished Mar 21 01:04:22 PM PDT 24
Peak memory 195784 kb
Host smart-d073b4f5-b29f-4b9e-a2a0-364f7cf70aae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209168184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3209168184
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.946770869
Short name T176
Test name
Test status
Simulation time 831549373 ps
CPU time 28.44 seconds
Started Mar 21 01:04:28 PM PDT 24
Finished Mar 21 01:04:57 PM PDT 24
Peak memory 224948 kb
Host smart-20d905b8-1f03-4522-adc8-fbfb9bef5233
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=946770869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.946770869
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1617821769
Short name T342
Test name
Test status
Simulation time 8153407415 ps
CPU time 41.7 seconds
Started Mar 21 01:04:25 PM PDT 24
Finished Mar 21 01:05:07 PM PDT 24
Peak memory 200420 kb
Host smart-e4cc15ef-0433-421e-b3c3-f9981844ee6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617821769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1617821769
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.600646673
Short name T527
Test name
Test status
Simulation time 2029110726 ps
CPU time 24.35 seconds
Started Mar 21 01:04:18 PM PDT 24
Finished Mar 21 01:04:46 PM PDT 24
Peak memory 200272 kb
Host smart-27265409-0aa4-4121-8e5e-6f5626628b6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=600646673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.600646673
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.2324900306
Short name T31
Test name
Test status
Simulation time 419296530 ps
CPU time 10.93 seconds
Started Mar 21 01:04:21 PM PDT 24
Finished Mar 21 01:04:33 PM PDT 24
Peak memory 200336 kb
Host smart-e61143fd-2512-45b0-846c-6ca3190c2a00
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324900306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2324900306
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1344350224
Short name T533
Test name
Test status
Simulation time 2342256299 ps
CPU time 34.1 seconds
Started Mar 21 01:04:23 PM PDT 24
Finished Mar 21 01:04:57 PM PDT 24
Peak memory 200540 kb
Host smart-282184ae-bdf6-4464-a4f0-261c25d010d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344350224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1344350224
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2820560190
Short name T601
Test name
Test status
Simulation time 775107059 ps
CPU time 3.24 seconds
Started Mar 21 01:04:14 PM PDT 24
Finished Mar 21 01:04:18 PM PDT 24
Peak memory 200356 kb
Host smart-0b617636-0522-4d54-92c0-67e93d9e28ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820560190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2820560190
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.4213156806
Short name T542
Test name
Test status
Simulation time 70712170 ps
CPU time 1.31 seconds
Started Mar 21 01:04:15 PM PDT 24
Finished Mar 21 01:04:22 PM PDT 24
Peak memory 200420 kb
Host smart-b1d500fc-5dfb-4b48-9d48-79acd2f3daf9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213156806 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.4213156806
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.2765414536
Short name T298
Test name
Test status
Simulation time 191246291115 ps
CPU time 577.87 seconds
Started Mar 21 01:04:20 PM PDT 24
Finished Mar 21 01:13:59 PM PDT 24
Peak memory 200340 kb
Host smart-50cf0493-633b-41d6-87df-d1fe9bc8779a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765414536 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.2765414536
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2235856954
Short name T233
Test name
Test status
Simulation time 3209884207 ps
CPU time 60.13 seconds
Started Mar 21 01:04:21 PM PDT 24
Finished Mar 21 01:05:22 PM PDT 24
Peak memory 200404 kb
Host smart-5491f083-19c6-4d73-8272-46c38bb05a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235856954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2235856954
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.4152359778
Short name T489
Test name
Test status
Simulation time 48883449 ps
CPU time 0.64 seconds
Started Mar 21 01:04:27 PM PDT 24
Finished Mar 21 01:04:28 PM PDT 24
Peak memory 195956 kb
Host smart-63fa00cc-9d85-49e8-a169-f8e00b371b16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152359778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.4152359778
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3579841330
Short name T293
Test name
Test status
Simulation time 1608361002 ps
CPU time 50.95 seconds
Started Mar 21 01:04:21 PM PDT 24
Finished Mar 21 01:05:13 PM PDT 24
Peak memory 200380 kb
Host smart-e7beb097-201d-440e-ac69-be68706516c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3579841330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3579841330
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.4192621029
Short name T590
Test name
Test status
Simulation time 4965132216 ps
CPU time 40.33 seconds
Started Mar 21 01:04:30 PM PDT 24
Finished Mar 21 01:05:12 PM PDT 24
Peak memory 200516 kb
Host smart-5d6ef171-8d24-4871-88a7-8043714c4f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192621029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.4192621029
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2681669144
Short name T303
Test name
Test status
Simulation time 8849803587 ps
CPU time 135.31 seconds
Started Mar 21 01:04:27 PM PDT 24
Finished Mar 21 01:06:43 PM PDT 24
Peak memory 200468 kb
Host smart-1d9ce4cb-1e58-4eb8-8dc7-ec086e007537
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2681669144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2681669144
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.2637476053
Short name T39
Test name
Test status
Simulation time 1108653257 ps
CPU time 15.58 seconds
Started Mar 21 01:04:14 PM PDT 24
Finished Mar 21 01:04:35 PM PDT 24
Peak memory 200308 kb
Host smart-1156b7f8-095d-4ddb-a189-bfa7f6ed1fb0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637476053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2637476053
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.1473735687
Short name T518
Test name
Test status
Simulation time 143868533 ps
CPU time 7.93 seconds
Started Mar 21 01:04:17 PM PDT 24
Finished Mar 21 01:04:29 PM PDT 24
Peak memory 200328 kb
Host smart-8f6b6455-6930-4c57-a201-b5418c52d142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473735687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1473735687
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2463009817
Short name T368
Test name
Test status
Simulation time 188626802 ps
CPU time 1.76 seconds
Started Mar 21 01:04:30 PM PDT 24
Finished Mar 21 01:04:34 PM PDT 24
Peak memory 200364 kb
Host smart-a5d78f01-7698-4497-b1c2-a44b95335a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463009817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2463009817
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.15884425
Short name T161
Test name
Test status
Simulation time 59490335 ps
CPU time 1.25 seconds
Started Mar 21 01:04:16 PM PDT 24
Finished Mar 21 01:04:22 PM PDT 24
Peak memory 200164 kb
Host smart-9fa7eeb6-1714-4b72-9f0c-cbc73d2368c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15884425 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.hmac_test_hmac_vectors.15884425
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.3898194490
Short name T503
Test name
Test status
Simulation time 45042063905 ps
CPU time 453.32 seconds
Started Mar 21 01:04:24 PM PDT 24
Finished Mar 21 01:11:58 PM PDT 24
Peak memory 200328 kb
Host smart-1d5f4ac6-5824-4b66-959f-3079946e50a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898194490 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.3898194490
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.846711994
Short name T599
Test name
Test status
Simulation time 660411855 ps
CPU time 33.13 seconds
Started Mar 21 01:04:30 PM PDT 24
Finished Mar 21 01:05:05 PM PDT 24
Peak memory 200320 kb
Host smart-7e31eb7a-36ae-4bf4-9efc-d166de41800f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846711994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.846711994
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.864734189
Short name T187
Test name
Test status
Simulation time 12396610 ps
CPU time 0.64 seconds
Started Mar 21 01:04:33 PM PDT 24
Finished Mar 21 01:04:34 PM PDT 24
Peak memory 195860 kb
Host smart-d80849e8-9f8e-4688-bcf7-b6f7ea9937c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864734189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.864734189
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.951831335
Short name T46
Test name
Test status
Simulation time 31723398 ps
CPU time 1.59 seconds
Started Mar 21 01:04:18 PM PDT 24
Finished Mar 21 01:04:23 PM PDT 24
Peak memory 200320 kb
Host smart-6024282b-a0a6-43de-ae08-ca228dc56ee8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=951831335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.951831335
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.961404108
Short name T434
Test name
Test status
Simulation time 868996060 ps
CPU time 42.29 seconds
Started Mar 21 01:04:24 PM PDT 24
Finished Mar 21 01:05:07 PM PDT 24
Peak memory 200380 kb
Host smart-8ff15d4c-0f67-4323-8112-b78442c24a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961404108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.961404108
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1652877968
Short name T53
Test name
Test status
Simulation time 7820917771 ps
CPU time 117.66 seconds
Started Mar 21 01:04:17 PM PDT 24
Finished Mar 21 01:06:19 PM PDT 24
Peak memory 200436 kb
Host smart-faf379c2-6048-45e0-abe0-23521a7dd5a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1652877968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1652877968
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.4168572106
Short name T362
Test name
Test status
Simulation time 19284754197 ps
CPU time 43.25 seconds
Started Mar 21 01:04:27 PM PDT 24
Finished Mar 21 01:05:11 PM PDT 24
Peak memory 200376 kb
Host smart-f81ec8c7-b342-447c-b928-3a6a78072f82
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168572106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.4168572106
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.464381890
Short name T25
Test name
Test status
Simulation time 29190541556 ps
CPU time 142.56 seconds
Started Mar 21 01:04:27 PM PDT 24
Finished Mar 21 01:06:50 PM PDT 24
Peak memory 200396 kb
Host smart-be692991-b732-4a29-aa0e-537f91d79560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464381890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.464381890
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3548517460
Short name T82
Test name
Test status
Simulation time 462517588 ps
CPU time 5.54 seconds
Started Mar 21 01:04:27 PM PDT 24
Finished Mar 21 01:04:33 PM PDT 24
Peak memory 200340 kb
Host smart-1ae63f16-8844-45d9-89f6-34ed5aa0e97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548517460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3548517460
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.353663333
Short name T426
Test name
Test status
Simulation time 18873494652 ps
CPU time 914.27 seconds
Started Mar 21 01:04:07 PM PDT 24
Finished Mar 21 01:19:22 PM PDT 24
Peak memory 237816 kb
Host smart-0e0d9622-5f65-4b9a-9268-fff9c6dc346d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353663333 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.353663333
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.2826680772
Short name T349
Test name
Test status
Simulation time 85677899 ps
CPU time 1.05 seconds
Started Mar 21 01:04:27 PM PDT 24
Finished Mar 21 01:04:28 PM PDT 24
Peak memory 200100 kb
Host smart-f490505d-7c7a-4e7b-8a74-766e0e19d5ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826680772 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.2826680772
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.2187947164
Short name T371
Test name
Test status
Simulation time 59451869256 ps
CPU time 547.84 seconds
Started Mar 21 01:04:27 PM PDT 24
Finished Mar 21 01:13:35 PM PDT 24
Peak memory 200364 kb
Host smart-3d13982a-b6ea-495c-bd89-3f7c5f2bf1fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187947164 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.2187947164
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.2960115778
Short name T200
Test name
Test status
Simulation time 2458909509 ps
CPU time 26.87 seconds
Started Mar 21 01:04:28 PM PDT 24
Finished Mar 21 01:04:56 PM PDT 24
Peak memory 200672 kb
Host smart-34381715-f53f-469f-8cfe-14347b9ccbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960115778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2960115778
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2540057802
Short name T339
Test name
Test status
Simulation time 15449451 ps
CPU time 0.6 seconds
Started Mar 21 01:04:31 PM PDT 24
Finished Mar 21 01:04:33 PM PDT 24
Peak memory 195156 kb
Host smart-27223b0f-9236-473d-825d-ceb6cc83350a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540057802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2540057802
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3985712189
Short name T48
Test name
Test status
Simulation time 2565464050 ps
CPU time 44.23 seconds
Started Mar 21 01:04:27 PM PDT 24
Finished Mar 21 01:05:12 PM PDT 24
Peak memory 216824 kb
Host smart-1531d625-01f3-44c1-8865-2fbc58472577
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3985712189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3985712189
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.630728578
Short name T129
Test name
Test status
Simulation time 2771834614 ps
CPU time 43.35 seconds
Started Mar 21 01:04:33 PM PDT 24
Finished Mar 21 01:05:17 PM PDT 24
Peak memory 200472 kb
Host smart-ed0450c7-309d-4992-9f12-7ed67c9db817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630728578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.630728578
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3173506835
Short name T102
Test name
Test status
Simulation time 4274188017 ps
CPU time 66.15 seconds
Started Mar 21 01:04:33 PM PDT 24
Finished Mar 21 01:05:39 PM PDT 24
Peak memory 200432 kb
Host smart-e24c882b-d095-4b93-9cd2-6617aee9e13c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3173506835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3173506835
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1385489393
Short name T169
Test name
Test status
Simulation time 83742046 ps
CPU time 4.07 seconds
Started Mar 21 01:04:28 PM PDT 24
Finished Mar 21 01:04:32 PM PDT 24
Peak memory 200352 kb
Host smart-ec9672ad-bab8-46ed-8d20-43c312bbb572
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385489393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1385489393
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.496740267
Short name T280
Test name
Test status
Simulation time 1648403460 ps
CPU time 94.21 seconds
Started Mar 21 01:04:28 PM PDT 24
Finished Mar 21 01:06:02 PM PDT 24
Peak memory 200420 kb
Host smart-05698354-75f7-42b0-9855-aa152ddb3810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496740267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.496740267
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3686536196
Short name T195
Test name
Test status
Simulation time 47469728 ps
CPU time 1.21 seconds
Started Mar 21 01:04:30 PM PDT 24
Finished Mar 21 01:04:31 PM PDT 24
Peak memory 200396 kb
Host smart-c8761e63-ff8f-4df8-bbd2-61657d7819f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686536196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3686536196
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.2027248935
Short name T500
Test name
Test status
Simulation time 29706099891 ps
CPU time 544.65 seconds
Started Mar 21 01:04:33 PM PDT 24
Finished Mar 21 01:13:38 PM PDT 24
Peak memory 200524 kb
Host smart-32edf465-dd7c-44dd-a726-12929206b5b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027248935 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2027248935
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.975486635
Short name T273
Test name
Test status
Simulation time 63042754 ps
CPU time 1.27 seconds
Started Mar 21 01:04:31 PM PDT 24
Finished Mar 21 01:04:33 PM PDT 24
Peak memory 200336 kb
Host smart-9a4ef5fa-937a-4803-91e6-958b802aba4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975486635 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.hmac_test_hmac_vectors.975486635
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.775047267
Short name T255
Test name
Test status
Simulation time 52664397775 ps
CPU time 503.25 seconds
Started Mar 21 01:04:30 PM PDT 24
Finished Mar 21 01:12:55 PM PDT 24
Peak memory 200416 kb
Host smart-4c63decf-abcd-46d7-8607-5b6f58014d40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775047267 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.775047267
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2060159323
Short name T275
Test name
Test status
Simulation time 10505312908 ps
CPU time 79.29 seconds
Started Mar 21 01:04:31 PM PDT 24
Finished Mar 21 01:05:51 PM PDT 24
Peak memory 200172 kb
Host smart-1d175d05-9f4c-4a37-abfa-0dc11b561183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060159323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2060159323
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.91432975
Short name T241
Test name
Test status
Simulation time 52928213 ps
CPU time 0.57 seconds
Started Mar 21 01:04:28 PM PDT 24
Finished Mar 21 01:04:29 PM PDT 24
Peak memory 195520 kb
Host smart-04673ea4-94a6-48e3-ad37-75ab4d2db74f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91432975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.91432975
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1250852544
Short name T545
Test name
Test status
Simulation time 1555599818 ps
CPU time 58.77 seconds
Started Mar 21 01:04:34 PM PDT 24
Finished Mar 21 01:05:33 PM PDT 24
Peak memory 219384 kb
Host smart-2fed2585-4460-4a0e-bfcd-303b519aaebf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1250852544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1250852544
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3743114275
Short name T243
Test name
Test status
Simulation time 2156778159 ps
CPU time 35.7 seconds
Started Mar 21 01:04:33 PM PDT 24
Finished Mar 21 01:05:09 PM PDT 24
Peak memory 200408 kb
Host smart-9b4aa3ea-e915-4a16-ba6e-a4710ca0ac56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743114275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3743114275
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2112688527
Short name T202
Test name
Test status
Simulation time 1525693822 ps
CPU time 93.1 seconds
Started Mar 21 01:04:28 PM PDT 24
Finished Mar 21 01:06:01 PM PDT 24
Peak memory 200404 kb
Host smart-92ee511e-f311-445d-bb34-8a7927178e50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2112688527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2112688527
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.2732454182
Short name T311
Test name
Test status
Simulation time 103640643920 ps
CPU time 253.43 seconds
Started Mar 21 01:04:29 PM PDT 24
Finished Mar 21 01:08:42 PM PDT 24
Peak memory 200412 kb
Host smart-ccff6fe7-4c07-4c6f-b952-5003a2c42269
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732454182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2732454182
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1792343842
Short name T461
Test name
Test status
Simulation time 2272907537 ps
CPU time 69.85 seconds
Started Mar 21 01:04:34 PM PDT 24
Finished Mar 21 01:05:44 PM PDT 24
Peak memory 200444 kb
Host smart-a070a890-9742-42bd-9376-337eeeb4c258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792343842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1792343842
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.1669532991
Short name T492
Test name
Test status
Simulation time 1651803453 ps
CPU time 7.2 seconds
Started Mar 21 01:04:29 PM PDT 24
Finished Mar 21 01:04:36 PM PDT 24
Peak memory 200348 kb
Host smart-2acde8bd-8306-4a68-92f8-dc2fedfb72f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669532991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.1669532991
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.2868705589
Short name T433
Test name
Test status
Simulation time 35549400553 ps
CPU time 920.34 seconds
Started Mar 21 01:04:30 PM PDT 24
Finished Mar 21 01:19:52 PM PDT 24
Peak memory 248836 kb
Host smart-6a1fe89b-3821-4b00-b577-e9beeda86aa7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868705589 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2868705589
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.335848988
Short name T216
Test name
Test status
Simulation time 110092617 ps
CPU time 1.27 seconds
Started Mar 21 01:04:31 PM PDT 24
Finished Mar 21 01:04:33 PM PDT 24
Peak memory 200412 kb
Host smart-4a50a2dc-c145-4791-93ab-15700c426a3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335848988 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_hmac_vectors.335848988
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.1384988770
Short name T301
Test name
Test status
Simulation time 31213168555 ps
CPU time 443.36 seconds
Started Mar 21 01:04:24 PM PDT 24
Finished Mar 21 01:11:48 PM PDT 24
Peak memory 200360 kb
Host smart-caa91299-a4bc-4be5-a618-d6d825c1eb5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384988770 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.1384988770
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.3409544451
Short name T305
Test name
Test status
Simulation time 12717235011 ps
CPU time 85.84 seconds
Started Mar 21 01:04:29 PM PDT 24
Finished Mar 21 01:05:56 PM PDT 24
Peak memory 200452 kb
Host smart-2c572b9a-8356-4988-aa26-7004ebb90eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409544451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3409544451
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3537602955
Short name T156
Test name
Test status
Simulation time 34867944 ps
CPU time 0.58 seconds
Started Mar 21 01:04:27 PM PDT 24
Finished Mar 21 01:04:28 PM PDT 24
Peak memory 195744 kb
Host smart-431d9ce6-e611-471c-b739-00307b116d55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537602955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3537602955
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.2252987856
Short name T247
Test name
Test status
Simulation time 1664128112 ps
CPU time 67.77 seconds
Started Mar 21 01:04:28 PM PDT 24
Finished Mar 21 01:05:36 PM PDT 24
Peak memory 230016 kb
Host smart-ad2c6d8d-743c-4899-9a3c-7ee167c44177
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2252987856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2252987856
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1622499709
Short name T175
Test name
Test status
Simulation time 4377744596 ps
CPU time 35.12 seconds
Started Mar 21 01:04:30 PM PDT 24
Finished Mar 21 01:05:07 PM PDT 24
Peak memory 200440 kb
Host smart-35ffadc7-3e6e-44c1-bdd5-fd4629a37335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622499709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1622499709
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3865766351
Short name T585
Test name
Test status
Simulation time 1569867490 ps
CPU time 95.26 seconds
Started Mar 21 01:04:28 PM PDT 24
Finished Mar 21 01:06:04 PM PDT 24
Peak memory 200456 kb
Host smart-0167de88-da3d-469a-ab10-51b007215c2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3865766351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3865766351
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1097924910
Short name T375
Test name
Test status
Simulation time 56628587394 ps
CPU time 142.89 seconds
Started Mar 21 01:04:29 PM PDT 24
Finished Mar 21 01:06:52 PM PDT 24
Peak memory 200404 kb
Host smart-bf9f4afa-2478-47b6-b57d-c854e6f7913f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097924910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1097924910
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.1852922245
Short name T38
Test name
Test status
Simulation time 1903146618 ps
CPU time 27.99 seconds
Started Mar 21 01:04:33 PM PDT 24
Finished Mar 21 01:05:01 PM PDT 24
Peak memory 200368 kb
Host smart-e2dd0317-b834-4791-9b29-7be517eaf6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852922245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1852922245
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2534378912
Short name T262
Test name
Test status
Simulation time 127354248 ps
CPU time 4.2 seconds
Started Mar 21 01:04:32 PM PDT 24
Finished Mar 21 01:04:37 PM PDT 24
Peak memory 200344 kb
Host smart-87816262-80c4-430f-9704-7843e4bf0a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534378912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2534378912
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.362156814
Short name T76
Test name
Test status
Simulation time 63006208376 ps
CPU time 908.09 seconds
Started Mar 21 01:04:31 PM PDT 24
Finished Mar 21 01:19:40 PM PDT 24
Peak memory 200404 kb
Host smart-591fe697-0eba-4971-af90-c48e214763b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362156814 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.362156814
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.92780041
Short name T558
Test name
Test status
Simulation time 33508475 ps
CPU time 1.24 seconds
Started Mar 21 01:04:28 PM PDT 24
Finished Mar 21 01:04:30 PM PDT 24
Peak memory 200304 kb
Host smart-96c5c0d6-3e94-48db-98da-df005c8a5521
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92780041 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.hmac_test_hmac_vectors.92780041
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.3972841121
Short name T402
Test name
Test status
Simulation time 359983663826 ps
CPU time 493.91 seconds
Started Mar 21 01:04:32 PM PDT 24
Finished Mar 21 01:12:46 PM PDT 24
Peak memory 200396 kb
Host smart-b989c81a-33a7-4e02-a277-0fef53510e57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972841121 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.3972841121
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.437991436
Short name T308
Test name
Test status
Simulation time 53219701 ps
CPU time 0.76 seconds
Started Mar 21 01:04:30 PM PDT 24
Finished Mar 21 01:04:33 PM PDT 24
Peak memory 197652 kb
Host smart-0b25c1b5-c13b-4a03-a35e-5e4395ae8b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437991436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.437991436
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.4137457061
Short name T17
Test name
Test status
Simulation time 22677030 ps
CPU time 0.56 seconds
Started Mar 21 01:04:29 PM PDT 24
Finished Mar 21 01:04:30 PM PDT 24
Peak memory 195748 kb
Host smart-7ff5639c-fd1a-4b58-9942-ac46677d2519
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137457061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.4137457061
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.159280291
Short name T278
Test name
Test status
Simulation time 994756489 ps
CPU time 9.19 seconds
Started Mar 21 01:04:29 PM PDT 24
Finished Mar 21 01:04:39 PM PDT 24
Peak memory 215964 kb
Host smart-055face9-bdb4-41f5-b8f8-1d30c7724b02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=159280291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.159280291
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1654203229
Short name T310
Test name
Test status
Simulation time 1259826201 ps
CPU time 26.4 seconds
Started Mar 21 01:04:31 PM PDT 24
Finished Mar 21 01:04:59 PM PDT 24
Peak memory 200616 kb
Host smart-829ed4b3-be85-4591-9c7b-c2fd57030349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654203229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1654203229
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2195870234
Short name T391
Test name
Test status
Simulation time 1285172017 ps
CPU time 38.58 seconds
Started Mar 21 01:04:32 PM PDT 24
Finished Mar 21 01:05:11 PM PDT 24
Peak memory 200364 kb
Host smart-22742979-cdc0-4ef3-9bac-011d880aa5d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2195870234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2195870234
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1471173537
Short name T578
Test name
Test status
Simulation time 4150895922 ps
CPU time 35.46 seconds
Started Mar 21 01:04:37 PM PDT 24
Finished Mar 21 01:05:13 PM PDT 24
Peak memory 200492 kb
Host smart-4ef7975b-f3a8-487c-8c02-80545917a409
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471173537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1471173537
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.387511415
Short name T290
Test name
Test status
Simulation time 5872699004 ps
CPU time 106.45 seconds
Started Mar 21 01:04:32 PM PDT 24
Finished Mar 21 01:06:19 PM PDT 24
Peak memory 200420 kb
Host smart-384542e6-dc3e-4459-894f-0bbc06cd0948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387511415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.387511415
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.1037934245
Short name T574
Test name
Test status
Simulation time 87696289 ps
CPU time 2.79 seconds
Started Mar 21 01:04:30 PM PDT 24
Finished Mar 21 01:04:32 PM PDT 24
Peak memory 200388 kb
Host smart-dd3a4ca0-74ec-4ddb-987b-3e3a924b3746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037934245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1037934245
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2348242381
Short name T379
Test name
Test status
Simulation time 31075786053 ps
CPU time 1666.31 seconds
Started Mar 21 01:04:35 PM PDT 24
Finished Mar 21 01:32:22 PM PDT 24
Peak memory 216844 kb
Host smart-d54fefcd-06b6-4be6-a7b1-09e7ef58b1fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348242381 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2348242381
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.766252492
Short name T209
Test name
Test status
Simulation time 44098033 ps
CPU time 1.08 seconds
Started Mar 21 01:04:31 PM PDT 24
Finished Mar 21 01:04:33 PM PDT 24
Peak memory 199856 kb
Host smart-c8573a0c-87b1-409e-a94f-0d677b2fa7b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766252492 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_hmac_vectors.766252492
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.2055057749
Short name T473
Test name
Test status
Simulation time 42516505458 ps
CPU time 433.25 seconds
Started Mar 21 01:04:33 PM PDT 24
Finished Mar 21 01:11:47 PM PDT 24
Peak memory 200344 kb
Host smart-f2a07487-aa43-4e72-88d0-22b6add5d57d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055057749 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.2055057749
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2278931708
Short name T306
Test name
Test status
Simulation time 4938022168 ps
CPU time 88.58 seconds
Started Mar 21 01:04:35 PM PDT 24
Finished Mar 21 01:06:04 PM PDT 24
Peak memory 200452 kb
Host smart-db71a759-4f7c-470e-9782-520166cdf782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278931708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2278931708
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.1406710232
Short name T83
Test name
Test status
Simulation time 39810199 ps
CPU time 0.58 seconds
Started Mar 21 01:04:28 PM PDT 24
Finished Mar 21 01:04:29 PM PDT 24
Peak memory 194732 kb
Host smart-7db3206e-afcd-4a28-9428-e449accce950
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406710232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1406710232
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3684690532
Short name T47
Test name
Test status
Simulation time 1780311414 ps
CPU time 62.11 seconds
Started Mar 21 01:04:34 PM PDT 24
Finished Mar 21 01:05:37 PM PDT 24
Peak memory 233032 kb
Host smart-4b54c589-3fe1-4577-9ec4-7a485f723aca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3684690532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3684690532
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1893659721
Short name T337
Test name
Test status
Simulation time 14018089388 ps
CPU time 55.99 seconds
Started Mar 21 01:04:33 PM PDT 24
Finished Mar 21 01:05:29 PM PDT 24
Peak memory 200416 kb
Host smart-1ce8b7ea-8f7b-4b3f-9a3f-479948c11bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893659721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1893659721
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3116240828
Short name T240
Test name
Test status
Simulation time 1699455776 ps
CPU time 49.02 seconds
Started Mar 21 01:04:34 PM PDT 24
Finished Mar 21 01:05:24 PM PDT 24
Peak memory 200540 kb
Host smart-855536ee-27b3-4a39-bd12-a751580b0315
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3116240828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3116240828
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2009190465
Short name T521
Test name
Test status
Simulation time 57060766 ps
CPU time 0.84 seconds
Started Mar 21 01:04:40 PM PDT 24
Finished Mar 21 01:04:42 PM PDT 24
Peak memory 197544 kb
Host smart-9413cdfa-cde4-4e6c-858b-bcf5c5f004df
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009190465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2009190465
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.137950365
Short name T549
Test name
Test status
Simulation time 702937503 ps
CPU time 10.27 seconds
Started Mar 21 01:04:32 PM PDT 24
Finished Mar 21 01:04:43 PM PDT 24
Peak memory 200392 kb
Host smart-6f51e26f-1820-40c3-9af6-21db66c8a800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137950365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.137950365
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1135615478
Short name T487
Test name
Test status
Simulation time 2178775457 ps
CPU time 6.37 seconds
Started Mar 21 01:04:38 PM PDT 24
Finished Mar 21 01:04:47 PM PDT 24
Peak memory 200440 kb
Host smart-8ac63fc9-9ac7-4034-ba17-4ab7d15907cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135615478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1135615478
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3227171281
Short name T582
Test name
Test status
Simulation time 12831810387 ps
CPU time 713.58 seconds
Started Mar 21 01:04:33 PM PDT 24
Finished Mar 21 01:16:27 PM PDT 24
Peak memory 224988 kb
Host smart-2644a448-e2b5-40af-be62-7ba9d7d579a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227171281 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3227171281
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.3534761087
Short name T526
Test name
Test status
Simulation time 214098485 ps
CPU time 1.22 seconds
Started Mar 21 01:04:34 PM PDT 24
Finished Mar 21 01:04:36 PM PDT 24
Peak memory 200436 kb
Host smart-343c988a-6a9b-4e42-af7c-c54566bebc1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534761087 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.3534761087
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.3891466567
Short name T493
Test name
Test status
Simulation time 247793040901 ps
CPU time 491.79 seconds
Started Mar 21 01:04:30 PM PDT 24
Finished Mar 21 01:12:44 PM PDT 24
Peak memory 200312 kb
Host smart-e3c45e89-b8b1-4fe4-9194-915e25e6a925
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891466567 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.3891466567
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.70205143
Short name T485
Test name
Test status
Simulation time 31782818309 ps
CPU time 72.02 seconds
Started Mar 21 01:04:38 PM PDT 24
Finished Mar 21 01:05:53 PM PDT 24
Peak memory 200476 kb
Host smart-561bd1e9-a004-44b9-bda6-e87c035fce2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70205143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.70205143
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2326848290
Short name T451
Test name
Test status
Simulation time 48807902 ps
CPU time 0.6 seconds
Started Mar 21 01:04:40 PM PDT 24
Finished Mar 21 01:04:42 PM PDT 24
Peak memory 195868 kb
Host smart-c0029bd7-eceb-4a79-8ed6-d4733210a607
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326848290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2326848290
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3759802837
Short name T272
Test name
Test status
Simulation time 14132900961 ps
CPU time 76.86 seconds
Started Mar 21 01:04:39 PM PDT 24
Finished Mar 21 01:05:58 PM PDT 24
Peak memory 225160 kb
Host smart-ee977c2b-ab2c-4878-acfb-74ea651cc92d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3759802837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3759802837
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.475000134
Short name T279
Test name
Test status
Simulation time 2825023880 ps
CPU time 11.24 seconds
Started Mar 21 01:04:41 PM PDT 24
Finished Mar 21 01:04:53 PM PDT 24
Peak memory 200432 kb
Host smart-a48423d8-15ce-4934-b9f4-52958c7e395c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475000134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.475000134
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.748935523
Short name T120
Test name
Test status
Simulation time 2131080777 ps
CPU time 125.13 seconds
Started Mar 21 01:04:46 PM PDT 24
Finished Mar 21 01:06:52 PM PDT 24
Peak memory 200404 kb
Host smart-47ce6389-a5bd-4ba6-9aa3-be3bb9182f0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=748935523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.748935523
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1339050894
Short name T596
Test name
Test status
Simulation time 6581308424 ps
CPU time 60.37 seconds
Started Mar 21 01:04:38 PM PDT 24
Finished Mar 21 01:05:41 PM PDT 24
Peak memory 200464 kb
Host smart-319cfae8-d966-4008-b6bf-7dd8e47b17b7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339050894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1339050894
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.6884996
Short name T155
Test name
Test status
Simulation time 8500472950 ps
CPU time 113.59 seconds
Started Mar 21 01:04:47 PM PDT 24
Finished Mar 21 01:06:41 PM PDT 24
Peak memory 200384 kb
Host smart-6106eb40-1545-42be-9f14-c80e84020c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6884996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.6884996
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1072710366
Short name T460
Test name
Test status
Simulation time 814609354 ps
CPU time 6.04 seconds
Started Mar 21 01:04:28 PM PDT 24
Finished Mar 21 01:04:35 PM PDT 24
Peak memory 200500 kb
Host smart-bd988376-050f-40f9-8402-0fd1e8e3f549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072710366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1072710366
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.2206339713
Short name T104
Test name
Test status
Simulation time 13356999465 ps
CPU time 322.55 seconds
Started Mar 21 01:04:41 PM PDT 24
Finished Mar 21 01:10:03 PM PDT 24
Peak memory 238916 kb
Host smart-114ba71e-a96c-46af-8b2c-e8363bee4ff9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206339713 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2206339713
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.3815101086
Short name T271
Test name
Test status
Simulation time 45963611 ps
CPU time 1.1 seconds
Started Mar 21 01:04:43 PM PDT 24
Finished Mar 21 01:04:45 PM PDT 24
Peak memory 199788 kb
Host smart-9c8c2bad-b26d-4b0c-b91b-0261a1da9b66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815101086 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.3815101086
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.1922676220
Short name T143
Test name
Test status
Simulation time 7270220693 ps
CPU time 389.26 seconds
Started Mar 21 01:04:38 PM PDT 24
Finished Mar 21 01:11:10 PM PDT 24
Peak memory 200332 kb
Host smart-f918daed-acc4-4c54-a410-ec7f97ff2828
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922676220 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.1922676220
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3825245560
Short name T3
Test name
Test status
Simulation time 3284039306 ps
CPU time 57.65 seconds
Started Mar 21 01:04:42 PM PDT 24
Finished Mar 21 01:05:41 PM PDT 24
Peak memory 200280 kb
Host smart-930483c9-7b81-46c0-a296-ecba77ec683b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825245560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3825245560
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.1258089134
Short name T459
Test name
Test status
Simulation time 72048123 ps
CPU time 0.6 seconds
Started Mar 21 01:03:44 PM PDT 24
Finished Mar 21 01:03:45 PM PDT 24
Peak memory 195484 kb
Host smart-16f42a84-c61f-4f63-a9b4-8f9059071a30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258089134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1258089134
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.2030587190
Short name T384
Test name
Test status
Simulation time 361054564 ps
CPU time 13.03 seconds
Started Mar 21 01:03:36 PM PDT 24
Finished Mar 21 01:03:50 PM PDT 24
Peak memory 200328 kb
Host smart-dec379fb-7791-4d23-b30a-d28a67296fd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2030587190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2030587190
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2975998734
Short name T36
Test name
Test status
Simulation time 7857469586 ps
CPU time 44.86 seconds
Started Mar 21 01:03:34 PM PDT 24
Finished Mar 21 01:04:19 PM PDT 24
Peak memory 200436 kb
Host smart-0e78e1c7-ec3d-4686-b239-ff69a547b657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975998734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2975998734
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2868219856
Short name T296
Test name
Test status
Simulation time 6621097743 ps
CPU time 93.22 seconds
Started Mar 21 01:03:39 PM PDT 24
Finished Mar 21 01:05:13 PM PDT 24
Peak memory 200468 kb
Host smart-6db0fcd5-762e-4522-82d2-439c51bc7d10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2868219856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2868219856
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1811609648
Short name T302
Test name
Test status
Simulation time 4078322556 ps
CPU time 226.6 seconds
Started Mar 21 01:03:39 PM PDT 24
Finished Mar 21 01:07:26 PM PDT 24
Peak memory 199724 kb
Host smart-f9feb0d3-a87a-4ac8-a528-b7d943b2b88a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811609648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1811609648
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1536124588
Short name T285
Test name
Test status
Simulation time 790236057 ps
CPU time 45.74 seconds
Started Mar 21 01:03:37 PM PDT 24
Finished Mar 21 01:04:23 PM PDT 24
Peak memory 200360 kb
Host smart-b39dd4f6-5e70-4498-9273-29326ff6ce8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536124588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1536124588
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.784187443
Short name T30
Test name
Test status
Simulation time 69477516 ps
CPU time 0.94 seconds
Started Mar 21 01:03:35 PM PDT 24
Finished Mar 21 01:03:37 PM PDT 24
Peak memory 218756 kb
Host smart-7307d4c3-ed3d-4482-9f50-a5ce63d4264c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784187443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.784187443
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.279490660
Short name T370
Test name
Test status
Simulation time 914481444 ps
CPU time 3.68 seconds
Started Mar 21 01:03:36 PM PDT 24
Finished Mar 21 01:03:41 PM PDT 24
Peak memory 200500 kb
Host smart-3aed90e2-a772-432d-9347-5ba423768e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279490660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.279490660
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1712998591
Short name T422
Test name
Test status
Simulation time 55285307670 ps
CPU time 978.35 seconds
Started Mar 21 01:03:43 PM PDT 24
Finished Mar 21 01:20:01 PM PDT 24
Peak memory 200396 kb
Host smart-3f18f1cb-8555-4b60-8c25-02a62ba03ce6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712998591 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1712998591
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.1505460140
Short name T121
Test name
Test status
Simulation time 153513598 ps
CPU time 1.02 seconds
Started Mar 21 01:03:36 PM PDT 24
Finished Mar 21 01:03:38 PM PDT 24
Peak memory 198520 kb
Host smart-5b6a31e0-9fe9-4a26-8d28-a8ad29f1883d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505460140 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.1505460140
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.4081573566
Short name T250
Test name
Test status
Simulation time 27397713492 ps
CPU time 488.82 seconds
Started Mar 21 01:03:36 PM PDT 24
Finished Mar 21 01:11:45 PM PDT 24
Peak memory 200496 kb
Host smart-146c6d77-fadd-4a17-bd4b-a4e4d3874973
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081573566 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.4081573566
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.4252785839
Short name T325
Test name
Test status
Simulation time 2378249325 ps
CPU time 34.09 seconds
Started Mar 21 01:03:44 PM PDT 24
Finished Mar 21 01:04:19 PM PDT 24
Peak memory 200492 kb
Host smart-eff8542c-d1df-4170-bcdd-927ae371d770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252785839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.4252785839
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.4162686674
Short name T417
Test name
Test status
Simulation time 14448825 ps
CPU time 0.61 seconds
Started Mar 21 01:04:44 PM PDT 24
Finished Mar 21 01:04:45 PM PDT 24
Peak memory 195828 kb
Host smart-ab68a2e4-4136-4148-8ef7-f2c50ee7f084
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162686674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.4162686674
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.3861578297
Short name T270
Test name
Test status
Simulation time 1045905528 ps
CPU time 37.56 seconds
Started Mar 21 01:04:40 PM PDT 24
Finished Mar 21 01:05:18 PM PDT 24
Peak memory 216704 kb
Host smart-56b365c6-3305-4078-a9f6-772d69f61348
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3861578297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3861578297
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.166329028
Short name T456
Test name
Test status
Simulation time 6115819993 ps
CPU time 34.57 seconds
Started Mar 21 01:04:37 PM PDT 24
Finished Mar 21 01:05:11 PM PDT 24
Peak memory 200484 kb
Host smart-19b7116e-ff60-46e0-8605-c629c1953ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166329028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.166329028
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.2975660388
Short name T369
Test name
Test status
Simulation time 625738109 ps
CPU time 8.91 seconds
Started Mar 21 01:04:56 PM PDT 24
Finished Mar 21 01:05:05 PM PDT 24
Peak memory 200344 kb
Host smart-4cad3819-331c-4dd9-bb97-77a104c63e84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2975660388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2975660388
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.603066660
Short name T21
Test name
Test status
Simulation time 1904208207 ps
CPU time 52.71 seconds
Started Mar 21 01:04:43 PM PDT 24
Finished Mar 21 01:05:36 PM PDT 24
Peak memory 200400 kb
Host smart-424f90fc-b571-4f6b-8628-eccdf38e84b9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603066660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.603066660
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.1091703295
Short name T203
Test name
Test status
Simulation time 748819434 ps
CPU time 11.98 seconds
Started Mar 21 01:04:56 PM PDT 24
Finished Mar 21 01:05:09 PM PDT 24
Peak memory 200292 kb
Host smart-8e8da2e8-f69c-45d5-96ef-82a1d9206b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091703295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1091703295
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1012330896
Short name T264
Test name
Test status
Simulation time 155592236 ps
CPU time 4.3 seconds
Started Mar 21 01:04:38 PM PDT 24
Finished Mar 21 01:04:45 PM PDT 24
Peak memory 200384 kb
Host smart-ffed156f-22f3-493b-b968-6110941a7f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012330896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1012330896
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1615233096
Short name T51
Test name
Test status
Simulation time 882966335 ps
CPU time 30.96 seconds
Started Mar 21 01:04:41 PM PDT 24
Finished Mar 21 01:05:12 PM PDT 24
Peak memory 200360 kb
Host smart-89535f2f-d417-4c85-9372-7885079d61c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615233096 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1615233096
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.3931410535
Short name T140
Test name
Test status
Simulation time 53123883 ps
CPU time 1.36 seconds
Started Mar 21 01:04:44 PM PDT 24
Finished Mar 21 01:04:46 PM PDT 24
Peak memory 200608 kb
Host smart-cc6e2979-e20c-4abd-9db9-14f3bf853b42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931410535 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.3931410535
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.766222956
Short name T323
Test name
Test status
Simulation time 36154059701 ps
CPU time 409.34 seconds
Started Mar 21 01:04:56 PM PDT 24
Finished Mar 21 01:11:46 PM PDT 24
Peak memory 200332 kb
Host smart-5fbd7cc6-9404-479d-961d-139e5639d263
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766222956 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.766222956
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2220280359
Short name T572
Test name
Test status
Simulation time 14065861591 ps
CPU time 19.52 seconds
Started Mar 21 01:04:42 PM PDT 24
Finished Mar 21 01:05:03 PM PDT 24
Peak memory 200400 kb
Host smart-b87e1146-79b0-407f-879b-5d519a5d1496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220280359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2220280359
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.715852108
Short name T291
Test name
Test status
Simulation time 158891710 ps
CPU time 0.61 seconds
Started Mar 21 01:04:56 PM PDT 24
Finished Mar 21 01:04:57 PM PDT 24
Peak memory 195796 kb
Host smart-57bae17d-f41d-4e3b-b3c3-da2d9267987c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715852108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.715852108
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.3922998397
Short name T220
Test name
Test status
Simulation time 617680095 ps
CPU time 5.01 seconds
Started Mar 21 01:04:40 PM PDT 24
Finished Mar 21 01:04:46 PM PDT 24
Peak memory 208604 kb
Host smart-38907637-972d-46af-a88b-bc97be00cbf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3922998397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.3922998397
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.203834248
Short name T490
Test name
Test status
Simulation time 1107425396 ps
CPU time 56.45 seconds
Started Mar 21 01:04:40 PM PDT 24
Finished Mar 21 01:05:38 PM PDT 24
Peak memory 200320 kb
Host smart-086e4e92-9b6e-4435-a0ce-605cd1bf25ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203834248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.203834248
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.4194454564
Short name T388
Test name
Test status
Simulation time 1784456768 ps
CPU time 105.88 seconds
Started Mar 21 01:04:56 PM PDT 24
Finished Mar 21 01:06:42 PM PDT 24
Peak memory 200344 kb
Host smart-4242a8fe-7c25-4570-8c8f-e6aa094929e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4194454564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.4194454564
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1916074385
Short name T354
Test name
Test status
Simulation time 55479490723 ps
CPU time 103.78 seconds
Started Mar 21 01:04:42 PM PDT 24
Finished Mar 21 01:06:27 PM PDT 24
Peak memory 200496 kb
Host smart-14e4f98a-b972-4388-b038-8f49844e45fe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916074385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1916074385
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3710214760
Short name T283
Test name
Test status
Simulation time 2573229940 ps
CPU time 52.02 seconds
Started Mar 21 01:04:43 PM PDT 24
Finished Mar 21 01:05:36 PM PDT 24
Peak memory 200436 kb
Host smart-7c7314b9-f27e-421b-80cb-f37b1ef1aab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710214760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3710214760
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.4264825118
Short name T588
Test name
Test status
Simulation time 24866532 ps
CPU time 0.82 seconds
Started Mar 21 01:04:39 PM PDT 24
Finished Mar 21 01:04:42 PM PDT 24
Peak memory 197408 kb
Host smart-03712d9a-8207-43b1-8b37-0df5263cea39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264825118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.4264825118
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.2706544485
Short name T15
Test name
Test status
Simulation time 13905154008 ps
CPU time 803.32 seconds
Started Mar 21 01:04:40 PM PDT 24
Finished Mar 21 01:18:04 PM PDT 24
Peak memory 234176 kb
Host smart-ce2611c9-4380-4d1a-89e2-1296e7c003bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706544485 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2706544485
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_stress_all_with_rand_reset.3696784712
Short name T494
Test name
Test status
Simulation time 49316290115 ps
CPU time 471.76 seconds
Started Mar 21 01:04:37 PM PDT 24
Finished Mar 21 01:12:33 PM PDT 24
Peak memory 216876 kb
Host smart-5c19c251-0a3a-440c-8b05-470881c41743
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3696784712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all_with_rand_reset.3696784712
Directory /workspace/41.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.806753494
Short name T231
Test name
Test status
Simulation time 184129160 ps
CPU time 1.23 seconds
Started Mar 21 01:04:45 PM PDT 24
Finished Mar 21 01:04:46 PM PDT 24
Peak memory 200324 kb
Host smart-a018f518-e0c9-43cf-9ecc-dc58aae3cc09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806753494 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.hmac_test_hmac_vectors.806753494
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.2972140688
Short name T479
Test name
Test status
Simulation time 77235473552 ps
CPU time 534.25 seconds
Started Mar 21 01:04:43 PM PDT 24
Finished Mar 21 01:13:38 PM PDT 24
Peak memory 200392 kb
Host smart-797cc553-b1a4-44a3-9537-1acb710a6ca9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972140688 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.2972140688
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.43189031
Short name T535
Test name
Test status
Simulation time 11096080431 ps
CPU time 39.26 seconds
Started Mar 21 01:04:47 PM PDT 24
Finished Mar 21 01:05:26 PM PDT 24
Peak memory 200484 kb
Host smart-59db243f-85ee-496e-a0f9-6d6040e2049a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43189031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.43189031
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.700428423
Short name T476
Test name
Test status
Simulation time 10750303 ps
CPU time 0.6 seconds
Started Mar 21 01:04:46 PM PDT 24
Finished Mar 21 01:04:47 PM PDT 24
Peak memory 194808 kb
Host smart-fc16415d-9791-4280-9512-8a2b6facfc72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700428423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.700428423
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1462656916
Short name T457
Test name
Test status
Simulation time 531747149 ps
CPU time 4.54 seconds
Started Mar 21 01:04:43 PM PDT 24
Finished Mar 21 01:04:48 PM PDT 24
Peak memory 216808 kb
Host smart-a43fa9f3-6fbf-4de4-abfb-61510bd4540a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1462656916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1462656916
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.4259932314
Short name T57
Test name
Test status
Simulation time 1209944743 ps
CPU time 6.71 seconds
Started Mar 21 01:04:42 PM PDT 24
Finished Mar 21 01:04:50 PM PDT 24
Peak memory 200388 kb
Host smart-750c3bd1-e42f-45e2-a74e-46642c0d7446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259932314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.4259932314
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.3022809794
Short name T69
Test name
Test status
Simulation time 3696519909 ps
CPU time 115.79 seconds
Started Mar 21 01:04:54 PM PDT 24
Finished Mar 21 01:06:51 PM PDT 24
Peak memory 200400 kb
Host smart-43e0f820-7492-4595-9df7-6334b886d463
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3022809794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3022809794
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.465948450
Short name T4
Test name
Test status
Simulation time 13712384802 ps
CPU time 185.58 seconds
Started Mar 21 01:04:43 PM PDT 24
Finished Mar 21 01:07:49 PM PDT 24
Peak memory 200392 kb
Host smart-195fb042-54c5-4f98-9215-3eb8348bc58e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465948450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.465948450
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.4130669935
Short name T424
Test name
Test status
Simulation time 21071199508 ps
CPU time 84.91 seconds
Started Mar 21 01:04:39 PM PDT 24
Finished Mar 21 01:06:06 PM PDT 24
Peak memory 200428 kb
Host smart-5672ad01-53fd-4a6e-88c6-bc460a64e450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130669935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.4130669935
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.95348819
Short name T506
Test name
Test status
Simulation time 270719141 ps
CPU time 2.32 seconds
Started Mar 21 01:04:43 PM PDT 24
Finished Mar 21 01:04:46 PM PDT 24
Peak memory 200204 kb
Host smart-7d2782e4-079e-437d-a2b2-31d25481c978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95348819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.95348819
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3518703630
Short name T45
Test name
Test status
Simulation time 64783896539 ps
CPU time 1266.04 seconds
Started Mar 21 01:04:56 PM PDT 24
Finished Mar 21 01:26:03 PM PDT 24
Peak memory 234204 kb
Host smart-d431e88e-a7f3-4393-8b87-cceb725b7753
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518703630 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3518703630
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.1397316334
Short name T182
Test name
Test status
Simulation time 372024691 ps
CPU time 1.36 seconds
Started Mar 21 01:04:39 PM PDT 24
Finished Mar 21 01:04:42 PM PDT 24
Peak memory 200368 kb
Host smart-6e5da0f1-f659-45fd-b898-9dfbf1bbf890
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397316334 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.1397316334
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.128437416
Short name T515
Test name
Test status
Simulation time 35698270815 ps
CPU time 468.73 seconds
Started Mar 21 01:04:44 PM PDT 24
Finished Mar 21 01:12:33 PM PDT 24
Peak memory 200340 kb
Host smart-e23bcf98-97a0-494b-839f-b8db02064bb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128437416 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.128437416
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3210270736
Short name T363
Test name
Test status
Simulation time 13485363547 ps
CPU time 48.15 seconds
Started Mar 21 01:04:41 PM PDT 24
Finished Mar 21 01:05:29 PM PDT 24
Peak memory 200436 kb
Host smart-63c4507a-9506-4b81-9e75-1d447943d411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210270736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3210270736
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.447360433
Short name T550
Test name
Test status
Simulation time 13454435 ps
CPU time 0.6 seconds
Started Mar 21 01:04:46 PM PDT 24
Finished Mar 21 01:04:47 PM PDT 24
Peak memory 195768 kb
Host smart-974c13e9-2d62-4d9e-9578-86533c30a861
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447360433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.447360433
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.4028535960
Short name T207
Test name
Test status
Simulation time 6130342343 ps
CPU time 51.09 seconds
Started Mar 21 01:04:52 PM PDT 24
Finished Mar 21 01:05:46 PM PDT 24
Peak memory 226968 kb
Host smart-abdbeadb-b5b2-4745-98b7-90d2729ed03f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4028535960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.4028535960
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2650393623
Short name T242
Test name
Test status
Simulation time 2607640305 ps
CPU time 63.91 seconds
Started Mar 21 01:04:48 PM PDT 24
Finished Mar 21 01:05:52 PM PDT 24
Peak memory 200400 kb
Host smart-7dc60c69-3312-4b77-91fd-831d24a9daa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650393623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2650393623
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.646339653
Short name T468
Test name
Test status
Simulation time 2625245958 ps
CPU time 110.21 seconds
Started Mar 21 01:04:51 PM PDT 24
Finished Mar 21 01:06:45 PM PDT 24
Peak memory 200376 kb
Host smart-1f924262-cf79-4d32-b966-0d3edbaf9e4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=646339653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.646339653
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.3834467505
Short name T597
Test name
Test status
Simulation time 7093198318 ps
CPU time 158.78 seconds
Started Mar 21 01:04:46 PM PDT 24
Finished Mar 21 01:07:24 PM PDT 24
Peak memory 200500 kb
Host smart-3284c9b7-da0d-4ef6-b5aa-1377ae699e39
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834467505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3834467505
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.2336834989
Short name T488
Test name
Test status
Simulation time 1188946689 ps
CPU time 76.14 seconds
Started Mar 21 01:04:47 PM PDT 24
Finished Mar 21 01:06:03 PM PDT 24
Peak memory 200408 kb
Host smart-38bfc013-98f6-476f-a048-c57e604e7efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336834989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2336834989
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.4061207392
Short name T373
Test name
Test status
Simulation time 408504818 ps
CPU time 6.79 seconds
Started Mar 21 01:04:38 PM PDT 24
Finished Mar 21 01:04:48 PM PDT 24
Peak memory 200380 kb
Host smart-b179eb8a-53f8-4c87-b44d-dca85bcfad4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061207392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.4061207392
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.9395125
Short name T75
Test name
Test status
Simulation time 1665836814514 ps
CPU time 2090.41 seconds
Started Mar 21 01:04:53 PM PDT 24
Finished Mar 21 01:39:46 PM PDT 24
Peak memory 200480 kb
Host smart-510ca892-f3dd-49fe-bc76-ef9a1d30109c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9395125 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.9395125
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.2315101418
Short name T258
Test name
Test status
Simulation time 60704131 ps
CPU time 1.3 seconds
Started Mar 21 01:04:46 PM PDT 24
Finished Mar 21 01:04:48 PM PDT 24
Peak memory 200280 kb
Host smart-910a2f5b-c50c-43e0-a2a8-63b4856f1e80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315101418 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.2315101418
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.740248409
Short name T408
Test name
Test status
Simulation time 8622033993 ps
CPU time 469.03 seconds
Started Mar 21 01:04:49 PM PDT 24
Finished Mar 21 01:12:38 PM PDT 24
Peak memory 200408 kb
Host smart-9a9d52c4-cc4b-40d6-a46c-053a27d644ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740248409 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.740248409
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.3816670453
Short name T19
Test name
Test status
Simulation time 1604425355 ps
CPU time 31.77 seconds
Started Mar 21 01:04:47 PM PDT 24
Finished Mar 21 01:05:19 PM PDT 24
Peak memory 200440 kb
Host smart-4aa998b2-36bb-4b2d-aaf7-aa229a53716a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816670453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3816670453
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2289407788
Short name T547
Test name
Test status
Simulation time 31495236 ps
CPU time 0.6 seconds
Started Mar 21 01:04:49 PM PDT 24
Finished Mar 21 01:04:50 PM PDT 24
Peak memory 194636 kb
Host smart-09f87203-c48b-4e6e-865f-73393566f489
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289407788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2289407788
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2692764122
Short name T577
Test name
Test status
Simulation time 81601395 ps
CPU time 1.73 seconds
Started Mar 21 01:04:48 PM PDT 24
Finished Mar 21 01:04:50 PM PDT 24
Peak memory 200408 kb
Host smart-d62360d3-d155-465a-9d47-9c4187cd85bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2692764122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2692764122
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3546470748
Short name T232
Test name
Test status
Simulation time 1305438942 ps
CPU time 57.59 seconds
Started Mar 21 01:04:47 PM PDT 24
Finished Mar 21 01:05:45 PM PDT 24
Peak memory 200340 kb
Host smart-7839f110-1670-4c48-853d-266e41693169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546470748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3546470748
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.3538814230
Short name T386
Test name
Test status
Simulation time 1658284261 ps
CPU time 98.51 seconds
Started Mar 21 01:04:51 PM PDT 24
Finished Mar 21 01:06:29 PM PDT 24
Peak memory 200384 kb
Host smart-9684125d-ba15-4077-af4e-1a9de04ddcb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3538814230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3538814230
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3325007363
Short name T131
Test name
Test status
Simulation time 1416147892 ps
CPU time 78.92 seconds
Started Mar 21 01:04:48 PM PDT 24
Finished Mar 21 01:06:07 PM PDT 24
Peak memory 200400 kb
Host smart-109a6f16-4e98-4682-a90e-6ec183dd24df
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325007363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3325007363
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.3513598607
Short name T228
Test name
Test status
Simulation time 2045559922 ps
CPU time 113.42 seconds
Started Mar 21 01:04:47 PM PDT 24
Finished Mar 21 01:06:41 PM PDT 24
Peak memory 200328 kb
Host smart-3bbbbe05-2974-461a-b093-a56002c8b1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513598607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3513598607
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.1025755854
Short name T564
Test name
Test status
Simulation time 82680318 ps
CPU time 1.03 seconds
Started Mar 21 01:04:47 PM PDT 24
Finished Mar 21 01:04:48 PM PDT 24
Peak memory 200124 kb
Host smart-04fa211a-6474-4ac5-ab02-0fc6f45622cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025755854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1025755854
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.429188269
Short name T430
Test name
Test status
Simulation time 81012241146 ps
CPU time 1088.81 seconds
Started Mar 21 01:04:47 PM PDT 24
Finished Mar 21 01:22:56 PM PDT 24
Peak memory 200492 kb
Host smart-7fccdbcd-ad40-4b85-8c20-bfcb69e11508
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429188269 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.429188269
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.2813695812
Short name T333
Test name
Test status
Simulation time 218908530 ps
CPU time 1.44 seconds
Started Mar 21 01:04:50 PM PDT 24
Finished Mar 21 01:04:51 PM PDT 24
Peak memory 200504 kb
Host smart-089788af-b423-4f54-8ede-1af09d4f1a85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813695812 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.2813695812
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.4049610776
Short name T294
Test name
Test status
Simulation time 52190356843 ps
CPU time 471.46 seconds
Started Mar 21 01:04:50 PM PDT 24
Finished Mar 21 01:12:42 PM PDT 24
Peak memory 200288 kb
Host smart-a8af0fcc-a268-4029-92f4-edd8cda9cb68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049610776 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.4049610776
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.503627579
Short name T55
Test name
Test status
Simulation time 292324537 ps
CPU time 14.34 seconds
Started Mar 21 01:04:47 PM PDT 24
Finished Mar 21 01:05:02 PM PDT 24
Peak memory 200360 kb
Host smart-1b593381-5edb-43f2-a068-6b61ba8bf327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503627579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.503627579
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2652993355
Short name T436
Test name
Test status
Simulation time 26812491 ps
CPU time 0.56 seconds
Started Mar 21 01:04:47 PM PDT 24
Finished Mar 21 01:04:48 PM PDT 24
Peak memory 194640 kb
Host smart-6fc693b5-6650-4e7b-9c30-598cd867200b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652993355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2652993355
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1211447433
Short name T50
Test name
Test status
Simulation time 21627278537 ps
CPU time 62.2 seconds
Started Mar 21 01:04:51 PM PDT 24
Finished Mar 21 01:05:53 PM PDT 24
Peak memory 224984 kb
Host smart-189bdff6-6933-4400-aad1-aabc4bbe5d5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1211447433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1211447433
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.803896454
Short name T288
Test name
Test status
Simulation time 1025167201 ps
CPU time 52.37 seconds
Started Mar 21 01:04:50 PM PDT 24
Finished Mar 21 01:05:43 PM PDT 24
Peak memory 200400 kb
Host smart-b4d40482-5659-4ea6-8d23-0e86ac6dee73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803896454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.803896454
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2394968171
Short name T183
Test name
Test status
Simulation time 3086209196 ps
CPU time 49.58 seconds
Started Mar 21 01:04:47 PM PDT 24
Finished Mar 21 01:05:37 PM PDT 24
Peak memory 200412 kb
Host smart-5319cee5-5e3d-4c52-b330-717bd92963e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2394968171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2394968171
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.377317794
Short name T540
Test name
Test status
Simulation time 5491137348 ps
CPU time 75.43 seconds
Started Mar 21 01:04:48 PM PDT 24
Finished Mar 21 01:06:04 PM PDT 24
Peak memory 200396 kb
Host smart-626f072d-9bf1-4819-8f7b-5079d7024760
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377317794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.377317794
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.962032234
Short name T376
Test name
Test status
Simulation time 25361430489 ps
CPU time 93.88 seconds
Started Mar 21 01:04:50 PM PDT 24
Finished Mar 21 01:06:24 PM PDT 24
Peak memory 200548 kb
Host smart-36f89a37-b42c-4fc4-a037-237248cb11eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962032234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.962032234
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.809678925
Short name T277
Test name
Test status
Simulation time 303151158 ps
CPU time 3.77 seconds
Started Mar 21 01:04:50 PM PDT 24
Finished Mar 21 01:04:54 PM PDT 24
Peak memory 200352 kb
Host smart-b2ffe9b9-67dd-4bab-b640-5d6efb5228bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809678925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.809678925
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.4141679538
Short name T72
Test name
Test status
Simulation time 174561670079 ps
CPU time 1169.1 seconds
Started Mar 21 01:04:52 PM PDT 24
Finished Mar 21 01:24:24 PM PDT 24
Peak memory 246556 kb
Host smart-8362e84b-e202-43fc-a9a7-082fb2ce6617
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141679538 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.4141679538
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.2198929980
Short name T239
Test name
Test status
Simulation time 283985368 ps
CPU time 1.36 seconds
Started Mar 21 01:04:49 PM PDT 24
Finished Mar 21 01:04:51 PM PDT 24
Peak memory 199980 kb
Host smart-d406ef4e-1bb1-49ac-8f4b-113fe8bdc54e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198929980 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.2198929980
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.3964264149
Short name T530
Test name
Test status
Simulation time 112704533926 ps
CPU time 520.86 seconds
Started Mar 21 01:04:51 PM PDT 24
Finished Mar 21 01:13:34 PM PDT 24
Peak memory 200344 kb
Host smart-b7846ce3-ac63-40c4-9e82-d2ff9dbd7a08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964264149 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.3964264149
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.2652685984
Short name T414
Test name
Test status
Simulation time 2220926610 ps
CPU time 29.05 seconds
Started Mar 21 01:04:48 PM PDT 24
Finished Mar 21 01:05:17 PM PDT 24
Peak memory 200532 kb
Host smart-e6f28e03-87d9-430a-8e00-02a610473958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652685984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2652685984
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.1704820426
Short name T208
Test name
Test status
Simulation time 25195235 ps
CPU time 0.62 seconds
Started Mar 21 01:04:51 PM PDT 24
Finished Mar 21 01:04:51 PM PDT 24
Peak memory 196048 kb
Host smart-d051ddd7-ba49-41fc-a650-0929642e1eea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704820426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.1704820426
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.625079212
Short name T470
Test name
Test status
Simulation time 425871172 ps
CPU time 15.22 seconds
Started Mar 21 01:04:51 PM PDT 24
Finished Mar 21 01:05:08 PM PDT 24
Peak memory 212636 kb
Host smart-6288aa2c-3a93-4121-a011-45b69812ee05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=625079212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.625079212
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2724817134
Short name T119
Test name
Test status
Simulation time 12456482587 ps
CPU time 57.95 seconds
Started Mar 21 01:04:47 PM PDT 24
Finished Mar 21 01:05:45 PM PDT 24
Peak memory 200460 kb
Host smart-d47e3bf2-e38f-49ff-9ec4-89b138dcc50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724817134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2724817134
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2437673034
Short name T566
Test name
Test status
Simulation time 830252925 ps
CPU time 48.4 seconds
Started Mar 21 01:04:50 PM PDT 24
Finished Mar 21 01:05:38 PM PDT 24
Peak memory 200404 kb
Host smart-6c902d0f-d1a7-4f18-8582-f5d60163e739
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2437673034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2437673034
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.439084263
Short name T327
Test name
Test status
Simulation time 2159373997 ps
CPU time 116.59 seconds
Started Mar 21 01:04:50 PM PDT 24
Finished Mar 21 01:06:47 PM PDT 24
Peak memory 200332 kb
Host smart-5bff4f87-946e-4731-a9f0-d85d02c30cc6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439084263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.439084263
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.2330131561
Short name T137
Test name
Test status
Simulation time 363677150 ps
CPU time 22.6 seconds
Started Mar 21 01:04:49 PM PDT 24
Finished Mar 21 01:05:12 PM PDT 24
Peak memory 200424 kb
Host smart-f2e3f761-7307-461a-a42d-db3d16482ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330131561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2330131561
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.2459786527
Short name T34
Test name
Test status
Simulation time 251228665 ps
CPU time 3.3 seconds
Started Mar 21 01:04:57 PM PDT 24
Finished Mar 21 01:05:00 PM PDT 24
Peak memory 200304 kb
Host smart-f6a3a0f0-9815-479a-a5f7-c5b197a10162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459786527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.2459786527
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2193330383
Short name T418
Test name
Test status
Simulation time 202192231477 ps
CPU time 1775.98 seconds
Started Mar 21 01:04:47 PM PDT 24
Finished Mar 21 01:34:24 PM PDT 24
Peak memory 200448 kb
Host smart-50c6bd02-838d-45d2-9616-93703d1555f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193330383 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2193330383
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.2730815701
Short name T359
Test name
Test status
Simulation time 194740642 ps
CPU time 1.12 seconds
Started Mar 21 01:04:50 PM PDT 24
Finished Mar 21 01:04:52 PM PDT 24
Peak memory 200260 kb
Host smart-d2f03c48-b07a-4250-a47b-ee5de0b68f3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730815701 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.2730815701
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.934185568
Short name T79
Test name
Test status
Simulation time 32053720428 ps
CPU time 466.64 seconds
Started Mar 21 01:04:47 PM PDT 24
Finished Mar 21 01:12:34 PM PDT 24
Peak memory 200420 kb
Host smart-ca14a0e4-e841-41ab-8f3e-dea0ec1d8b96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934185568 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.934185568
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.2643007776
Short name T210
Test name
Test status
Simulation time 28255592776 ps
CPU time 76.97 seconds
Started Mar 21 01:04:48 PM PDT 24
Finished Mar 21 01:06:05 PM PDT 24
Peak memory 200484 kb
Host smart-a180f8e7-c131-4ab5-95ae-2178fe884396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643007776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2643007776
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1094250489
Short name T67
Test name
Test status
Simulation time 14697700 ps
CPU time 0.65 seconds
Started Mar 21 01:04:57 PM PDT 24
Finished Mar 21 01:04:58 PM PDT 24
Peak memory 196056 kb
Host smart-2c509623-3c61-4738-9447-c047f932ecb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094250489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1094250489
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.3684245504
Short name T432
Test name
Test status
Simulation time 981443002 ps
CPU time 43.35 seconds
Started Mar 21 01:04:47 PM PDT 24
Finished Mar 21 01:05:31 PM PDT 24
Peak memory 227356 kb
Host smart-fafd11a5-7194-494a-9879-ec98009329fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3684245504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3684245504
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1812128847
Short name T229
Test name
Test status
Simulation time 21417267688 ps
CPU time 75.16 seconds
Started Mar 21 01:04:51 PM PDT 24
Finished Mar 21 01:06:06 PM PDT 24
Peak memory 200404 kb
Host smart-59042517-0073-4334-a9fb-326f152a9df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812128847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1812128847
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.922221886
Short name T401
Test name
Test status
Simulation time 4028949746 ps
CPU time 126.31 seconds
Started Mar 21 01:04:49 PM PDT 24
Finished Mar 21 01:06:56 PM PDT 24
Peak memory 200492 kb
Host smart-34524975-8ce6-486e-a9e1-ec1c00cc9477
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=922221886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.922221886
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.3757007471
Short name T324
Test name
Test status
Simulation time 3927523580 ps
CPU time 89.76 seconds
Started Mar 21 01:04:55 PM PDT 24
Finished Mar 21 01:06:25 PM PDT 24
Peak memory 200500 kb
Host smart-218666d9-54bf-4fb9-b783-311b07d959ec
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757007471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3757007471
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1947808365
Short name T300
Test name
Test status
Simulation time 50488298974 ps
CPU time 102.94 seconds
Started Mar 21 01:04:50 PM PDT 24
Finished Mar 21 01:06:34 PM PDT 24
Peak memory 200404 kb
Host smart-6a7ba280-49ed-4c55-bf55-dc508b2ee36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947808365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1947808365
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2004726971
Short name T329
Test name
Test status
Simulation time 767021823 ps
CPU time 1.82 seconds
Started Mar 21 01:04:47 PM PDT 24
Finished Mar 21 01:04:49 PM PDT 24
Peak memory 200328 kb
Host smart-997a96e7-0d3f-4a18-b45c-84dec9b70591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004726971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2004726971
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.2352559000
Short name T600
Test name
Test status
Simulation time 16039778055 ps
CPU time 822.44 seconds
Started Mar 21 01:04:58 PM PDT 24
Finished Mar 21 01:18:41 PM PDT 24
Peak memory 229216 kb
Host smart-635e5144-2118-4d2a-be29-f2d946f09c52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352559000 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2352559000
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.2762140148
Short name T353
Test name
Test status
Simulation time 175720275 ps
CPU time 1.07 seconds
Started Mar 21 01:04:57 PM PDT 24
Finished Mar 21 01:04:58 PM PDT 24
Peak memory 199852 kb
Host smart-44cf0096-bac4-4679-93f7-d103ac0b8e80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762140148 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.2762140148
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.2691952583
Short name T498
Test name
Test status
Simulation time 470885639471 ps
CPU time 509.4 seconds
Started Mar 21 01:04:58 PM PDT 24
Finished Mar 21 01:13:28 PM PDT 24
Peak memory 200304 kb
Host smart-5c9caaf5-ef9a-4a7f-8746-72e0a0f76607
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691952583 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.2691952583
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.745923563
Short name T351
Test name
Test status
Simulation time 4697101408 ps
CPU time 44.91 seconds
Started Mar 21 01:04:58 PM PDT 24
Finished Mar 21 01:05:43 PM PDT 24
Peak memory 200660 kb
Host smart-a1f74d03-c64f-4b56-a3ad-808935f95bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745923563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.745923563
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.191465299
Short name T32
Test name
Test status
Simulation time 21231476 ps
CPU time 0.56 seconds
Started Mar 21 01:04:55 PM PDT 24
Finished Mar 21 01:04:56 PM PDT 24
Peak memory 195664 kb
Host smart-460c3c37-73a5-4e37-bec8-0de485c029aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191465299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.191465299
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.609777217
Short name T528
Test name
Test status
Simulation time 99048956 ps
CPU time 3.98 seconds
Started Mar 21 01:04:56 PM PDT 24
Finished Mar 21 01:05:00 PM PDT 24
Peak memory 213828 kb
Host smart-16a28206-750b-41b3-8f6d-67e670e25655
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=609777217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.609777217
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.927650631
Short name T553
Test name
Test status
Simulation time 1675059399 ps
CPU time 28.18 seconds
Started Mar 21 01:04:59 PM PDT 24
Finished Mar 21 01:05:27 PM PDT 24
Peak memory 200384 kb
Host smart-f6b8e08e-c6f2-4d39-b3f6-9a7d91fcfad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927650631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.927650631
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.436178742
Short name T505
Test name
Test status
Simulation time 3522962307 ps
CPU time 103.68 seconds
Started Mar 21 01:04:58 PM PDT 24
Finished Mar 21 01:06:42 PM PDT 24
Peak memory 200444 kb
Host smart-6905ac46-6fe1-43c6-8f0e-8f583bf1daf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=436178742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.436178742
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.2814235930
Short name T328
Test name
Test status
Simulation time 51916300418 ps
CPU time 178.13 seconds
Started Mar 21 01:04:58 PM PDT 24
Finished Mar 21 01:07:56 PM PDT 24
Peak memory 200468 kb
Host smart-73195070-1302-498b-b69e-44aaf0511c89
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814235930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.2814235930
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2244577140
Short name T151
Test name
Test status
Simulation time 16748081215 ps
CPU time 38.58 seconds
Started Mar 21 01:04:56 PM PDT 24
Finished Mar 21 01:05:35 PM PDT 24
Peak memory 200452 kb
Host smart-d5baf739-b831-4b5a-a12d-a3d54897f4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244577140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2244577140
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.896332462
Short name T576
Test name
Test status
Simulation time 836615632 ps
CPU time 2.97 seconds
Started Mar 21 01:04:58 PM PDT 24
Finished Mar 21 01:05:01 PM PDT 24
Peak memory 200412 kb
Host smart-39888f03-cbca-4c7e-92d8-af915853db1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896332462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.896332462
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2716167772
Short name T502
Test name
Test status
Simulation time 12970879783 ps
CPU time 503.03 seconds
Started Mar 21 01:04:56 PM PDT 24
Finished Mar 21 01:13:20 PM PDT 24
Peak memory 216868 kb
Host smart-39ca48f8-adff-4194-888d-4e7ebef8ae82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716167772 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2716167772
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.471167990
Short name T152
Test name
Test status
Simulation time 70463256 ps
CPU time 1.37 seconds
Started Mar 21 01:04:58 PM PDT 24
Finished Mar 21 01:05:00 PM PDT 24
Peak memory 200284 kb
Host smart-1b63cd3f-e088-49f3-ad85-23383a33717e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471167990 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_hmac_vectors.471167990
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.1752506836
Short name T14
Test name
Test status
Simulation time 167420353676 ps
CPU time 546.8 seconds
Started Mar 21 01:04:56 PM PDT 24
Finished Mar 21 01:14:03 PM PDT 24
Peak memory 200340 kb
Host smart-49b5a716-e4ee-4154-b3c7-a5421f27fb9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752506836 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.1752506836
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3464006397
Short name T595
Test name
Test status
Simulation time 3437202445 ps
CPU time 63.51 seconds
Started Mar 21 01:04:57 PM PDT 24
Finished Mar 21 01:06:00 PM PDT 24
Peak memory 200468 kb
Host smart-7f6c0daf-e7c7-451a-971b-b663ae1c3129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464006397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3464006397
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3520353700
Short name T218
Test name
Test status
Simulation time 43903406 ps
CPU time 0.57 seconds
Started Mar 21 01:05:08 PM PDT 24
Finished Mar 21 01:05:09 PM PDT 24
Peak memory 194824 kb
Host smart-656c1e25-fa49-4a0b-9fb1-3a981338af68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520353700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3520353700
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.4040813923
Short name T589
Test name
Test status
Simulation time 4797497805 ps
CPU time 46.24 seconds
Started Mar 21 01:04:56 PM PDT 24
Finished Mar 21 01:05:43 PM PDT 24
Peak memory 219828 kb
Host smart-07fdd406-2c91-416a-8e95-63d8516fcfca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4040813923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.4040813923
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3287618746
Short name T598
Test name
Test status
Simulation time 6324500073 ps
CPU time 26.38 seconds
Started Mar 21 01:05:06 PM PDT 24
Finished Mar 21 01:05:33 PM PDT 24
Peak memory 200388 kb
Host smart-3b58f4d7-21bb-4656-a852-7c82255557ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287618746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3287618746
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.1705406598
Short name T463
Test name
Test status
Simulation time 9949306454 ps
CPU time 93.9 seconds
Started Mar 21 01:04:57 PM PDT 24
Finished Mar 21 01:06:31 PM PDT 24
Peak memory 200416 kb
Host smart-743bdca4-9af3-437f-acb3-9e155cafadad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1705406598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1705406598
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.297405078
Short name T361
Test name
Test status
Simulation time 30429312958 ps
CPU time 88.03 seconds
Started Mar 21 01:05:04 PM PDT 24
Finished Mar 21 01:06:33 PM PDT 24
Peak memory 200388 kb
Host smart-9e764ac8-bf0e-4a48-8c54-10c4d3cdb798
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297405078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.297405078
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.502954814
Short name T458
Test name
Test status
Simulation time 578638573 ps
CPU time 34.69 seconds
Started Mar 21 01:04:58 PM PDT 24
Finished Mar 21 01:05:33 PM PDT 24
Peak memory 200320 kb
Host smart-8a23f79a-4e65-4873-9e38-f6ecdaa44440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502954814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.502954814
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3515589951
Short name T397
Test name
Test status
Simulation time 359431146 ps
CPU time 5.62 seconds
Started Mar 21 01:04:57 PM PDT 24
Finished Mar 21 01:05:04 PM PDT 24
Peak memory 200428 kb
Host smart-a770e730-ca67-4f84-9f0a-c1f40db1e68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515589951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3515589951
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2637274295
Short name T481
Test name
Test status
Simulation time 187956757013 ps
CPU time 581.61 seconds
Started Mar 21 01:05:06 PM PDT 24
Finished Mar 21 01:14:48 PM PDT 24
Peak memory 216840 kb
Host smart-47404217-8abe-423e-9454-835feeba83d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637274295 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2637274295
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.3139513220
Short name T245
Test name
Test status
Simulation time 192468713 ps
CPU time 1.16 seconds
Started Mar 21 01:05:06 PM PDT 24
Finished Mar 21 01:05:08 PM PDT 24
Peak memory 199860 kb
Host smart-80950da6-6c1f-4821-82b9-f337fe6e4d7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139513220 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.3139513220
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.266374623
Short name T378
Test name
Test status
Simulation time 8126314906 ps
CPU time 464.39 seconds
Started Mar 21 01:05:07 PM PDT 24
Finished Mar 21 01:12:52 PM PDT 24
Peak memory 200356 kb
Host smart-97e889da-105e-4ee4-9a4f-a343c829dd41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266374623 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.266374623
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1708338736
Short name T575
Test name
Test status
Simulation time 27217928677 ps
CPU time 48.05 seconds
Started Mar 21 01:05:05 PM PDT 24
Finished Mar 21 01:05:55 PM PDT 24
Peak memory 200436 kb
Host smart-530a7769-7c2c-48d1-b74f-3f90a6766d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708338736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1708338736
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.4265652444
Short name T364
Test name
Test status
Simulation time 13450597 ps
CPU time 0.58 seconds
Started Mar 21 01:03:46 PM PDT 24
Finished Mar 21 01:03:48 PM PDT 24
Peak memory 195888 kb
Host smart-38abf554-d73d-45b9-b6bc-28ce87f77599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265652444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.4265652444
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2191446148
Short name T387
Test name
Test status
Simulation time 3099731207 ps
CPU time 55.94 seconds
Started Mar 21 01:03:44 PM PDT 24
Finished Mar 21 01:04:41 PM PDT 24
Peak memory 225392 kb
Host smart-6122796f-d738-4fe8-8d38-df1ab032a346
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2191446148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2191446148
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1675062984
Short name T138
Test name
Test status
Simulation time 1053558648 ps
CPU time 17.13 seconds
Started Mar 21 01:03:38 PM PDT 24
Finished Mar 21 01:03:56 PM PDT 24
Peak memory 200268 kb
Host smart-b6aaa4f6-ae99-4600-b2cc-42927afc65a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675062984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1675062984
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.102121071
Short name T213
Test name
Test status
Simulation time 399690503 ps
CPU time 19.83 seconds
Started Mar 21 01:03:35 PM PDT 24
Finished Mar 21 01:03:56 PM PDT 24
Peak memory 200300 kb
Host smart-1e083abc-ad01-4ffd-b9f1-d9ecc52ac2b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=102121071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.102121071
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.2836129445
Short name T286
Test name
Test status
Simulation time 7746255693 ps
CPU time 113.44 seconds
Started Mar 21 01:03:45 PM PDT 24
Finished Mar 21 01:05:38 PM PDT 24
Peak memory 200452 kb
Host smart-eb397d88-4980-40ef-88d8-9ac4ac13c66f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836129445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.2836129445
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3468443810
Short name T393
Test name
Test status
Simulation time 449071527 ps
CPU time 27.14 seconds
Started Mar 21 01:03:35 PM PDT 24
Finished Mar 21 01:04:03 PM PDT 24
Peak memory 200344 kb
Host smart-e437dbea-0d91-44b2-bd0d-0bf1432bb6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468443810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3468443810
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.2042100025
Short name T466
Test name
Test status
Simulation time 394397282 ps
CPU time 4.77 seconds
Started Mar 21 01:03:45 PM PDT 24
Finished Mar 21 01:03:50 PM PDT 24
Peak memory 200384 kb
Host smart-f1f69e5b-86a4-4883-aa0b-f871ee126891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042100025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2042100025
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1146235794
Short name T593
Test name
Test status
Simulation time 5164908479 ps
CPU time 231.36 seconds
Started Mar 21 01:03:36 PM PDT 24
Finished Mar 21 01:07:28 PM PDT 24
Peak memory 216808 kb
Host smart-3dc83177-9fd2-4bc5-bc9b-ef45f4e715a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146235794 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1146235794
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.867877127
Short name T372
Test name
Test status
Simulation time 193235705 ps
CPU time 1.11 seconds
Started Mar 21 01:03:36 PM PDT 24
Finished Mar 21 01:03:38 PM PDT 24
Peak memory 199856 kb
Host smart-af8a5f14-d137-4dbe-93f1-8bf9624592be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867877127 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_hmac_vectors.867877127
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.3474645782
Short name T284
Test name
Test status
Simulation time 7917574802 ps
CPU time 448.29 seconds
Started Mar 21 01:03:45 PM PDT 24
Finished Mar 21 01:11:13 PM PDT 24
Peak memory 200400 kb
Host smart-d152da1b-1b2b-427d-9f65-9c1d7dd5cd8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474645782 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.3474645782
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.4126934672
Short name T254
Test name
Test status
Simulation time 5560268776 ps
CPU time 46.99 seconds
Started Mar 21 01:03:36 PM PDT 24
Finished Mar 21 01:04:24 PM PDT 24
Peak memory 200416 kb
Host smart-42f929a4-fb36-40ea-9373-79147067a2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126934672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.4126934672
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2559595418
Short name T222
Test name
Test status
Simulation time 14425585 ps
CPU time 0.59 seconds
Started Mar 21 01:03:45 PM PDT 24
Finished Mar 21 01:03:46 PM PDT 24
Peak memory 194820 kb
Host smart-ebf030ae-5bf9-483f-ad90-137c20e8aa4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559595418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2559595418
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.2970736025
Short name T297
Test name
Test status
Simulation time 2907652180 ps
CPU time 27.14 seconds
Started Mar 21 01:03:48 PM PDT 24
Finished Mar 21 01:04:17 PM PDT 24
Peak memory 216412 kb
Host smart-615b19d9-0a5a-4940-a5f8-ce21fbde7e85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2970736025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2970736025
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.295367597
Short name T189
Test name
Test status
Simulation time 3504904788 ps
CPU time 44.29 seconds
Started Mar 21 01:03:57 PM PDT 24
Finished Mar 21 01:04:42 PM PDT 24
Peak memory 200428 kb
Host smart-a104bcd1-4eba-4258-bf61-97b58a9b06a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295367597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.295367597
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3557901849
Short name T162
Test name
Test status
Simulation time 1432659312 ps
CPU time 40.31 seconds
Started Mar 21 01:03:46 PM PDT 24
Finished Mar 21 01:04:28 PM PDT 24
Peak memory 200412 kb
Host smart-82e230e0-d1e0-4e28-a45b-07026b329790
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3557901849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3557901849
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1260541222
Short name T267
Test name
Test status
Simulation time 1009824447 ps
CPU time 14.84 seconds
Started Mar 21 01:03:48 PM PDT 24
Finished Mar 21 01:04:03 PM PDT 24
Peak memory 200340 kb
Host smart-5c69d0b8-570a-4a8d-afb7-99dfe882eab1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260541222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1260541222
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3703131230
Short name T501
Test name
Test status
Simulation time 6572028017 ps
CPU time 90.25 seconds
Started Mar 21 01:03:49 PM PDT 24
Finished Mar 21 01:05:20 PM PDT 24
Peak memory 200388 kb
Host smart-f2d308b0-1543-46e9-813e-800919c32040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703131230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3703131230
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.994974734
Short name T366
Test name
Test status
Simulation time 892922205 ps
CPU time 3.63 seconds
Started Mar 21 01:03:42 PM PDT 24
Finished Mar 21 01:03:46 PM PDT 24
Peak memory 200340 kb
Host smart-d0f81364-b93d-471a-9f23-2c5fc27a02df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994974734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.994974734
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.562550166
Short name T253
Test name
Test status
Simulation time 82940130615 ps
CPU time 395.23 seconds
Started Mar 21 01:03:49 PM PDT 24
Finished Mar 21 01:10:25 PM PDT 24
Peak memory 239404 kb
Host smart-9eaf7ced-f4e6-458a-84d2-efcb532c247e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562550166 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.562550166
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.219696978
Short name T509
Test name
Test status
Simulation time 117716505 ps
CPU time 0.93 seconds
Started Mar 21 01:03:50 PM PDT 24
Finished Mar 21 01:03:51 PM PDT 24
Peak memory 198560 kb
Host smart-ddd7fe83-aa2d-48fc-aad0-5a1e6d7a7d8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219696978 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_hmac_vectors.219696978
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.2719834829
Short name T420
Test name
Test status
Simulation time 106354798581 ps
CPU time 488.94 seconds
Started Mar 21 01:03:49 PM PDT 24
Finished Mar 21 01:11:59 PM PDT 24
Peak memory 200272 kb
Host smart-3600044b-95a9-43f5-8130-bae5d590854e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719834829 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.2719834829
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.727958554
Short name T465
Test name
Test status
Simulation time 3964080516 ps
CPU time 58.74 seconds
Started Mar 21 01:03:58 PM PDT 24
Finished Mar 21 01:04:58 PM PDT 24
Peak memory 200400 kb
Host smart-deea7e64-3cc1-4920-81bb-7c76bdbe7e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727958554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.727958554
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/61.hmac_stress_all_with_rand_reset.1324412669
Short name T541
Test name
Test status
Simulation time 128826383269 ps
CPU time 1049.14 seconds
Started Mar 21 01:05:06 PM PDT 24
Finished Mar 21 01:22:36 PM PDT 24
Peak memory 249648 kb
Host smart-13764457-5d28-4115-a70d-05b817f5ae27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1324412669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.hmac_stress_all_with_rand_reset.1324412669
Directory /workspace/61.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3853617289
Short name T358
Test name
Test status
Simulation time 43225953 ps
CPU time 0.6 seconds
Started Mar 21 01:03:50 PM PDT 24
Finished Mar 21 01:03:53 PM PDT 24
Peak memory 195512 kb
Host smart-50feeeb8-252b-4dd3-b1a2-8dc29ed8ef3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853617289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3853617289
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.3449044388
Short name T246
Test name
Test status
Simulation time 1163806945 ps
CPU time 42.07 seconds
Started Mar 21 01:04:00 PM PDT 24
Finished Mar 21 01:04:43 PM PDT 24
Peak memory 216880 kb
Host smart-08bbd814-3cca-4fff-83a0-201e5f4e5d63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3449044388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3449044388
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.296569206
Short name T173
Test name
Test status
Simulation time 32713245276 ps
CPU time 30.54 seconds
Started Mar 21 01:03:52 PM PDT 24
Finished Mar 21 01:04:23 PM PDT 24
Peak memory 200408 kb
Host smart-ce95a840-81aa-411d-b9e5-3e68f6740211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296569206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.296569206
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.504815920
Short name T23
Test name
Test status
Simulation time 5916478242 ps
CPU time 85.62 seconds
Started Mar 21 01:03:54 PM PDT 24
Finished Mar 21 01:05:20 PM PDT 24
Peak memory 200476 kb
Host smart-3975bb46-669f-41b1-9f9d-9e2e1b1a4302
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=504815920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.504815920
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.3392529595
Short name T237
Test name
Test status
Simulation time 3169099816 ps
CPU time 173.08 seconds
Started Mar 21 01:04:00 PM PDT 24
Finished Mar 21 01:06:54 PM PDT 24
Peak memory 200228 kb
Host smart-fac52878-dfbe-440c-98c3-4937534041a0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392529595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3392529595
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2937768689
Short name T266
Test name
Test status
Simulation time 13944198064 ps
CPU time 99.29 seconds
Started Mar 21 01:04:07 PM PDT 24
Finished Mar 21 01:05:47 PM PDT 24
Peak memory 200404 kb
Host smart-0fb143ae-a83c-4d8b-984c-cf1a6c43ddde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937768689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2937768689
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.3667455584
Short name T531
Test name
Test status
Simulation time 139116563 ps
CPU time 2.38 seconds
Started Mar 21 01:03:44 PM PDT 24
Finished Mar 21 01:03:47 PM PDT 24
Peak memory 200488 kb
Host smart-7d28cad9-9303-4f8e-90d8-230e81104ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667455584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3667455584
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.582794352
Short name T44
Test name
Test status
Simulation time 18265193702 ps
CPU time 1016.88 seconds
Started Mar 21 01:03:50 PM PDT 24
Finished Mar 21 01:20:50 PM PDT 24
Peak memory 244476 kb
Host smart-26dc76fc-38c2-4b63-9906-3e2d2fd5916d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582794352 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.582794352
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.4029824579
Short name T352
Test name
Test status
Simulation time 28485236 ps
CPU time 0.98 seconds
Started Mar 21 01:03:48 PM PDT 24
Finished Mar 21 01:03:51 PM PDT 24
Peak memory 198732 kb
Host smart-84019ec6-2b6b-474d-bbd5-c2d3bd6a88fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029824579 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.4029824579
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.504568182
Short name T443
Test name
Test status
Simulation time 140840256140 ps
CPU time 449.68 seconds
Started Mar 21 01:04:01 PM PDT 24
Finished Mar 21 01:11:31 PM PDT 24
Peak memory 200360 kb
Host smart-c77e1e33-168e-43b1-83c7-4976e35dfbc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504568182 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.504568182
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.667440932
Short name T319
Test name
Test status
Simulation time 1334351867 ps
CPU time 10.09 seconds
Started Mar 21 01:04:00 PM PDT 24
Finished Mar 21 01:04:11 PM PDT 24
Peak memory 200460 kb
Host smart-64cd394d-e810-4982-9ef5-d3ce981132ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667440932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.667440932
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/76.hmac_stress_all_with_rand_reset.1667735580
Short name T7
Test name
Test status
Simulation time 220732827106 ps
CPU time 2083.33 seconds
Started Mar 21 01:05:08 PM PDT 24
Finished Mar 21 01:39:52 PM PDT 24
Peak memory 264616 kb
Host smart-7feff60b-f4bc-4807-b143-103144e417e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1667735580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.hmac_stress_all_with_rand_reset.1667735580
Directory /workspace/76.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1237016740
Short name T584
Test name
Test status
Simulation time 34154768 ps
CPU time 0.55 seconds
Started Mar 21 01:03:47 PM PDT 24
Finished Mar 21 01:03:49 PM PDT 24
Peak memory 195652 kb
Host smart-a4e0375e-2897-4451-9e9c-99f5a3398206
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237016740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1237016740
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.284940066
Short name T249
Test name
Test status
Simulation time 2033309295 ps
CPU time 37.18 seconds
Started Mar 21 01:03:50 PM PDT 24
Finished Mar 21 01:04:30 PM PDT 24
Peak memory 218856 kb
Host smart-d0fa1272-5a7f-4624-ac2b-afe7566d172f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=284940066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.284940066
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3838957522
Short name T360
Test name
Test status
Simulation time 942757208 ps
CPU time 44.81 seconds
Started Mar 21 01:03:44 PM PDT 24
Finished Mar 21 01:04:29 PM PDT 24
Peak memory 200428 kb
Host smart-a310ca6e-9205-4831-bee1-6d475101a8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838957522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3838957522
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.1324300318
Short name T428
Test name
Test status
Simulation time 476847705 ps
CPU time 27.72 seconds
Started Mar 21 01:03:51 PM PDT 24
Finished Mar 21 01:04:21 PM PDT 24
Peak memory 200328 kb
Host smart-222d6a3a-340d-4bfa-b7ac-71ab32e8efbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1324300318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1324300318
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.629272485
Short name T496
Test name
Test status
Simulation time 1968115594 ps
CPU time 25.31 seconds
Started Mar 21 01:03:50 PM PDT 24
Finished Mar 21 01:04:18 PM PDT 24
Peak memory 200368 kb
Host smart-0dfe47f5-b1ba-4c16-9155-7d9602529ac2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629272485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.629272485
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.11425990
Short name T123
Test name
Test status
Simulation time 1003592221 ps
CPU time 58.77 seconds
Started Mar 21 01:03:46 PM PDT 24
Finished Mar 21 01:04:46 PM PDT 24
Peak memory 200404 kb
Host smart-44e90db3-5f7f-4329-9051-d173ff9a69d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11425990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.11425990
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.4230387887
Short name T344
Test name
Test status
Simulation time 691284796 ps
CPU time 2.7 seconds
Started Mar 21 01:04:00 PM PDT 24
Finished Mar 21 01:04:03 PM PDT 24
Peak memory 200404 kb
Host smart-669d30c6-16d6-40d9-b07b-28b0d08b3f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230387887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.4230387887
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.3200984051
Short name T42
Test name
Test status
Simulation time 158868617537 ps
CPU time 977.85 seconds
Started Mar 21 01:03:47 PM PDT 24
Finished Mar 21 01:20:06 PM PDT 24
Peak memory 200500 kb
Host smart-47a9dc40-4393-4e9a-b991-8c30205bf246
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200984051 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3200984051
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.191416887
Short name T157
Test name
Test status
Simulation time 57200632 ps
CPU time 1.23 seconds
Started Mar 21 01:03:47 PM PDT 24
Finished Mar 21 01:03:49 PM PDT 24
Peak memory 200356 kb
Host smart-860c0535-b1b3-4e16-99e4-88d94136c155
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191416887 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.hmac_test_hmac_vectors.191416887
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.1606734796
Short name T170
Test name
Test status
Simulation time 16763552973 ps
CPU time 469.82 seconds
Started Mar 21 01:03:48 PM PDT 24
Finished Mar 21 01:11:39 PM PDT 24
Peak memory 200404 kb
Host smart-da1feca7-ac36-4569-989d-9c455bcb59aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606734796 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.1606734796
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1382466318
Short name T126
Test name
Test status
Simulation time 6306947405 ps
CPU time 33.98 seconds
Started Mar 21 01:03:49 PM PDT 24
Finished Mar 21 01:04:24 PM PDT 24
Peak memory 200420 kb
Host smart-4ac92bf7-7328-4c25-8158-10bb3b06073d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382466318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1382466318
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3696899913
Short name T172
Test name
Test status
Simulation time 16439466 ps
CPU time 0.61 seconds
Started Mar 21 01:03:50 PM PDT 24
Finished Mar 21 01:03:53 PM PDT 24
Peak memory 195876 kb
Host smart-ec0a3a70-a633-4b67-85e1-efb46c708fa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696899913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3696899913
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.3271734050
Short name T469
Test name
Test status
Simulation time 209528822 ps
CPU time 7.7 seconds
Started Mar 21 01:03:54 PM PDT 24
Finished Mar 21 01:04:02 PM PDT 24
Peak memory 215872 kb
Host smart-3798d61a-3da1-481f-88e7-d0d99ef88b37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3271734050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.3271734050
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.4001739549
Short name T225
Test name
Test status
Simulation time 174889064 ps
CPU time 1.14 seconds
Started Mar 21 01:03:48 PM PDT 24
Finished Mar 21 01:03:50 PM PDT 24
Peak memory 200256 kb
Host smart-af5f9b0b-630f-4405-9f4a-6363b816d37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001739549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.4001739549
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1364317216
Short name T224
Test name
Test status
Simulation time 1502004739 ps
CPU time 88.07 seconds
Started Mar 21 01:03:48 PM PDT 24
Finished Mar 21 01:05:17 PM PDT 24
Peak memory 200420 kb
Host smart-8487a218-f14f-426f-9051-70a9e0c660f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1364317216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1364317216
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.2513984218
Short name T230
Test name
Test status
Simulation time 1672832811 ps
CPU time 28.2 seconds
Started Mar 21 01:03:47 PM PDT 24
Finished Mar 21 01:04:16 PM PDT 24
Peak memory 200404 kb
Host smart-c287632e-f6db-4e66-9077-6bbd3364ed6f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513984218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2513984218
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.937383701
Short name T54
Test name
Test status
Simulation time 10683101563 ps
CPU time 77.45 seconds
Started Mar 21 01:03:53 PM PDT 24
Finished Mar 21 01:05:10 PM PDT 24
Peak memory 200420 kb
Host smart-f036d1e7-3c21-4fc4-a0d2-ff2b7b19187b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937383701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.937383701
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3669733446
Short name T475
Test name
Test status
Simulation time 4927995640 ps
CPU time 7.38 seconds
Started Mar 21 01:03:44 PM PDT 24
Finished Mar 21 01:03:52 PM PDT 24
Peak memory 200384 kb
Host smart-be7293f9-c477-4ced-8556-930c879688aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669733446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3669733446
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.3764496722
Short name T423
Test name
Test status
Simulation time 90340428558 ps
CPU time 1622.15 seconds
Started Mar 21 01:03:48 PM PDT 24
Finished Mar 21 01:30:51 PM PDT 24
Peak memory 242408 kb
Host smart-06a73ec7-e186-4990-91dc-af9b568dedf4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764496722 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3764496722
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.3675031885
Short name T150
Test name
Test status
Simulation time 70524526 ps
CPU time 0.99 seconds
Started Mar 21 01:03:47 PM PDT 24
Finished Mar 21 01:03:49 PM PDT 24
Peak memory 198532 kb
Host smart-ab1e3f45-a99d-4ef0-8d1d-43f7b7529a3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675031885 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.3675031885
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.4293964704
Short name T147
Test name
Test status
Simulation time 103748863524 ps
CPU time 487.68 seconds
Started Mar 21 01:03:54 PM PDT 24
Finished Mar 21 01:12:02 PM PDT 24
Peak memory 200412 kb
Host smart-21da9fe2-0f39-4acd-ac32-e33235fbd40d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293964704 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.4293964704
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.286197392
Short name T295
Test name
Test status
Simulation time 31036658155 ps
CPU time 62.7 seconds
Started Mar 21 01:03:57 PM PDT 24
Finished Mar 21 01:05:01 PM PDT 24
Peak memory 200428 kb
Host smart-483badb3-2d18-4ba9-a75a-18c46bb08982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286197392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.286197392
Directory /workspace/9.hmac_wipe_secret/latest
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