Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	12687206	1			T2	362		T3	38111		T4	258
all_values[1]	12687206	1			T2	362		T3	38111		T4	258
all_values[2]	12687206	1			T2	362		T3	38111		T4	258

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

124468

1

T2

341

T3

471

T4

2

auto[1]

37937150

1

T2

745

T3

113862

T4

772

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35985871

1

T2

1058

T3

102046

T4

753

auto[1]

2075747

1

T2

28

T3

12287

T4

21

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	40200	1			T2	226		T3	2		T13	480
all_values[0]	auto[0]	auto[1]	452	1			T2	6		T3	5		T13	2
all_values[0]	auto[1]	auto[0]	12603545	1			T2	108		T3	37976		T4	237
all_values[0]	auto[1]	auto[1]	43009	1			T2	22		T3	128		T4	21
all_values[1]	auto[0]	auto[0]	32011	1			T3	455		T4	2		T21	301
all_values[1]	auto[0]	auto[1]	188	1			T3	1		T20	1		T12	2
all_values[1]	auto[1]	auto[0]	12654660	1			T2	362		T3	37653		T4	256
all_values[1]	auto[1]	auto[1]	347	1			T3	2		T20	2		T12	1
all_values[2]	auto[0]	auto[0]	36024	1			T2	109		T3	4		T13	482
all_values[2]	auto[0]	auto[1]	15593	1			T3	4		T12	1		T15	4
all_values[2]	auto[1]	auto[0]	10619431	1			T2	253		T3	25956		T4	258
all_values[2]	auto[1]	auto[1]	2016158	1			T3	12147		T14	14		T13	4863