Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6046694

1

T2

5261

T3

13652

T4

12

auto[1]

2424266

1

T2

5515

T3

7477

T4

7

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2373502

1

T2

5792

T3

8735

T4

9

auto[1]

6097458

1

T2

4984

T3

12394

T4

10

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5388766

1

T2

6060

T3

7051

T4

7

auto[1]

3082194

1

T2

4716

T3

14078

T4

12

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	5617716	1			T2	2223		T3	18834		T4	1
fifo_depth[1]	414478	1			T2	108		T3	1112		T14	2
fifo_depth[2]	338539	1			T2	110		T3	699		T13	10
fifo_depth[3]	270135	1			T2	107		T3	323		T13	5
fifo_depth[4]	231577	1			T2	114		T3	107		T6	183
fifo_depth[5]	202965	1			T2	117		T3	35		T6	200
fifo_depth[6]	194729	1			T2	117		T3	14		T6	195
fifo_depth[7]	168828	1			T2	125		T3	4		T6	166
fifo_depth[8]	154326	1			T2	143		T3	1		T6	137
fifo_depth[9]	104159	1			T2	116		T6	102		T5	343
fifo_depth[10]	80595	1			T2	94		T6	66		T5	257
fifo_depth[11]	48273	1			T2	66		T6	38		T5	142
fifo_depth[12]	50442	1			T2	56		T6	23		T5	82
fifo_depth[13]	24077	1			T2	32		T6	10		T5	43
fifo_depth[14]	31873	1			T2	35		T6	9		T5	13
fifo_depth[15]	19526	1			T2	30		T6	1		T5	1
fifo_depth[16]	82633	1			T2	759		T5	2		T42	3

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2942907

1

T2

10368

T3

2295

T4

19

auto[1]

5528053

1

T2

408

T3

18834

T14

21

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8381297

1

T2

8961

T3

21129

T4

18

auto[1]

89663

1

T2

1815

T4

1

T12

435

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

182108

1

T2

1206

T3

59

T4

1

auto[0]

auto[0]

auto[0]

auto[1]

193295

1

T2

1886

T3

152

T4

1

auto[0]

auto[0]

auto[1]

auto[0]

911392

1

T2

1792

T3

295

T4

3

auto[0]

auto[0]

auto[1]

auto[1]

198564

1

T2

936

T3

121

T4

2

auto[0]

auto[1]

auto[0]

auto[0]

347260

1

T2

952

T3

498

T4

4

auto[0]

auto[1]

auto[0]

auto[1]

362357

1

T2

1364

T3

253

T4

3

auto[0]

auto[1]

auto[1]

auto[0]

366135

1

T2

1286

T3

644

T4

4

auto[0]

auto[1]

auto[1]

auto[1]

381796

1

T2

946

T3

273

T4

1

auto[1]

auto[0]

auto[0]

auto[0]

248005

1

T2

18

T3

623

T13

745

auto[1]

auto[0]

auto[0]

auto[1]

236324

1

T2

201

T3

1088

T13

692

auto[1]

auto[0]

auto[1]

auto[0]

3177397

1

T2

3

T3

3029

T13

636

auto[1]

auto[0]

auto[1]

auto[1]

241681

1

T2

18

T3

1684

T13

2

auto[1]

auto[1]

auto[0]

auto[0]

401186

1

T2

2

T3

4160

T13

555

auto[1]

auto[1]

auto[0]

auto[1]

402967

1

T2

163

T3

1902

T13

763

auto[1]

auto[1]

auto[1]

auto[0]

413211

1

T2

2

T3

4344

T14

21

auto[1]

auto[1]

auto[1]

auto[1]

407282

1

T2

1

T3

2004

T6

52

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

420781

1

T2

1014

T3

682

T4

1

auto[0]

auto[0]

auto[0]

auto[1]

419452

1

T2

2005

T3

1240

T4

1

auto[0]

auto[0]

auto[1]

auto[0]

4075431

1

T2

1135

T3

3324

T4

3

auto[0]

auto[0]

auto[1]

auto[1]

429910

1

T2

839

T3

1805

T4

2

auto[0]

auto[1]

auto[0]

auto[0]

739184

1

T2

890

T3

4658

T4

3

auto[0]

auto[1]

auto[0]

auto[1]

755545

1

T2

1412

T3

2155

T4

3

auto[0]

auto[1]

auto[1]

auto[0]

766282

1

T2

775

T3

4988

T4

4

auto[0]

auto[1]

auto[1]

auto[1]

774712

1

T2

891

T3

2277

T4

1

auto[1]

auto[0]

auto[0]

auto[0]

9332

1

T2

210

T12

1

T15

22

auto[1]

auto[0]

auto[0]

auto[1]

10167

1

T2

82

T12

34

T15

70

auto[1]

auto[0]

auto[1]

auto[0]

13358

1

T2

660

T12

376

T15

202

auto[1]

auto[0]

auto[1]

auto[1]

10335

1

T2

115

T12

1

T15

87

auto[1]

auto[1]

auto[0]

auto[0]

9262

1

T2

64

T4

1

T12

1

auto[1]

auto[1]

auto[0]

auto[1]

9779

1

T2

115

T15

645

T54

2

auto[1]

auto[1]

auto[1]

auto[0]

13064

1

T2

513

T12

21

T15

545

auto[1]

auto[1]

auto[1]

auto[1]

14366

1

T2

56

T12

1

T15

102

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	257337	1			T2	228		T3	623		T13	745
fifo_depth[0]	auto[0]	auto[0]	auto[1]	246491	1			T2	283		T3	1088		T13	692
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3190755	1			T2	663		T3	3029		T13	636
fifo_depth[0]	auto[0]	auto[1]	auto[1]	252016	1			T2	133		T3	1684		T13	2
fifo_depth[0]	auto[1]	auto[0]	auto[0]	410448	1			T2	66		T3	4160		T4	1
fifo_depth[0]	auto[1]	auto[0]	auto[1]	412746	1			T2	278		T3	1902		T13	763
fifo_depth[0]	auto[1]	auto[1]	auto[0]	426275	1			T2	515		T3	4344		T14	21
fifo_depth[0]	auto[1]	auto[1]	auto[1]	421648	1			T2	57		T3	2004		T6	52
fifo_depth[1]	auto[0]	auto[0]	auto[0]	17731	1			T3	27		T13	15		T5	140
fifo_depth[1]	auto[0]	auto[0]	auto[1]	18527	1			T2	54		T3	73		T6	43
fifo_depth[1]	auto[0]	auto[1]	auto[0]	194704	1			T3	178		T13	7		T6	38
fifo_depth[1]	auto[0]	auto[1]	auto[1]	18895	1			T3	67		T5	31		T20	49
fifo_depth[1]	auto[1]	auto[0]	auto[0]	40302	1			T3	223		T13	4		T6	16
fifo_depth[1]	auto[1]	auto[0]	auto[1]	41432	1			T2	54		T3	115		T13	7
fifo_depth[1]	auto[1]	auto[1]	auto[0]	40980	1			T3	288		T14	2		T13	18
fifo_depth[1]	auto[1]	auto[1]	auto[1]	41907	1			T3	141		T6	15		T21	28
fifo_depth[2]	auto[0]	auto[0]	auto[0]	14316	1			T2	2		T3	12		T5	161
fifo_depth[2]	auto[0]	auto[0]	auto[1]	15433	1			T2	52		T3	43		T6	60
fifo_depth[2]	auto[0]	auto[1]	auto[0]	149692	1			T3	70		T6	36		T5	162
fifo_depth[2]	auto[0]	auto[1]	auto[1]	15610	1			T3	37		T5	30		T20	33
fifo_depth[2]	auto[1]	auto[0]	auto[0]	35295	1			T3	152		T6	11		T5	25
fifo_depth[2]	auto[1]	auto[0]	auto[1]	36361	1			T2	56		T3	90		T6	30
fifo_depth[2]	auto[1]	auto[1]	auto[0]	35482	1			T3	212		T13	10		T6	28
fifo_depth[2]	auto[1]	auto[1]	auto[1]	36350	1			T3	83		T6	10		T21	14
fifo_depth[3]	auto[0]	auto[0]	auto[0]	10854	1			T3	16		T5	145		T21	13
fifo_depth[3]	auto[0]	auto[0]	auto[1]	11899	1			T2	52		T3	27		T6	45
fifo_depth[3]	auto[0]	auto[1]	auto[0]	112667	1			T3	29		T6	35		T5	183
fifo_depth[3]	auto[0]	auto[1]	auto[1]	11846	1			T3	14		T5	36		T20	25
fifo_depth[3]	auto[1]	auto[0]	auto[0]	30251	1			T3	77		T6	19		T5	20
fifo_depth[3]	auto[1]	auto[0]	auto[1]	31616	1			T2	55		T3	31		T6	16
fifo_depth[3]	auto[1]	auto[1]	auto[0]	29934	1			T3	97		T13	5		T6	34
fifo_depth[3]	auto[1]	auto[1]	auto[1]	31068	1			T3	32		T6	18		T21	7
fifo_depth[4]	auto[0]	auto[0]	auto[0]	10304	1			T2	2		T3	3		T5	160
fifo_depth[4]	auto[0]	auto[0]	auto[1]	11182	1			T2	56		T3	5		T6	58
fifo_depth[4]	auto[0]	auto[1]	auto[0]	82569	1			T3	13		T6	38		T5	159
fifo_depth[4]	auto[0]	auto[1]	auto[1]	11266	1			T3	3		T5	37		T20	12
fifo_depth[4]	auto[1]	auto[0]	auto[0]	28595	1			T3	30		T6	19		T5	24
fifo_depth[4]	auto[1]	auto[0]	auto[1]	30320	1			T2	55		T3	10		T6	29
fifo_depth[4]	auto[1]	auto[1]	auto[0]	27719	1			T2	1		T3	29		T6	27
fifo_depth[4]	auto[1]	auto[1]	auto[1]	29622	1			T3	14		T6	12		T21	3
fifo_depth[5]	auto[0]	auto[0]	auto[0]	8485	1			T2	1		T3	1		T5	135
fifo_depth[5]	auto[0]	auto[0]	auto[1]	9656	1			T2	58		T3	3		T6	59
fifo_depth[5]	auto[0]	auto[1]	auto[0]	67465	1			T3	2		T6	49		T5	182
fifo_depth[5]	auto[0]	auto[1]	auto[1]	9653	1			T2	1		T5	30		T20	4
fifo_depth[5]	auto[1]	auto[0]	auto[0]	26475	1			T2	1		T3	11		T6	20
fifo_depth[5]	auto[1]	auto[0]	auto[1]	28043	1			T2	56		T3	4		T6	28
fifo_depth[5]	auto[1]	auto[1]	auto[0]	25893	1			T3	13		T6	30		T5	91
fifo_depth[5]	auto[1]	auto[1]	auto[1]	27295	1			T3	1		T6	14		T20	34
fifo_depth[6]	auto[0]	auto[0]	auto[0]	8962	1			T2	1		T5	137		T21	1
fifo_depth[6]	auto[0]	auto[0]	auto[1]	9670	1			T2	57		T3	1		T6	65
fifo_depth[6]	auto[0]	auto[1]	auto[0]	59275	1			T3	2		T6	39		T5	141
fifo_depth[6]	auto[0]	auto[1]	auto[1]	9676	1			T5	35		T12	356		T15	4
fifo_depth[6]	auto[1]	auto[0]	auto[0]	26307	1			T3	3		T6	15		T5	25
fifo_depth[6]	auto[1]	auto[0]	auto[1]	28048	1			T2	59		T3	3		T6	23
fifo_depth[6]	auto[1]	auto[1]	auto[0]	25416	1			T3	4		T6	32		T5	80
fifo_depth[6]	auto[1]	auto[1]	auto[1]	27375	1			T3	1		T6	21		T20	9
fifo_depth[7]	auto[0]	auto[0]	auto[0]	7985	1			T2	6		T5	147		T20	16
fifo_depth[7]	auto[0]	auto[0]	auto[1]	8530	1			T2	56		T6	43		T5	30
fifo_depth[7]	auto[0]	auto[1]	auto[0]	46977	1			T2	7		T3	1		T6	40
fifo_depth[7]	auto[0]	auto[1]	auto[1]	8615	1			T2	1		T5	29		T12	327
fifo_depth[7]	auto[1]	auto[0]	auto[0]	23874	1			T3	1		T6	11		T5	26
fifo_depth[7]	auto[1]	auto[0]	auto[1]	25101	1			T2	55		T6	27		T5	174
fifo_depth[7]	auto[1]	auto[1]	auto[0]	23005	1			T3	1		T6	33		T5	62
fifo_depth[7]	auto[1]	auto[1]	auto[1]	24741	1			T3	1		T6	12		T20	1
fifo_depth[8]	auto[0]	auto[0]	auto[0]	8783	1			T2	12		T5	105		T20	23
fifo_depth[8]	auto[0]	auto[0]	auto[1]	9655	1			T2	54		T6	37		T5	33
fifo_depth[8]	auto[0]	auto[1]	auto[0]	37864	1			T2	19		T6	21		T5	138
fifo_depth[8]	auto[0]	auto[1]	auto[1]	8722	1			T2	2		T5	24		T20	9
fifo_depth[8]	auto[1]	auto[0]	auto[0]	21022	1			T3	1		T6	19		T5	24
fifo_depth[8]	auto[1]	auto[0]	auto[1]	24182	1			T2	55		T6	17		T5	134
fifo_depth[8]	auto[1]	auto[1]	auto[0]	22104	1			T2	1		T6	30		T5	66
fifo_depth[8]	auto[1]	auto[1]	auto[1]	21994	1			T6	13		T20	7		T42	292
fifo_depth[9]	auto[0]	auto[0]	auto[0]	5468	1			T2	4		T5	62		T20	3
fifo_depth[9]	auto[0]	auto[0]	auto[1]	5956	1			T2	48		T6	24		T5	21
fifo_depth[9]	auto[0]	auto[1]	auto[0]	24691	1			T2	13		T6	18		T5	86
fifo_depth[9]	auto[0]	auto[1]	auto[1]	5982	1			T5	11		T12	226		T49	1
fifo_depth[9]	auto[1]	auto[0]	auto[0]	15042	1			T6	11		T5	14		T20	1
fifo_depth[9]	auto[1]	auto[0]	auto[1]	16302	1			T2	50		T6	14		T5	105
fifo_depth[9]	auto[1]	auto[1]	auto[0]	14860	1			T6	25		T5	44		T20	9
fifo_depth[9]	auto[1]	auto[1]	auto[1]	15858	1			T2	1		T6	10		T42	196
fifo_depth[10]	auto[0]	auto[0]	auto[0]	4903	1			T2	5		T5	50		T20	2
fifo_depth[10]	auto[0]	auto[0]	auto[1]	5425	1			T2	35		T6	14		T5	14
fifo_depth[10]	auto[0]	auto[1]	auto[0]	17422	1			T2	13		T6	12		T5	77
fifo_depth[10]	auto[0]	auto[1]	auto[1]	5366	1			T5	6		T12	151		T15	11
fifo_depth[10]	auto[1]	auto[0]	auto[0]	11353	1			T2	1		T6	8		T5	9
fifo_depth[10]	auto[1]	auto[0]	auto[1]	12616	1			T2	39		T6	7		T5	69
fifo_depth[10]	auto[1]	auto[1]	auto[0]	11539	1			T2	1		T6	17		T5	32
fifo_depth[10]	auto[1]	auto[1]	auto[1]	11971	1			T6	8		T42	120		T56	77
fifo_depth[11]	auto[0]	auto[0]	auto[0]	3247	1			T2	4		T5	30		T12	73
fifo_depth[11]	auto[0]	auto[0]	auto[1]	3368	1			T2	24		T6	11		T5	2
fifo_depth[11]	auto[0]	auto[1]	auto[0]	10022	1			T2	12		T6	6		T5	39
fifo_depth[11]	auto[0]	auto[1]	auto[1]	3450	1			T5	8		T12	70		T15	9
fifo_depth[11]	auto[1]	auto[0]	auto[0]	6526	1			T6	7		T5	7		T42	34
fifo_depth[11]	auto[1]	auto[0]	auto[1]	7407	1			T2	26		T6	5		T5	42
fifo_depth[11]	auto[1]	auto[1]	auto[0]	6931	1			T6	6		T5	14		T42	153
fifo_depth[11]	auto[1]	auto[1]	auto[1]	7322	1			T6	3		T42	72		T56	53
fifo_depth[12]	auto[0]	auto[0]	auto[0]	5190	1			T2	6		T5	16		T12	41
fifo_depth[12]	auto[0]	auto[0]	auto[1]	5604	1			T2	19		T6	8		T5	7
fifo_depth[12]	auto[0]	auto[1]	auto[0]	8547	1			T2	13		T6	5		T5	19
fifo_depth[12]	auto[0]	auto[1]	auto[1]	3971	1			T2	1		T5	2		T12	32
fifo_depth[12]	auto[1]	auto[0]	auto[0]	5934	1			T2	1		T6	1		T5	6
fifo_depth[12]	auto[1]	auto[0]	auto[1]	7270	1			T2	14		T6	3		T5	28
fifo_depth[12]	auto[1]	auto[1]	auto[0]	7655	1			T2	2		T6	5		T5	4
fifo_depth[12]	auto[1]	auto[1]	auto[1]	6271	1			T6	1		T42	32		T56	23
fifo_depth[13]	auto[0]	auto[0]	auto[0]	2382	1			T2	5		T5	9		T12	18
fifo_depth[13]	auto[0]	auto[0]	auto[1]	2290	1			T2	9		T6	4		T5	2
fifo_depth[13]	auto[0]	auto[1]	auto[0]	4081	1			T2	13		T6	1		T5	7
fifo_depth[13]	auto[0]	auto[1]	auto[1]	2354	1			T5	1		T12	10		T15	39
fifo_depth[13]	auto[1]	auto[0]	auto[0]	3109	1			T6	1		T5	2		T42	10
fifo_depth[13]	auto[1]	auto[0]	auto[1]	3402	1			T2	5		T6	2		T5	20
fifo_depth[13]	auto[1]	auto[1]	auto[0]	3102	1			T6	1		T5	2		T42	33
fifo_depth[13]	auto[1]	auto[1]	auto[1]	3357	1			T6	1		T42	20		T56	9
fifo_depth[14]	auto[0]	auto[0]	auto[0]	3984	1			T2	7		T5	4		T12	5
fifo_depth[14]	auto[0]	auto[0]	auto[1]	3725	1			T2	10		T6	4		T12	4
fifo_depth[14]	auto[0]	auto[1]	auto[0]	4498	1			T2	13		T5	2		T12	16
fifo_depth[14]	auto[0]	auto[1]	auto[1]	3141	1			T12	6		T15	44		T77	1
fifo_depth[14]	auto[1]	auto[0]	auto[0]	3937	1			T2	3		T6	2		T42	2
fifo_depth[14]	auto[1]	auto[0]	auto[1]	4113	1			T2	2		T5	5		T42	18
fifo_depth[14]	auto[1]	auto[1]	auto[0]	4235	1			T5	2		T42	23		T56	5
fifo_depth[14]	auto[1]	auto[1]	auto[1]	4240	1			T6	3		T42	7		T56	6
fifo_depth[15]	auto[0]	auto[0]	auto[0]	2420	1			T2	4		T12	1		T15	52
fifo_depth[15]	auto[0]	auto[0]	auto[1]	2213	1			T2	12		T5	1		T12	1
fifo_depth[15]	auto[0]	auto[1]	auto[0]	2843	1			T2	12		T12	3		T15	14
fifo_depth[15]	auto[0]	auto[1]	auto[1]	2257	1			T12	1		T15	42		T77	1
fifo_depth[15]	auto[1]	auto[0]	auto[0]	2260	1			T2	1		T6	1		T42	1
fifo_depth[15]	auto[1]	auto[0]	auto[1]	2462	1			T2	1		T42	6		T56	2
fifo_depth[15]	auto[1]	auto[1]	auto[0]	2371	1			T42	4		T56	1		T12	87
fifo_depth[15]	auto[1]	auto[1]	auto[1]	2700	1			T56	2		T12	5		T22	2
fifo_depth[16]	auto[0]	auto[0]	auto[0]	12684	1			T2	169		T15	88		T25	672
fifo_depth[16]	auto[0]	auto[0]	auto[1]	7790	1			T2	139		T12	2		T25	405
fifo_depth[16]	auto[0]	auto[1]	auto[0]	11185	1			T2	446		T12	4		T119	2
fifo_depth[16]	auto[0]	auto[1]	auto[1]	10832	1			T2	1		T12	2		T15	43
fifo_depth[16]	auto[1]	auto[0]	auto[0]	9599	1			T2	1		T56	1		T109	3
fifo_depth[16]	auto[1]	auto[0]	auto[1]	7131	1			T5	1		T56	3		T12	1
fifo_depth[16]	auto[1]	auto[1]	auto[0]	13460	1			T2	2		T5	1		T42	1
fifo_depth[16]	auto[1]	auto[1]	auto[1]	9952	1			T2	1		T42	2		T23	1