Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	12687206	1			T2	362		T3	38111		T4	258
all_pins[1]	12687206	1			T2	362		T3	38111		T4	258
all_pins[2]	12687206	1			T2	362		T3	38111		T4	258

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	36000949	1			T2	1064		T3	102054		T4	752
values[0x1]	2060669	1			T2	22		T3	12279		T4	22
transitions[0x0=>0x1]	2060539	1			T2	22		T3	12279		T4	22
transitions[0x1=>0x0]	2060558	1			T2	22		T3	12279		T4	22

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	12643063	1			T2	340		T3	37981		T4	236
all_pins[0]	values[0x1]	44143	1			T2	22		T3	130		T4	22
all_pins[0]	transitions[0x0=>0x1]	44085	1			T2	22		T3	130		T4	22
all_pins[0]	transitions[0x1=>0x0]	2016119	1			T3	12147		T14	14		T13	4863
all_pins[1]	values[0x0]	12686838	1			T2	362		T3	38109		T4	258
all_pins[1]	values[0x1]	368	1			T3	2		T20	2		T12	1
all_pins[1]	transitions[0x0=>0x1]	335	1			T3	2		T20	1		T12	1
all_pins[1]	transitions[0x1=>0x0]	44110	1			T2	22		T3	130		T4	22
all_pins[2]	values[0x0]	10671048	1			T2	362		T3	25964		T4	258
all_pins[2]	values[0x1]	2016158	1			T3	12147		T14	14		T13	4863
all_pins[2]	transitions[0x0=>0x1]	2016119	1			T3	12147		T14	14		T13	4863
all_pins[2]	transitions[0x1=>0x0]	329	1			T3	2		T20	2		T12	1