Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	18	0	18	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	18	0	18	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	824	1			T3	14		T20	4		T12	7
all_values[1]	824	1			T3	14		T20	4		T12	7
all_values[2]	824	1			T3	14		T20	4		T12	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1251

1

T3

21

T20

7

T12

13

auto[1]

1221

1

T3

21

T20

5

T12

8

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

894

1

T3

16

T20

4

T12

7

auto[1]

1578

1

T3

26

T20

8

T12

14

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1430

1

T3

25

T20

7

T12

12

auto[1]

1042

1

T3

17

T20

5

T12

9

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	18	0	18	100.00
Automatically Generated Cross Bins	18	0	18	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

181

1

T3

1

T12

1

T49

3

all_values[0]

auto[0]

auto[0]

auto[1]

73

1

T3

1

T20

1

T12

1

all_values[0]

auto[0]

auto[1]

auto[0]

152

1

T12

1

T49

2

T70

1

all_values[0]

auto[0]

auto[1]

auto[1]

79

1

T3

2

T20

1

T12

1

all_values[0]

auto[1]

auto[0]

auto[1]

179

1

T3

5

T20

1

T12

2

all_values[0]

auto[1]

auto[1]

auto[1]

160

1

T3

5

T20

1

T12

1

all_values[1]

auto[0]

auto[0]

auto[0]

117

1

T3

6

T15

1

T7

4

all_values[1]

auto[0]

auto[0]

auto[1]

104

1

T3

1

T20

1

T12

2

all_values[1]

auto[0]

auto[1]

auto[0]

136

1

T3

3

T12

1

T15

1

all_values[1]

auto[0]

auto[1]

auto[1]

109

1

T3

1

T12

1

T15

1

all_values[1]

auto[1]

auto[0]

auto[1]

188

1

T3

1

T20

1

T12

3

all_values[1]

auto[1]

auto[1]

auto[1]

170

1

T3

2

T20

2

T15

4

all_values[2]

auto[0]

auto[0]

auto[0]

156

1

T3

2

T20

3

T12

2

all_values[2]

auto[0]

auto[0]

auto[1]

88

1

T3

3

T15

1

T70

1

all_values[2]

auto[0]

auto[1]

auto[0]

152

1

T3

4

T20

1

T12

2

all_values[2]

auto[0]

auto[1]

auto[1]

83

1

T3

1

T15

2

T49

1

all_values[2]

auto[1]

auto[0]

auto[1]

165

1

T3

1

T12

2

T15

4

all_values[2]

auto[1]

auto[1]

auto[1]

180

1

T3

3

T12

1

T15

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal