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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.58 92.34 85.35 100.00 73.68 86.11 99.49 69.08


Total test records in report: 730
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T535 /workspace/coverage/default/33.hmac_smoke.3152410374 Mar 24 01:02:48 PM PDT 24 Mar 24 01:02:56 PM PDT 24 1152836577 ps
T536 /workspace/coverage/default/10.hmac_smoke.1015021261 Mar 24 01:02:00 PM PDT 24 Mar 24 01:02:06 PM PDT 24 1968672542 ps
T537 /workspace/coverage/default/21.hmac_datapath_stress.4072959046 Mar 24 01:02:15 PM PDT 24 Mar 24 01:03:16 PM PDT 24 1116244608 ps
T538 /workspace/coverage/default/1.hmac_test_sha_vectors.267452526 Mar 24 01:01:21 PM PDT 24 Mar 24 01:09:11 PM PDT 24 150181530891 ps
T539 /workspace/coverage/default/7.hmac_test_sha_vectors.2298450866 Mar 24 01:01:43 PM PDT 24 Mar 24 01:09:40 PM PDT 24 106957975652 ps
T540 /workspace/coverage/default/40.hmac_error.3831637483 Mar 24 01:03:09 PM PDT 24 Mar 24 01:03:34 PM PDT 24 408899760 ps
T541 /workspace/coverage/default/14.hmac_datapath_stress.3039998704 Mar 24 01:01:59 PM PDT 24 Mar 24 01:04:46 PM PDT 24 11977237502 ps
T542 /workspace/coverage/default/0.hmac_test_sha_vectors.3510564018 Mar 24 01:01:21 PM PDT 24 Mar 24 01:10:36 PM PDT 24 183079725749 ps
T65 /workspace/coverage/default/44.hmac_stress_all_with_rand_reset.3644413286 Mar 24 01:03:27 PM PDT 24 Mar 24 01:04:24 PM PDT 24 3245761045 ps
T543 /workspace/coverage/default/37.hmac_burst_wr.2386575574 Mar 24 01:03:00 PM PDT 24 Mar 24 01:03:44 PM PDT 24 3573281592 ps
T544 /workspace/coverage/default/9.hmac_wipe_secret.3744464408 Mar 24 01:01:49 PM PDT 24 Mar 24 01:03:24 PM PDT 24 31246226103 ps
T545 /workspace/coverage/default/9.hmac_stress_all.176454554 Mar 24 01:01:48 PM PDT 24 Mar 24 01:13:55 PM PDT 24 12972302874 ps
T546 /workspace/coverage/default/33.hmac_long_msg.2657175219 Mar 24 01:02:51 PM PDT 24 Mar 24 01:03:47 PM PDT 24 13784888537 ps
T547 /workspace/coverage/default/10.hmac_stress_all.619923413 Mar 24 01:01:54 PM PDT 24 Mar 24 01:08:28 PM PDT 24 7386331221 ps
T548 /workspace/coverage/default/26.hmac_wipe_secret.106978014 Mar 24 01:02:30 PM PDT 24 Mar 24 01:03:20 PM PDT 24 28727329941 ps
T549 /workspace/coverage/default/39.hmac_long_msg.3872656969 Mar 24 01:03:04 PM PDT 24 Mar 24 01:05:01 PM PDT 24 15645576759 ps
T76 /workspace/coverage/default/17.hmac_stress_all.1948233438 Mar 24 01:02:07 PM PDT 24 Mar 24 01:12:55 PM PDT 24 179626879192 ps
T550 /workspace/coverage/default/26.hmac_error.1972652048 Mar 24 01:02:30 PM PDT 24 Mar 24 01:03:25 PM PDT 24 1567907580 ps
T551 /workspace/coverage/default/21.hmac_alert_test.3756707380 Mar 24 01:02:20 PM PDT 24 Mar 24 01:02:21 PM PDT 24 37470071 ps
T552 /workspace/coverage/default/44.hmac_smoke.2405747946 Mar 24 01:03:24 PM PDT 24 Mar 24 01:03:28 PM PDT 24 152469735 ps
T553 /workspace/coverage/default/10.hmac_datapath_stress.3926246834 Mar 24 01:01:55 PM PDT 24 Mar 24 01:02:26 PM PDT 24 1010304734 ps
T554 /workspace/coverage/default/2.hmac_error.3143347947 Mar 24 01:01:25 PM PDT 24 Mar 24 01:03:14 PM PDT 24 2052638540 ps
T555 /workspace/coverage/default/35.hmac_test_sha_vectors.771835687 Mar 24 01:03:04 PM PDT 24 Mar 24 01:10:12 PM PDT 24 32134015943 ps
T556 /workspace/coverage/default/13.hmac_wipe_secret.1967977800 Mar 24 01:02:00 PM PDT 24 Mar 24 01:03:40 PM PDT 24 19503790717 ps
T557 /workspace/coverage/default/14.hmac_burst_wr.3780672915 Mar 24 01:01:58 PM PDT 24 Mar 24 01:02:45 PM PDT 24 3277878837 ps
T558 /workspace/coverage/default/10.hmac_long_msg.3476590870 Mar 24 01:01:56 PM PDT 24 Mar 24 01:02:59 PM PDT 24 3208744319 ps
T559 /workspace/coverage/default/22.hmac_datapath_stress.3062139940 Mar 24 01:02:20 PM PDT 24 Mar 24 01:02:42 PM PDT 24 392896781 ps
T560 /workspace/coverage/default/32.hmac_back_pressure.2293414476 Mar 24 01:02:44 PM PDT 24 Mar 24 01:03:02 PM PDT 24 1458404648 ps
T561 /workspace/coverage/default/17.hmac_test_sha_vectors.493890857 Mar 24 01:02:08 PM PDT 24 Mar 24 01:10:22 PM PDT 24 28391986439 ps
T562 /workspace/coverage/default/9.hmac_alert_test.2092078487 Mar 24 01:01:52 PM PDT 24 Mar 24 01:01:52 PM PDT 24 35881750 ps
T563 /workspace/coverage/default/32.hmac_error.2213776650 Mar 24 01:02:42 PM PDT 24 Mar 24 01:04:49 PM PDT 24 37629399265 ps
T564 /workspace/coverage/default/47.hmac_stress_all.2434572525 Mar 24 01:03:31 PM PDT 24 Mar 24 01:10:48 PM PDT 24 7822003561 ps
T565 /workspace/coverage/default/23.hmac_back_pressure.1356927329 Mar 24 01:02:23 PM PDT 24 Mar 24 01:02:33 PM PDT 24 655007349 ps
T566 /workspace/coverage/default/1.hmac_long_msg.1574825420 Mar 24 01:01:20 PM PDT 24 Mar 24 01:02:09 PM PDT 24 9895747240 ps
T567 /workspace/coverage/default/19.hmac_datapath_stress.929112133 Mar 24 01:02:14 PM PDT 24 Mar 24 01:03:16 PM PDT 24 2076478197 ps
T568 /workspace/coverage/default/8.hmac_test_hmac_vectors.4166846270 Mar 24 01:01:47 PM PDT 24 Mar 24 01:01:49 PM PDT 24 223727027 ps
T569 /workspace/coverage/default/24.hmac_test_sha_vectors.82523744 Mar 24 01:02:27 PM PDT 24 Mar 24 01:11:18 PM PDT 24 153111453844 ps
T570 /workspace/coverage/default/0.hmac_long_msg.1647403576 Mar 24 01:01:15 PM PDT 24 Mar 24 01:02:54 PM PDT 24 4943199208 ps
T571 /workspace/coverage/default/45.hmac_error.708838048 Mar 24 01:03:27 PM PDT 24 Mar 24 01:04:55 PM PDT 24 3440832619 ps
T572 /workspace/coverage/default/38.hmac_back_pressure.1398356263 Mar 24 01:03:06 PM PDT 24 Mar 24 01:03:44 PM PDT 24 4660364881 ps
T573 /workspace/coverage/default/10.hmac_burst_wr.3240850401 Mar 24 01:01:51 PM PDT 24 Mar 24 01:02:30 PM PDT 24 2561045321 ps
T574 /workspace/coverage/default/32.hmac_wipe_secret.3269484977 Mar 24 01:03:04 PM PDT 24 Mar 24 01:03:59 PM PDT 24 6144308732 ps
T575 /workspace/coverage/default/13.hmac_datapath_stress.3625907050 Mar 24 01:01:58 PM PDT 24 Mar 24 01:03:55 PM PDT 24 2113199608 ps
T576 /workspace/coverage/default/41.hmac_alert_test.326538157 Mar 24 01:03:15 PM PDT 24 Mar 24 01:03:16 PM PDT 24 40095820 ps
T577 /workspace/coverage/default/27.hmac_datapath_stress.1748159123 Mar 24 01:02:31 PM PDT 24 Mar 24 01:04:12 PM PDT 24 2083120731 ps
T578 /workspace/coverage/default/34.hmac_burst_wr.253392898 Mar 24 01:02:50 PM PDT 24 Mar 24 01:03:23 PM PDT 24 3965387716 ps
T579 /workspace/coverage/default/15.hmac_test_hmac_vectors.2670134487 Mar 24 01:02:05 PM PDT 24 Mar 24 01:02:06 PM PDT 24 38551656 ps
T580 /workspace/coverage/default/9.hmac_datapath_stress.3859106471 Mar 24 01:01:51 PM PDT 24 Mar 24 01:03:34 PM PDT 24 1905651114 ps
T581 /workspace/coverage/default/19.hmac_burst_wr.2920502989 Mar 24 01:02:15 PM PDT 24 Mar 24 01:02:46 PM PDT 24 645741916 ps
T582 /workspace/coverage/default/15.hmac_datapath_stress.1511304358 Mar 24 01:02:06 PM PDT 24 Mar 24 01:03:37 PM PDT 24 1581489793 ps
T583 /workspace/coverage/default/39.hmac_error.3615525358 Mar 24 01:03:07 PM PDT 24 Mar 24 01:03:48 PM PDT 24 1505180331 ps
T584 /workspace/coverage/default/34.hmac_alert_test.633798107 Mar 24 01:02:55 PM PDT 24 Mar 24 01:02:55 PM PDT 24 121762311 ps
T585 /workspace/coverage/default/49.hmac_burst_wr.803105740 Mar 24 01:03:44 PM PDT 24 Mar 24 01:04:03 PM PDT 24 1781013300 ps
T586 /workspace/coverage/default/8.hmac_datapath_stress.2142017056 Mar 24 01:01:47 PM PDT 24 Mar 24 01:02:08 PM PDT 24 4204531773 ps
T587 /workspace/coverage/default/37.hmac_error.573537547 Mar 24 01:03:01 PM PDT 24 Mar 24 01:04:16 PM PDT 24 8502465099 ps
T588 /workspace/coverage/default/1.hmac_wipe_secret.1395404984 Mar 24 01:01:21 PM PDT 24 Mar 24 01:01:54 PM PDT 24 4387898733 ps
T589 /workspace/coverage/default/2.hmac_datapath_stress.1187464545 Mar 24 01:01:29 PM PDT 24 Mar 24 01:03:20 PM PDT 24 7251262188 ps
T590 /workspace/coverage/default/3.hmac_stress_all.1664619274 Mar 24 01:01:32 PM PDT 24 Mar 24 01:03:46 PM PDT 24 4838531906 ps
T591 /workspace/coverage/default/25.hmac_wipe_secret.2150816957 Mar 24 01:02:27 PM PDT 24 Mar 24 01:02:40 PM PDT 24 229358971 ps
T592 /workspace/coverage/default/41.hmac_back_pressure.1835688043 Mar 24 01:03:22 PM PDT 24 Mar 24 01:04:14 PM PDT 24 1077094115 ps
T593 /workspace/coverage/default/14.hmac_back_pressure.3802799224 Mar 24 01:01:57 PM PDT 24 Mar 24 01:02:32 PM PDT 24 4590270577 ps
T50 /workspace/coverage/default/48.hmac_error.332207708 Mar 24 01:03:39 PM PDT 24 Mar 24 01:05:57 PM PDT 24 30988200585 ps
T594 /workspace/coverage/default/35.hmac_stress_all.4061236722 Mar 24 01:02:54 PM PDT 24 Mar 24 01:18:07 PM PDT 24 16670083960 ps
T595 /workspace/coverage/default/45.hmac_long_msg.2271999659 Mar 24 01:03:26 PM PDT 24 Mar 24 01:04:29 PM PDT 24 5477132352 ps
T596 /workspace/coverage/default/2.hmac_test_hmac_vectors.1296470681 Mar 24 01:01:26 PM PDT 24 Mar 24 01:01:27 PM PDT 24 347823454 ps
T57 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3805767869 Mar 24 12:20:56 PM PDT 24 Mar 24 12:20:59 PM PDT 24 310032722 ps
T60 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2193906776 Mar 24 12:20:08 PM PDT 24 Mar 24 12:32:21 PM PDT 24 519086194173 ps
T61 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.909041577 Mar 24 12:19:49 PM PDT 24 Mar 24 12:19:50 PM PDT 24 201325066 ps
T597 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.4098816016 Mar 24 12:21:56 PM PDT 24 Mar 24 12:21:57 PM PDT 24 15054557 ps
T598 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.195444715 Mar 24 12:21:19 PM PDT 24 Mar 24 12:21:22 PM PDT 24 736902674 ps
T599 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.948983284 Mar 24 12:21:57 PM PDT 24 Mar 24 12:30:51 PM PDT 24 206106074957 ps
T600 /workspace/coverage/cover_reg_top/30.hmac_intr_test.517161783 Mar 24 12:22:37 PM PDT 24 Mar 24 12:22:37 PM PDT 24 37435236 ps
T601 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3535152239 Mar 24 12:20:19 PM PDT 24 Mar 24 12:20:21 PM PDT 24 139945404 ps
T602 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.955501094 Mar 24 12:19:18 PM PDT 24 Mar 24 12:19:23 PM PDT 24 202916999 ps
T58 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1469910254 Mar 24 12:21:40 PM PDT 24 Mar 24 12:21:43 PM PDT 24 773211814 ps
T92 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.719953298 Mar 24 12:21:54 PM PDT 24 Mar 24 12:21:55 PM PDT 24 23979598 ps
T603 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1570543933 Mar 24 12:19:20 PM PDT 24 Mar 24 12:19:23 PM PDT 24 149604562 ps
T604 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3200543110 Mar 24 12:21:04 PM PDT 24 Mar 24 12:21:10 PM PDT 24 436964067 ps
T605 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3370689044 Mar 24 12:22:31 PM PDT 24 Mar 24 12:22:33 PM PDT 24 75100756 ps
T59 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2491894379 Mar 24 12:19:43 PM PDT 24 Mar 24 12:19:45 PM PDT 24 122036503 ps
T606 /workspace/coverage/cover_reg_top/11.hmac_intr_test.3521689917 Mar 24 12:21:56 PM PDT 24 Mar 24 12:21:57 PM PDT 24 39217635 ps
T607 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.652908067 Mar 24 12:21:04 PM PDT 24 Mar 24 12:21:06 PM PDT 24 44559802 ps
T608 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3292078212 Mar 24 12:20:45 PM PDT 24 Mar 24 12:20:47 PM PDT 24 81880560 ps
T609 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2875646979 Mar 24 12:22:10 PM PDT 24 Mar 24 12:22:11 PM PDT 24 13282489 ps
T93 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.4015045244 Mar 24 12:19:09 PM PDT 24 Mar 24 12:19:15 PM PDT 24 109416380 ps
T610 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1941807956 Mar 24 12:19:18 PM PDT 24 Mar 24 12:19:20 PM PDT 24 172140427 ps
T611 /workspace/coverage/cover_reg_top/9.hmac_intr_test.1190264287 Mar 24 12:21:57 PM PDT 24 Mar 24 12:21:58 PM PDT 24 58219560 ps
T612 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2814780362 Mar 24 12:20:22 PM PDT 24 Mar 24 12:20:22 PM PDT 24 11842592 ps
T111 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1446514809 Mar 24 12:19:45 PM PDT 24 Mar 24 12:19:47 PM PDT 24 99400694 ps
T613 /workspace/coverage/cover_reg_top/14.hmac_intr_test.2889452806 Mar 24 12:20:01 PM PDT 24 Mar 24 12:20:03 PM PDT 24 37543035 ps
T614 /workspace/coverage/cover_reg_top/47.hmac_intr_test.3077298718 Mar 24 12:20:34 PM PDT 24 Mar 24 12:20:35 PM PDT 24 13328761 ps
T615 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2863048766 Mar 24 12:19:38 PM PDT 24 Mar 24 12:19:41 PM PDT 24 150694693 ps
T616 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3207560079 Mar 24 12:19:51 PM PDT 24 Mar 24 12:19:52 PM PDT 24 15781404 ps
T617 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2551050280 Mar 24 12:19:18 PM PDT 24 Mar 24 12:19:21 PM PDT 24 35461825 ps
T94 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.4067573379 Mar 24 12:20:56 PM PDT 24 Mar 24 12:21:02 PM PDT 24 224823419 ps
T110 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3356066015 Mar 24 12:22:04 PM PDT 24 Mar 24 12:22:08 PM PDT 24 231133712 ps
T618 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2968221832 Mar 24 12:20:57 PM PDT 24 Mar 24 12:21:00 PM PDT 24 324736785 ps
T619 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1736985061 Mar 24 12:22:01 PM PDT 24 Mar 24 12:22:03 PM PDT 24 114676625 ps
T620 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.10249167 Mar 24 12:21:43 PM PDT 24 Mar 24 12:21:44 PM PDT 24 288088295 ps
T95 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1216462264 Mar 24 12:21:08 PM PDT 24 Mar 24 12:21:12 PM PDT 24 163358569 ps
T621 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1294110329 Mar 24 12:21:40 PM PDT 24 Mar 24 12:21:42 PM PDT 24 45173208 ps
T114 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2360605876 Mar 24 12:21:24 PM PDT 24 Mar 24 12:21:29 PM PDT 24 134102438 ps
T622 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.769761163 Mar 24 12:20:05 PM PDT 24 Mar 24 12:20:08 PM PDT 24 260175763 ps
T623 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3165836419 Mar 24 12:20:08 PM PDT 24 Mar 24 12:20:09 PM PDT 24 13367134 ps
T112 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2437583272 Mar 24 12:22:44 PM PDT 24 Mar 24 12:22:47 PM PDT 24 311495408 ps
T96 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.239884708 Mar 24 12:19:09 PM PDT 24 Mar 24 12:19:10 PM PDT 24 20363255 ps
T113 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1972167493 Mar 24 12:20:34 PM PDT 24 Mar 24 12:20:39 PM PDT 24 267987453 ps
T624 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2847468535 Mar 24 12:21:40 PM PDT 24 Mar 24 12:21:44 PM PDT 24 748477709 ps
T625 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.217364072 Mar 24 12:21:18 PM PDT 24 Mar 24 12:21:22 PM PDT 24 150988164 ps
T626 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3993093701 Mar 24 12:21:46 PM PDT 24 Mar 24 12:21:47 PM PDT 24 117181876 ps
T627 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2477650926 Mar 24 12:19:48 PM PDT 24 Mar 24 12:19:49 PM PDT 24 53847401 ps
T628 /workspace/coverage/cover_reg_top/36.hmac_intr_test.161555071 Mar 24 12:22:43 PM PDT 24 Mar 24 12:22:43 PM PDT 24 32665504 ps
T629 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3784633246 Mar 24 12:22:51 PM PDT 24 Mar 24 12:23:02 PM PDT 24 24794850 ps
T97 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2271138178 Mar 24 12:19:39 PM PDT 24 Mar 24 12:19:40 PM PDT 24 30186880 ps
T630 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3627105346 Mar 24 12:21:56 PM PDT 24 Mar 24 12:32:53 PM PDT 24 302524148442 ps
T98 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3316272591 Mar 24 12:22:04 PM PDT 24 Mar 24 12:22:05 PM PDT 24 14057084 ps
T631 /workspace/coverage/cover_reg_top/44.hmac_intr_test.703160953 Mar 24 12:20:33 PM PDT 24 Mar 24 12:20:34 PM PDT 24 14024048 ps
T99 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1484049273 Mar 24 12:20:08 PM PDT 24 Mar 24 12:20:10 PM PDT 24 27616080 ps
T632 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3891145487 Mar 24 12:20:34 PM PDT 24 Mar 24 12:20:35 PM PDT 24 17703233 ps
T100 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1248748071 Mar 24 12:19:06 PM PDT 24 Mar 24 12:19:07 PM PDT 24 16734375 ps
T116 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2212485625 Mar 24 12:20:54 PM PDT 24 Mar 24 12:20:56 PM PDT 24 84085443 ps
T633 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4019039423 Mar 24 12:21:22 PM PDT 24 Mar 24 12:21:26 PM PDT 24 55034481 ps
T634 /workspace/coverage/cover_reg_top/28.hmac_intr_test.3495375102 Mar 24 12:21:56 PM PDT 24 Mar 24 12:21:57 PM PDT 24 19271549 ps
T635 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3072500210 Mar 24 12:21:20 PM PDT 24 Mar 24 12:21:21 PM PDT 24 200751795 ps
T636 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.669454961 Mar 24 12:20:53 PM PDT 24 Mar 24 12:20:55 PM PDT 24 65719775 ps
T637 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1828843400 Mar 24 12:19:49 PM PDT 24 Mar 24 12:19:51 PM PDT 24 251130361 ps
T101 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1392772860 Mar 24 12:20:09 PM PDT 24 Mar 24 12:20:11 PM PDT 24 13563312 ps
T638 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1862970567 Mar 24 12:20:03 PM PDT 24 Mar 24 12:20:05 PM PDT 24 32982086 ps
T639 /workspace/coverage/cover_reg_top/33.hmac_intr_test.1284849972 Mar 24 12:22:35 PM PDT 24 Mar 24 12:22:36 PM PDT 24 47326550 ps
T640 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1662402384 Mar 24 12:22:15 PM PDT 24 Mar 24 12:22:16 PM PDT 24 14110028 ps
T641 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1811513072 Mar 24 12:22:00 PM PDT 24 Mar 24 12:22:02 PM PDT 24 292022735 ps
T642 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1981142975 Mar 24 12:20:23 PM PDT 24 Mar 24 12:20:24 PM PDT 24 16423929 ps
T643 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.126156981 Mar 24 12:20:19 PM PDT 24 Mar 24 12:20:20 PM PDT 24 78406545 ps
T644 /workspace/coverage/cover_reg_top/29.hmac_intr_test.3309096834 Mar 24 12:20:23 PM PDT 24 Mar 24 12:20:24 PM PDT 24 112423291 ps
T645 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3213563012 Mar 24 12:20:29 PM PDT 24 Mar 24 12:20:30 PM PDT 24 43872234 ps
T115 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.712543650 Mar 24 12:21:40 PM PDT 24 Mar 24 12:21:44 PM PDT 24 341816641 ps
T103 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3640515069 Mar 24 12:19:49 PM PDT 24 Mar 24 12:20:04 PM PDT 24 311053543 ps
T646 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.4294947220 Mar 24 12:20:10 PM PDT 24 Mar 24 12:20:13 PM PDT 24 81665109 ps
T647 /workspace/coverage/cover_reg_top/22.hmac_intr_test.404950420 Mar 24 12:20:20 PM PDT 24 Mar 24 12:20:20 PM PDT 24 50857477 ps
T648 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1313386812 Mar 24 12:22:02 PM PDT 24 Mar 24 12:22:05 PM PDT 24 221426736 ps
T102 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3496200775 Mar 24 12:20:53 PM PDT 24 Mar 24 12:20:59 PM PDT 24 314865590 ps
T649 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.243766049 Mar 24 12:20:03 PM PDT 24 Mar 24 12:20:07 PM PDT 24 298640318 ps
T650 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3555528978 Mar 24 12:20:57 PM PDT 24 Mar 24 12:21:02 PM PDT 24 1447198302 ps
T651 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2500755028 Mar 24 12:22:59 PM PDT 24 Mar 24 12:23:00 PM PDT 24 14065362 ps
T104 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.885419470 Mar 24 12:20:09 PM PDT 24 Mar 24 12:20:11 PM PDT 24 134597255 ps
T117 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.565321590 Mar 24 12:19:28 PM PDT 24 Mar 24 12:19:30 PM PDT 24 95082366 ps
T652 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1893291338 Mar 24 12:22:38 PM PDT 24 Mar 24 12:22:39 PM PDT 24 31405110 ps
T653 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1442998237 Mar 24 12:20:02 PM PDT 24 Mar 24 12:20:05 PM PDT 24 333664324 ps
T654 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2726727926 Mar 24 12:19:49 PM PDT 24 Mar 24 12:19:50 PM PDT 24 167678614 ps
T655 /workspace/coverage/cover_reg_top/10.hmac_intr_test.356511247 Mar 24 12:22:09 PM PDT 24 Mar 24 12:22:09 PM PDT 24 12826904 ps
T656 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2367588861 Mar 24 12:20:32 PM PDT 24 Mar 24 12:20:33 PM PDT 24 35175277 ps
T657 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4112869458 Mar 24 12:21:08 PM PDT 24 Mar 24 12:21:10 PM PDT 24 118873614 ps
T118 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1949241249 Mar 24 12:20:04 PM PDT 24 Mar 24 12:20:08 PM PDT 24 154154812 ps
T658 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3102765183 Mar 24 12:20:05 PM PDT 24 Mar 24 12:20:09 PM PDT 24 394581736 ps
T659 /workspace/coverage/cover_reg_top/35.hmac_intr_test.4186408189 Mar 24 12:22:47 PM PDT 24 Mar 24 12:22:48 PM PDT 24 43096104 ps
T660 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.832408133 Mar 24 12:20:38 PM PDT 24 Mar 24 12:20:39 PM PDT 24 110634005 ps
T661 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.512160919 Mar 24 12:22:09 PM PDT 24 Mar 24 12:27:35 PM PDT 24 91713058697 ps
T662 /workspace/coverage/cover_reg_top/48.hmac_intr_test.1064511811 Mar 24 12:20:38 PM PDT 24 Mar 24 12:20:38 PM PDT 24 16391720 ps
T663 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3442570462 Mar 24 12:22:51 PM PDT 24 Mar 24 12:22:54 PM PDT 24 96174374 ps
T664 /workspace/coverage/cover_reg_top/4.hmac_intr_test.1640864551 Mar 24 12:20:38 PM PDT 24 Mar 24 12:20:39 PM PDT 24 37525526 ps
T665 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2468550479 Mar 24 12:21:47 PM PDT 24 Mar 24 12:21:48 PM PDT 24 33142057 ps
T666 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1259997122 Mar 24 12:21:08 PM PDT 24 Mar 24 12:21:14 PM PDT 24 605147197 ps
T667 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2824839541 Mar 24 12:21:47 PM PDT 24 Mar 24 12:21:49 PM PDT 24 28316548 ps
T668 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3179830125 Mar 24 12:22:04 PM PDT 24 Mar 24 12:22:05 PM PDT 24 22566326 ps
T669 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1042610604 Mar 24 12:23:13 PM PDT 24 Mar 24 12:23:14 PM PDT 24 103971366 ps
T105 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2386681867 Mar 24 12:21:41 PM PDT 24 Mar 24 12:21:42 PM PDT 24 39198389 ps
T670 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1439573391 Mar 24 12:20:26 PM PDT 24 Mar 24 12:20:27 PM PDT 24 20995577 ps
T671 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.955541717 Mar 24 12:21:57 PM PDT 24 Mar 24 12:21:59 PM PDT 24 37108037 ps
T672 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1151900623 Mar 24 12:22:05 PM PDT 24 Mar 24 12:22:07 PM PDT 24 122110725 ps
T673 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.368655018 Mar 24 12:20:09 PM PDT 24 Mar 24 12:20:12 PM PDT 24 33667636 ps
T674 /workspace/coverage/cover_reg_top/40.hmac_intr_test.807690323 Mar 24 12:20:34 PM PDT 24 Mar 24 12:20:35 PM PDT 24 14474117 ps
T675 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3243892056 Mar 24 12:21:44 PM PDT 24 Mar 24 12:21:46 PM PDT 24 50529174 ps
T676 /workspace/coverage/cover_reg_top/38.hmac_intr_test.4218003140 Mar 24 12:20:36 PM PDT 24 Mar 24 12:20:37 PM PDT 24 15568650 ps
T677 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2945940798 Mar 24 12:21:34 PM PDT 24 Mar 24 12:21:36 PM PDT 24 598271298 ps
T678 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3286539755 Mar 24 12:21:41 PM PDT 24 Mar 24 12:21:43 PM PDT 24 342126609 ps
T679 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1624778449 Mar 24 12:20:03 PM PDT 24 Mar 24 12:20:06 PM PDT 24 80722881 ps
T680 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3979533679 Mar 24 12:21:44 PM PDT 24 Mar 24 12:21:46 PM PDT 24 1534963046 ps
T681 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.195677826 Mar 24 12:22:05 PM PDT 24 Mar 24 12:22:05 PM PDT 24 26963148 ps
T682 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3584812855 Mar 24 12:20:34 PM PDT 24 Mar 24 12:20:37 PM PDT 24 45564918 ps
T683 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1041952424 Mar 24 12:20:08 PM PDT 24 Mar 24 12:20:13 PM PDT 24 153962749 ps
T684 /workspace/coverage/cover_reg_top/15.hmac_intr_test.176260296 Mar 24 12:21:24 PM PDT 24 Mar 24 12:21:25 PM PDT 24 23986341 ps
T685 /workspace/coverage/cover_reg_top/41.hmac_intr_test.3485514101 Mar 24 12:20:34 PM PDT 24 Mar 24 12:20:35 PM PDT 24 28971370 ps
T686 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2206474654 Mar 24 12:20:32 PM PDT 24 Mar 24 12:20:33 PM PDT 24 45132864 ps
T687 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1418627250 Mar 24 12:19:51 PM PDT 24 Mar 24 12:19:55 PM PDT 24 585668634 ps
T688 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.205381598 Mar 24 12:21:48 PM PDT 24 Mar 24 12:21:49 PM PDT 24 92152970 ps
T689 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1850924724 Mar 24 12:22:50 PM PDT 24 Mar 24 12:22:51 PM PDT 24 47299377 ps
T690 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.822783163 Mar 24 12:19:56 PM PDT 24 Mar 24 12:19:57 PM PDT 24 26371463 ps
T691 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.629952642 Mar 24 12:19:07 PM PDT 24 Mar 24 12:19:12 PM PDT 24 270141188 ps
T692 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1180404531 Mar 24 12:20:01 PM PDT 24 Mar 24 12:20:03 PM PDT 24 40159096 ps
T693 /workspace/coverage/cover_reg_top/46.hmac_intr_test.1847464945 Mar 24 12:20:25 PM PDT 24 Mar 24 12:20:26 PM PDT 24 13115493 ps
T694 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1980951334 Mar 24 12:19:37 PM PDT 24 Mar 24 12:19:40 PM PDT 24 88404206 ps
T695 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.804058899 Mar 24 12:21:08 PM PDT 24 Mar 24 12:21:10 PM PDT 24 509455981 ps
T696 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.589763046 Mar 24 12:21:45 PM PDT 24 Mar 24 12:21:47 PM PDT 24 470653738 ps
T697 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2626405647 Mar 24 12:19:20 PM PDT 24 Mar 24 12:19:21 PM PDT 24 71631390 ps
T698 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2758084856 Mar 24 12:21:22 PM PDT 24 Mar 24 12:21:23 PM PDT 24 47010608 ps
T699 /workspace/coverage/cover_reg_top/5.hmac_intr_test.184459385 Mar 24 12:20:53 PM PDT 24 Mar 24 12:20:54 PM PDT 24 17480255 ps
T700 /workspace/coverage/cover_reg_top/3.hmac_intr_test.3151051161 Mar 24 12:19:18 PM PDT 24 Mar 24 12:19:19 PM PDT 24 40731557 ps
T701 /workspace/coverage/cover_reg_top/8.hmac_intr_test.993906875 Mar 24 12:21:58 PM PDT 24 Mar 24 12:21:59 PM PDT 24 56233201 ps
T702 /workspace/coverage/cover_reg_top/25.hmac_intr_test.74212710 Mar 24 12:20:27 PM PDT 24 Mar 24 12:20:28 PM PDT 24 15642541 ps
T703 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.366558338 Mar 24 12:21:59 PM PDT 24 Mar 24 12:22:04 PM PDT 24 2404152211 ps
T704 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3526925003 Mar 24 12:22:09 PM PDT 24 Mar 24 12:22:12 PM PDT 24 663080889 ps
T705 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.4183338234 Mar 24 12:21:40 PM PDT 24 Mar 24 12:21:42 PM PDT 24 124161982 ps
T706 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.833018588 Mar 24 12:21:44 PM PDT 24 Mar 24 12:21:45 PM PDT 24 39567640 ps
T707 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.252044552 Mar 24 12:19:38 PM PDT 24 Mar 24 12:19:41 PM PDT 24 431046259 ps
T708 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1046939710 Mar 24 12:22:47 PM PDT 24 Mar 24 12:22:48 PM PDT 24 17795997 ps
T709 /workspace/coverage/cover_reg_top/24.hmac_intr_test.2342995240 Mar 24 12:22:27 PM PDT 24 Mar 24 12:22:28 PM PDT 24 23571449 ps
T710 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1037874431 Mar 24 12:19:19 PM PDT 24 Mar 24 12:19:20 PM PDT 24 58609257 ps
T711 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.988617706 Mar 24 12:20:01 PM PDT 24 Mar 24 12:20:02 PM PDT 24 175086319 ps
T712 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1174021150 Mar 24 12:21:56 PM PDT 24 Mar 24 12:21:57 PM PDT 24 144046635 ps
T713 /workspace/coverage/cover_reg_top/6.hmac_intr_test.2635044534 Mar 24 12:22:09 PM PDT 24 Mar 24 12:22:09 PM PDT 24 31386536 ps
T714 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2382759792 Mar 24 12:19:38 PM PDT 24 Mar 24 12:24:10 PM PDT 24 285401322725 ps
T715 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.142834435 Mar 24 12:19:51 PM PDT 24 Mar 24 12:19:54 PM PDT 24 120568033 ps
T716 /workspace/coverage/cover_reg_top/21.hmac_intr_test.826839618 Mar 24 12:22:35 PM PDT 24 Mar 24 12:22:36 PM PDT 24 12986490 ps
T717 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.524725544 Mar 24 12:20:08 PM PDT 24 Mar 24 12:20:11 PM PDT 24 147462355 ps
T718 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2813950333 Mar 24 12:19:07 PM PDT 24 Mar 24 12:19:11 PM PDT 24 56228669 ps
T719 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1816552493 Mar 24 12:21:46 PM PDT 24 Mar 24 12:21:51 PM PDT 24 355169025 ps
T106 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3507343616 Mar 24 12:20:53 PM PDT 24 Mar 24 12:20:54 PM PDT 24 20443133 ps
T720 /workspace/coverage/cover_reg_top/37.hmac_intr_test.797367946 Mar 24 12:20:20 PM PDT 24 Mar 24 12:20:21 PM PDT 24 27296879 ps
T721 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3955646555 Mar 24 12:22:36 PM PDT 24 Mar 24 12:22:37 PM PDT 24 32532413 ps
T722 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3884026654 Mar 24 12:20:31 PM PDT 24 Mar 24 12:20:34 PM PDT 24 187840578 ps
T107 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1976916504 Mar 24 12:19:11 PM PDT 24 Mar 24 12:19:17 PM PDT 24 2129486430 ps
T723 /workspace/coverage/cover_reg_top/17.hmac_intr_test.1024637068 Mar 24 12:20:08 PM PDT 24 Mar 24 12:20:10 PM PDT 24 12956707 ps
T724 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2686641447 Mar 24 12:20:55 PM PDT 24 Mar 24 12:20:56 PM PDT 24 64446271 ps
T725 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.496071140 Mar 24 12:20:10 PM PDT 24 Mar 24 12:20:14 PM PDT 24 243453518 ps
T726 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1818239505 Mar 24 12:22:42 PM PDT 24 Mar 24 12:22:45 PM PDT 24 784747932 ps
T727 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1418516269 Mar 24 12:19:49 PM PDT 24 Mar 24 12:19:50 PM PDT 24 65409769 ps
T108 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.528271765 Mar 24 12:20:10 PM PDT 24 Mar 24 12:20:12 PM PDT 24 88815334 ps
T728 /workspace/coverage/cover_reg_top/23.hmac_intr_test.3434829146 Mar 24 12:20:34 PM PDT 24 Mar 24 12:20:35 PM PDT 24 50053196 ps
T729 /workspace/coverage/cover_reg_top/19.hmac_intr_test.907040395 Mar 24 12:20:19 PM PDT 24 Mar 24 12:20:20 PM PDT 24 45660815 ps
T730 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1277703822 Mar 24 12:21:08 PM PDT 24 Mar 24 12:21:09 PM PDT 24 76287065 ps

Test location /workspace/coverage/default/38.hmac_wipe_secret.1671196296
Short name T21
Test name
Test status
Simulation time 8762648936 ps
CPU time 24.77 seconds
Started Mar 24 01:03:07 PM PDT 24
Finished Mar 24 01:03:32 PM PDT 24
Peak memory 200080 kb
Host smart-8df2862e-d2d0-41aa-b609-74cb84c5f786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671196296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1671196296
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_stress_all_with_rand_reset.996986745
Short name T7
Test name
Test status
Simulation time 105281417198 ps
CPU time 2249.94 seconds
Started Mar 24 01:03:05 PM PDT 24
Finished Mar 24 01:40:35 PM PDT 24
Peak memory 249204 kb
Host smart-4f9dd7a0-1759-4566-8639-674c387cf2c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=996986745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all_with_rand_reset.996986745
Directory /workspace/39.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.hmac_stress_all.2916377045
Short name T12
Test name
Test status
Simulation time 25298828907 ps
CPU time 1389.05 seconds
Started Mar 24 01:03:16 PM PDT 24
Finished Mar 24 01:26:26 PM PDT 24
Peak memory 241052 kb
Host smart-dd86e9c4-d01c-4ebf-b01d-82426689c7c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916377045 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2916377045
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2081806284
Short name T29
Test name
Test status
Simulation time 64965308 ps
CPU time 0.92 seconds
Started Mar 24 01:01:36 PM PDT 24
Finished Mar 24 01:01:37 PM PDT 24
Peak memory 218200 kb
Host smart-6580e931-e910-449b-80db-a1a5f3074205
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081806284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2081806284
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3805767869
Short name T57
Test name
Test status
Simulation time 310032722 ps
CPU time 1.73 seconds
Started Mar 24 12:20:56 PM PDT 24
Finished Mar 24 12:20:59 PM PDT 24
Peak memory 198996 kb
Host smart-50780a9b-d68f-4fb2-b934-ed28301874dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805767869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3805767869
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/15.hmac_stress_all_with_rand_reset.2332531195
Short name T10
Test name
Test status
Simulation time 74108671776 ps
CPU time 487.05 seconds
Started Mar 24 01:02:05 PM PDT 24
Finished Mar 24 01:10:12 PM PDT 24
Peak memory 209296 kb
Host smart-2f31e159-f268-49fa-a5a6-b945588bd5bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2332531195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all_with_rand_reset.2332531195
Directory /workspace/15.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.4015045244
Short name T93
Test name
Test status
Simulation time 109416380 ps
CPU time 5.59 seconds
Started Mar 24 12:19:09 PM PDT 24
Finished Mar 24 12:19:15 PM PDT 24
Peak memory 198376 kb
Host smart-e9938806-385b-4669-8c30-a975800f7e2c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015045244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.4015045244
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/default/23.hmac_stress_all.1523020618
Short name T27
Test name
Test status
Simulation time 32102257744 ps
CPU time 468.61 seconds
Started Mar 24 01:02:30 PM PDT 24
Finished Mar 24 01:10:19 PM PDT 24
Peak memory 232856 kb
Host smart-a94e3957-0b89-4a0e-927d-78b1da29e5cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523020618 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1523020618
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.712543650
Short name T115
Test name
Test status
Simulation time 341816641 ps
CPU time 3.07 seconds
Started Mar 24 12:21:40 PM PDT 24
Finished Mar 24 12:21:44 PM PDT 24
Peak memory 196620 kb
Host smart-4e656aa2-04b3-4b91-b3a9-57ccddbe66b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712543650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.712543650
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2288760853
Short name T17
Test name
Test status
Simulation time 20386478 ps
CPU time 0.62 seconds
Started Mar 24 01:01:52 PM PDT 24
Finished Mar 24 01:01:53 PM PDT 24
Peak memory 195508 kb
Host smart-ea41f8a6-9a13-4593-ad3a-5deb659b99c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288760853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2288760853
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1446514809
Short name T111
Test name
Test status
Simulation time 99400694 ps
CPU time 2.07 seconds
Started Mar 24 12:19:45 PM PDT 24
Finished Mar 24 12:19:47 PM PDT 24
Peak memory 199548 kb
Host smart-cb4a5db8-6da1-4c1a-99d6-2e6c10035aec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446514809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1446514809
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3425932833
Short name T5
Test name
Test status
Simulation time 2235573228 ps
CPU time 66.51 seconds
Started Mar 24 01:02:05 PM PDT 24
Finished Mar 24 01:03:12 PM PDT 24
Peak memory 200068 kb
Host smart-8876e093-1d73-40ff-88b9-eea5e3ad537f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425932833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3425932833
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1949241249
Short name T118
Test name
Test status
Simulation time 154154812 ps
CPU time 4.17 seconds
Started Mar 24 12:20:04 PM PDT 24
Finished Mar 24 12:20:08 PM PDT 24
Peak memory 199548 kb
Host smart-e75e9a92-9e12-4dfb-b76c-bc2011322ef3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949241249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1949241249
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/48.hmac_error.332207708
Short name T50
Test name
Test status
Simulation time 30988200585 ps
CPU time 137.1 seconds
Started Mar 24 01:03:39 PM PDT 24
Finished Mar 24 01:05:57 PM PDT 24
Peak memory 200068 kb
Host smart-91c699e7-e9a2-4b3f-867f-13f6daaa6e47
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332207708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.332207708
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.4067573379
Short name T94
Test name
Test status
Simulation time 224823419 ps
CPU time 5.48 seconds
Started Mar 24 12:20:56 PM PDT 24
Finished Mar 24 12:21:02 PM PDT 24
Peak memory 197784 kb
Host smart-20d24401-8fb1-4fe2-a73c-cbb2e8d16dc7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067573379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.4067573379
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3640515069
Short name T103
Test name
Test status
Simulation time 311053543 ps
CPU time 14.43 seconds
Started Mar 24 12:19:49 PM PDT 24
Finished Mar 24 12:20:04 PM PDT 24
Peak memory 198804 kb
Host smart-78cf3d8c-1491-4ad0-87d7-1ececd4cf572
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640515069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3640515069
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1248748071
Short name T100
Test name
Test status
Simulation time 16734375 ps
CPU time 0.81 seconds
Started Mar 24 12:19:06 PM PDT 24
Finished Mar 24 12:19:07 PM PDT 24
Peak memory 197772 kb
Host smart-5a5e59d7-a34c-4c1a-9ff8-44192b6d9ae0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248748071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1248748071
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2813950333
Short name T718
Test name
Test status
Simulation time 56228669 ps
CPU time 3.64 seconds
Started Mar 24 12:19:07 PM PDT 24
Finished Mar 24 12:19:11 PM PDT 24
Peak memory 199248 kb
Host smart-53767e11-8d7a-456a-91fb-60ef3ecad410
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813950333 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2813950333
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.832408133
Short name T660
Test name
Test status
Simulation time 110634005 ps
CPU time 0.81 seconds
Started Mar 24 12:20:38 PM PDT 24
Finished Mar 24 12:20:39 PM PDT 24
Peak memory 197436 kb
Host smart-d9cca468-5514-4037-9d0b-e06ecb093d39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832408133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.832408133
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2758084856
Short name T698
Test name
Test status
Simulation time 47010608 ps
CPU time 0.59 seconds
Started Mar 24 12:21:22 PM PDT 24
Finished Mar 24 12:21:23 PM PDT 24
Peak memory 192896 kb
Host smart-894b845b-474a-4b3b-90b3-c3f7cd02769a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758084856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2758084856
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1570543933
Short name T603
Test name
Test status
Simulation time 149604562 ps
CPU time 2.68 seconds
Started Mar 24 12:19:20 PM PDT 24
Finished Mar 24 12:19:23 PM PDT 24
Peak memory 198708 kb
Host smart-96475db4-67f0-4983-a8f5-996038e5bb18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570543933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.1570543933
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3292078212
Short name T608
Test name
Test status
Simulation time 81880560 ps
CPU time 2.19 seconds
Started Mar 24 12:20:45 PM PDT 24
Finished Mar 24 12:20:47 PM PDT 24
Peak memory 199024 kb
Host smart-c3196d02-601d-43ec-a91f-d653101c67f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292078212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.3292078212
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1972167493
Short name T113
Test name
Test status
Simulation time 267987453 ps
CPU time 4.2 seconds
Started Mar 24 12:20:34 PM PDT 24
Finished Mar 24 12:20:39 PM PDT 24
Peak memory 199076 kb
Host smart-13ce76a1-047e-423f-ae47-8227b12daf89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972167493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1972167493
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1976916504
Short name T107
Test name
Test status
Simulation time 2129486430 ps
CPU time 5.95 seconds
Started Mar 24 12:19:11 PM PDT 24
Finished Mar 24 12:19:17 PM PDT 24
Peak memory 197936 kb
Host smart-6c6090fb-be53-42a6-88f1-c612c79ee531
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976916504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1976916504
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2686641447
Short name T724
Test name
Test status
Simulation time 64446271 ps
CPU time 0.69 seconds
Started Mar 24 12:20:55 PM PDT 24
Finished Mar 24 12:20:56 PM PDT 24
Peak memory 196312 kb
Host smart-25ea9aef-30da-4cf0-a388-7b91008d34ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686641447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2686641447
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2824839541
Short name T667
Test name
Test status
Simulation time 28316548 ps
CPU time 1.53 seconds
Started Mar 24 12:21:47 PM PDT 24
Finished Mar 24 12:21:49 PM PDT 24
Peak memory 198944 kb
Host smart-43314ce0-e8fc-4ff0-866a-3502c3bed344
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824839541 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2824839541
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2626405647
Short name T697
Test name
Test status
Simulation time 71631390 ps
CPU time 0.71 seconds
Started Mar 24 12:19:20 PM PDT 24
Finished Mar 24 12:19:21 PM PDT 24
Peak memory 197384 kb
Host smart-521de0fd-2baf-434c-ae58-ce3bd19b7752
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626405647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2626405647
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1418516269
Short name T727
Test name
Test status
Simulation time 65409769 ps
CPU time 0.58 seconds
Started Mar 24 12:19:49 PM PDT 24
Finished Mar 24 12:19:50 PM PDT 24
Peak memory 193780 kb
Host smart-9d704e38-8def-47b6-8c47-b408182ba633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418516269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1418516269
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1037874431
Short name T710
Test name
Test status
Simulation time 58609257 ps
CPU time 1.34 seconds
Started Mar 24 12:19:19 PM PDT 24
Finished Mar 24 12:19:20 PM PDT 24
Peak memory 199120 kb
Host smart-f0371b16-4156-4ba2-b268-d0f59535d25e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037874431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.1037874431
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.955501094
Short name T602
Test name
Test status
Simulation time 202916999 ps
CPU time 4.08 seconds
Started Mar 24 12:19:18 PM PDT 24
Finished Mar 24 12:19:23 PM PDT 24
Peak memory 199608 kb
Host smart-66ab5560-c401-41e5-bf9c-1671de263397
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955501094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.955501094
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1294110329
Short name T621
Test name
Test status
Simulation time 45173208 ps
CPU time 1.42 seconds
Started Mar 24 12:21:40 PM PDT 24
Finished Mar 24 12:21:42 PM PDT 24
Peak memory 197104 kb
Host smart-7d0c3578-854a-4437-ad37-de0e9a68932c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294110329 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.1294110329
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2386681867
Short name T105
Test name
Test status
Simulation time 39198389 ps
CPU time 0.94 seconds
Started Mar 24 12:21:41 PM PDT 24
Finished Mar 24 12:21:42 PM PDT 24
Peak memory 196824 kb
Host smart-07b49ec9-a275-41a4-9ff9-10404d808939
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386681867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2386681867
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.356511247
Short name T655
Test name
Test status
Simulation time 12826904 ps
CPU time 0.56 seconds
Started Mar 24 12:22:09 PM PDT 24
Finished Mar 24 12:22:09 PM PDT 24
Peak memory 193740 kb
Host smart-a249f243-8391-454b-b89f-b66a5f83ec7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356511247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.356511247
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1828843400
Short name T637
Test name
Test status
Simulation time 251130361 ps
CPU time 1.69 seconds
Started Mar 24 12:19:49 PM PDT 24
Finished Mar 24 12:19:51 PM PDT 24
Peak memory 198792 kb
Host smart-c7462b92-73a7-42ad-b604-a422ea79ed6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828843400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1828843400
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2847468535
Short name T624
Test name
Test status
Simulation time 748477709 ps
CPU time 2.71 seconds
Started Mar 24 12:21:40 PM PDT 24
Finished Mar 24 12:21:44 PM PDT 24
Peak memory 197124 kb
Host smart-e07b2800-fde2-43f3-a3ab-16874a302c3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847468535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2847468535
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2491894379
Short name T59
Test name
Test status
Simulation time 122036503 ps
CPU time 1.83 seconds
Started Mar 24 12:19:43 PM PDT 24
Finished Mar 24 12:19:45 PM PDT 24
Peak memory 199144 kb
Host smart-353602d3-03d6-41c5-8941-6e3209edc70b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491894379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2491894379
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3627105346
Short name T630
Test name
Test status
Simulation time 302524148442 ps
CPU time 657.34 seconds
Started Mar 24 12:21:56 PM PDT 24
Finished Mar 24 12:32:53 PM PDT 24
Peak memory 222420 kb
Host smart-0b1b8bc0-a231-406e-8e44-2e2ea98cd018
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627105346 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.3627105346
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.909041577
Short name T61
Test name
Test status
Simulation time 201325066 ps
CPU time 0.82 seconds
Started Mar 24 12:19:49 PM PDT 24
Finished Mar 24 12:19:50 PM PDT 24
Peak memory 198304 kb
Host smart-cf9754c1-a6f9-4197-9a0b-0b5ac885094d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909041577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.909041577
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.3521689917
Short name T606
Test name
Test status
Simulation time 39217635 ps
CPU time 0.6 seconds
Started Mar 24 12:21:56 PM PDT 24
Finished Mar 24 12:21:57 PM PDT 24
Peak memory 193008 kb
Host smart-114c8fc1-2ed6-4027-b49f-12a4dd0e2c8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521689917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3521689917
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.769761163
Short name T622
Test name
Test status
Simulation time 260175763 ps
CPU time 2.4 seconds
Started Mar 24 12:20:05 PM PDT 24
Finished Mar 24 12:20:08 PM PDT 24
Peak memory 199332 kb
Host smart-573faeac-5d58-4182-991b-d2ef2f8c118c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769761163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.769761163
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.252044552
Short name T707
Test name
Test status
Simulation time 431046259 ps
CPU time 2.55 seconds
Started Mar 24 12:19:38 PM PDT 24
Finished Mar 24 12:19:41 PM PDT 24
Peak memory 199132 kb
Host smart-99f7ce13-f4b5-45c7-a46d-aa0c058ee7b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252044552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.252044552
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1313386812
Short name T648
Test name
Test status
Simulation time 221426736 ps
CPU time 2.65 seconds
Started Mar 24 12:22:02 PM PDT 24
Finished Mar 24 12:22:05 PM PDT 24
Peak memory 199036 kb
Host smart-84485e74-53f8-4c5c-b3b0-dcb65925fe4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313386812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1313386812
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.142834435
Short name T715
Test name
Test status
Simulation time 120568033 ps
CPU time 2.38 seconds
Started Mar 24 12:19:51 PM PDT 24
Finished Mar 24 12:19:54 PM PDT 24
Peak memory 199220 kb
Host smart-243f828f-3abb-48d3-b4e3-6b29c69ff189
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142834435 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.142834435
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3955646555
Short name T721
Test name
Test status
Simulation time 32532413 ps
CPU time 0.92 seconds
Started Mar 24 12:22:36 PM PDT 24
Finished Mar 24 12:22:37 PM PDT 24
Peak memory 197908 kb
Host smart-20b78285-a5b2-4465-a8c3-0860f9cb3d37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955646555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3955646555
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2726727926
Short name T654
Test name
Test status
Simulation time 167678614 ps
CPU time 0.56 seconds
Started Mar 24 12:19:49 PM PDT 24
Finished Mar 24 12:19:50 PM PDT 24
Peak memory 193724 kb
Host smart-089b7b2b-3cfd-4e85-8288-9db4083c1f93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726727926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2726727926
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2477650926
Short name T627
Test name
Test status
Simulation time 53847401 ps
CPU time 1.27 seconds
Started Mar 24 12:19:48 PM PDT 24
Finished Mar 24 12:19:49 PM PDT 24
Peak memory 197752 kb
Host smart-60027e2a-a632-4e91-a63a-3f226f0199bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477650926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2477650926
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3535152239
Short name T601
Test name
Test status
Simulation time 139945404 ps
CPU time 1.8 seconds
Started Mar 24 12:20:19 PM PDT 24
Finished Mar 24 12:20:21 PM PDT 24
Peak memory 199616 kb
Host smart-38f63dff-f574-4e80-8a8d-c7ff1e241dde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535152239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3535152239
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1180404531
Short name T692
Test name
Test status
Simulation time 40159096 ps
CPU time 1.17 seconds
Started Mar 24 12:20:01 PM PDT 24
Finished Mar 24 12:20:03 PM PDT 24
Peak memory 199080 kb
Host smart-ba9f6201-51df-4954-ab07-54e3742174e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180404531 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1180404531
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.822783163
Short name T690
Test name
Test status
Simulation time 26371463 ps
CPU time 0.81 seconds
Started Mar 24 12:19:56 PM PDT 24
Finished Mar 24 12:19:57 PM PDT 24
Peak memory 197944 kb
Host smart-68735a87-f9d0-4ce3-ba59-ad74ea6baf84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822783163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.822783163
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3207560079
Short name T616
Test name
Test status
Simulation time 15781404 ps
CPU time 0.63 seconds
Started Mar 24 12:19:51 PM PDT 24
Finished Mar 24 12:19:52 PM PDT 24
Peak memory 193880 kb
Host smart-ea291e09-5722-4570-a9b8-324188c70f66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207560079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3207560079
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.10249167
Short name T620
Test name
Test status
Simulation time 288088295 ps
CPU time 1.05 seconds
Started Mar 24 12:21:43 PM PDT 24
Finished Mar 24 12:21:44 PM PDT 24
Peak memory 199000 kb
Host smart-4f476c99-a578-4d1e-81f7-8fdc433f55b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10249167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr_
outstanding.10249167
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1811513072
Short name T641
Test name
Test status
Simulation time 292022735 ps
CPU time 1.68 seconds
Started Mar 24 12:22:00 PM PDT 24
Finished Mar 24 12:22:02 PM PDT 24
Peak memory 198952 kb
Host smart-056fb463-4d5c-4255-87ae-2a28ce378de4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811513072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1811513072
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1418627250
Short name T687
Test name
Test status
Simulation time 585668634 ps
CPU time 3.02 seconds
Started Mar 24 12:19:51 PM PDT 24
Finished Mar 24 12:19:55 PM PDT 24
Peak memory 199240 kb
Host smart-090d32c3-b9c9-463b-a434-9ec991ae4e69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418627250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1418627250
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3584812855
Short name T682
Test name
Test status
Simulation time 45564918 ps
CPU time 2.75 seconds
Started Mar 24 12:20:34 PM PDT 24
Finished Mar 24 12:20:37 PM PDT 24
Peak memory 199232 kb
Host smart-2b6f6856-cbcf-450e-ad58-1175c43a1eee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584812855 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.3584812855
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3993093701
Short name T626
Test name
Test status
Simulation time 117181876 ps
CPU time 0.87 seconds
Started Mar 24 12:21:46 PM PDT 24
Finished Mar 24 12:21:47 PM PDT 24
Peak memory 198928 kb
Host smart-15a6d249-d304-47b9-8237-ce13bb6f6cf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993093701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3993093701
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.2889452806
Short name T613
Test name
Test status
Simulation time 37543035 ps
CPU time 0.61 seconds
Started Mar 24 12:20:01 PM PDT 24
Finished Mar 24 12:20:03 PM PDT 24
Peak memory 194008 kb
Host smart-c0f41272-b218-4e3e-821b-a3f0e48a2698
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889452806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2889452806
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.205381598
Short name T688
Test name
Test status
Simulation time 92152970 ps
CPU time 1.18 seconds
Started Mar 24 12:21:48 PM PDT 24
Finished Mar 24 12:21:49 PM PDT 24
Peak memory 198456 kb
Host smart-2932f27f-eaf2-4ce1-b3df-bdcfa6a5500b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205381598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr
_outstanding.205381598
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.988617706
Short name T711
Test name
Test status
Simulation time 175086319 ps
CPU time 1.3 seconds
Started Mar 24 12:20:01 PM PDT 24
Finished Mar 24 12:20:02 PM PDT 24
Peak memory 199136 kb
Host smart-26d198b6-5e66-4b92-8ec2-b4222a9facf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988617706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.988617706
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2360605876
Short name T114
Test name
Test status
Simulation time 134102438 ps
CPU time 4.24 seconds
Started Mar 24 12:21:24 PM PDT 24
Finished Mar 24 12:21:29 PM PDT 24
Peak memory 199112 kb
Host smart-fa133680-7c39-4f71-99cf-bdea49eb3d9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360605876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2360605876
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1862970567
Short name T638
Test name
Test status
Simulation time 32982086 ps
CPU time 2.08 seconds
Started Mar 24 12:20:03 PM PDT 24
Finished Mar 24 12:20:05 PM PDT 24
Peak memory 199680 kb
Host smart-ea035df9-384c-4242-8ad5-5b02a68e956e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862970567 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1862970567
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.528271765
Short name T108
Test name
Test status
Simulation time 88815334 ps
CPU time 0.89 seconds
Started Mar 24 12:20:10 PM PDT 24
Finished Mar 24 12:20:12 PM PDT 24
Peak memory 198264 kb
Host smart-b4501947-e2b0-466a-8e88-a61d10d44897
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528271765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.528271765
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.176260296
Short name T684
Test name
Test status
Simulation time 23986341 ps
CPU time 0.62 seconds
Started Mar 24 12:21:24 PM PDT 24
Finished Mar 24 12:21:25 PM PDT 24
Peak memory 193724 kb
Host smart-79b9981d-fbb9-46bd-af4c-74ca22500922
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176260296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.176260296
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.4294947220
Short name T646
Test name
Test status
Simulation time 81665109 ps
CPU time 1.9 seconds
Started Mar 24 12:20:10 PM PDT 24
Finished Mar 24 12:20:13 PM PDT 24
Peak memory 198152 kb
Host smart-7e1248bb-c76e-414c-9476-56a62c99addb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294947220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.4294947220
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2945940798
Short name T677
Test name
Test status
Simulation time 598271298 ps
CPU time 2.58 seconds
Started Mar 24 12:21:34 PM PDT 24
Finished Mar 24 12:21:36 PM PDT 24
Peak memory 199312 kb
Host smart-dd69ba9c-e42f-4a43-90d5-8c0d713c1a7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945940798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.2945940798
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3884026654
Short name T722
Test name
Test status
Simulation time 187840578 ps
CPU time 2.91 seconds
Started Mar 24 12:20:31 PM PDT 24
Finished Mar 24 12:20:34 PM PDT 24
Peak memory 199240 kb
Host smart-700e3ad7-86b6-492f-8b31-26d68fc5dd41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884026654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3884026654
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2193906776
Short name T60
Test name
Test status
Simulation time 519086194173 ps
CPU time 732.58 seconds
Started Mar 24 12:20:08 PM PDT 24
Finished Mar 24 12:32:21 PM PDT 24
Peak memory 215716 kb
Host smart-fba07fdc-c5f0-4e8e-888f-58e3d41c5c84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193906776 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2193906776
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1484049273
Short name T99
Test name
Test status
Simulation time 27616080 ps
CPU time 0.92 seconds
Started Mar 24 12:20:08 PM PDT 24
Finished Mar 24 12:20:10 PM PDT 24
Peak memory 198600 kb
Host smart-a360f73f-9298-4712-9051-8b424ac9a904
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484049273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1484049273
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3165836419
Short name T623
Test name
Test status
Simulation time 13367134 ps
CPU time 0.67 seconds
Started Mar 24 12:20:08 PM PDT 24
Finished Mar 24 12:20:09 PM PDT 24
Peak memory 193812 kb
Host smart-796da860-d8e1-4bba-aba2-7ac28ad78098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165836419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3165836419
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.368655018
Short name T673
Test name
Test status
Simulation time 33667636 ps
CPU time 1.7 seconds
Started Mar 24 12:20:09 PM PDT 24
Finished Mar 24 12:20:12 PM PDT 24
Peak memory 199200 kb
Host smart-9a8eb780-d484-4cd6-a9c4-a7ef8c9a850c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368655018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr
_outstanding.368655018
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1442998237
Short name T653
Test name
Test status
Simulation time 333664324 ps
CPU time 2.13 seconds
Started Mar 24 12:20:02 PM PDT 24
Finished Mar 24 12:20:05 PM PDT 24
Peak memory 199588 kb
Host smart-0a60718a-473f-4d40-8058-5d1acf217b0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442998237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1442998237
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.524725544
Short name T717
Test name
Test status
Simulation time 147462355 ps
CPU time 1.22 seconds
Started Mar 24 12:20:08 PM PDT 24
Finished Mar 24 12:20:11 PM PDT 24
Peak memory 199032 kb
Host smart-65e22d28-e5fd-4728-87e1-13385e1d7779
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524725544 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.524725544
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1392772860
Short name T101
Test name
Test status
Simulation time 13563312 ps
CPU time 0.68 seconds
Started Mar 24 12:20:09 PM PDT 24
Finished Mar 24 12:20:11 PM PDT 24
Peak memory 196700 kb
Host smart-8e5bddeb-4a4a-40ed-bb9f-e0f9c817ae48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392772860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1392772860
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1024637068
Short name T723
Test name
Test status
Simulation time 12956707 ps
CPU time 0.61 seconds
Started Mar 24 12:20:08 PM PDT 24
Finished Mar 24 12:20:10 PM PDT 24
Peak memory 193880 kb
Host smart-40b7fcb5-a708-4a43-b073-69291990dca7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024637068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1024637068
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.496071140
Short name T725
Test name
Test status
Simulation time 243453518 ps
CPU time 2.67 seconds
Started Mar 24 12:20:10 PM PDT 24
Finished Mar 24 12:20:14 PM PDT 24
Peak memory 198748 kb
Host smart-6b8d8a3a-8572-4cb3-98aa-7457b1ea0e72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496071140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr
_outstanding.496071140
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3102765183
Short name T658
Test name
Test status
Simulation time 394581736 ps
CPU time 4.14 seconds
Started Mar 24 12:20:05 PM PDT 24
Finished Mar 24 12:20:09 PM PDT 24
Peak memory 199612 kb
Host smart-e0faeb42-30c5-459f-b251-2c02f6a9bfe8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102765183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.3102765183
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1624778449
Short name T679
Test name
Test status
Simulation time 80722881 ps
CPU time 1.77 seconds
Started Mar 24 12:20:03 PM PDT 24
Finished Mar 24 12:20:06 PM PDT 24
Peak memory 199612 kb
Host smart-8f154d20-1638-414a-9290-9b0b946d1980
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624778449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1624778449
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3370689044
Short name T605
Test name
Test status
Simulation time 75100756 ps
CPU time 1.18 seconds
Started Mar 24 12:22:31 PM PDT 24
Finished Mar 24 12:22:33 PM PDT 24
Peak memory 198368 kb
Host smart-557e9147-1d1e-46c6-aae6-b757c684916d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370689044 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3370689044
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.885419470
Short name T104
Test name
Test status
Simulation time 134597255 ps
CPU time 0.94 seconds
Started Mar 24 12:20:09 PM PDT 24
Finished Mar 24 12:20:11 PM PDT 24
Peak memory 199296 kb
Host smart-0d32ccd6-3b4f-4c37-afc4-7b5e4aa1f258
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885419470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.885419470
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2500755028
Short name T651
Test name
Test status
Simulation time 14065362 ps
CPU time 0.57 seconds
Started Mar 24 12:22:59 PM PDT 24
Finished Mar 24 12:23:00 PM PDT 24
Peak memory 193976 kb
Host smart-be15d627-edf5-4be7-a6a6-f12f66318cb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500755028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2500755028
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1042610604
Short name T669
Test name
Test status
Simulation time 103971366 ps
CPU time 1.12 seconds
Started Mar 24 12:23:13 PM PDT 24
Finished Mar 24 12:23:14 PM PDT 24
Peak memory 199116 kb
Host smart-d0840530-2272-4c72-924d-9fdea8a70599
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042610604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.1042610604
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.243766049
Short name T649
Test name
Test status
Simulation time 298640318 ps
CPU time 2.88 seconds
Started Mar 24 12:20:03 PM PDT 24
Finished Mar 24 12:20:07 PM PDT 24
Peak memory 199676 kb
Host smart-b1f485a0-ae45-40de-ba97-09283117e1ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243766049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.243766049
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1041952424
Short name T683
Test name
Test status
Simulation time 153962749 ps
CPU time 3.09 seconds
Started Mar 24 12:20:08 PM PDT 24
Finished Mar 24 12:20:13 PM PDT 24
Peak memory 199104 kb
Host smart-1f84920c-5e38-4365-9eeb-e248d5390a99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041952424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.1041952424
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3442570462
Short name T663
Test name
Test status
Simulation time 96174374 ps
CPU time 2.14 seconds
Started Mar 24 12:22:51 PM PDT 24
Finished Mar 24 12:22:54 PM PDT 24
Peak memory 199108 kb
Host smart-e40c521f-92e7-4eab-b4e3-0abf8054bd8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442570462 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3442570462
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1850924724
Short name T689
Test name
Test status
Simulation time 47299377 ps
CPU time 0.67 seconds
Started Mar 24 12:22:50 PM PDT 24
Finished Mar 24 12:22:51 PM PDT 24
Peak memory 196528 kb
Host smart-b9cd0e7a-cd55-46a5-83ad-e4dbdec80fef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850924724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1850924724
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.907040395
Short name T729
Test name
Test status
Simulation time 45660815 ps
CPU time 0.59 seconds
Started Mar 24 12:20:19 PM PDT 24
Finished Mar 24 12:20:20 PM PDT 24
Peak memory 193716 kb
Host smart-b95b9ed7-c826-493a-93a4-8838f840e50c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907040395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.907040395
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.126156981
Short name T643
Test name
Test status
Simulation time 78406545 ps
CPU time 0.99 seconds
Started Mar 24 12:20:19 PM PDT 24
Finished Mar 24 12:20:20 PM PDT 24
Peak memory 198496 kb
Host smart-a11d30f7-8afd-4c69-94cc-768bf22b0504
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126156981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.126156981
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1818239505
Short name T726
Test name
Test status
Simulation time 784747932 ps
CPU time 2.72 seconds
Started Mar 24 12:22:42 PM PDT 24
Finished Mar 24 12:22:45 PM PDT 24
Peak memory 199144 kb
Host smart-699e8f53-c7b4-4610-acd1-3b460f0735e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818239505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1818239505
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2437583272
Short name T112
Test name
Test status
Simulation time 311495408 ps
CPU time 2.77 seconds
Started Mar 24 12:22:44 PM PDT 24
Finished Mar 24 12:22:47 PM PDT 24
Peak memory 199112 kb
Host smart-9caba8c8-6057-4ed2-9952-effe9f62677f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437583272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2437583272
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3496200775
Short name T102
Test name
Test status
Simulation time 314865590 ps
CPU time 5.71 seconds
Started Mar 24 12:20:53 PM PDT 24
Finished Mar 24 12:20:59 PM PDT 24
Peak memory 198620 kb
Host smart-87f42066-e946-4438-b95e-4e0a6504fb8c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496200775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3496200775
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.366558338
Short name T703
Test name
Test status
Simulation time 2404152211 ps
CPU time 5.44 seconds
Started Mar 24 12:21:59 PM PDT 24
Finished Mar 24 12:22:04 PM PDT 24
Peak memory 197624 kb
Host smart-ec30106b-8117-4483-a1b7-54425f050bb7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366558338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.366558338
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.239884708
Short name T96
Test name
Test status
Simulation time 20363255 ps
CPU time 1.05 seconds
Started Mar 24 12:19:09 PM PDT 24
Finished Mar 24 12:19:10 PM PDT 24
Peak memory 199376 kb
Host smart-1ca31223-69bf-4530-a48a-61044a214193
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239884708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.239884708
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2551050280
Short name T617
Test name
Test status
Simulation time 35461825 ps
CPU time 2.59 seconds
Started Mar 24 12:19:18 PM PDT 24
Finished Mar 24 12:19:21 PM PDT 24
Peak memory 199592 kb
Host smart-0a798e82-2356-4bf3-8c31-f7c4639c006e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551050280 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2551050280
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.719953298
Short name T92
Test name
Test status
Simulation time 23979598 ps
CPU time 0.79 seconds
Started Mar 24 12:21:54 PM PDT 24
Finished Mar 24 12:21:55 PM PDT 24
Peak memory 197904 kb
Host smart-e9d7c71f-ed6f-43d4-9e0e-f69daba90d0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719953298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.719953298
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2468550479
Short name T665
Test name
Test status
Simulation time 33142057 ps
CPU time 0.56 seconds
Started Mar 24 12:21:47 PM PDT 24
Finished Mar 24 12:21:48 PM PDT 24
Peak memory 193584 kb
Host smart-77bd910c-5c0f-41b1-95f8-aa7535b2201a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468550479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2468550479
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3979533679
Short name T680
Test name
Test status
Simulation time 1534963046 ps
CPU time 2.21 seconds
Started Mar 24 12:21:44 PM PDT 24
Finished Mar 24 12:21:46 PM PDT 24
Peak memory 197836 kb
Host smart-ae3b286a-7c67-4022-94e1-3d1901af2461
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979533679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3979533679
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.589763046
Short name T696
Test name
Test status
Simulation time 470653738 ps
CPU time 2.38 seconds
Started Mar 24 12:21:45 PM PDT 24
Finished Mar 24 12:21:47 PM PDT 24
Peak memory 198436 kb
Host smart-8b74e9c6-e7d9-47bc-8d9f-9c7b97ee3dbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589763046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.589763046
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.629952642
Short name T691
Test name
Test status
Simulation time 270141188 ps
CPU time 4.52 seconds
Started Mar 24 12:19:07 PM PDT 24
Finished Mar 24 12:19:12 PM PDT 24
Peak memory 199144 kb
Host smart-31482c58-18d9-4b85-86e5-45c8b998bba5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629952642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.629952642
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2814780362
Short name T612
Test name
Test status
Simulation time 11842592 ps
CPU time 0.64 seconds
Started Mar 24 12:20:22 PM PDT 24
Finished Mar 24 12:20:22 PM PDT 24
Peak memory 194252 kb
Host smart-fdd2e0a5-2e94-43f5-bd1d-49d1c85b9d65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814780362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2814780362
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.826839618
Short name T716
Test name
Test status
Simulation time 12986490 ps
CPU time 0.56 seconds
Started Mar 24 12:22:35 PM PDT 24
Finished Mar 24 12:22:36 PM PDT 24
Peak memory 193784 kb
Host smart-93a51a76-a10e-4ced-a0c1-33e177e43c6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826839618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.826839618
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.404950420
Short name T647
Test name
Test status
Simulation time 50857477 ps
CPU time 0.71 seconds
Started Mar 24 12:20:20 PM PDT 24
Finished Mar 24 12:20:20 PM PDT 24
Peak memory 193784 kb
Host smart-c62f487a-5bd0-4e48-8d55-6d1f3b8dc1b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404950420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.404950420
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.3434829146
Short name T728
Test name
Test status
Simulation time 50053196 ps
CPU time 0.61 seconds
Started Mar 24 12:20:34 PM PDT 24
Finished Mar 24 12:20:35 PM PDT 24
Peak memory 193820 kb
Host smart-03c49b5f-0688-4c40-8e8a-d6fbf46c1668
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434829146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.3434829146
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2342995240
Short name T709
Test name
Test status
Simulation time 23571449 ps
CPU time 0.59 seconds
Started Mar 24 12:22:27 PM PDT 24
Finished Mar 24 12:22:28 PM PDT 24
Peak memory 193148 kb
Host smart-d8b22ab3-e9f3-4da9-b079-a029b4876e88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342995240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2342995240
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.74212710
Short name T702
Test name
Test status
Simulation time 15642541 ps
CPU time 0.6 seconds
Started Mar 24 12:20:27 PM PDT 24
Finished Mar 24 12:20:28 PM PDT 24
Peak memory 194128 kb
Host smart-00e2a302-520e-4ad9-bbed-90bd950a99d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74212710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.74212710
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1046939710
Short name T708
Test name
Test status
Simulation time 17795997 ps
CPU time 0.56 seconds
Started Mar 24 12:22:47 PM PDT 24
Finished Mar 24 12:22:48 PM PDT 24
Peak memory 193952 kb
Host smart-96ebaa92-790d-43e9-b963-b255351d275d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046939710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1046939710
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1981142975
Short name T642
Test name
Test status
Simulation time 16423929 ps
CPU time 0.61 seconds
Started Mar 24 12:20:23 PM PDT 24
Finished Mar 24 12:20:24 PM PDT 24
Peak memory 193712 kb
Host smart-dbee80ec-390c-4500-952f-b70de89f464c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981142975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1981142975
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.3495375102
Short name T634
Test name
Test status
Simulation time 19271549 ps
CPU time 0.61 seconds
Started Mar 24 12:21:56 PM PDT 24
Finished Mar 24 12:21:57 PM PDT 24
Peak memory 193048 kb
Host smart-719fd3a4-618a-456a-bdf0-08c353ebdb5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495375102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3495375102
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3309096834
Short name T644
Test name
Test status
Simulation time 112423291 ps
CPU time 0.59 seconds
Started Mar 24 12:20:23 PM PDT 24
Finished Mar 24 12:20:24 PM PDT 24
Peak memory 193780 kb
Host smart-5b36abd0-8052-4a0f-be5e-cab9d6d3750e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309096834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3309096834
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.195444715
Short name T598
Test name
Test status
Simulation time 736902674 ps
CPU time 3.18 seconds
Started Mar 24 12:21:19 PM PDT 24
Finished Mar 24 12:21:22 PM PDT 24
Peak memory 199020 kb
Host smart-ee0beb47-bf65-4d5e-8401-7f06130f6ac4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195444715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.195444715
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1259997122
Short name T666
Test name
Test status
Simulation time 605147197 ps
CPU time 6.01 seconds
Started Mar 24 12:21:08 PM PDT 24
Finished Mar 24 12:21:14 PM PDT 24
Peak memory 198976 kb
Host smart-fdceae37-66ef-4e80-9009-ab2041230e76
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259997122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1259997122
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.833018588
Short name T706
Test name
Test status
Simulation time 39567640 ps
CPU time 1 seconds
Started Mar 24 12:21:44 PM PDT 24
Finished Mar 24 12:21:45 PM PDT 24
Peak memory 197920 kb
Host smart-9f45aa70-4b22-4f65-847a-9f692c7ab9fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833018588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.833018588
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.652908067
Short name T607
Test name
Test status
Simulation time 44559802 ps
CPU time 1.6 seconds
Started Mar 24 12:21:04 PM PDT 24
Finished Mar 24 12:21:06 PM PDT 24
Peak memory 198188 kb
Host smart-5913f37d-fbf1-4dc5-bcdb-cec0468150d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652908067 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.652908067
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3507343616
Short name T106
Test name
Test status
Simulation time 20443133 ps
CPU time 0.71 seconds
Started Mar 24 12:20:53 PM PDT 24
Finished Mar 24 12:20:54 PM PDT 24
Peak memory 195720 kb
Host smart-e9e02d0b-5156-426e-953c-3eab8a733dc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507343616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3507343616
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3151051161
Short name T700
Test name
Test status
Simulation time 40731557 ps
CPU time 0.68 seconds
Started Mar 24 12:19:18 PM PDT 24
Finished Mar 24 12:19:19 PM PDT 24
Peak memory 194188 kb
Host smart-e235b025-5357-4700-8332-7d140b2f1728
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151051161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3151051161
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4112869458
Short name T657
Test name
Test status
Simulation time 118873614 ps
CPU time 2.33 seconds
Started Mar 24 12:21:08 PM PDT 24
Finished Mar 24 12:21:10 PM PDT 24
Peak memory 198728 kb
Host smart-7f6f32a1-c0f4-4b1a-8476-a1373642db01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112869458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.4112869458
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1941807956
Short name T610
Test name
Test status
Simulation time 172140427 ps
CPU time 2.08 seconds
Started Mar 24 12:19:18 PM PDT 24
Finished Mar 24 12:19:20 PM PDT 24
Peak memory 199604 kb
Host smart-c1ef4b33-aa5c-48dc-bef0-2b596d9c22c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941807956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1941807956
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3243892056
Short name T675
Test name
Test status
Simulation time 50529174 ps
CPU time 1.67 seconds
Started Mar 24 12:21:44 PM PDT 24
Finished Mar 24 12:21:46 PM PDT 24
Peak memory 197864 kb
Host smart-9fec73c4-fae5-4373-82d0-e8f8978a1585
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243892056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.3243892056
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.517161783
Short name T600
Test name
Test status
Simulation time 37435236 ps
CPU time 0.59 seconds
Started Mar 24 12:22:37 PM PDT 24
Finished Mar 24 12:22:37 PM PDT 24
Peak memory 193984 kb
Host smart-6d1b5d48-dfcf-4ef0-8314-2007ac520ed4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517161783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.517161783
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3784633246
Short name T629
Test name
Test status
Simulation time 24794850 ps
CPU time 0.57 seconds
Started Mar 24 12:22:51 PM PDT 24
Finished Mar 24 12:23:02 PM PDT 24
Peak memory 193956 kb
Host smart-76226a9e-b23e-43dd-8d6b-586a8508f660
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784633246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3784633246
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1662402384
Short name T640
Test name
Test status
Simulation time 14110028 ps
CPU time 0.56 seconds
Started Mar 24 12:22:15 PM PDT 24
Finished Mar 24 12:22:16 PM PDT 24
Peak memory 193736 kb
Host smart-e6bdd4b7-c1a9-47d6-8a1e-0e558073e3b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662402384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1662402384
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.1284849972
Short name T639
Test name
Test status
Simulation time 47326550 ps
CPU time 0.56 seconds
Started Mar 24 12:22:35 PM PDT 24
Finished Mar 24 12:22:36 PM PDT 24
Peak memory 193728 kb
Host smart-d7a77cc5-76bb-4733-92d4-7bd66bb6ec4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284849972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1284849972
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1893291338
Short name T652
Test name
Test status
Simulation time 31405110 ps
CPU time 0.57 seconds
Started Mar 24 12:22:38 PM PDT 24
Finished Mar 24 12:22:39 PM PDT 24
Peak memory 193720 kb
Host smart-9b8416ec-1e47-4432-9a65-882bcdb91e71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893291338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1893291338
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.4186408189
Short name T659
Test name
Test status
Simulation time 43096104 ps
CPU time 0.57 seconds
Started Mar 24 12:22:47 PM PDT 24
Finished Mar 24 12:22:48 PM PDT 24
Peak memory 193952 kb
Host smart-5081dd73-5f27-4f86-b7d5-c1b62ee4c86d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186408189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.4186408189
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.161555071
Short name T628
Test name
Test status
Simulation time 32665504 ps
CPU time 0.6 seconds
Started Mar 24 12:22:43 PM PDT 24
Finished Mar 24 12:22:43 PM PDT 24
Peak memory 193964 kb
Host smart-6ff0b79a-75ae-43d9-96bc-d6ff8213d3d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161555071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.161555071
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.797367946
Short name T720
Test name
Test status
Simulation time 27296879 ps
CPU time 0.59 seconds
Started Mar 24 12:20:20 PM PDT 24
Finished Mar 24 12:20:21 PM PDT 24
Peak memory 194192 kb
Host smart-4278318c-d549-46d0-aff6-4f04dfa9cd0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797367946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.797367946
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.4218003140
Short name T676
Test name
Test status
Simulation time 15568650 ps
CPU time 0.6 seconds
Started Mar 24 12:20:36 PM PDT 24
Finished Mar 24 12:20:37 PM PDT 24
Peak memory 193964 kb
Host smart-1ba620ec-67d9-4591-bf19-b1a1ce386db8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218003140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.4218003140
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3213563012
Short name T645
Test name
Test status
Simulation time 43872234 ps
CPU time 0.62 seconds
Started Mar 24 12:20:29 PM PDT 24
Finished Mar 24 12:20:30 PM PDT 24
Peak memory 193828 kb
Host smart-0995a41d-f68e-4407-aebf-32e27e1ac34d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213563012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3213563012
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1216462264
Short name T95
Test name
Test status
Simulation time 163358569 ps
CPU time 3.18 seconds
Started Mar 24 12:21:08 PM PDT 24
Finished Mar 24 12:21:12 PM PDT 24
Peak memory 198568 kb
Host smart-c9de71c4-0153-442c-bb55-36edcbfd4748
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216462264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1216462264
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3200543110
Short name T604
Test name
Test status
Simulation time 436964067 ps
CPU time 5.08 seconds
Started Mar 24 12:21:04 PM PDT 24
Finished Mar 24 12:21:10 PM PDT 24
Peak memory 198036 kb
Host smart-3cb09f68-b721-44d5-82a6-6de72b545404
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200543110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3200543110
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1277703822
Short name T730
Test name
Test status
Simulation time 76287065 ps
CPU time 0.91 seconds
Started Mar 24 12:21:08 PM PDT 24
Finished Mar 24 12:21:09 PM PDT 24
Peak memory 198072 kb
Host smart-9d084cb3-b7a7-4ca2-bd36-5e0b94afcf77
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277703822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1277703822
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.669454961
Short name T636
Test name
Test status
Simulation time 65719775 ps
CPU time 1.83 seconds
Started Mar 24 12:20:53 PM PDT 24
Finished Mar 24 12:20:55 PM PDT 24
Peak memory 198752 kb
Host smart-a87b88e3-9264-48a3-a083-380ddddd8413
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669454961 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.669454961
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3072500210
Short name T635
Test name
Test status
Simulation time 200751795 ps
CPU time 0.67 seconds
Started Mar 24 12:21:20 PM PDT 24
Finished Mar 24 12:21:21 PM PDT 24
Peak memory 196696 kb
Host smart-98dea60e-b607-403f-9428-a7c2d6893bf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072500210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3072500210
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.1640864551
Short name T664
Test name
Test status
Simulation time 37525526 ps
CPU time 0.58 seconds
Started Mar 24 12:20:38 PM PDT 24
Finished Mar 24 12:20:39 PM PDT 24
Peak memory 192620 kb
Host smart-f4a3121a-0ec9-4e8b-b766-4ae649a1f5d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640864551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1640864551
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.804058899
Short name T695
Test name
Test status
Simulation time 509455981 ps
CPU time 2.21 seconds
Started Mar 24 12:21:08 PM PDT 24
Finished Mar 24 12:21:10 PM PDT 24
Peak memory 198796 kb
Host smart-6175d46e-f65e-48f3-b0e8-faed19a63a66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804058899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_
outstanding.804058899
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.217364072
Short name T625
Test name
Test status
Simulation time 150988164 ps
CPU time 2.79 seconds
Started Mar 24 12:21:18 PM PDT 24
Finished Mar 24 12:21:22 PM PDT 24
Peak memory 199144 kb
Host smart-b5edf439-342a-437f-8c83-b042451443dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217364072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.217364072
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.565321590
Short name T117
Test name
Test status
Simulation time 95082366 ps
CPU time 1.89 seconds
Started Mar 24 12:19:28 PM PDT 24
Finished Mar 24 12:19:30 PM PDT 24
Peak memory 199132 kb
Host smart-8bb5a5ce-c28c-4f8c-aac0-870ec9f6856c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565321590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.565321590
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.807690323
Short name T674
Test name
Test status
Simulation time 14474117 ps
CPU time 0.57 seconds
Started Mar 24 12:20:34 PM PDT 24
Finished Mar 24 12:20:35 PM PDT 24
Peak memory 193760 kb
Host smart-d10f248b-0912-4064-8065-936e6f22c354
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807690323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.807690323
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.3485514101
Short name T685
Test name
Test status
Simulation time 28971370 ps
CPU time 0.56 seconds
Started Mar 24 12:20:34 PM PDT 24
Finished Mar 24 12:20:35 PM PDT 24
Peak memory 193764 kb
Host smart-026f4907-f0e4-4c6b-befc-97877eeca403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485514101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3485514101
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2206474654
Short name T686
Test name
Test status
Simulation time 45132864 ps
CPU time 0.6 seconds
Started Mar 24 12:20:32 PM PDT 24
Finished Mar 24 12:20:33 PM PDT 24
Peak memory 193816 kb
Host smart-6bffee5c-ad35-451e-950c-e7a4463f5642
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206474654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2206474654
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3891145487
Short name T632
Test name
Test status
Simulation time 17703233 ps
CPU time 0.62 seconds
Started Mar 24 12:20:34 PM PDT 24
Finished Mar 24 12:20:35 PM PDT 24
Peak memory 194008 kb
Host smart-77e1a45c-7dfa-4dcb-9532-4cd1f88a25b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891145487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3891145487
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.703160953
Short name T631
Test name
Test status
Simulation time 14024048 ps
CPU time 0.64 seconds
Started Mar 24 12:20:33 PM PDT 24
Finished Mar 24 12:20:34 PM PDT 24
Peak memory 194192 kb
Host smart-ba6d1c98-5994-476a-aed1-5f21212f3eee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703160953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.703160953
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1439573391
Short name T670
Test name
Test status
Simulation time 20995577 ps
CPU time 0.56 seconds
Started Mar 24 12:20:26 PM PDT 24
Finished Mar 24 12:20:27 PM PDT 24
Peak memory 193716 kb
Host smart-7f0b7376-0004-4e0e-a9ca-5e01f86ecfd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439573391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1439573391
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1847464945
Short name T693
Test name
Test status
Simulation time 13115493 ps
CPU time 0.61 seconds
Started Mar 24 12:20:25 PM PDT 24
Finished Mar 24 12:20:26 PM PDT 24
Peak memory 193780 kb
Host smart-ece96dc3-c1ef-4f47-948f-50e539f1506c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847464945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1847464945
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3077298718
Short name T614
Test name
Test status
Simulation time 13328761 ps
CPU time 0.57 seconds
Started Mar 24 12:20:34 PM PDT 24
Finished Mar 24 12:20:35 PM PDT 24
Peak memory 193760 kb
Host smart-f6cab8b7-adb3-4c37-b292-8fe22c1e80b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077298718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3077298718
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1064511811
Short name T662
Test name
Test status
Simulation time 16391720 ps
CPU time 0.67 seconds
Started Mar 24 12:20:38 PM PDT 24
Finished Mar 24 12:20:38 PM PDT 24
Peak memory 193792 kb
Host smart-d2bb911a-2698-4126-a36f-59caaa76f9c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064511811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1064511811
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2367588861
Short name T656
Test name
Test status
Simulation time 35175277 ps
CPU time 0.59 seconds
Started Mar 24 12:20:32 PM PDT 24
Finished Mar 24 12:20:33 PM PDT 24
Peak memory 193544 kb
Host smart-b16e6c54-f4a0-4785-bae6-6817d3a1e576
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367588861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2367588861
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4019039423
Short name T633
Test name
Test status
Simulation time 55034481 ps
CPU time 3.48 seconds
Started Mar 24 12:21:22 PM PDT 24
Finished Mar 24 12:21:26 PM PDT 24
Peak memory 198636 kb
Host smart-fd889a33-27a7-470a-9e59-9a3b7c3b5b99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019039423 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.4019039423
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2271138178
Short name T97
Test name
Test status
Simulation time 30186880 ps
CPU time 0.82 seconds
Started Mar 24 12:19:39 PM PDT 24
Finished Mar 24 12:19:40 PM PDT 24
Peak memory 198336 kb
Host smart-18c19440-cf15-4658-890c-5057a24e5cd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271138178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2271138178
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.184459385
Short name T699
Test name
Test status
Simulation time 17480255 ps
CPU time 0.62 seconds
Started Mar 24 12:20:53 PM PDT 24
Finished Mar 24 12:20:54 PM PDT 24
Peak memory 193720 kb
Host smart-b5dd46f0-dff8-48f1-a08e-59035fefecaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184459385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.184459385
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3286539755
Short name T678
Test name
Test status
Simulation time 342126609 ps
CPU time 1.84 seconds
Started Mar 24 12:21:41 PM PDT 24
Finished Mar 24 12:21:43 PM PDT 24
Peak memory 197472 kb
Host smart-486d0477-7763-44a3-ae5b-314badb065ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286539755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3286539755
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2968221832
Short name T618
Test name
Test status
Simulation time 324736785 ps
CPU time 2.15 seconds
Started Mar 24 12:20:57 PM PDT 24
Finished Mar 24 12:21:00 PM PDT 24
Peak memory 198276 kb
Host smart-6073b380-1e4a-4efd-9f69-ca75ac060a72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968221832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.2968221832
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3555528978
Short name T650
Test name
Test status
Simulation time 1447198302 ps
CPU time 4.25 seconds
Started Mar 24 12:20:57 PM PDT 24
Finished Mar 24 12:21:02 PM PDT 24
Peak memory 198104 kb
Host smart-3c557993-1422-4219-8c28-01c9f3fed592
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555528978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3555528978
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.948983284
Short name T599
Test name
Test status
Simulation time 206106074957 ps
CPU time 534.28 seconds
Started Mar 24 12:21:57 PM PDT 24
Finished Mar 24 12:30:51 PM PDT 24
Peak memory 223636 kb
Host smart-452543f5-6a2b-4a3b-b319-21fda40328df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948983284 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.948983284
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1174021150
Short name T712
Test name
Test status
Simulation time 144046635 ps
CPU time 0.8 seconds
Started Mar 24 12:21:56 PM PDT 24
Finished Mar 24 12:21:57 PM PDT 24
Peak memory 197640 kb
Host smart-9d94649c-437d-4744-a3ff-3e298fb2e1c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174021150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1174021150
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2635044534
Short name T713
Test name
Test status
Simulation time 31386536 ps
CPU time 0.54 seconds
Started Mar 24 12:22:09 PM PDT 24
Finished Mar 24 12:22:09 PM PDT 24
Peak memory 193468 kb
Host smart-d6d53c9b-c63e-4190-a02b-eecd6bee6877
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635044534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2635044534
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.955541717
Short name T671
Test name
Test status
Simulation time 37108037 ps
CPU time 1.68 seconds
Started Mar 24 12:21:57 PM PDT 24
Finished Mar 24 12:21:59 PM PDT 24
Peak memory 198832 kb
Host smart-703832c7-d0b9-44ad-aec1-ae8daf4984a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955541717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_
outstanding.955541717
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3526925003
Short name T704
Test name
Test status
Simulation time 663080889 ps
CPU time 3.1 seconds
Started Mar 24 12:22:09 PM PDT 24
Finished Mar 24 12:22:12 PM PDT 24
Peak memory 198920 kb
Host smart-9935abf7-f722-413f-92a8-f7b62ea9180e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526925003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3526925003
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2382759792
Short name T714
Test name
Test status
Simulation time 285401322725 ps
CPU time 272.02 seconds
Started Mar 24 12:19:38 PM PDT 24
Finished Mar 24 12:24:10 PM PDT 24
Peak memory 214696 kb
Host smart-a2e076b9-c51c-415c-8e90-8acbfd281a9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382759792 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.2382759792
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.4098816016
Short name T597
Test name
Test status
Simulation time 15054557 ps
CPU time 0.82 seconds
Started Mar 24 12:21:56 PM PDT 24
Finished Mar 24 12:21:57 PM PDT 24
Peak memory 197464 kb
Host smart-98243c10-4f08-4cce-856c-6c6510469e3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098816016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.4098816016
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2875646979
Short name T609
Test name
Test status
Simulation time 13282489 ps
CPU time 0.6 seconds
Started Mar 24 12:22:10 PM PDT 24
Finished Mar 24 12:22:11 PM PDT 24
Peak memory 193796 kb
Host smart-dd4d49f9-3d1f-48fa-9c0a-192d29358472
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875646979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2875646979
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3179830125
Short name T668
Test name
Test status
Simulation time 22566326 ps
CPU time 1.01 seconds
Started Mar 24 12:22:04 PM PDT 24
Finished Mar 24 12:22:05 PM PDT 24
Peak memory 199016 kb
Host smart-432964aa-143b-4295-a037-dd3ecf0115ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179830125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3179830125
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.4183338234
Short name T705
Test name
Test status
Simulation time 124161982 ps
CPU time 1.56 seconds
Started Mar 24 12:21:40 PM PDT 24
Finished Mar 24 12:21:42 PM PDT 24
Peak memory 196456 kb
Host smart-5c181538-cdf0-494f-bdfb-5ed4fad36f24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183338234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.4183338234
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1469910254
Short name T58
Test name
Test status
Simulation time 773211814 ps
CPU time 1.89 seconds
Started Mar 24 12:21:40 PM PDT 24
Finished Mar 24 12:21:43 PM PDT 24
Peak memory 196628 kb
Host smart-c55a37c3-6c30-4aa3-ba09-a68cce301924
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469910254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1469910254
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2863048766
Short name T615
Test name
Test status
Simulation time 150694693 ps
CPU time 2.78 seconds
Started Mar 24 12:19:38 PM PDT 24
Finished Mar 24 12:19:41 PM PDT 24
Peak memory 199360 kb
Host smart-47dd4e39-5d5e-4df2-8c9d-e3bc9f8e3ad0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863048766 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2863048766
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3316272591
Short name T98
Test name
Test status
Simulation time 14057084 ps
CPU time 0.77 seconds
Started Mar 24 12:22:04 PM PDT 24
Finished Mar 24 12:22:05 PM PDT 24
Peak memory 198840 kb
Host smart-c3babcd0-f0a6-4114-8586-7c12a0395ccb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316272591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3316272591
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.993906875
Short name T701
Test name
Test status
Simulation time 56233201 ps
CPU time 0.58 seconds
Started Mar 24 12:21:58 PM PDT 24
Finished Mar 24 12:21:59 PM PDT 24
Peak memory 193912 kb
Host smart-dc6ba1b1-635b-4550-a63a-e3d0a4a813e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993906875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.993906875
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1736985061
Short name T619
Test name
Test status
Simulation time 114676625 ps
CPU time 1.24 seconds
Started Mar 24 12:22:01 PM PDT 24
Finished Mar 24 12:22:03 PM PDT 24
Peak memory 198976 kb
Host smart-3b5c6469-8bee-48f1-82ca-b099e7d083bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736985061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1736985061
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1980951334
Short name T694
Test name
Test status
Simulation time 88404206 ps
CPU time 1.47 seconds
Started Mar 24 12:19:37 PM PDT 24
Finished Mar 24 12:19:40 PM PDT 24
Peak memory 199216 kb
Host smart-422de70c-17b8-4db4-86e1-11f03a8ebfc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980951334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.1980951334
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3356066015
Short name T110
Test name
Test status
Simulation time 231133712 ps
CPU time 3.89 seconds
Started Mar 24 12:22:04 PM PDT 24
Finished Mar 24 12:22:08 PM PDT 24
Peak memory 199068 kb
Host smart-39311363-5425-4984-9573-971274332573
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356066015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3356066015
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.512160919
Short name T661
Test name
Test status
Simulation time 91713058697 ps
CPU time 326.12 seconds
Started Mar 24 12:22:09 PM PDT 24
Finished Mar 24 12:27:35 PM PDT 24
Peak memory 214728 kb
Host smart-de719a37-754f-41f0-bb56-c3f1395f46a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512160919 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.512160919
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.195677826
Short name T681
Test name
Test status
Simulation time 26963148 ps
CPU time 0.7 seconds
Started Mar 24 12:22:05 PM PDT 24
Finished Mar 24 12:22:05 PM PDT 24
Peak memory 196480 kb
Host smart-65aaf96d-a7cd-4ff3-9150-88c3da4decc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195677826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.195677826
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1190264287
Short name T611
Test name
Test status
Simulation time 58219560 ps
CPU time 0.57 seconds
Started Mar 24 12:21:57 PM PDT 24
Finished Mar 24 12:21:58 PM PDT 24
Peak memory 193724 kb
Host smart-9c0fdd56-23c8-49b5-99d6-09504771a2d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190264287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1190264287
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1151900623
Short name T672
Test name
Test status
Simulation time 122110725 ps
CPU time 1.55 seconds
Started Mar 24 12:22:05 PM PDT 24
Finished Mar 24 12:22:07 PM PDT 24
Peak memory 199020 kb
Host smart-a455263d-46b5-4fde-84a2-365569fbf482
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151900623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.1151900623
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1816552493
Short name T719
Test name
Test status
Simulation time 355169025 ps
CPU time 3.88 seconds
Started Mar 24 12:21:46 PM PDT 24
Finished Mar 24 12:21:51 PM PDT 24
Peak memory 198464 kb
Host smart-6b8ef4da-b346-4f7b-863e-674f65ec3c14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816552493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1816552493
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2212485625
Short name T116
Test name
Test status
Simulation time 84085443 ps
CPU time 1.8 seconds
Started Mar 24 12:20:54 PM PDT 24
Finished Mar 24 12:20:56 PM PDT 24
Peak memory 198940 kb
Host smart-10ecb914-9460-4511-ab59-59d6d5274b31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212485625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2212485625
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.4106386582
Short name T307
Test name
Test status
Simulation time 16754438 ps
CPU time 0.58 seconds
Started Mar 24 01:01:20 PM PDT 24
Finished Mar 24 01:01:21 PM PDT 24
Peak memory 194504 kb
Host smart-d04df493-4c42-4c25-8336-4e4f9bd21fe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106386582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.4106386582
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.1373260049
Short name T148
Test name
Test status
Simulation time 2599063038 ps
CPU time 20.76 seconds
Started Mar 24 01:01:15 PM PDT 24
Finished Mar 24 01:01:36 PM PDT 24
Peak memory 215656 kb
Host smart-60fc9fb4-89e5-47d8-9adb-10ae19eb466c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1373260049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.1373260049
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3462048165
Short name T262
Test name
Test status
Simulation time 1833415034 ps
CPU time 36.9 seconds
Started Mar 24 01:01:24 PM PDT 24
Finished Mar 24 01:02:01 PM PDT 24
Peak memory 199944 kb
Host smart-e41a8979-3ab9-4cfa-b1ee-d68ed9f38e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462048165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3462048165
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1008456522
Short name T287
Test name
Test status
Simulation time 277017418 ps
CPU time 15.68 seconds
Started Mar 24 01:01:16 PM PDT 24
Finished Mar 24 01:01:31 PM PDT 24
Peak memory 199816 kb
Host smart-80642b9e-8c9d-49fc-a1f9-0d9e14b9c1b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1008456522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1008456522
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2699518382
Short name T423
Test name
Test status
Simulation time 939061735 ps
CPU time 52.28 seconds
Started Mar 24 01:01:24 PM PDT 24
Finished Mar 24 01:02:17 PM PDT 24
Peak memory 199912 kb
Host smart-e1d21a15-f4bb-41c1-a6e5-2d7d2406e7be
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699518382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2699518382
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1647403576
Short name T570
Test name
Test status
Simulation time 4943199208 ps
CPU time 98.72 seconds
Started Mar 24 01:01:15 PM PDT 24
Finished Mar 24 01:02:54 PM PDT 24
Peak memory 200096 kb
Host smart-a5bf8bf1-7fbf-4e2e-b014-636033b1ba55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647403576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1647403576
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1441758704
Short name T30
Test name
Test status
Simulation time 167360579 ps
CPU time 0.98 seconds
Started Mar 24 01:01:21 PM PDT 24
Finished Mar 24 01:01:22 PM PDT 24
Peak memory 219232 kb
Host smart-08463e68-c4d6-4096-a362-566b38f0d8eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441758704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1441758704
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.2421343883
Short name T281
Test name
Test status
Simulation time 499408275 ps
CPU time 4.04 seconds
Started Mar 24 01:01:13 PM PDT 24
Finished Mar 24 01:01:17 PM PDT 24
Peak memory 200020 kb
Host smart-6b88bd27-1a06-455c-aca9-57942bf31845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421343883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2421343883
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3328550727
Short name T444
Test name
Test status
Simulation time 66917662 ps
CPU time 0.63 seconds
Started Mar 24 01:01:21 PM PDT 24
Finished Mar 24 01:01:22 PM PDT 24
Peak memory 195236 kb
Host smart-4c77bca5-2e06-45f3-bb05-f909b21cfdd4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328550727 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3328550727
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.2885643674
Short name T259
Test name
Test status
Simulation time 61042519 ps
CPU time 1.4 seconds
Started Mar 24 01:01:22 PM PDT 24
Finished Mar 24 01:01:23 PM PDT 24
Peak memory 199736 kb
Host smart-35f9c07e-c45b-4f86-bf6a-f4990950b6d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885643674 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.2885643674
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.3510564018
Short name T542
Test name
Test status
Simulation time 183079725749 ps
CPU time 554.44 seconds
Started Mar 24 01:01:21 PM PDT 24
Finished Mar 24 01:10:36 PM PDT 24
Peak memory 200012 kb
Host smart-9983d4e1-3cb3-4822-b3f7-3298058ca977
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510564018 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.3510564018
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3178610592
Short name T517
Test name
Test status
Simulation time 19714857076 ps
CPU time 71.59 seconds
Started Mar 24 01:01:21 PM PDT 24
Finished Mar 24 01:02:33 PM PDT 24
Peak memory 200132 kb
Host smart-4e4dc2bd-bfa0-4af0-aad2-2ddc8a672a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178610592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3178610592
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.1104875265
Short name T321
Test name
Test status
Simulation time 16195854 ps
CPU time 0.64 seconds
Started Mar 24 01:01:21 PM PDT 24
Finished Mar 24 01:01:22 PM PDT 24
Peak memory 195444 kb
Host smart-c6940172-3afd-43b5-b12c-e5c03cfa2f50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104875265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1104875265
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.2004158132
Short name T356
Test name
Test status
Simulation time 9504964440 ps
CPU time 46.07 seconds
Started Mar 24 01:01:22 PM PDT 24
Finished Mar 24 01:02:08 PM PDT 24
Peak memory 209752 kb
Host smart-1abdcfc4-9e1c-49b9-a6de-f9067d555c81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2004158132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.2004158132
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.1150269532
Short name T85
Test name
Test status
Simulation time 10103031138 ps
CPU time 59.77 seconds
Started Mar 24 01:01:20 PM PDT 24
Finished Mar 24 01:02:21 PM PDT 24
Peak memory 200072 kb
Host smart-c2655e79-718b-4551-853c-7a82eb29d73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150269532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1150269532
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2597338415
Short name T375
Test name
Test status
Simulation time 930524693 ps
CPU time 50.27 seconds
Started Mar 24 01:01:19 PM PDT 24
Finished Mar 24 01:02:10 PM PDT 24
Peak memory 199988 kb
Host smart-f2e522aa-ef66-45ca-8661-f56575e6e5e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2597338415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2597338415
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.1130587113
Short name T292
Test name
Test status
Simulation time 3552872942 ps
CPU time 49.05 seconds
Started Mar 24 01:01:22 PM PDT 24
Finished Mar 24 01:02:11 PM PDT 24
Peak memory 200092 kb
Host smart-0c18df80-ce82-4af1-a0bb-5e07ebf88c1d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130587113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1130587113
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.1574825420
Short name T566
Test name
Test status
Simulation time 9895747240 ps
CPU time 49.1 seconds
Started Mar 24 01:01:20 PM PDT 24
Finished Mar 24 01:02:09 PM PDT 24
Peak memory 200024 kb
Host smart-99a26967-db66-4cf0-91b1-984c1a2c74d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574825420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.1574825420
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.2251822405
Short name T32
Test name
Test status
Simulation time 347495530 ps
CPU time 1 seconds
Started Mar 24 01:01:21 PM PDT 24
Finished Mar 24 01:01:22 PM PDT 24
Peak memory 219148 kb
Host smart-bf73e0f0-f328-4bdc-bb97-07947e3475d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251822405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2251822405
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.2256887188
Short name T248
Test name
Test status
Simulation time 822459304 ps
CPU time 3.42 seconds
Started Mar 24 01:01:22 PM PDT 24
Finished Mar 24 01:01:26 PM PDT 24
Peak memory 199952 kb
Host smart-f5bf263d-ef02-4515-9314-88526ecedf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256887188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2256887188
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.983376397
Short name T49
Test name
Test status
Simulation time 690611928122 ps
CPU time 505.04 seconds
Started Mar 24 01:01:22 PM PDT 24
Finished Mar 24 01:09:47 PM PDT 24
Peak memory 208284 kb
Host smart-c1c85d63-f4c1-4bbb-87db-8be74e67d4f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983376397 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.983376397
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.857337181
Short name T69
Test name
Test status
Simulation time 76136375 ps
CPU time 1.3 seconds
Started Mar 24 01:01:21 PM PDT 24
Finished Mar 24 01:01:23 PM PDT 24
Peak memory 199984 kb
Host smart-3932cc60-ee13-4a36-8c3a-a5048a23500e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857337181 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_hmac_vectors.857337181
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.267452526
Short name T538
Test name
Test status
Simulation time 150181530891 ps
CPU time 469.64 seconds
Started Mar 24 01:01:21 PM PDT 24
Finished Mar 24 01:09:11 PM PDT 24
Peak memory 200024 kb
Host smart-d3c611b0-102f-4014-9cd0-b8e253de00c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267452526 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.267452526
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1395404984
Short name T588
Test name
Test status
Simulation time 4387898733 ps
CPU time 32.79 seconds
Started Mar 24 01:01:21 PM PDT 24
Finished Mar 24 01:01:54 PM PDT 24
Peak memory 200096 kb
Host smart-9824ea44-efbc-48b0-823c-0a13f53358a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395404984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1395404984
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3740839576
Short name T55
Test name
Test status
Simulation time 313499845 ps
CPU time 12.72 seconds
Started Mar 24 01:01:55 PM PDT 24
Finished Mar 24 01:02:08 PM PDT 24
Peak memory 221548 kb
Host smart-91c69650-31c5-4931-acfc-2c0f121d9fc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3740839576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3740839576
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.3240850401
Short name T573
Test name
Test status
Simulation time 2561045321 ps
CPU time 39.72 seconds
Started Mar 24 01:01:51 PM PDT 24
Finished Mar 24 01:02:30 PM PDT 24
Peak memory 200000 kb
Host smart-7adbcb1e-12b5-4690-8149-c7a2c8a51d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240850401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3240850401
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.3926246834
Short name T553
Test name
Test status
Simulation time 1010304734 ps
CPU time 31.44 seconds
Started Mar 24 01:01:55 PM PDT 24
Finished Mar 24 01:02:26 PM PDT 24
Peak memory 200240 kb
Host smart-5fc5205b-829c-44a5-93d6-352acad2edf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3926246834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.3926246834
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.322663125
Short name T490
Test name
Test status
Simulation time 2770621196 ps
CPU time 148.91 seconds
Started Mar 24 01:02:00 PM PDT 24
Finished Mar 24 01:04:29 PM PDT 24
Peak memory 200088 kb
Host smart-cdadb5c9-8026-45c2-9fda-435faa47097b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322663125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.322663125
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3476590870
Short name T558
Test name
Test status
Simulation time 3208744319 ps
CPU time 62.83 seconds
Started Mar 24 01:01:56 PM PDT 24
Finished Mar 24 01:02:59 PM PDT 24
Peak memory 200092 kb
Host smart-459f1629-c917-406e-8a35-ea911bf57c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476590870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3476590870
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1015021261
Short name T536
Test name
Test status
Simulation time 1968672542 ps
CPU time 5.73 seconds
Started Mar 24 01:02:00 PM PDT 24
Finished Mar 24 01:02:06 PM PDT 24
Peak memory 199980 kb
Host smart-83b4b9ba-ca3e-4a92-bf09-790c7b72a2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015021261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1015021261
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.619923413
Short name T547
Test name
Test status
Simulation time 7386331221 ps
CPU time 394.07 seconds
Started Mar 24 01:01:54 PM PDT 24
Finished Mar 24 01:08:28 PM PDT 24
Peak memory 232472 kb
Host smart-27c0dd7b-62c4-40e1-aa1a-71d936fbd963
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619923413 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.619923413
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.4217198504
Short name T142
Test name
Test status
Simulation time 51791612 ps
CPU time 1.05 seconds
Started Mar 24 01:01:53 PM PDT 24
Finished Mar 24 01:01:54 PM PDT 24
Peak memory 199532 kb
Host smart-e0ef0f3e-1a14-48f1-bad5-74a2781f83bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217198504 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.4217198504
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.3804222200
Short name T398
Test name
Test status
Simulation time 58673766259 ps
CPU time 511.69 seconds
Started Mar 24 01:01:57 PM PDT 24
Finished Mar 24 01:10:29 PM PDT 24
Peak memory 200028 kb
Host smart-bd0167cf-89e6-41dc-b2af-49144215b51c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804222200 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.3804222200
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2320924172
Short name T188
Test name
Test status
Simulation time 1082669503 ps
CPU time 6.16 seconds
Started Mar 24 01:01:56 PM PDT 24
Finished Mar 24 01:02:02 PM PDT 24
Peak memory 199968 kb
Host smart-4fc1a75b-7f8b-46b6-ae5e-b0d3c9d92df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320924172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2320924172
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3392478663
Short name T1
Test name
Test status
Simulation time 13467981 ps
CPU time 0.6 seconds
Started Mar 24 01:02:00 PM PDT 24
Finished Mar 24 01:02:01 PM PDT 24
Peak memory 194488 kb
Host smart-9e78df3a-0f2c-44c6-82ff-daaf9a30f25f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392478663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3392478663
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.3543663385
Short name T4
Test name
Test status
Simulation time 989518964 ps
CPU time 18.6 seconds
Started Mar 24 01:01:52 PM PDT 24
Finished Mar 24 01:02:11 PM PDT 24
Peak memory 208160 kb
Host smart-3db91199-649e-470b-a6c7-0309f5ffde4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3543663385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3543663385
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.1192476361
Short name T160
Test name
Test status
Simulation time 2718788285 ps
CPU time 56.56 seconds
Started Mar 24 01:01:55 PM PDT 24
Finished Mar 24 01:02:51 PM PDT 24
Peak memory 200344 kb
Host smart-46ca0e8f-1191-47fb-beae-c9d61747a116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192476361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1192476361
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.4229750869
Short name T293
Test name
Test status
Simulation time 8167750194 ps
CPU time 121.22 seconds
Started Mar 24 01:01:55 PM PDT 24
Finished Mar 24 01:03:56 PM PDT 24
Peak memory 200072 kb
Host smart-f2e038f9-e93d-41ca-8087-abb1334c71a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4229750869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.4229750869
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.4217221959
Short name T201
Test name
Test status
Simulation time 4361027240 ps
CPU time 236.44 seconds
Started Mar 24 01:01:56 PM PDT 24
Finished Mar 24 01:05:52 PM PDT 24
Peak memory 200004 kb
Host smart-0f0c33a6-7870-40ad-9aab-805de7f6d171
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217221959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.4217221959
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.746569748
Short name T164
Test name
Test status
Simulation time 4104448918 ps
CPU time 77.82 seconds
Started Mar 24 01:01:55 PM PDT 24
Finished Mar 24 01:03:13 PM PDT 24
Peak memory 200036 kb
Host smart-ec421515-01ee-4d0c-9d7e-0b6b19a4fe9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746569748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.746569748
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.3698044114
Short name T206
Test name
Test status
Simulation time 563233588 ps
CPU time 1.84 seconds
Started Mar 24 01:02:00 PM PDT 24
Finished Mar 24 01:02:02 PM PDT 24
Peak memory 199988 kb
Host smart-3f4c6a07-5bd8-4673-8736-6afba37eb7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698044114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3698044114
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3794505616
Short name T469
Test name
Test status
Simulation time 457303751543 ps
CPU time 1915.11 seconds
Started Mar 24 01:01:55 PM PDT 24
Finished Mar 24 01:33:50 PM PDT 24
Peak memory 241060 kb
Host smart-4ffa3e57-a9ae-44c4-b2df-75667715ccbe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794505616 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3794505616
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.330653418
Short name T283
Test name
Test status
Simulation time 54499260 ps
CPU time 1.04 seconds
Started Mar 24 01:01:55 PM PDT 24
Finished Mar 24 01:01:56 PM PDT 24
Peak memory 199300 kb
Host smart-b3dba8fd-708b-4079-b877-ca7e5d2307f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330653418 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_test_hmac_vectors.330653418
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.2987105449
Short name T351
Test name
Test status
Simulation time 52248383403 ps
CPU time 498.55 seconds
Started Mar 24 01:02:00 PM PDT 24
Finished Mar 24 01:10:19 PM PDT 24
Peak memory 200016 kb
Host smart-4991b7f0-aac1-4753-aeae-50f0d304fada
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987105449 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.2987105449
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.3823524360
Short name T153
Test name
Test status
Simulation time 2978237023 ps
CPU time 65.47 seconds
Started Mar 24 01:01:57 PM PDT 24
Finished Mar 24 01:03:03 PM PDT 24
Peak memory 200104 kb
Host smart-04ab05ea-5733-4fcb-abc2-c070cc6c74db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823524360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3823524360
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1734832600
Short name T503
Test name
Test status
Simulation time 36079004 ps
CPU time 0.59 seconds
Started Mar 24 01:01:59 PM PDT 24
Finished Mar 24 01:02:00 PM PDT 24
Peak memory 195136 kb
Host smart-201040c2-7e59-4185-9894-e7a4e5c2b283
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734832600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1734832600
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1037738253
Short name T200
Test name
Test status
Simulation time 1051009449 ps
CPU time 36.89 seconds
Started Mar 24 01:01:51 PM PDT 24
Finished Mar 24 01:02:28 PM PDT 24
Peak memory 212176 kb
Host smart-407a2cee-e829-4f0e-9cf4-57ffe3d92bc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1037738253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1037738253
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1332749468
Short name T304
Test name
Test status
Simulation time 2340215102 ps
CPU time 37.31 seconds
Started Mar 24 01:01:52 PM PDT 24
Finished Mar 24 01:02:30 PM PDT 24
Peak memory 200012 kb
Host smart-4de135f6-088f-4256-9d51-a97395823599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332749468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1332749468
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.1672542318
Short name T374
Test name
Test status
Simulation time 1116311431 ps
CPU time 40.18 seconds
Started Mar 24 01:01:55 PM PDT 24
Finished Mar 24 01:02:36 PM PDT 24
Peak memory 200024 kb
Host smart-3c52ab3e-effd-4660-b01e-cbb879a2af5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1672542318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1672542318
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2458641968
Short name T368
Test name
Test status
Simulation time 34297372801 ps
CPU time 105.22 seconds
Started Mar 24 01:01:53 PM PDT 24
Finished Mar 24 01:03:38 PM PDT 24
Peak memory 200092 kb
Host smart-b6b4725e-a17a-4fab-a5d5-64afd947e188
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458641968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2458641968
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1262340270
Short name T447
Test name
Test status
Simulation time 27032692018 ps
CPU time 93.15 seconds
Started Mar 24 01:01:57 PM PDT 24
Finished Mar 24 01:03:31 PM PDT 24
Peak memory 200064 kb
Host smart-04d33f5c-77cf-48c7-91a4-635680a6fc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262340270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1262340270
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.2722660820
Short name T220
Test name
Test status
Simulation time 280815028 ps
CPU time 2.42 seconds
Started Mar 24 01:01:57 PM PDT 24
Finished Mar 24 01:02:00 PM PDT 24
Peak memory 199992 kb
Host smart-4946618c-4ca2-4d5e-b4b2-2c8e8042e423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722660820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2722660820
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1994065740
Short name T357
Test name
Test status
Simulation time 51018993015 ps
CPU time 925.09 seconds
Started Mar 24 01:01:59 PM PDT 24
Finished Mar 24 01:17:24 PM PDT 24
Peak memory 200096 kb
Host smart-5f19f6ad-8e1f-488f-9fa8-abae16dc96ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994065740 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1994065740
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.407563790
Short name T156
Test name
Test status
Simulation time 55999201 ps
CPU time 1.05 seconds
Started Mar 24 01:01:58 PM PDT 24
Finished Mar 24 01:01:59 PM PDT 24
Peak memory 199564 kb
Host smart-e06f4f4a-bc4e-49e8-918e-3e9e88ca34a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407563790 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_hmac_vectors.407563790
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.1858650557
Short name T199
Test name
Test status
Simulation time 18185150655 ps
CPU time 462.09 seconds
Started Mar 24 01:01:57 PM PDT 24
Finished Mar 24 01:09:39 PM PDT 24
Peak memory 200052 kb
Host smart-e4e6bca1-f11a-4ae2-9b36-d1980f791042
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858650557 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.1858650557
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.629718526
Short name T124
Test name
Test status
Simulation time 21240352656 ps
CPU time 72.9 seconds
Started Mar 24 01:01:53 PM PDT 24
Finished Mar 24 01:03:06 PM PDT 24
Peak memory 200088 kb
Host smart-3527ff13-4fd2-43bf-aa4b-3dc627707878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629718526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.629718526
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/123.hmac_stress_all_with_rand_reset.3901622638
Short name T64
Test name
Test status
Simulation time 34977549855 ps
CPU time 1160.96 seconds
Started Mar 24 01:04:04 PM PDT 24
Finished Mar 24 01:23:25 PM PDT 24
Peak memory 239088 kb
Host smart-51ce6138-0b24-439d-99c8-1bd187877919
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3901622638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.hmac_stress_all_with_rand_reset.3901622638
Directory /workspace/123.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.4036840120
Short name T192
Test name
Test status
Simulation time 41494073 ps
CPU time 0.56 seconds
Started Mar 24 01:01:58 PM PDT 24
Finished Mar 24 01:01:58 PM PDT 24
Peak memory 194508 kb
Host smart-48d16dca-b474-4b9b-b312-bdaf2f8ad3cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036840120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.4036840120
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2128735890
Short name T52
Test name
Test status
Simulation time 1186040205 ps
CPU time 10.58 seconds
Started Mar 24 01:01:59 PM PDT 24
Finished Mar 24 01:02:10 PM PDT 24
Peak memory 199992 kb
Host smart-56e74f89-f372-4082-9aaa-5e5ec33a1619
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2128735890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2128735890
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2638958089
Short name T331
Test name
Test status
Simulation time 54104766 ps
CPU time 2.75 seconds
Started Mar 24 01:02:00 PM PDT 24
Finished Mar 24 01:02:03 PM PDT 24
Peak memory 199912 kb
Host smart-0da9c9c6-2367-4cf9-a96b-7489f850e8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638958089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2638958089
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.3625907050
Short name T575
Test name
Test status
Simulation time 2113199608 ps
CPU time 116.55 seconds
Started Mar 24 01:01:58 PM PDT 24
Finished Mar 24 01:03:55 PM PDT 24
Peak memory 199976 kb
Host smart-a116985f-7cb2-4fda-bd5c-0904271413e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3625907050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.3625907050
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.298644088
Short name T250
Test name
Test status
Simulation time 15646068761 ps
CPU time 196.46 seconds
Started Mar 24 01:01:59 PM PDT 24
Finished Mar 24 01:05:16 PM PDT 24
Peak memory 200080 kb
Host smart-3b36ee1c-43a8-4e1a-a6bf-70b03349e132
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298644088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.298644088
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.3378983798
Short name T158
Test name
Test status
Simulation time 24743278274 ps
CPU time 104.68 seconds
Started Mar 24 01:01:58 PM PDT 24
Finished Mar 24 01:03:43 PM PDT 24
Peak memory 200040 kb
Host smart-de24bb0e-ba96-4043-b88b-7bfe2ac99e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378983798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.3378983798
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.4273834343
Short name T219
Test name
Test status
Simulation time 285311773 ps
CPU time 3.79 seconds
Started Mar 24 01:01:59 PM PDT 24
Finished Mar 24 01:02:02 PM PDT 24
Peak memory 199936 kb
Host smart-b0115b73-4c58-4f45-a49a-a9dbcfda4894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273834343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.4273834343
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.567756630
Short name T25
Test name
Test status
Simulation time 79694392383 ps
CPU time 821.51 seconds
Started Mar 24 01:01:58 PM PDT 24
Finished Mar 24 01:15:40 PM PDT 24
Peak memory 200076 kb
Host smart-2a3142e4-bcf5-4d2e-a50e-f9f8174de85f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567756630 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.567756630
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.2499007548
Short name T190
Test name
Test status
Simulation time 159904639 ps
CPU time 0.98 seconds
Started Mar 24 01:01:58 PM PDT 24
Finished Mar 24 01:01:59 PM PDT 24
Peak memory 198664 kb
Host smart-4a3ca947-b69c-4429-81ac-8a945ff7be6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499007548 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.2499007548
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.2485501426
Short name T529
Test name
Test status
Simulation time 9438044656 ps
CPU time 475.73 seconds
Started Mar 24 01:01:59 PM PDT 24
Finished Mar 24 01:09:55 PM PDT 24
Peak memory 199948 kb
Host smart-3482cb6f-124c-4345-b184-7dca445391d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485501426 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.2485501426
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.1967977800
Short name T556
Test name
Test status
Simulation time 19503790717 ps
CPU time 99.61 seconds
Started Mar 24 01:02:00 PM PDT 24
Finished Mar 24 01:03:40 PM PDT 24
Peak memory 200040 kb
Host smart-c9ad3228-2f5a-43a6-a8a6-e3ba0b70d9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967977800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.1967977800
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.3301281803
Short name T280
Test name
Test status
Simulation time 14330925 ps
CPU time 0.58 seconds
Started Mar 24 01:02:10 PM PDT 24
Finished Mar 24 01:02:10 PM PDT 24
Peak memory 194552 kb
Host smart-0024d3ba-47d0-437b-adbe-95646c4ce5de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301281803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.3301281803
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.3802799224
Short name T593
Test name
Test status
Simulation time 4590270577 ps
CPU time 35.34 seconds
Started Mar 24 01:01:57 PM PDT 24
Finished Mar 24 01:02:32 PM PDT 24
Peak memory 232608 kb
Host smart-8b85b0a4-3cab-47a5-ab3b-ef07d6717b83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3802799224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.3802799224
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3780672915
Short name T557
Test name
Test status
Simulation time 3277878837 ps
CPU time 46.89 seconds
Started Mar 24 01:01:58 PM PDT 24
Finished Mar 24 01:02:45 PM PDT 24
Peak memory 200032 kb
Host smart-7da7e3d2-1c4b-4878-8683-bf92e68c2158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780672915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3780672915
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3039998704
Short name T541
Test name
Test status
Simulation time 11977237502 ps
CPU time 166.43 seconds
Started Mar 24 01:01:59 PM PDT 24
Finished Mar 24 01:04:46 PM PDT 24
Peak memory 200020 kb
Host smart-1f97e37d-a406-4981-88b7-f7a72ba8171e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3039998704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3039998704
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.940106348
Short name T403
Test name
Test status
Simulation time 2059827449 ps
CPU time 28.13 seconds
Started Mar 24 01:02:00 PM PDT 24
Finished Mar 24 01:02:28 PM PDT 24
Peak memory 200040 kb
Host smart-08f83cb2-89ad-4cdf-8d57-7e0e8fc79388
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940106348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.940106348
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.725176524
Short name T239
Test name
Test status
Simulation time 1225451827 ps
CPU time 72.08 seconds
Started Mar 24 01:01:57 PM PDT 24
Finished Mar 24 01:03:09 PM PDT 24
Peak memory 200012 kb
Host smart-a4271595-6af7-4146-8bc5-45c4c9f7baa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725176524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.725176524
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3168592183
Short name T240
Test name
Test status
Simulation time 82493213 ps
CPU time 1.77 seconds
Started Mar 24 01:01:58 PM PDT 24
Finished Mar 24 01:02:00 PM PDT 24
Peak memory 199972 kb
Host smart-8afbe5e4-0be7-4bb2-8001-de074150ad7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168592183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3168592183
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.4192254032
Short name T404
Test name
Test status
Simulation time 6359948425 ps
CPU time 369.12 seconds
Started Mar 24 01:01:58 PM PDT 24
Finished Mar 24 01:08:07 PM PDT 24
Peak memory 200076 kb
Host smart-68c40133-53ad-46a2-80d1-c69d7d5b64f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192254032 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.4192254032
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.3288285209
Short name T236
Test name
Test status
Simulation time 370704886 ps
CPU time 1.08 seconds
Started Mar 24 01:01:58 PM PDT 24
Finished Mar 24 01:01:59 PM PDT 24
Peak memory 199400 kb
Host smart-83699845-5803-4646-9413-db53d79952e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288285209 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.3288285209
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.3487766095
Short name T242
Test name
Test status
Simulation time 63108497344 ps
CPU time 424.99 seconds
Started Mar 24 01:01:59 PM PDT 24
Finished Mar 24 01:09:04 PM PDT 24
Peak memory 200044 kb
Host smart-0e8cdff4-2175-4efe-820e-742737d92de9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487766095 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.3487766095
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2468985594
Short name T324
Test name
Test status
Simulation time 2513015726 ps
CPU time 37.84 seconds
Started Mar 24 01:01:57 PM PDT 24
Finished Mar 24 01:02:35 PM PDT 24
Peak memory 200096 kb
Host smart-38c563ba-b735-4721-9afb-93dfc3c51815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468985594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2468985594
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.792688372
Short name T297
Test name
Test status
Simulation time 17087603 ps
CPU time 0.56 seconds
Started Mar 24 01:02:07 PM PDT 24
Finished Mar 24 01:02:08 PM PDT 24
Peak memory 195272 kb
Host smart-379a32e9-ea27-4ffa-ae85-16e2ce042c71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792688372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.792688372
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3037257412
Short name T397
Test name
Test status
Simulation time 1948859857 ps
CPU time 35.48 seconds
Started Mar 24 01:02:09 PM PDT 24
Finished Mar 24 01:02:45 PM PDT 24
Peak memory 218300 kb
Host smart-47d1eaf0-973c-4b84-b197-fa46c1bbacda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3037257412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3037257412
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2567396970
Short name T385
Test name
Test status
Simulation time 1390214427 ps
CPU time 17.35 seconds
Started Mar 24 01:02:05 PM PDT 24
Finished Mar 24 01:02:23 PM PDT 24
Peak memory 200016 kb
Host smart-471f2809-4a7e-40e9-92e7-316ec60e770f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567396970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2567396970
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1511304358
Short name T582
Test name
Test status
Simulation time 1581489793 ps
CPU time 91.28 seconds
Started Mar 24 01:02:06 PM PDT 24
Finished Mar 24 01:03:37 PM PDT 24
Peak memory 200008 kb
Host smart-32166169-2de0-4958-b27c-d175f8401cd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1511304358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1511304358
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.117052624
Short name T474
Test name
Test status
Simulation time 2577369532 ps
CPU time 112.31 seconds
Started Mar 24 01:02:05 PM PDT 24
Finished Mar 24 01:03:58 PM PDT 24
Peak memory 200048 kb
Host smart-6c686607-23ce-455d-9c24-322f93c0b345
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117052624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.117052624
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_smoke.3140121302
Short name T440
Test name
Test status
Simulation time 274030896 ps
CPU time 1.44 seconds
Started Mar 24 01:02:06 PM PDT 24
Finished Mar 24 01:02:07 PM PDT 24
Peak memory 200044 kb
Host smart-ed7c05ac-d3d4-416e-a2ba-fe900c9ae037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140121302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3140121302
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1986035180
Short name T525
Test name
Test status
Simulation time 363121644962 ps
CPU time 1496.14 seconds
Started Mar 24 01:02:05 PM PDT 24
Finished Mar 24 01:27:02 PM PDT 24
Peak memory 208204 kb
Host smart-24f57457-b450-48ca-b2ad-d3b33ca17cf6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986035180 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1986035180
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.2670134487
Short name T579
Test name
Test status
Simulation time 38551656 ps
CPU time 0.99 seconds
Started Mar 24 01:02:05 PM PDT 24
Finished Mar 24 01:02:06 PM PDT 24
Peak memory 198936 kb
Host smart-af1cd9c8-a3e5-4943-9761-a3502561e942
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670134487 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.2670134487
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.190465846
Short name T406
Test name
Test status
Simulation time 40293874936 ps
CPU time 489.1 seconds
Started Mar 24 01:02:05 PM PDT 24
Finished Mar 24 01:10:14 PM PDT 24
Peak memory 200008 kb
Host smart-cc964ee8-5574-4f90-8c38-af951b5c952f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190465846 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.190465846
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3977219880
Short name T194
Test name
Test status
Simulation time 5603909926 ps
CPU time 60.27 seconds
Started Mar 24 01:02:03 PM PDT 24
Finished Mar 24 01:03:04 PM PDT 24
Peak memory 200020 kb
Host smart-8cb6aed7-5869-4b69-ac1f-8b40a8af0767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977219880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3977219880
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3842423248
Short name T237
Test name
Test status
Simulation time 11743888 ps
CPU time 0.62 seconds
Started Mar 24 01:02:04 PM PDT 24
Finished Mar 24 01:02:05 PM PDT 24
Peak memory 194488 kb
Host smart-134346b7-d20d-43be-8a28-b23f43ace37e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842423248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3842423248
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.223430316
Short name T157
Test name
Test status
Simulation time 1467982667 ps
CPU time 54.75 seconds
Started Mar 24 01:02:08 PM PDT 24
Finished Mar 24 01:03:03 PM PDT 24
Peak memory 213296 kb
Host smart-5d102ba8-6ab1-47cd-a915-4800a481174b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=223430316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.223430316
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1891801146
Short name T373
Test name
Test status
Simulation time 3951745678 ps
CPU time 40.3 seconds
Started Mar 24 01:02:05 PM PDT 24
Finished Mar 24 01:02:46 PM PDT 24
Peak memory 200040 kb
Host smart-ced4ba86-30e3-47e6-a5bf-ef0bb39b8fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891801146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1891801146
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.1477472194
Short name T270
Test name
Test status
Simulation time 10495444225 ps
CPU time 145.45 seconds
Started Mar 24 01:02:08 PM PDT 24
Finished Mar 24 01:04:34 PM PDT 24
Peak memory 199904 kb
Host smart-63b24382-8473-470c-829f-8b669144d604
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1477472194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1477472194
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.1082699430
Short name T421
Test name
Test status
Simulation time 4247704287 ps
CPU time 119.67 seconds
Started Mar 24 01:02:02 PM PDT 24
Finished Mar 24 01:04:02 PM PDT 24
Peak memory 200124 kb
Host smart-c62d4ad6-8b44-4b6d-8230-9b87380f02ae
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082699430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1082699430
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2208195434
Short name T400
Test name
Test status
Simulation time 560330542 ps
CPU time 33.06 seconds
Started Mar 24 01:02:06 PM PDT 24
Finished Mar 24 01:02:39 PM PDT 24
Peak memory 200028 kb
Host smart-193e8401-95ca-4b26-87bc-e2e8a20d7cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208195434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2208195434
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.1097999759
Short name T325
Test name
Test status
Simulation time 180763111 ps
CPU time 1.74 seconds
Started Mar 24 01:02:04 PM PDT 24
Finished Mar 24 01:02:06 PM PDT 24
Peak memory 200036 kb
Host smart-26c4ea55-900d-4e21-bfca-820dcb5baa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097999759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1097999759
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.497558801
Short name T47
Test name
Test status
Simulation time 937185185734 ps
CPU time 1929.46 seconds
Started Mar 24 01:02:03 PM PDT 24
Finished Mar 24 01:34:13 PM PDT 24
Peak memory 199976 kb
Host smart-9da2fd44-dd9e-4b01-b58b-9802c3490adf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497558801 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.497558801
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.2976697006
Short name T122
Test name
Test status
Simulation time 47713980 ps
CPU time 0.93 seconds
Started Mar 24 01:02:07 PM PDT 24
Finished Mar 24 01:02:08 PM PDT 24
Peak memory 198320 kb
Host smart-9296c9c7-c951-4394-98fd-4d5f8404f23e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976697006 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.2976697006
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.689796128
Short name T484
Test name
Test status
Simulation time 49311024280 ps
CPU time 453.81 seconds
Started Mar 24 01:02:05 PM PDT 24
Finished Mar 24 01:09:39 PM PDT 24
Peak memory 200028 kb
Host smart-b4f668e1-ce46-4966-9a1e-5e9f22b83162
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689796128 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.689796128
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3078039009
Short name T531
Test name
Test status
Simulation time 3681162899 ps
CPU time 21.45 seconds
Started Mar 24 01:02:10 PM PDT 24
Finished Mar 24 01:02:31 PM PDT 24
Peak memory 199980 kb
Host smart-a4d7943d-964a-4087-b3cd-03823a7a846b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078039009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3078039009
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2075170234
Short name T19
Test name
Test status
Simulation time 93881852 ps
CPU time 0.59 seconds
Started Mar 24 01:02:11 PM PDT 24
Finished Mar 24 01:02:12 PM PDT 24
Peak memory 194460 kb
Host smart-6b0d79d5-3c5a-4d8d-8ede-8318b7b744d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075170234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2075170234
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.1826454999
Short name T232
Test name
Test status
Simulation time 6790954817 ps
CPU time 49.49 seconds
Started Mar 24 01:02:04 PM PDT 24
Finished Mar 24 01:02:54 PM PDT 24
Peak memory 216444 kb
Host smart-a94a0bbe-34a9-4f10-b91f-449ae758571c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1826454999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1826454999
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3610806692
Short name T384
Test name
Test status
Simulation time 244910713 ps
CPU time 4.88 seconds
Started Mar 24 01:02:13 PM PDT 24
Finished Mar 24 01:02:18 PM PDT 24
Peak memory 199968 kb
Host smart-eb440a39-da69-4d1d-a17e-d36aefc511e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610806692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3610806692
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2609918587
Short name T56
Test name
Test status
Simulation time 9236287471 ps
CPU time 110.12 seconds
Started Mar 24 01:02:05 PM PDT 24
Finished Mar 24 01:03:56 PM PDT 24
Peak memory 200092 kb
Host smart-dd95e99c-f3e5-48c2-a1c0-ce37e4cf9120
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2609918587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2609918587
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1550913400
Short name T278
Test name
Test status
Simulation time 6024495848 ps
CPU time 112.99 seconds
Started Mar 24 01:02:12 PM PDT 24
Finished Mar 24 01:04:05 PM PDT 24
Peak memory 200000 kb
Host smart-66c8e41a-0112-4d57-ad0e-e81f663d02c7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550913400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1550913400
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.1112800492
Short name T302
Test name
Test status
Simulation time 8894093931 ps
CPU time 91.43 seconds
Started Mar 24 01:02:05 PM PDT 24
Finished Mar 24 01:03:36 PM PDT 24
Peak memory 200072 kb
Host smart-a261148f-87be-4211-b3b6-4e7cad613f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112800492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1112800492
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.456566538
Short name T243
Test name
Test status
Simulation time 1100121615 ps
CPU time 7.01 seconds
Started Mar 24 01:02:03 PM PDT 24
Finished Mar 24 01:02:10 PM PDT 24
Peak memory 199984 kb
Host smart-d4765afa-4a88-4f02-9717-ce1284513358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456566538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.456566538
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.1948233438
Short name T76
Test name
Test status
Simulation time 179626879192 ps
CPU time 647.43 seconds
Started Mar 24 01:02:07 PM PDT 24
Finished Mar 24 01:12:55 PM PDT 24
Peak memory 215968 kb
Host smart-153328c0-f1d8-41b4-b3ca-275e372db599
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948233438 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.1948233438
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.2969175712
Short name T203
Test name
Test status
Simulation time 98999891 ps
CPU time 1.03 seconds
Started Mar 24 01:02:09 PM PDT 24
Finished Mar 24 01:02:10 PM PDT 24
Peak memory 199388 kb
Host smart-25d9cf74-0fde-4d00-8605-9ceb2f5836e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969175712 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.2969175712
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.493890857
Short name T561
Test name
Test status
Simulation time 28391986439 ps
CPU time 493.3 seconds
Started Mar 24 01:02:08 PM PDT 24
Finished Mar 24 01:10:22 PM PDT 24
Peak memory 200028 kb
Host smart-89d9bd89-6009-4f23-bef3-7064ba0f7412
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493890857 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.493890857
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1831705425
Short name T320
Test name
Test status
Simulation time 3758148872 ps
CPU time 72.73 seconds
Started Mar 24 01:02:09 PM PDT 24
Finished Mar 24 01:03:22 PM PDT 24
Peak memory 200076 kb
Host smart-9ec037d9-fe2d-42b8-bfd9-acb4064b12ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831705425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1831705425
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3074078966
Short name T277
Test name
Test status
Simulation time 12769704 ps
CPU time 0.63 seconds
Started Mar 24 01:02:12 PM PDT 24
Finished Mar 24 01:02:13 PM PDT 24
Peak memory 195444 kb
Host smart-2ac0a64a-44ea-4aa8-b35b-c2c947e13cb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074078966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3074078966
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1537397916
Short name T439
Test name
Test status
Simulation time 1102402294 ps
CPU time 6.84 seconds
Started Mar 24 01:02:10 PM PDT 24
Finished Mar 24 01:02:17 PM PDT 24
Peak memory 199956 kb
Host smart-2a25ba58-4a6f-4498-bb17-ce6ede41dbd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1537397916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1537397916
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1600049503
Short name T412
Test name
Test status
Simulation time 2507161869 ps
CPU time 6.47 seconds
Started Mar 24 01:02:10 PM PDT 24
Finished Mar 24 01:02:17 PM PDT 24
Peak memory 200048 kb
Host smart-4b8a859b-edf1-48a8-9ab0-b19674cb9289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600049503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1600049503
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.731568829
Short name T132
Test name
Test status
Simulation time 18051112 ps
CPU time 0.74 seconds
Started Mar 24 01:02:09 PM PDT 24
Finished Mar 24 01:02:10 PM PDT 24
Peak memory 198076 kb
Host smart-f0a3ac50-8a8a-4cf1-b407-dafe4afe7375
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=731568829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.731568829
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.249029586
Short name T11
Test name
Test status
Simulation time 107784283589 ps
CPU time 214.59 seconds
Started Mar 24 01:02:07 PM PDT 24
Finished Mar 24 01:05:42 PM PDT 24
Peak memory 200096 kb
Host smart-5c2c6365-6ee2-4e6b-808e-7fabb38a32df
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249029586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.249029586
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1584122391
Short name T295
Test name
Test status
Simulation time 5715221540 ps
CPU time 111.22 seconds
Started Mar 24 01:02:12 PM PDT 24
Finished Mar 24 01:04:03 PM PDT 24
Peak memory 200076 kb
Host smart-f1451969-f60b-4bd2-bb00-62a5660b6747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584122391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1584122391
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3105025612
Short name T420
Test name
Test status
Simulation time 3500366261 ps
CPU time 4.36 seconds
Started Mar 24 01:02:08 PM PDT 24
Finished Mar 24 01:02:12 PM PDT 24
Peak memory 200100 kb
Host smart-9449f619-0b9c-47d3-8100-3dea164c79ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105025612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3105025612
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1560341672
Short name T316
Test name
Test status
Simulation time 31445193523 ps
CPU time 1710.43 seconds
Started Mar 24 01:02:11 PM PDT 24
Finished Mar 24 01:30:42 PM PDT 24
Peak memory 200088 kb
Host smart-b19c48d5-527f-4fb4-a5db-44c221143b0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560341672 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1560341672
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.3037860576
Short name T449
Test name
Test status
Simulation time 263246790 ps
CPU time 1.05 seconds
Started Mar 24 01:02:12 PM PDT 24
Finished Mar 24 01:02:14 PM PDT 24
Peak memory 199292 kb
Host smart-d1fc7d58-da3a-4524-ad43-e378e1ac8954
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037860576 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.3037860576
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.3016617276
Short name T480
Test name
Test status
Simulation time 18644254858 ps
CPU time 499.58 seconds
Started Mar 24 01:02:08 PM PDT 24
Finished Mar 24 01:10:28 PM PDT 24
Peak memory 200020 kb
Host smart-efe4ad93-0a08-4cbc-ad9f-42ece79679c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016617276 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.3016617276
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.4265507827
Short name T229
Test name
Test status
Simulation time 5060703683 ps
CPU time 46.17 seconds
Started Mar 24 01:02:11 PM PDT 24
Finished Mar 24 01:02:57 PM PDT 24
Peak memory 200088 kb
Host smart-fddae41b-4d71-4524-af67-a84024fdbec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265507827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.4265507827
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1098377319
Short name T463
Test name
Test status
Simulation time 32990180 ps
CPU time 0.58 seconds
Started Mar 24 01:02:18 PM PDT 24
Finished Mar 24 01:02:19 PM PDT 24
Peak memory 195356 kb
Host smart-ba8c3af6-7d3e-4a7b-93be-4e0b8e32ac1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098377319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1098377319
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.737829508
Short name T218
Test name
Test status
Simulation time 2855826667 ps
CPU time 41.45 seconds
Started Mar 24 01:02:14 PM PDT 24
Finished Mar 24 01:02:56 PM PDT 24
Peak memory 224628 kb
Host smart-0818119d-602e-41a7-9393-e9b9310ac6f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=737829508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.737829508
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2920502989
Short name T581
Test name
Test status
Simulation time 645741916 ps
CPU time 30.86 seconds
Started Mar 24 01:02:15 PM PDT 24
Finished Mar 24 01:02:46 PM PDT 24
Peak memory 199984 kb
Host smart-9ab165ad-14f8-41f3-90e5-a07d6a52b2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920502989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2920502989
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.929112133
Short name T567
Test name
Test status
Simulation time 2076478197 ps
CPU time 61.61 seconds
Started Mar 24 01:02:14 PM PDT 24
Finished Mar 24 01:03:16 PM PDT 24
Peak memory 199964 kb
Host smart-1a6621b3-ce7c-4c4f-86ac-a53f1b7de56a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=929112133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.929112133
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.4260046931
Short name T228
Test name
Test status
Simulation time 2632440069 ps
CPU time 150.35 seconds
Started Mar 24 01:02:15 PM PDT 24
Finished Mar 24 01:04:45 PM PDT 24
Peak memory 200080 kb
Host smart-ccd8ca68-1d04-4252-a174-ee4722b39069
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260046931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.4260046931
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.3570921149
Short name T272
Test name
Test status
Simulation time 110262223 ps
CPU time 3.33 seconds
Started Mar 24 01:02:14 PM PDT 24
Finished Mar 24 01:02:18 PM PDT 24
Peak memory 200008 kb
Host smart-d25f422b-cfdb-41bc-b1d2-9b3a3dfc157f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570921149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3570921149
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.997650935
Short name T185
Test name
Test status
Simulation time 1397323800 ps
CPU time 5.38 seconds
Started Mar 24 01:02:11 PM PDT 24
Finished Mar 24 01:02:16 PM PDT 24
Peak memory 199828 kb
Host smart-f07d7d56-9e42-469e-aebf-b02663d4accb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997650935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.997650935
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.483062880
Short name T72
Test name
Test status
Simulation time 381198898449 ps
CPU time 1408.13 seconds
Started Mar 24 01:02:13 PM PDT 24
Finished Mar 24 01:25:41 PM PDT 24
Peak memory 238576 kb
Host smart-354a1135-a09f-4879-966f-95d4fde2e3b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483062880 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.483062880
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.408821769
Short name T387
Test name
Test status
Simulation time 425672665 ps
CPU time 0.94 seconds
Started Mar 24 01:02:16 PM PDT 24
Finished Mar 24 01:02:17 PM PDT 24
Peak memory 198140 kb
Host smart-f2585863-e075-4af0-804e-02446b461566
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408821769 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_hmac_vectors.408821769
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.3552458110
Short name T140
Test name
Test status
Simulation time 30200099020 ps
CPU time 413.36 seconds
Started Mar 24 01:02:15 PM PDT 24
Finished Mar 24 01:09:09 PM PDT 24
Peak memory 200036 kb
Host smart-9a3549eb-633e-4126-8111-0d661ba6ab3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552458110 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.3552458110
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.4164059466
Short name T393
Test name
Test status
Simulation time 593075388 ps
CPU time 26.36 seconds
Started Mar 24 01:02:14 PM PDT 24
Finished Mar 24 01:02:40 PM PDT 24
Peak memory 200300 kb
Host smart-90c79f9e-b1b7-4180-a10f-2a1a47078b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164059466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.4164059466
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/197.hmac_stress_all_with_rand_reset.2996898348
Short name T43
Test name
Test status
Simulation time 178411365218 ps
CPU time 1942.85 seconds
Started Mar 24 01:04:18 PM PDT 24
Finished Mar 24 01:36:41 PM PDT 24
Peak memory 246740 kb
Host smart-cf5f36bd-9c1f-441a-bfb3-cba0b606df54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2996898348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.hmac_stress_all_with_rand_reset.2996898348
Directory /workspace/197.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.3818437901
Short name T246
Test name
Test status
Simulation time 44226387 ps
CPU time 0.57 seconds
Started Mar 24 01:01:26 PM PDT 24
Finished Mar 24 01:01:27 PM PDT 24
Peak memory 195532 kb
Host smart-34f2a0a2-5a65-47dc-a130-143ef9582a5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818437901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3818437901
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.377480500
Short name T177
Test name
Test status
Simulation time 1244092321 ps
CPU time 36.05 seconds
Started Mar 24 01:01:29 PM PDT 24
Finished Mar 24 01:02:05 PM PDT 24
Peak memory 224044 kb
Host smart-221b413f-2922-4a9e-81df-6da24e7a0e4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=377480500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.377480500
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1384520153
Short name T380
Test name
Test status
Simulation time 2699107936 ps
CPU time 17.79 seconds
Started Mar 24 01:01:25 PM PDT 24
Finished Mar 24 01:01:43 PM PDT 24
Peak memory 200000 kb
Host smart-38712adc-da20-4c22-a1dd-f2ea39d06962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384520153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1384520153
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.1187464545
Short name T589
Test name
Test status
Simulation time 7251262188 ps
CPU time 110.49 seconds
Started Mar 24 01:01:29 PM PDT 24
Finished Mar 24 01:03:20 PM PDT 24
Peak memory 200056 kb
Host smart-8f591172-c7be-48f5-8414-61fa6530cfd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1187464545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1187464545
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3143347947
Short name T554
Test name
Test status
Simulation time 2052638540 ps
CPU time 108.99 seconds
Started Mar 24 01:01:25 PM PDT 24
Finished Mar 24 01:03:14 PM PDT 24
Peak memory 200008 kb
Host smart-0f01bae3-876c-456c-a041-294abd8c60bb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143347947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3143347947
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.2601598165
Short name T415
Test name
Test status
Simulation time 7332478643 ps
CPU time 100.28 seconds
Started Mar 24 01:01:27 PM PDT 24
Finished Mar 24 01:03:07 PM PDT 24
Peak memory 200076 kb
Host smart-a0695f39-dcf1-49ba-8521-04be48ebe971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601598165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2601598165
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2707778791
Short name T28
Test name
Test status
Simulation time 67143767 ps
CPU time 0.9 seconds
Started Mar 24 01:01:25 PM PDT 24
Finished Mar 24 01:01:26 PM PDT 24
Peak memory 218216 kb
Host smart-46b7b902-739a-4fb1-92e7-ddee35e2b9d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707778791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2707778791
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.3459946643
Short name T452
Test name
Test status
Simulation time 922483386 ps
CPU time 2.26 seconds
Started Mar 24 01:01:26 PM PDT 24
Finished Mar 24 01:01:28 PM PDT 24
Peak memory 199980 kb
Host smart-d36d2ccb-b46b-4fba-acf7-49781d642af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459946643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3459946643
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3524794296
Short name T71
Test name
Test status
Simulation time 430759484762 ps
CPU time 1429.2 seconds
Started Mar 24 01:01:25 PM PDT 24
Finished Mar 24 01:25:15 PM PDT 24
Peak memory 200060 kb
Host smart-de8457a2-d1c3-4d63-9dcc-854930767cc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524794296 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3524794296
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.1296470681
Short name T596
Test name
Test status
Simulation time 347823454 ps
CPU time 1.27 seconds
Started Mar 24 01:01:26 PM PDT 24
Finished Mar 24 01:01:27 PM PDT 24
Peak memory 199944 kb
Host smart-216eb3bf-9063-44f6-83aa-f60223bfaaf2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296470681 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.1296470681
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.2192387521
Short name T162
Test name
Test status
Simulation time 9893761643 ps
CPU time 445.64 seconds
Started Mar 24 01:01:26 PM PDT 24
Finished Mar 24 01:08:52 PM PDT 24
Peak memory 200032 kb
Host smart-b64d928b-3fd1-4013-bb92-95c584b895e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192387521 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.2192387521
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.4252118672
Short name T208
Test name
Test status
Simulation time 15647351597 ps
CPU time 77.66 seconds
Started Mar 24 01:01:26 PM PDT 24
Finished Mar 24 01:02:43 PM PDT 24
Peak memory 200060 kb
Host smart-480b6049-3763-463c-9e44-41a2e314bea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252118672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.4252118672
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.923088683
Short name T186
Test name
Test status
Simulation time 12795181 ps
CPU time 0.57 seconds
Started Mar 24 01:02:18 PM PDT 24
Finished Mar 24 01:02:19 PM PDT 24
Peak memory 194144 kb
Host smart-79a60563-93cf-4d63-8538-27733ecf7c41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923088683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.923088683
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.104338763
Short name T145
Test name
Test status
Simulation time 3930845766 ps
CPU time 69.42 seconds
Started Mar 24 01:02:15 PM PDT 24
Finished Mar 24 01:03:24 PM PDT 24
Peak memory 232780 kb
Host smart-3888aeb6-276c-4058-b84a-e3f0da4d17cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=104338763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.104338763
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2821881903
Short name T144
Test name
Test status
Simulation time 2543726622 ps
CPU time 44.17 seconds
Started Mar 24 01:02:29 PM PDT 24
Finished Mar 24 01:03:14 PM PDT 24
Peak memory 199884 kb
Host smart-e39df7a0-23f0-4e9f-a979-81566733ff95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821881903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2821881903
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3996625540
Short name T512
Test name
Test status
Simulation time 871512002 ps
CPU time 49.97 seconds
Started Mar 24 01:02:15 PM PDT 24
Finished Mar 24 01:03:05 PM PDT 24
Peak memory 200036 kb
Host smart-83b85466-34e7-4e39-b224-c0dc42ace9ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3996625540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3996625540
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.2746349245
Short name T265
Test name
Test status
Simulation time 1533402916 ps
CPU time 18.88 seconds
Started Mar 24 01:02:14 PM PDT 24
Finished Mar 24 01:02:33 PM PDT 24
Peak memory 200016 kb
Host smart-59ae9c7d-2d24-47b6-81f8-a323feb44f15
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746349245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2746349245
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2700757098
Short name T358
Test name
Test status
Simulation time 467514275 ps
CPU time 28.19 seconds
Started Mar 24 01:02:15 PM PDT 24
Finished Mar 24 01:02:44 PM PDT 24
Peak memory 200020 kb
Host smart-b39cb766-8472-4815-bd2a-cf69cbdf712f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700757098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2700757098
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1995387093
Short name T332
Test name
Test status
Simulation time 476523747 ps
CPU time 3.45 seconds
Started Mar 24 01:02:17 PM PDT 24
Finished Mar 24 01:02:21 PM PDT 24
Peak memory 200020 kb
Host smart-6c21a0ce-476f-4e29-8740-4ea82d6aac76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995387093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1995387093
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2921821629
Short name T499
Test name
Test status
Simulation time 19387245675 ps
CPU time 361.54 seconds
Started Mar 24 01:02:30 PM PDT 24
Finished Mar 24 01:08:31 PM PDT 24
Peak memory 208056 kb
Host smart-61886231-13e0-4d87-b3cb-6ac4d0c14ce5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921821629 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2921821629
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.2291557036
Short name T509
Test name
Test status
Simulation time 72064767 ps
CPU time 1.42 seconds
Started Mar 24 01:02:30 PM PDT 24
Finished Mar 24 01:02:31 PM PDT 24
Peak memory 199568 kb
Host smart-fce945d0-5104-4842-adde-b43f231ddc3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291557036 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.2291557036
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.3132635054
Short name T438
Test name
Test status
Simulation time 156249409581 ps
CPU time 440.9 seconds
Started Mar 24 01:02:14 PM PDT 24
Finished Mar 24 01:09:35 PM PDT 24
Peak memory 200024 kb
Host smart-de88004f-6b31-4e2d-9d25-3fa47727325d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132635054 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.3132635054
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.1467144936
Short name T88
Test name
Test status
Simulation time 3112174736 ps
CPU time 56.65 seconds
Started Mar 24 01:02:30 PM PDT 24
Finished Mar 24 01:03:27 PM PDT 24
Peak memory 199888 kb
Host smart-a49a596f-81e0-4085-af06-fffbc748022c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467144936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1467144936
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3756707380
Short name T551
Test name
Test status
Simulation time 37470071 ps
CPU time 0.59 seconds
Started Mar 24 01:02:20 PM PDT 24
Finished Mar 24 01:02:21 PM PDT 24
Peak memory 195212 kb
Host smart-083a5cc4-9f92-4a3f-b202-cebb8a44db7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756707380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3756707380
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1345750154
Short name T394
Test name
Test status
Simulation time 1580676969 ps
CPU time 65.72 seconds
Started Mar 24 01:02:13 PM PDT 24
Finished Mar 24 01:03:19 PM PDT 24
Peak memory 234756 kb
Host smart-e0430a8e-0108-4a2e-88c8-4aad6badee8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1345750154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1345750154
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1402543519
Short name T294
Test name
Test status
Simulation time 4268794322 ps
CPU time 49.95 seconds
Started Mar 24 01:02:17 PM PDT 24
Finished Mar 24 01:03:07 PM PDT 24
Peak memory 200064 kb
Host smart-3349dfbd-0e8a-4655-a02c-5b6a7192d3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402543519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1402543519
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.4072959046
Short name T537
Test name
Test status
Simulation time 1116244608 ps
CPU time 60.82 seconds
Started Mar 24 01:02:15 PM PDT 24
Finished Mar 24 01:03:16 PM PDT 24
Peak memory 200008 kb
Host smart-cf591c11-fcd8-412d-8473-4e8c07e70ccd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4072959046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.4072959046
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1677167724
Short name T505
Test name
Test status
Simulation time 11022721775 ps
CPU time 71.81 seconds
Started Mar 24 01:02:30 PM PDT 24
Finished Mar 24 01:03:42 PM PDT 24
Peak memory 199860 kb
Host smart-277eef9e-ed1b-45bc-b9e7-2dc0aef52fe8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677167724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1677167724
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1193366914
Short name T323
Test name
Test status
Simulation time 4734653885 ps
CPU time 88.65 seconds
Started Mar 24 01:02:15 PM PDT 24
Finished Mar 24 01:03:44 PM PDT 24
Peak memory 200044 kb
Host smart-7375f17e-f06a-4052-a30a-675dc8dc7e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193366914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1193366914
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.4093064462
Short name T80
Test name
Test status
Simulation time 610176783 ps
CPU time 2.15 seconds
Started Mar 24 01:02:14 PM PDT 24
Finished Mar 24 01:02:16 PM PDT 24
Peak memory 199968 kb
Host smart-97bd1ab2-d8ec-437f-be81-59ec2b950e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093064462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.4093064462
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2271338284
Short name T46
Test name
Test status
Simulation time 28342321747 ps
CPU time 801.11 seconds
Started Mar 24 01:02:18 PM PDT 24
Finished Mar 24 01:15:39 PM PDT 24
Peak memory 200044 kb
Host smart-1a7b5e04-d976-40b5-8105-fdadab7df931
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271338284 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2271338284
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.419776017
Short name T330
Test name
Test status
Simulation time 112564188 ps
CPU time 1.21 seconds
Started Mar 24 01:02:30 PM PDT 24
Finished Mar 24 01:02:31 PM PDT 24
Peak memory 199420 kb
Host smart-76b91fa4-a72a-401a-bf83-6a1feb4894e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419776017 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_hmac_vectors.419776017
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.1375666305
Short name T204
Test name
Test status
Simulation time 40634649959 ps
CPU time 495.31 seconds
Started Mar 24 01:02:17 PM PDT 24
Finished Mar 24 01:10:32 PM PDT 24
Peak memory 199984 kb
Host smart-64ad17e8-558f-4828-8caf-d8494945f1a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375666305 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.1375666305
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.1061367795
Short name T389
Test name
Test status
Simulation time 3369059275 ps
CPU time 22.68 seconds
Started Mar 24 01:02:30 PM PDT 24
Finished Mar 24 01:02:53 PM PDT 24
Peak memory 199868 kb
Host smart-ba969b6e-d451-4250-b351-3c370e1b0acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061367795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1061367795
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1585153060
Short name T472
Test name
Test status
Simulation time 132795520 ps
CPU time 0.58 seconds
Started Mar 24 01:02:21 PM PDT 24
Finished Mar 24 01:02:21 PM PDT 24
Peak memory 194712 kb
Host smart-2b63cc91-cac0-40b7-8118-c10eec7e3bcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585153060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1585153060
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.549101534
Short name T54
Test name
Test status
Simulation time 4763697270 ps
CPU time 47.78 seconds
Started Mar 24 01:02:20 PM PDT 24
Finished Mar 24 01:03:08 PM PDT 24
Peak memory 208268 kb
Host smart-f6d7be30-7931-4adc-8895-cb7f631cf198
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=549101534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.549101534
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2653959071
Short name T205
Test name
Test status
Simulation time 1041446214 ps
CPU time 51.53 seconds
Started Mar 24 01:02:21 PM PDT 24
Finished Mar 24 01:03:13 PM PDT 24
Peak memory 200024 kb
Host smart-68895131-c893-4d6d-b69c-dc4c7590afb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653959071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2653959071
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3062139940
Short name T559
Test name
Test status
Simulation time 392896781 ps
CPU time 21.42 seconds
Started Mar 24 01:02:20 PM PDT 24
Finished Mar 24 01:02:42 PM PDT 24
Peak memory 200040 kb
Host smart-bdfef4fc-c7ba-4118-b31a-10a63490dbbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3062139940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3062139940
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.1037560655
Short name T147
Test name
Test status
Simulation time 3990923733 ps
CPU time 11.94 seconds
Started Mar 24 01:02:19 PM PDT 24
Finished Mar 24 01:02:31 PM PDT 24
Peak memory 199912 kb
Host smart-879113bd-fdf7-4b62-b928-9f4f461feb0a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037560655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.1037560655
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2262128784
Short name T77
Test name
Test status
Simulation time 1274166082 ps
CPU time 66.56 seconds
Started Mar 24 01:02:19 PM PDT 24
Finished Mar 24 01:03:26 PM PDT 24
Peak memory 200040 kb
Host smart-90c68726-950f-42a8-b100-9801b7d036f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262128784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2262128784
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1099651928
Short name T66
Test name
Test status
Simulation time 1839690316 ps
CPU time 6.05 seconds
Started Mar 24 01:02:24 PM PDT 24
Finished Mar 24 01:02:30 PM PDT 24
Peak memory 199976 kb
Host smart-b2f80a98-8efb-466c-90cc-5768d0034e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099651928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1099651928
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2819104642
Short name T471
Test name
Test status
Simulation time 2677632549 ps
CPU time 65.51 seconds
Started Mar 24 01:02:24 PM PDT 24
Finished Mar 24 01:03:30 PM PDT 24
Peak memory 231424 kb
Host smart-81302c63-8d12-4576-8c75-6bc091493d9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819104642 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2819104642
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.2054789774
Short name T152
Test name
Test status
Simulation time 44340610 ps
CPU time 0.96 seconds
Started Mar 24 01:02:20 PM PDT 24
Finished Mar 24 01:02:21 PM PDT 24
Peak memory 199428 kb
Host smart-eb154f4d-3036-4f7d-a039-be90049c467a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054789774 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.2054789774
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.2405195811
Short name T360
Test name
Test status
Simulation time 8214935393 ps
CPU time 439.08 seconds
Started Mar 24 01:02:21 PM PDT 24
Finished Mar 24 01:09:40 PM PDT 24
Peak memory 199952 kb
Host smart-e67d7e67-4fab-4196-8528-5d08a09dd9d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405195811 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.2405195811
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.165218442
Short name T207
Test name
Test status
Simulation time 12248956053 ps
CPU time 56.65 seconds
Started Mar 24 01:02:21 PM PDT 24
Finished Mar 24 01:03:17 PM PDT 24
Peak memory 200056 kb
Host smart-b33aadec-9b6e-4e1b-9ecb-1cf6c4e43127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165218442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.165218442
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.3698087946
Short name T282
Test name
Test status
Simulation time 13402091 ps
CPU time 0.6 seconds
Started Mar 24 01:02:26 PM PDT 24
Finished Mar 24 01:02:26 PM PDT 24
Peak memory 194464 kb
Host smart-f4c4acc6-5b49-4543-b281-c953b4e61c6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698087946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3698087946
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1356927329
Short name T565
Test name
Test status
Simulation time 655007349 ps
CPU time 10.77 seconds
Started Mar 24 01:02:23 PM PDT 24
Finished Mar 24 01:02:33 PM PDT 24
Peak memory 211280 kb
Host smart-8037dd17-1335-4fea-af99-81dc2d55ec4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1356927329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1356927329
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.3994640181
Short name T172
Test name
Test status
Simulation time 9384084247 ps
CPU time 32.64 seconds
Started Mar 24 01:02:19 PM PDT 24
Finished Mar 24 01:02:52 PM PDT 24
Peak memory 200056 kb
Host smart-0249ae66-d721-4ce7-b117-36a9cda870e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994640181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3994640181
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2136908975
Short name T209
Test name
Test status
Simulation time 15993799992 ps
CPU time 92.17 seconds
Started Mar 24 01:02:20 PM PDT 24
Finished Mar 24 01:03:52 PM PDT 24
Peak memory 200052 kb
Host smart-ab07d920-ad6f-494e-9dfc-f931d488d98b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2136908975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2136908975
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.654868786
Short name T226
Test name
Test status
Simulation time 1378799277 ps
CPU time 79.18 seconds
Started Mar 24 01:02:21 PM PDT 24
Finished Mar 24 01:03:40 PM PDT 24
Peak memory 200060 kb
Host smart-cc158f79-8630-4afc-b0ce-aaf5de8be2a3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654868786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.654868786
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1728182139
Short name T372
Test name
Test status
Simulation time 4159403892 ps
CPU time 58.11 seconds
Started Mar 24 01:02:22 PM PDT 24
Finished Mar 24 01:03:20 PM PDT 24
Peak memory 200064 kb
Host smart-bcac3100-0a3b-4598-957d-0256fd48cb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728182139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1728182139
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.3929565537
Short name T341
Test name
Test status
Simulation time 1383107435 ps
CPU time 5.4 seconds
Started Mar 24 01:02:19 PM PDT 24
Finished Mar 24 01:02:25 PM PDT 24
Peak memory 200032 kb
Host smart-609b790c-f844-4674-b873-acac1f99284a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929565537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3929565537
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.511474186
Short name T279
Test name
Test status
Simulation time 47999335 ps
CPU time 1.1 seconds
Started Mar 24 01:02:29 PM PDT 24
Finished Mar 24 01:02:30 PM PDT 24
Peak memory 199564 kb
Host smart-1e7f3ba9-e918-455c-9189-0b1c5fd94282
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511474186 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_hmac_vectors.511474186
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.193396653
Short name T319
Test name
Test status
Simulation time 118881300170 ps
CPU time 501.85 seconds
Started Mar 24 01:02:18 PM PDT 24
Finished Mar 24 01:10:41 PM PDT 24
Peak memory 199996 kb
Host smart-ca5b99d9-5202-4adc-9509-683c063dfa46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193396653 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.193396653
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.4088059845
Short name T81
Test name
Test status
Simulation time 3092778619 ps
CPU time 77.14 seconds
Started Mar 24 01:02:19 PM PDT 24
Finished Mar 24 01:03:36 PM PDT 24
Peak memory 199976 kb
Host smart-bb03fe83-2256-4ffd-a0f9-ae2984b86c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088059845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.4088059845
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2745234006
Short name T343
Test name
Test status
Simulation time 25211454 ps
CPU time 0.58 seconds
Started Mar 24 01:02:26 PM PDT 24
Finished Mar 24 01:02:26 PM PDT 24
Peak memory 195552 kb
Host smart-e29c4078-f61b-4b3c-b29d-3358b386eb68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745234006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2745234006
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2424336241
Short name T530
Test name
Test status
Simulation time 1672072006 ps
CPU time 51.59 seconds
Started Mar 24 01:02:27 PM PDT 24
Finished Mar 24 01:03:19 PM PDT 24
Peak memory 212240 kb
Host smart-ebdc0b12-005c-4ac0-ac9b-fa8fc4e6d2b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2424336241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2424336241
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.890506146
Short name T318
Test name
Test status
Simulation time 1959078388 ps
CPU time 40.49 seconds
Started Mar 24 01:02:27 PM PDT 24
Finished Mar 24 01:03:08 PM PDT 24
Peak memory 200024 kb
Host smart-31fa3cdb-c6b1-48e7-953e-41120345fa2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890506146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.890506146
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.4272530106
Short name T414
Test name
Test status
Simulation time 6393111196 ps
CPU time 92.64 seconds
Started Mar 24 01:02:24 PM PDT 24
Finished Mar 24 01:03:57 PM PDT 24
Peak memory 200076 kb
Host smart-a878e3a7-9142-45f2-901d-e21ed539f047
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4272530106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.4272530106
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2282530341
Short name T315
Test name
Test status
Simulation time 19509124951 ps
CPU time 109.86 seconds
Started Mar 24 01:02:25 PM PDT 24
Finished Mar 24 01:04:15 PM PDT 24
Peak memory 200016 kb
Host smart-655c32e0-c325-4c92-849f-5102184f24a3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282530341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2282530341
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2706507461
Short name T161
Test name
Test status
Simulation time 3357059449 ps
CPU time 60.87 seconds
Started Mar 24 01:02:27 PM PDT 24
Finished Mar 24 01:03:28 PM PDT 24
Peak memory 200044 kb
Host smart-1242861b-899e-4f12-ba84-0284518bba0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706507461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2706507461
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2655320282
Short name T193
Test name
Test status
Simulation time 387352320 ps
CPU time 4.92 seconds
Started Mar 24 01:02:23 PM PDT 24
Finished Mar 24 01:02:28 PM PDT 24
Peak memory 200008 kb
Host smart-f0335f80-3273-4063-bf15-7d49d8bcbb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655320282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2655320282
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.821956115
Short name T74
Test name
Test status
Simulation time 241732959880 ps
CPU time 1697.26 seconds
Started Mar 24 01:02:29 PM PDT 24
Finished Mar 24 01:30:46 PM PDT 24
Peak memory 199912 kb
Host smart-55639826-da78-4735-80f1-e3e096202b84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821956115 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.821956115
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.1405660801
Short name T339
Test name
Test status
Simulation time 139951732 ps
CPU time 1.17 seconds
Started Mar 24 01:02:27 PM PDT 24
Finished Mar 24 01:02:28 PM PDT 24
Peak memory 199304 kb
Host smart-c2c36aa0-2b14-43c5-ac14-f1e8de379ee2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405660801 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.1405660801
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.82523744
Short name T569
Test name
Test status
Simulation time 153111453844 ps
CPU time 531.43 seconds
Started Mar 24 01:02:27 PM PDT 24
Finished Mar 24 01:11:18 PM PDT 24
Peak memory 200024 kb
Host smart-2ab0de17-951e-4ef5-a55a-2c4ccdba1f28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82523744 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.82523744
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.1433568035
Short name T296
Test name
Test status
Simulation time 886028859 ps
CPU time 40.44 seconds
Started Mar 24 01:02:30 PM PDT 24
Finished Mar 24 01:03:11 PM PDT 24
Peak memory 200024 kb
Host smart-8c2e9a57-52c2-4c08-a60d-9ad52ff703c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433568035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1433568035
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2842370420
Short name T435
Test name
Test status
Simulation time 32149959 ps
CPU time 0.55 seconds
Started Mar 24 01:02:31 PM PDT 24
Finished Mar 24 01:02:31 PM PDT 24
Peak memory 195516 kb
Host smart-4eeab9cc-2f27-4c35-8903-24a6e48bc485
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842370420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2842370420
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1447142025
Short name T329
Test name
Test status
Simulation time 663424557 ps
CPU time 25.08 seconds
Started Mar 24 01:02:25 PM PDT 24
Finished Mar 24 01:02:50 PM PDT 24
Peak memory 232240 kb
Host smart-9ca43863-b030-4213-8abf-b84b7ec408ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1447142025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1447142025
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1695702875
Short name T364
Test name
Test status
Simulation time 1016816091 ps
CPU time 13.54 seconds
Started Mar 24 01:02:24 PM PDT 24
Finished Mar 24 01:02:37 PM PDT 24
Peak memory 199996 kb
Host smart-c46f5622-5c12-444f-934c-895a0b5880de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695702875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1695702875
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.3240359402
Short name T402
Test name
Test status
Simulation time 559138824 ps
CPU time 31.9 seconds
Started Mar 24 01:02:26 PM PDT 24
Finished Mar 24 01:02:58 PM PDT 24
Peak memory 199924 kb
Host smart-1b9ab18a-55ea-4386-8250-e2c1de318bbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3240359402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3240359402
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.1312811172
Short name T128
Test name
Test status
Simulation time 1342334767 ps
CPU time 13.06 seconds
Started Mar 24 01:02:27 PM PDT 24
Finished Mar 24 01:02:40 PM PDT 24
Peak memory 200024 kb
Host smart-6df34434-221c-400e-a417-26071c21a921
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312811172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.1312811172
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3220061983
Short name T450
Test name
Test status
Simulation time 222357576 ps
CPU time 9.54 seconds
Started Mar 24 01:02:23 PM PDT 24
Finished Mar 24 01:02:33 PM PDT 24
Peak memory 199928 kb
Host smart-5b7761e0-20bf-47fc-bf01-7ba96c472a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220061983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3220061983
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2470098209
Short name T429
Test name
Test status
Simulation time 121157571 ps
CPU time 4.15 seconds
Started Mar 24 01:02:24 PM PDT 24
Finished Mar 24 01:02:29 PM PDT 24
Peak memory 200008 kb
Host smart-524f1a25-c90f-4cb8-9207-ec8d71a5fbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470098209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2470098209
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.587818769
Short name T89
Test name
Test status
Simulation time 83928628875 ps
CPU time 578.88 seconds
Started Mar 24 01:02:33 PM PDT 24
Finished Mar 24 01:12:12 PM PDT 24
Peak memory 208244 kb
Host smart-8415cdba-b7f4-4fc8-bd56-c659283086e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587818769 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.587818769
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.2191450560
Short name T269
Test name
Test status
Simulation time 53908683 ps
CPU time 1.07 seconds
Started Mar 24 01:02:30 PM PDT 24
Finished Mar 24 01:02:31 PM PDT 24
Peak memory 199076 kb
Host smart-4146caec-9093-44e4-9863-548dad4f0724
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191450560 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.2191450560
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.689357519
Short name T498
Test name
Test status
Simulation time 8153894406 ps
CPU time 437.14 seconds
Started Mar 24 01:02:26 PM PDT 24
Finished Mar 24 01:09:43 PM PDT 24
Peak memory 200060 kb
Host smart-11d66d2a-a7dd-462d-834f-2cc968924b27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689357519 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.689357519
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2150816957
Short name T591
Test name
Test status
Simulation time 229358971 ps
CPU time 12.32 seconds
Started Mar 24 01:02:27 PM PDT 24
Finished Mar 24 01:02:40 PM PDT 24
Peak memory 200016 kb
Host smart-de68cbb7-d351-42c3-895f-3276fde2e5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150816957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2150816957
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1347676152
Short name T180
Test name
Test status
Simulation time 11791420 ps
CPU time 0.53 seconds
Started Mar 24 01:02:31 PM PDT 24
Finished Mar 24 01:02:32 PM PDT 24
Peak memory 194384 kb
Host smart-13730eb0-c869-43b2-8a56-777cb5b84103
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347676152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1347676152
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3312552528
Short name T489
Test name
Test status
Simulation time 770787211 ps
CPU time 12.85 seconds
Started Mar 24 01:02:30 PM PDT 24
Finished Mar 24 01:02:43 PM PDT 24
Peak memory 208156 kb
Host smart-6a6f0bed-e2d7-412a-8a15-f78baa630ffc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3312552528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3312552528
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.3711303606
Short name T174
Test name
Test status
Simulation time 1653617254 ps
CPU time 10.36 seconds
Started Mar 24 01:02:37 PM PDT 24
Finished Mar 24 01:02:48 PM PDT 24
Peak memory 199916 kb
Host smart-a55453a6-e6d6-4161-ab21-e71330fbe26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711303606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.3711303606
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1884564203
Short name T22
Test name
Test status
Simulation time 1497021955 ps
CPU time 80.78 seconds
Started Mar 24 01:02:31 PM PDT 24
Finished Mar 24 01:03:52 PM PDT 24
Peak memory 200244 kb
Host smart-1851c2ba-7ed2-4f74-aa74-5fbad90c9699
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1884564203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1884564203
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.1972652048
Short name T550
Test name
Test status
Simulation time 1567907580 ps
CPU time 54.6 seconds
Started Mar 24 01:02:30 PM PDT 24
Finished Mar 24 01:03:25 PM PDT 24
Peak memory 200020 kb
Host smart-4374c32b-9330-480a-886c-38ab8791afbc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972652048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1972652048
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.764968975
Short name T399
Test name
Test status
Simulation time 20334098609 ps
CPU time 71.3 seconds
Started Mar 24 01:02:30 PM PDT 24
Finished Mar 24 01:03:41 PM PDT 24
Peak memory 200036 kb
Host smart-551570c3-f777-4ba7-b0cc-f042f534fee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764968975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.764968975
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.1580762985
Short name T495
Test name
Test status
Simulation time 297563516 ps
CPU time 3.51 seconds
Started Mar 24 01:02:30 PM PDT 24
Finished Mar 24 01:02:34 PM PDT 24
Peak memory 200008 kb
Host smart-227d700a-b68b-4d72-97e0-86ba50e379a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580762985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1580762985
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.677196253
Short name T299
Test name
Test status
Simulation time 444191930151 ps
CPU time 888.2 seconds
Started Mar 24 01:02:28 PM PDT 24
Finished Mar 24 01:17:17 PM PDT 24
Peak memory 200092 kb
Host smart-f56d7daf-afbd-4aee-9d0a-bed22fe19255
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677196253 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.677196253
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.2842502513
Short name T212
Test name
Test status
Simulation time 209593025 ps
CPU time 1.27 seconds
Started Mar 24 01:02:30 PM PDT 24
Finished Mar 24 01:02:32 PM PDT 24
Peak memory 199740 kb
Host smart-43d7d8b9-3c22-4643-ab5b-2adc0a78d744
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842502513 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.2842502513
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.1229797422
Short name T241
Test name
Test status
Simulation time 155915560957 ps
CPU time 474.23 seconds
Started Mar 24 01:02:31 PM PDT 24
Finished Mar 24 01:10:25 PM PDT 24
Peak memory 200020 kb
Host smart-7ef300eb-9288-4afe-8233-ca029236033a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229797422 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.1229797422
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.106978014
Short name T548
Test name
Test status
Simulation time 28727329941 ps
CPU time 49.78 seconds
Started Mar 24 01:02:30 PM PDT 24
Finished Mar 24 01:03:20 PM PDT 24
Peak memory 200096 kb
Host smart-00d0ebb1-92cd-4d06-b9ea-53db5895416f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106978014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.106978014
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1224008511
Short name T521
Test name
Test status
Simulation time 11617891 ps
CPU time 0.62 seconds
Started Mar 24 01:02:35 PM PDT 24
Finished Mar 24 01:02:36 PM PDT 24
Peak memory 194500 kb
Host smart-bff58f99-9143-4b42-9405-ec3c7004178f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224008511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1224008511
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3589370543
Short name T149
Test name
Test status
Simulation time 497040606 ps
CPU time 17.58 seconds
Started Mar 24 01:02:37 PM PDT 24
Finished Mar 24 01:02:55 PM PDT 24
Peak memory 216060 kb
Host smart-ecd3dcca-9b3d-4c19-ad12-23b695e42eef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3589370543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3589370543
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.2112985915
Short name T520
Test name
Test status
Simulation time 10026330043 ps
CPU time 46.73 seconds
Started Mar 24 01:02:30 PM PDT 24
Finished Mar 24 01:03:17 PM PDT 24
Peak memory 200060 kb
Host smart-3e5fac4e-17a2-4081-ab57-835568d2a46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112985915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2112985915
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1748159123
Short name T577
Test name
Test status
Simulation time 2083120731 ps
CPU time 100.98 seconds
Started Mar 24 01:02:31 PM PDT 24
Finished Mar 24 01:04:12 PM PDT 24
Peak memory 200036 kb
Host smart-2f4bdbd0-8cbc-4481-a084-1ec97252420b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1748159123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1748159123
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.1307833882
Short name T45
Test name
Test status
Simulation time 28870417017 ps
CPU time 133.25 seconds
Started Mar 24 01:02:30 PM PDT 24
Finished Mar 24 01:04:43 PM PDT 24
Peak memory 199960 kb
Host smart-cbcc3e17-30e3-4352-a48f-0ab4c3a08249
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307833882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1307833882
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3579923529
Short name T44
Test name
Test status
Simulation time 992930279 ps
CPU time 7.59 seconds
Started Mar 24 01:02:32 PM PDT 24
Finished Mar 24 01:02:39 PM PDT 24
Peak memory 199808 kb
Host smart-5bf87c02-f3fe-4831-8147-33e538684d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579923529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3579923529
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1084242569
Short name T133
Test name
Test status
Simulation time 592083222 ps
CPU time 4.31 seconds
Started Mar 24 01:02:37 PM PDT 24
Finished Mar 24 01:02:42 PM PDT 24
Peak memory 199904 kb
Host smart-9e3f9e37-f758-4af1-ad4e-1f140919f717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084242569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1084242569
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.392666184
Short name T411
Test name
Test status
Simulation time 25997377116 ps
CPU time 71.84 seconds
Started Mar 24 01:02:41 PM PDT 24
Finished Mar 24 01:03:53 PM PDT 24
Peak memory 199992 kb
Host smart-61f86479-78c3-41c6-ba48-32767a5b5294
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392666184 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.392666184
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.2025254622
Short name T264
Test name
Test status
Simulation time 190527357 ps
CPU time 1.08 seconds
Started Mar 24 01:02:30 PM PDT 24
Finished Mar 24 01:02:31 PM PDT 24
Peak memory 199372 kb
Host smart-fa831d98-d04e-471f-929f-53c65f909b39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025254622 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.2025254622
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.488955305
Short name T121
Test name
Test status
Simulation time 187077793818 ps
CPU time 511.13 seconds
Started Mar 24 01:02:32 PM PDT 24
Finished Mar 24 01:11:03 PM PDT 24
Peak memory 200056 kb
Host smart-a1138783-e141-441e-bcc8-7a55eb3e6fef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488955305 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.488955305
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1438770847
Short name T314
Test name
Test status
Simulation time 4471388913 ps
CPU time 58.6 seconds
Started Mar 24 01:02:30 PM PDT 24
Finished Mar 24 01:03:29 PM PDT 24
Peak memory 200068 kb
Host smart-8ed4b626-e6c2-424d-8189-23b67aa4694c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438770847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1438770847
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2906564168
Short name T137
Test name
Test status
Simulation time 20873395 ps
CPU time 0.56 seconds
Started Mar 24 01:02:39 PM PDT 24
Finished Mar 24 01:02:39 PM PDT 24
Peak memory 194516 kb
Host smart-d06249da-b901-47d6-bee5-88c5c0393223
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906564168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2906564168
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1422491817
Short name T534
Test name
Test status
Simulation time 1329627156 ps
CPU time 31.32 seconds
Started Mar 24 01:02:37 PM PDT 24
Finished Mar 24 01:03:09 PM PDT 24
Peak memory 208160 kb
Host smart-09bd04dd-7817-447d-b5c3-3b557b1686fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1422491817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1422491817
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1023238816
Short name T213
Test name
Test status
Simulation time 10594654050 ps
CPU time 39.52 seconds
Started Mar 24 01:02:36 PM PDT 24
Finished Mar 24 01:03:16 PM PDT 24
Peak memory 200048 kb
Host smart-9f593de1-b99f-486d-9f07-8167e38b690c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023238816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1023238816
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.2670362372
Short name T91
Test name
Test status
Simulation time 633778726 ps
CPU time 36.02 seconds
Started Mar 24 01:02:35 PM PDT 24
Finished Mar 24 01:03:11 PM PDT 24
Peak memory 200056 kb
Host smart-e714ddf1-82db-4733-aadd-dcd7ea51c2c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2670362372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2670362372
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3038889067
Short name T349
Test name
Test status
Simulation time 6751858395 ps
CPU time 96.14 seconds
Started Mar 24 01:02:37 PM PDT 24
Finished Mar 24 01:04:14 PM PDT 24
Peak memory 200220 kb
Host smart-2fbc8270-67ec-46ba-924f-6bcefbc6e82c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038889067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3038889067
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2207620437
Short name T143
Test name
Test status
Simulation time 24514379276 ps
CPU time 92 seconds
Started Mar 24 01:02:37 PM PDT 24
Finished Mar 24 01:04:09 PM PDT 24
Peak memory 200068 kb
Host smart-d50a1539-278b-4fb2-82ed-2dafad313a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207620437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2207620437
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1430471938
Short name T378
Test name
Test status
Simulation time 788189966 ps
CPU time 6.81 seconds
Started Mar 24 01:02:36 PM PDT 24
Finished Mar 24 01:02:43 PM PDT 24
Peak memory 200256 kb
Host smart-1bdf153c-3074-4f3a-aadf-1206d1c8676f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430471938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1430471938
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2593073386
Short name T430
Test name
Test status
Simulation time 29775622409 ps
CPU time 1665.86 seconds
Started Mar 24 01:02:37 PM PDT 24
Finished Mar 24 01:30:23 PM PDT 24
Peak memory 216412 kb
Host smart-cc14c825-fbaf-4837-bc9c-632ca13752a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593073386 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2593073386
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_stress_all_with_rand_reset.1760763394
Short name T63
Test name
Test status
Simulation time 456174203998 ps
CPU time 932.96 seconds
Started Mar 24 01:02:36 PM PDT 24
Finished Mar 24 01:18:09 PM PDT 24
Peak memory 246308 kb
Host smart-d3e8811d-0242-4158-a48c-e5ba9bc129aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1760763394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all_with_rand_reset.1760763394
Directory /workspace/28.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.2330324208
Short name T14
Test name
Test status
Simulation time 232868964 ps
CPU time 1.28 seconds
Started Mar 24 01:02:36 PM PDT 24
Finished Mar 24 01:02:37 PM PDT 24
Peak memory 199720 kb
Host smart-4d930f8e-8fa9-4468-9749-e42570b8c7b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330324208 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.2330324208
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.650738267
Short name T300
Test name
Test status
Simulation time 15865868737 ps
CPU time 424.24 seconds
Started Mar 24 01:02:36 PM PDT 24
Finished Mar 24 01:09:40 PM PDT 24
Peak memory 199992 kb
Host smart-46ba9ea2-4abf-44b1-8f91-67d8c99a0bf3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650738267 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.650738267
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3236161984
Short name T363
Test name
Test status
Simulation time 6382102513 ps
CPU time 79.99 seconds
Started Mar 24 01:02:36 PM PDT 24
Finished Mar 24 01:03:56 PM PDT 24
Peak memory 200000 kb
Host smart-81a9f3d9-bad0-40ab-83fa-45dcefc96e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236161984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3236161984
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1629512047
Short name T317
Test name
Test status
Simulation time 12422250 ps
CPU time 0.6 seconds
Started Mar 24 01:02:41 PM PDT 24
Finished Mar 24 01:02:42 PM PDT 24
Peak memory 195188 kb
Host smart-1f2ad92b-c771-423f-860a-9657b38a82f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629512047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1629512047
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3556840868
Short name T135
Test name
Test status
Simulation time 1539023835 ps
CPU time 60.23 seconds
Started Mar 24 01:02:34 PM PDT 24
Finished Mar 24 01:03:35 PM PDT 24
Peak memory 227352 kb
Host smart-d59d7946-1faa-400d-8bbe-9798f50fddeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3556840868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3556840868
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.3772210725
Short name T510
Test name
Test status
Simulation time 3578793027 ps
CPU time 55.11 seconds
Started Mar 24 01:02:41 PM PDT 24
Finished Mar 24 01:03:37 PM PDT 24
Peak memory 199944 kb
Host smart-eb6eabcc-9f52-4c24-a2b1-5902fc8e4eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772210725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3772210725
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.4038826603
Short name T326
Test name
Test status
Simulation time 2774932307 ps
CPU time 79.53 seconds
Started Mar 24 01:02:35 PM PDT 24
Finished Mar 24 01:03:55 PM PDT 24
Peak memory 200100 kb
Host smart-3b797387-7bfc-4df0-b284-20a9416da269
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4038826603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.4038826603
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2703124132
Short name T284
Test name
Test status
Simulation time 1112386103 ps
CPU time 59.9 seconds
Started Mar 24 01:02:39 PM PDT 24
Finished Mar 24 01:03:39 PM PDT 24
Peak memory 200044 kb
Host smart-94f0bff0-6601-4222-80d4-b399f015baae
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703124132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2703124132
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.4180093707
Short name T482
Test name
Test status
Simulation time 7184353167 ps
CPU time 41.25 seconds
Started Mar 24 01:02:39 PM PDT 24
Finished Mar 24 01:03:20 PM PDT 24
Peak memory 200096 kb
Host smart-ace2d158-37bf-4194-855d-0c10b0e5cec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180093707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.4180093707
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.596361002
Short name T150
Test name
Test status
Simulation time 396006411 ps
CPU time 5.06 seconds
Started Mar 24 01:02:38 PM PDT 24
Finished Mar 24 01:02:43 PM PDT 24
Peak memory 199960 kb
Host smart-b2874100-1434-445d-8523-e8f833c5504f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596361002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.596361002
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.1093404329
Short name T15
Test name
Test status
Simulation time 51787476408 ps
CPU time 1494.23 seconds
Started Mar 24 01:02:35 PM PDT 24
Finished Mar 24 01:27:29 PM PDT 24
Peak memory 240980 kb
Host smart-41a4a9d1-d782-4869-9c1e-070a693feb4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093404329 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1093404329
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.2993415800
Short name T526
Test name
Test status
Simulation time 74037112 ps
CPU time 1.39 seconds
Started Mar 24 01:02:36 PM PDT 24
Finished Mar 24 01:02:37 PM PDT 24
Peak memory 199788 kb
Host smart-28983146-3643-4ea1-82dd-cd9e348d8858
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993415800 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.2993415800
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.2977052572
Short name T433
Test name
Test status
Simulation time 45220052136 ps
CPU time 470.81 seconds
Started Mar 24 01:02:37 PM PDT 24
Finished Mar 24 01:10:28 PM PDT 24
Peak memory 200004 kb
Host smart-d22ace83-625a-4354-921d-3f1cec68ff8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977052572 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.2977052572
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2692134093
Short name T508
Test name
Test status
Simulation time 796952912 ps
CPU time 16.46 seconds
Started Mar 24 01:02:35 PM PDT 24
Finished Mar 24 01:02:52 PM PDT 24
Peak memory 200036 kb
Host smart-e66f7142-a882-4efa-ac76-6e402c415ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692134093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2692134093
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.86548516
Short name T413
Test name
Test status
Simulation time 17197394 ps
CPU time 0.6 seconds
Started Mar 24 01:01:31 PM PDT 24
Finished Mar 24 01:01:32 PM PDT 24
Peak memory 195608 kb
Host smart-4159f418-0a63-4f32-be65-0f77581ef689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86548516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.86548516
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.1132836005
Short name T350
Test name
Test status
Simulation time 1005735044 ps
CPU time 36.21 seconds
Started Mar 24 01:01:31 PM PDT 24
Finished Mar 24 01:02:08 PM PDT 24
Peak memory 225412 kb
Host smart-9bf99ea7-e169-47a9-a14d-0a8f24cfdb8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1132836005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1132836005
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3703584959
Short name T524
Test name
Test status
Simulation time 590849006 ps
CPU time 10.53 seconds
Started Mar 24 01:01:28 PM PDT 24
Finished Mar 24 01:01:39 PM PDT 24
Peak memory 200000 kb
Host smart-9a38eb37-2138-441a-a21e-acf8632bc1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703584959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3703584959
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.371507421
Short name T131
Test name
Test status
Simulation time 1655152534 ps
CPU time 96.61 seconds
Started Mar 24 01:01:42 PM PDT 24
Finished Mar 24 01:03:19 PM PDT 24
Peak memory 199956 kb
Host smart-239a3400-12d4-4839-b5d2-e15a84d61a8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=371507421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.371507421
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1372126731
Short name T268
Test name
Test status
Simulation time 784580221 ps
CPU time 43.06 seconds
Started Mar 24 01:01:33 PM PDT 24
Finished Mar 24 01:02:16 PM PDT 24
Peak memory 200060 kb
Host smart-51d79a7a-3751-46b8-a33a-4d896f355bfe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372126731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1372126731
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.529179016
Short name T336
Test name
Test status
Simulation time 50996566 ps
CPU time 2.86 seconds
Started Mar 24 01:01:26 PM PDT 24
Finished Mar 24 01:01:30 PM PDT 24
Peak memory 199888 kb
Host smart-49b189f9-4ded-479f-b95e-0e73b870f9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529179016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.529179016
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3474584113
Short name T31
Test name
Test status
Simulation time 202876626 ps
CPU time 0.82 seconds
Started Mar 24 01:01:30 PM PDT 24
Finished Mar 24 01:01:30 PM PDT 24
Peak memory 218152 kb
Host smart-6df0cda6-cb16-4e96-8b5f-ac7216c875bc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474584113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3474584113
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.2036431486
Short name T126
Test name
Test status
Simulation time 164713993 ps
CPU time 1.58 seconds
Started Mar 24 01:01:26 PM PDT 24
Finished Mar 24 01:01:29 PM PDT 24
Peak memory 199968 kb
Host smart-eab357d0-5cde-42a1-aff2-f9396ef49a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036431486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.2036431486
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1664619274
Short name T590
Test name
Test status
Simulation time 4838531906 ps
CPU time 133.31 seconds
Started Mar 24 01:01:32 PM PDT 24
Finished Mar 24 01:03:46 PM PDT 24
Peak memory 199992 kb
Host smart-83e1119d-f762-4edc-9cd2-160b730ca925
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664619274 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1664619274
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.3601715726
Short name T532
Test name
Test status
Simulation time 220204631 ps
CPU time 1.28 seconds
Started Mar 24 01:01:30 PM PDT 24
Finished Mar 24 01:01:32 PM PDT 24
Peak memory 199988 kb
Host smart-9fad5e9c-00f4-4083-9411-764c74ad355b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601715726 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.3601715726
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.832387613
Short name T120
Test name
Test status
Simulation time 166513655320 ps
CPU time 527.8 seconds
Started Mar 24 01:01:32 PM PDT 24
Finished Mar 24 01:10:20 PM PDT 24
Peak memory 200032 kb
Host smart-f038063b-efdf-4a3c-a5eb-2c77aa343f3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832387613 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.832387613
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3163913483
Short name T166
Test name
Test status
Simulation time 1440074314 ps
CPU time 20.84 seconds
Started Mar 24 01:01:32 PM PDT 24
Finished Mar 24 01:01:54 PM PDT 24
Peak memory 199892 kb
Host smart-9670f561-4f41-493d-aeb4-7ea64048e13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163913483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3163913483
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.553969567
Short name T465
Test name
Test status
Simulation time 14152187 ps
CPU time 0.63 seconds
Started Mar 24 01:02:44 PM PDT 24
Finished Mar 24 01:02:45 PM PDT 24
Peak memory 195512 kb
Host smart-aa66734f-15d3-4af2-b965-a75e523142c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553969567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.553969567
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2883252065
Short name T234
Test name
Test status
Simulation time 2261489617 ps
CPU time 11.98 seconds
Started Mar 24 01:02:36 PM PDT 24
Finished Mar 24 01:02:49 PM PDT 24
Peak memory 208268 kb
Host smart-650d5ce7-7826-40dd-b688-2dc405f06aed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2883252065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2883252065
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.4097920597
Short name T2
Test name
Test status
Simulation time 587791649 ps
CPU time 27.03 seconds
Started Mar 24 01:02:43 PM PDT 24
Finished Mar 24 01:03:11 PM PDT 24
Peak memory 200020 kb
Host smart-74c87ba5-9b1f-42f7-a661-6722205a3306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097920597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.4097920597
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.3117514492
Short name T310
Test name
Test status
Simulation time 232608319 ps
CPU time 14.14 seconds
Started Mar 24 01:02:37 PM PDT 24
Finished Mar 24 01:02:51 PM PDT 24
Peak memory 200020 kb
Host smart-2c3d45d6-d750-430e-a1b2-0be414c3f0ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3117514492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3117514492
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.2581694173
Short name T340
Test name
Test status
Simulation time 5706371529 ps
CPU time 95.87 seconds
Started Mar 24 01:02:44 PM PDT 24
Finished Mar 24 01:04:20 PM PDT 24
Peak memory 200124 kb
Host smart-dcf0abd1-58de-45c7-a874-f4a313dd76d7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581694173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2581694173
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2256989545
Short name T182
Test name
Test status
Simulation time 5118066714 ps
CPU time 104.95 seconds
Started Mar 24 01:02:37 PM PDT 24
Finished Mar 24 01:04:22 PM PDT 24
Peak memory 200064 kb
Host smart-3fff9ccb-6b28-48d0-84a2-a5f12f4778e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256989545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2256989545
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3274163343
Short name T377
Test name
Test status
Simulation time 67076799 ps
CPU time 2.12 seconds
Started Mar 24 01:02:45 PM PDT 24
Finished Mar 24 01:02:48 PM PDT 24
Peak memory 199840 kb
Host smart-03ab6444-0e5e-4b63-a967-9a272ba9d674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274163343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3274163343
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.991324561
Short name T70
Test name
Test status
Simulation time 6035283652 ps
CPU time 7.05 seconds
Started Mar 24 01:02:42 PM PDT 24
Finished Mar 24 01:02:50 PM PDT 24
Peak memory 199972 kb
Host smart-d3d8aac5-0bf2-4c1d-9c69-3935da69a78b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991324561 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.991324561
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.4224151516
Short name T483
Test name
Test status
Simulation time 103303331 ps
CPU time 1.1 seconds
Started Mar 24 01:02:44 PM PDT 24
Finished Mar 24 01:02:45 PM PDT 24
Peak memory 199508 kb
Host smart-77185ddb-86c1-414c-a796-9c59e708a59c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224151516 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.4224151516
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.3112084271
Short name T496
Test name
Test status
Simulation time 21991883587 ps
CPU time 396.7 seconds
Started Mar 24 01:02:42 PM PDT 24
Finished Mar 24 01:09:20 PM PDT 24
Peak memory 200024 kb
Host smart-dddae1a0-9e70-4d6a-a7fd-264f251527bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112084271 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.3112084271
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3365758123
Short name T391
Test name
Test status
Simulation time 29537488046 ps
CPU time 89.38 seconds
Started Mar 24 01:02:43 PM PDT 24
Finished Mar 24 01:04:13 PM PDT 24
Peak memory 200084 kb
Host smart-168549b6-39f9-4535-b207-4426a2dab342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365758123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3365758123
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.591842350
Short name T448
Test name
Test status
Simulation time 20760677 ps
CPU time 0.6 seconds
Started Mar 24 01:02:42 PM PDT 24
Finished Mar 24 01:02:44 PM PDT 24
Peak memory 195632 kb
Host smart-a1929494-d562-4626-9302-dbdb46d8bf14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591842350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.591842350
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3763397340
Short name T460
Test name
Test status
Simulation time 1298049217 ps
CPU time 48.91 seconds
Started Mar 24 01:02:46 PM PDT 24
Finished Mar 24 01:03:35 PM PDT 24
Peak memory 224552 kb
Host smart-9cfa9a23-4742-4111-bedd-90d723bd3aea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3763397340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3763397340
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2369248493
Short name T410
Test name
Test status
Simulation time 7812488958 ps
CPU time 47.67 seconds
Started Mar 24 01:02:43 PM PDT 24
Finished Mar 24 01:03:31 PM PDT 24
Peak memory 200040 kb
Host smart-b4376837-9879-4224-956a-1aba7ee0455d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369248493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2369248493
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2483773778
Short name T222
Test name
Test status
Simulation time 2003258494 ps
CPU time 36.45 seconds
Started Mar 24 01:02:44 PM PDT 24
Finished Mar 24 01:03:21 PM PDT 24
Peak memory 200020 kb
Host smart-0d400316-41ed-4d7c-aa58-0dd6ba64d5dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2483773778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2483773778
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.1230312242
Short name T34
Test name
Test status
Simulation time 4528581222 ps
CPU time 43.18 seconds
Started Mar 24 01:02:41 PM PDT 24
Finished Mar 24 01:03:25 PM PDT 24
Peak memory 200128 kb
Host smart-9f575094-a0f8-4c5a-82f8-1dec6dbc057c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230312242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1230312242
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.334409975
Short name T125
Test name
Test status
Simulation time 692653323 ps
CPU time 9.76 seconds
Started Mar 24 01:02:48 PM PDT 24
Finished Mar 24 01:02:58 PM PDT 24
Peak memory 199860 kb
Host smart-7f0fafa6-aeac-47c9-bd13-94c03ec8a8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334409975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.334409975
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.375565428
Short name T511
Test name
Test status
Simulation time 140001790 ps
CPU time 4.46 seconds
Started Mar 24 01:02:46 PM PDT 24
Finished Mar 24 01:02:50 PM PDT 24
Peak memory 199968 kb
Host smart-f81ea64e-5046-4c9a-9351-917c5bf7be15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375565428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.375565428
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.1838776362
Short name T75
Test name
Test status
Simulation time 65569234144 ps
CPU time 903.45 seconds
Started Mar 24 01:02:44 PM PDT 24
Finished Mar 24 01:17:48 PM PDT 24
Peak memory 200100 kb
Host smart-cd3a66c4-43dd-4d35-b20b-48242e9f0e88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838776362 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1838776362
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.3167445635
Short name T418
Test name
Test status
Simulation time 117775972 ps
CPU time 1.23 seconds
Started Mar 24 01:02:45 PM PDT 24
Finished Mar 24 01:02:46 PM PDT 24
Peak memory 199832 kb
Host smart-575f8537-50a5-4b8a-87d6-f50b22bd58fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167445635 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.3167445635
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.2483022914
Short name T312
Test name
Test status
Simulation time 30523008965 ps
CPU time 555.88 seconds
Started Mar 24 01:02:43 PM PDT 24
Finished Mar 24 01:11:59 PM PDT 24
Peak memory 200032 kb
Host smart-c8a645b0-adc4-4f93-bb3b-b4709670dcb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483022914 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.2483022914
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1723682297
Short name T369
Test name
Test status
Simulation time 273051966 ps
CPU time 4.54 seconds
Started Mar 24 01:02:44 PM PDT 24
Finished Mar 24 01:02:49 PM PDT 24
Peak memory 199988 kb
Host smart-a27f05e0-527f-4804-be22-62d1d0c8e99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723682297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1723682297
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1670068339
Short name T383
Test name
Test status
Simulation time 13958529 ps
CPU time 0.58 seconds
Started Mar 24 01:02:50 PM PDT 24
Finished Mar 24 01:02:52 PM PDT 24
Peak memory 195256 kb
Host smart-a63c34a2-218a-4ada-9aca-d4101aeed0ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670068339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1670068339
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2293414476
Short name T560
Test name
Test status
Simulation time 1458404648 ps
CPU time 17.34 seconds
Started Mar 24 01:02:44 PM PDT 24
Finished Mar 24 01:03:02 PM PDT 24
Peak memory 229348 kb
Host smart-9a5c4a8d-9681-4b5a-8e39-591831ec24a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2293414476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2293414476
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.643560738
Short name T155
Test name
Test status
Simulation time 467654359 ps
CPU time 23.01 seconds
Started Mar 24 01:02:53 PM PDT 24
Finished Mar 24 01:03:16 PM PDT 24
Peak memory 200020 kb
Host smart-64883fbb-dc61-486f-aeb2-c808c294647a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643560738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.643560738
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2009884543
Short name T263
Test name
Test status
Simulation time 6030901998 ps
CPU time 57.34 seconds
Started Mar 24 01:02:44 PM PDT 24
Finished Mar 24 01:03:42 PM PDT 24
Peak memory 200096 kb
Host smart-824a7f6d-1a62-48d8-8058-afcde632198c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2009884543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2009884543
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.2213776650
Short name T563
Test name
Test status
Simulation time 37629399265 ps
CPU time 125.62 seconds
Started Mar 24 01:02:42 PM PDT 24
Finished Mar 24 01:04:49 PM PDT 24
Peak memory 200008 kb
Host smart-d7149eaf-17e7-461a-a01b-7060b91a0b37
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213776650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2213776650
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.4074264599
Short name T170
Test name
Test status
Simulation time 22469815359 ps
CPU time 102.43 seconds
Started Mar 24 01:02:43 PM PDT 24
Finished Mar 24 01:04:27 PM PDT 24
Peak memory 200076 kb
Host smart-230c4604-e14f-47aa-803d-37a31c04d099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074264599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.4074264599
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2414477638
Short name T371
Test name
Test status
Simulation time 126836493 ps
CPU time 3.75 seconds
Started Mar 24 01:02:43 PM PDT 24
Finished Mar 24 01:02:47 PM PDT 24
Peak memory 199972 kb
Host smart-9698993b-8822-4159-979b-bbe636ca11f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414477638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2414477638
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.3735198644
Short name T462
Test name
Test status
Simulation time 345839386010 ps
CPU time 1600.67 seconds
Started Mar 24 01:02:49 PM PDT 24
Finished Mar 24 01:29:32 PM PDT 24
Peak memory 216464 kb
Host smart-123f3656-3d54-4471-8984-aa57ff941131
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735198644 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.3735198644
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.1648241362
Short name T485
Test name
Test status
Simulation time 160694667 ps
CPU time 1.07 seconds
Started Mar 24 01:02:48 PM PDT 24
Finished Mar 24 01:02:49 PM PDT 24
Peak memory 199256 kb
Host smart-5110d54d-b830-4f41-a12b-0bfae9701630
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648241362 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.1648241362
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.2404455591
Short name T251
Test name
Test status
Simulation time 489779365829 ps
CPU time 533.16 seconds
Started Mar 24 01:02:50 PM PDT 24
Finished Mar 24 01:11:44 PM PDT 24
Peak memory 200052 kb
Host smart-c5f7eb1c-31ae-4466-8208-5d805a04c2d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404455591 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.2404455591
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3269484977
Short name T574
Test name
Test status
Simulation time 6144308732 ps
CPU time 54.76 seconds
Started Mar 24 01:03:04 PM PDT 24
Finished Mar 24 01:03:59 PM PDT 24
Peak memory 200056 kb
Host smart-fea8d17d-279d-41d7-89e4-0af576351e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269484977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3269484977
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.3412479162
Short name T504
Test name
Test status
Simulation time 14887204 ps
CPU time 0.61 seconds
Started Mar 24 01:02:51 PM PDT 24
Finished Mar 24 01:02:52 PM PDT 24
Peak memory 195536 kb
Host smart-e14ac48f-1c94-44a0-a001-a4c337ad831d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412479162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3412479162
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.250292972
Short name T533
Test name
Test status
Simulation time 5451765059 ps
CPU time 25.66 seconds
Started Mar 24 01:02:50 PM PDT 24
Finished Mar 24 01:03:17 PM PDT 24
Peak memory 200056 kb
Host smart-2855e80f-f7c5-4868-9d85-6e39939e4933
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=250292972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.250292972
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3223121041
Short name T386
Test name
Test status
Simulation time 5481941577 ps
CPU time 75.42 seconds
Started Mar 24 01:02:48 PM PDT 24
Finished Mar 24 01:04:06 PM PDT 24
Peak memory 200068 kb
Host smart-6cb6b0ed-5c6a-444c-a58f-dbce53743afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223121041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3223121041
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.233792454
Short name T23
Test name
Test status
Simulation time 1419669762 ps
CPU time 83.78 seconds
Started Mar 24 01:02:48 PM PDT 24
Finished Mar 24 01:04:12 PM PDT 24
Peak memory 199980 kb
Host smart-ff05166c-2167-4dff-9649-f8388168cc84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=233792454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.233792454
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.2568059645
Short name T26
Test name
Test status
Simulation time 9066075822 ps
CPU time 127.9 seconds
Started Mar 24 01:02:50 PM PDT 24
Finished Mar 24 01:04:59 PM PDT 24
Peak memory 200056 kb
Host smart-a1a73fd0-9bb8-48cf-a6ff-1b664fbcf9e8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568059645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2568059645
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.2657175219
Short name T546
Test name
Test status
Simulation time 13784888537 ps
CPU time 54.45 seconds
Started Mar 24 01:02:51 PM PDT 24
Finished Mar 24 01:03:47 PM PDT 24
Peak memory 200020 kb
Host smart-f5c07cfe-e6ba-46e9-99a0-3936cd85789c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657175219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2657175219
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3152410374
Short name T535
Test name
Test status
Simulation time 1152836577 ps
CPU time 6.56 seconds
Started Mar 24 01:02:48 PM PDT 24
Finished Mar 24 01:02:56 PM PDT 24
Peak memory 199976 kb
Host smart-cef32be3-21d6-4fdc-bba8-ba00da4dac62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152410374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3152410374
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3366619097
Short name T337
Test name
Test status
Simulation time 286644183037 ps
CPU time 616.11 seconds
Started Mar 24 01:02:52 PM PDT 24
Finished Mar 24 01:13:08 PM PDT 24
Peak memory 235884 kb
Host smart-63e91e6f-1c9c-487d-8807-d78271ba42b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366619097 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3366619097
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.1239055660
Short name T257
Test name
Test status
Simulation time 562650522 ps
CPU time 1.2 seconds
Started Mar 24 01:02:49 PM PDT 24
Finished Mar 24 01:02:52 PM PDT 24
Peak memory 199768 kb
Host smart-58675104-6206-4770-874a-478c82f3c8e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239055660 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.1239055660
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.4105341621
Short name T227
Test name
Test status
Simulation time 23229008139 ps
CPU time 373.48 seconds
Started Mar 24 01:02:50 PM PDT 24
Finished Mar 24 01:09:04 PM PDT 24
Peak memory 200072 kb
Host smart-94db3c81-267d-4186-b9bf-52da6377b4c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105341621 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.4105341621
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.2167723645
Short name T290
Test name
Test status
Simulation time 2132658219 ps
CPU time 26.92 seconds
Started Mar 24 01:02:51 PM PDT 24
Finished Mar 24 01:03:18 PM PDT 24
Peak memory 200028 kb
Host smart-178beac9-9bec-460d-8db3-f809b93dc911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167723645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2167723645
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.633798107
Short name T584
Test name
Test status
Simulation time 121762311 ps
CPU time 0.57 seconds
Started Mar 24 01:02:55 PM PDT 24
Finished Mar 24 01:02:55 PM PDT 24
Peak memory 195512 kb
Host smart-7a5dfae4-c862-4b1c-a630-ccb83641a978
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633798107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.633798107
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3024147660
Short name T38
Test name
Test status
Simulation time 615290570 ps
CPU time 21.23 seconds
Started Mar 24 01:02:50 PM PDT 24
Finished Mar 24 01:03:12 PM PDT 24
Peak memory 224532 kb
Host smart-a3fcf8f6-616a-46f0-9499-ee92023d0e15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3024147660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3024147660
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.253392898
Short name T578
Test name
Test status
Simulation time 3965387716 ps
CPU time 31.68 seconds
Started Mar 24 01:02:50 PM PDT 24
Finished Mar 24 01:03:23 PM PDT 24
Peak memory 200068 kb
Host smart-fdab3ba7-b25c-4fde-92d6-ee4e6e6ad9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253392898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.253392898
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.953582637
Short name T347
Test name
Test status
Simulation time 2162567723 ps
CPU time 120.65 seconds
Started Mar 24 01:02:50 PM PDT 24
Finished Mar 24 01:04:52 PM PDT 24
Peak memory 200028 kb
Host smart-0967df70-7ee7-4790-83cb-68a17a9994a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=953582637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.953582637
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.742479102
Short name T309
Test name
Test status
Simulation time 31857459595 ps
CPU time 137.89 seconds
Started Mar 24 01:02:50 PM PDT 24
Finished Mar 24 01:05:09 PM PDT 24
Peak memory 200084 kb
Host smart-b04d3d42-788a-4777-bcda-087b8153afdc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742479102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.742479102
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.2003707931
Short name T235
Test name
Test status
Simulation time 9376963882 ps
CPU time 134.95 seconds
Started Mar 24 01:02:48 PM PDT 24
Finished Mar 24 01:05:06 PM PDT 24
Peak memory 200052 kb
Host smart-cda16e4d-7bf6-428c-a34f-9a9b4d1e100c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003707931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.2003707931
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1699314655
Short name T486
Test name
Test status
Simulation time 707583428 ps
CPU time 5.49 seconds
Started Mar 24 01:02:50 PM PDT 24
Finished Mar 24 01:02:56 PM PDT 24
Peak memory 200000 kb
Host smart-17b6ebe0-5baa-4ddd-9916-57f34a78e7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699314655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1699314655
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.3406290507
Short name T20
Test name
Test status
Simulation time 16690930121 ps
CPU time 344.12 seconds
Started Mar 24 01:02:50 PM PDT 24
Finished Mar 24 01:08:35 PM PDT 24
Peak memory 200012 kb
Host smart-5c8777a5-473b-45b9-b2bb-24c572638040
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406290507 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.3406290507
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.1600384879
Short name T456
Test name
Test status
Simulation time 30107523 ps
CPU time 0.96 seconds
Started Mar 24 01:02:49 PM PDT 24
Finished Mar 24 01:02:52 PM PDT 24
Peak memory 198272 kb
Host smart-2b9c405a-3970-44e5-bf57-a152671a0819
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600384879 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.1600384879
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.1000025760
Short name T392
Test name
Test status
Simulation time 15575984094 ps
CPU time 416.37 seconds
Started Mar 24 01:03:04 PM PDT 24
Finished Mar 24 01:10:01 PM PDT 24
Peak memory 199952 kb
Host smart-c82985ad-71c8-46ff-b891-491560b3470c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000025760 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.1000025760
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1248646736
Short name T141
Test name
Test status
Simulation time 2739007746 ps
CPU time 56.07 seconds
Started Mar 24 01:03:04 PM PDT 24
Finished Mar 24 01:04:01 PM PDT 24
Peak memory 200052 kb
Host smart-c86ce007-b395-4028-a292-9ba1ba37c16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248646736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1248646736
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3409489976
Short name T216
Test name
Test status
Simulation time 38806051 ps
CPU time 0.6 seconds
Started Mar 24 01:02:53 PM PDT 24
Finished Mar 24 01:02:54 PM PDT 24
Peak memory 195480 kb
Host smart-a3de3108-c0e3-4130-a2ab-9626afd33cc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409489976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3409489976
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.740362001
Short name T501
Test name
Test status
Simulation time 1427229076 ps
CPU time 55.35 seconds
Started Mar 24 01:02:53 PM PDT 24
Finished Mar 24 01:03:48 PM PDT 24
Peak memory 224704 kb
Host smart-f7fab498-37b5-47d3-8712-ec5a5ed78be3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=740362001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.740362001
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.460940958
Short name T481
Test name
Test status
Simulation time 4763986971 ps
CPU time 34.54 seconds
Started Mar 24 01:02:54 PM PDT 24
Finished Mar 24 01:03:29 PM PDT 24
Peak memory 200088 kb
Host smart-9d54e4ff-362c-417c-a576-c0d14433a75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460940958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.460940958
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.7493189
Short name T379
Test name
Test status
Simulation time 1435625249 ps
CPU time 78.89 seconds
Started Mar 24 01:02:55 PM PDT 24
Finished Mar 24 01:04:14 PM PDT 24
Peak memory 199980 kb
Host smart-f1f9a475-2bb4-4e44-b548-2034a9374dc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=7493189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.7493189
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3511706510
Short name T301
Test name
Test status
Simulation time 37291352216 ps
CPU time 247.08 seconds
Started Mar 24 01:03:15 PM PDT 24
Finished Mar 24 01:07:23 PM PDT 24
Peak memory 200108 kb
Host smart-6f704137-574e-4a42-b5e5-83a1606dfc56
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511706510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3511706510
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3946238865
Short name T211
Test name
Test status
Simulation time 17585891602 ps
CPU time 122.14 seconds
Started Mar 24 01:02:52 PM PDT 24
Finished Mar 24 01:04:54 PM PDT 24
Peak memory 200056 kb
Host smart-fd65047a-26e8-4b8f-a7b8-f1b27993de1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946238865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3946238865
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.1456680584
Short name T245
Test name
Test status
Simulation time 177761053 ps
CPU time 1.4 seconds
Started Mar 24 01:02:55 PM PDT 24
Finished Mar 24 01:02:56 PM PDT 24
Peak memory 199992 kb
Host smart-5744ee0b-0c7f-4fc0-97cc-3f203c9048e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456680584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.1456680584
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.4061236722
Short name T594
Test name
Test status
Simulation time 16670083960 ps
CPU time 912.58 seconds
Started Mar 24 01:02:54 PM PDT 24
Finished Mar 24 01:18:07 PM PDT 24
Peak memory 241100 kb
Host smart-efb2f33d-169f-4cc8-be19-bfe918dd2156
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061236722 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.4061236722
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.5599472
Short name T136
Test name
Test status
Simulation time 125184047 ps
CPU time 1.24 seconds
Started Mar 24 01:02:53 PM PDT 24
Finished Mar 24 01:02:54 PM PDT 24
Peak memory 199404 kb
Host smart-a7b3495a-8bf8-4124-a639-45113731cd38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5599472 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.hmac_test_hmac_vectors.5599472
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.771835687
Short name T555
Test name
Test status
Simulation time 32134015943 ps
CPU time 427.68 seconds
Started Mar 24 01:03:04 PM PDT 24
Finished Mar 24 01:10:12 PM PDT 24
Peak memory 199796 kb
Host smart-3cdf2d3c-6522-475c-a557-34d41a5c4311
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771835687 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.771835687
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.998883479
Short name T523
Test name
Test status
Simulation time 406499620 ps
CPU time 5.95 seconds
Started Mar 24 01:02:54 PM PDT 24
Finished Mar 24 01:03:00 PM PDT 24
Peak memory 199916 kb
Host smart-a374ac7e-1970-4429-bba7-585bf9b43895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998883479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.998883479
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.800745312
Short name T457
Test name
Test status
Simulation time 40279633 ps
CPU time 0.56 seconds
Started Mar 24 01:02:54 PM PDT 24
Finished Mar 24 01:02:55 PM PDT 24
Peak memory 195240 kb
Host smart-d5c3f5ab-d150-4576-84f0-cc2a868f881d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800745312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.800745312
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3888280346
Short name T233
Test name
Test status
Simulation time 340295018 ps
CPU time 15.09 seconds
Started Mar 24 01:02:54 PM PDT 24
Finished Mar 24 01:03:09 PM PDT 24
Peak memory 233176 kb
Host smart-acb63075-cf9b-4a5f-b250-d053d1870312
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3888280346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3888280346
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2836736816
Short name T424
Test name
Test status
Simulation time 1810730124 ps
CPU time 9.38 seconds
Started Mar 24 01:02:54 PM PDT 24
Finished Mar 24 01:03:04 PM PDT 24
Peak memory 199988 kb
Host smart-1ff287d4-e4fb-4218-900e-1e8c7369359b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836736816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2836736816
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3536582457
Short name T432
Test name
Test status
Simulation time 7923956322 ps
CPU time 51.36 seconds
Started Mar 24 01:02:55 PM PDT 24
Finished Mar 24 01:03:47 PM PDT 24
Peak memory 199992 kb
Host smart-df8aefb4-6e80-41bf-b5a3-0332128b0990
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3536582457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3536582457
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1858727083
Short name T247
Test name
Test status
Simulation time 3035110810 ps
CPU time 21.76 seconds
Started Mar 24 01:02:54 PM PDT 24
Finished Mar 24 01:03:16 PM PDT 24
Peak memory 200052 kb
Host smart-4eec9d39-5de8-4ab1-93ef-df179ccf59c3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858727083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1858727083
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.859803120
Short name T455
Test name
Test status
Simulation time 422162035 ps
CPU time 25.33 seconds
Started Mar 24 01:02:55 PM PDT 24
Finished Mar 24 01:03:21 PM PDT 24
Peak memory 200064 kb
Host smart-bbb16762-870e-4a8d-9988-3a6fe776969a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859803120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.859803120
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.3086741524
Short name T502
Test name
Test status
Simulation time 1436646842 ps
CPU time 4.76 seconds
Started Mar 24 01:03:04 PM PDT 24
Finished Mar 24 01:03:09 PM PDT 24
Peak memory 199888 kb
Host smart-fd846f27-b2f1-4736-9e04-618e8abeaefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086741524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.3086741524
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.1670813603
Short name T470
Test name
Test status
Simulation time 182275860762 ps
CPU time 403.33 seconds
Started Mar 24 01:02:54 PM PDT 24
Finished Mar 24 01:09:37 PM PDT 24
Peak memory 231816 kb
Host smart-6efb6806-8571-4e8f-82f0-cbc32a2f6412
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670813603 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1670813603
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.1782522080
Short name T416
Test name
Test status
Simulation time 489105531 ps
CPU time 1.3 seconds
Started Mar 24 01:03:04 PM PDT 24
Finished Mar 24 01:03:06 PM PDT 24
Peak memory 199552 kb
Host smart-c67296a2-7ed6-4435-828f-633f45dd86f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782522080 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.1782522080
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.1750104528
Short name T528
Test name
Test status
Simulation time 16059376601 ps
CPU time 427.35 seconds
Started Mar 24 01:02:55 PM PDT 24
Finished Mar 24 01:10:02 PM PDT 24
Peak memory 199936 kb
Host smart-377b08a8-2091-428c-89ad-967ec0424e71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750104528 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.1750104528
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2096992343
Short name T359
Test name
Test status
Simulation time 10625375436 ps
CPU time 38.35 seconds
Started Mar 24 01:03:04 PM PDT 24
Finished Mar 24 01:03:43 PM PDT 24
Peak memory 199824 kb
Host smart-944a3d40-3f0e-4668-a423-b5e6f904195c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096992343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2096992343
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.4247027640
Short name T255
Test name
Test status
Simulation time 21062653 ps
CPU time 0.62 seconds
Started Mar 24 01:03:04 PM PDT 24
Finished Mar 24 01:03:04 PM PDT 24
Peak memory 195520 kb
Host smart-4c205994-8176-4a69-83fc-a6a58eeb60c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247027640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.4247027640
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2338762527
Short name T527
Test name
Test status
Simulation time 1188565987 ps
CPU time 25.29 seconds
Started Mar 24 01:02:58 PM PDT 24
Finished Mar 24 01:03:24 PM PDT 24
Peak memory 228620 kb
Host smart-3b752119-dee2-4d19-a7e0-a39909d776fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2338762527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2338762527
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.2386575574
Short name T543
Test name
Test status
Simulation time 3573281592 ps
CPU time 43.52 seconds
Started Mar 24 01:03:00 PM PDT 24
Finished Mar 24 01:03:44 PM PDT 24
Peak memory 199868 kb
Host smart-8346ad03-6ef1-4352-aec8-cf15a10eca4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386575574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2386575574
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.491714694
Short name T473
Test name
Test status
Simulation time 243956195 ps
CPU time 14.3 seconds
Started Mar 24 01:02:59 PM PDT 24
Finished Mar 24 01:03:15 PM PDT 24
Peak memory 200260 kb
Host smart-b3f08236-3f87-4876-bfe0-7890c58ba41e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=491714694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.491714694
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.573537547
Short name T587
Test name
Test status
Simulation time 8502465099 ps
CPU time 75.41 seconds
Started Mar 24 01:03:01 PM PDT 24
Finished Mar 24 01:04:16 PM PDT 24
Peak memory 200084 kb
Host smart-fe5e7947-6109-4d02-85f5-ef40fadff347
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573537547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.573537547
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.4007825594
Short name T84
Test name
Test status
Simulation time 2290698695 ps
CPU time 20.7 seconds
Started Mar 24 01:02:59 PM PDT 24
Finished Mar 24 01:03:22 PM PDT 24
Peak memory 200028 kb
Host smart-3845edf2-1850-4d49-a08d-5c779e290cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007825594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.4007825594
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3405283844
Short name T134
Test name
Test status
Simulation time 216169261 ps
CPU time 6.77 seconds
Started Mar 24 01:02:53 PM PDT 24
Finished Mar 24 01:03:00 PM PDT 24
Peak memory 199964 kb
Host smart-01d0421c-25ce-4435-872c-73313ed0bc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405283844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3405283844
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.3625056149
Short name T516
Test name
Test status
Simulation time 18803851264 ps
CPU time 435.45 seconds
Started Mar 24 01:02:59 PM PDT 24
Finished Mar 24 01:10:16 PM PDT 24
Peak memory 216312 kb
Host smart-cb12c61d-20a3-479d-8e87-3587bc4b6562
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625056149 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3625056149
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.351003150
Short name T267
Test name
Test status
Simulation time 118196548 ps
CPU time 1.37 seconds
Started Mar 24 01:03:01 PM PDT 24
Finished Mar 24 01:03:04 PM PDT 24
Peak memory 199976 kb
Host smart-41990fed-f91d-4e14-b702-0b8ccbca7eb8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351003150 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_hmac_vectors.351003150
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.884084270
Short name T260
Test name
Test status
Simulation time 7699038650 ps
CPU time 445.37 seconds
Started Mar 24 01:02:58 PM PDT 24
Finished Mar 24 01:10:26 PM PDT 24
Peak memory 200016 kb
Host smart-acbab43f-b2b4-49b6-a1fd-05672ae3adde
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884084270 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.884084270
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3976593713
Short name T276
Test name
Test status
Simulation time 6974633718 ps
CPU time 96.77 seconds
Started Mar 24 01:03:00 PM PDT 24
Finished Mar 24 01:04:38 PM PDT 24
Peak memory 200108 kb
Host smart-e12f9d0d-bf5f-48a2-a60f-97c90300be86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976593713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3976593713
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3326405444
Short name T165
Test name
Test status
Simulation time 27151044 ps
CPU time 0.57 seconds
Started Mar 24 01:03:08 PM PDT 24
Finished Mar 24 01:03:08 PM PDT 24
Peak memory 195556 kb
Host smart-e1d7d3b2-1ecc-42d7-bb88-d11c46f954eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326405444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3326405444
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.1398356263
Short name T572
Test name
Test status
Simulation time 4660364881 ps
CPU time 38.75 seconds
Started Mar 24 01:03:06 PM PDT 24
Finished Mar 24 01:03:44 PM PDT 24
Peak memory 215956 kb
Host smart-515f79a5-95ee-4e22-9c9d-eb089da77eac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1398356263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1398356263
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.588210787
Short name T271
Test name
Test status
Simulation time 24687082657 ps
CPU time 42.55 seconds
Started Mar 24 01:03:07 PM PDT 24
Finished Mar 24 01:03:49 PM PDT 24
Peak memory 200072 kb
Host smart-f19f0145-5da5-4f9d-9937-b2d18856e5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588210787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.588210787
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2088388991
Short name T274
Test name
Test status
Simulation time 22259711648 ps
CPU time 88.94 seconds
Started Mar 24 01:03:05 PM PDT 24
Finished Mar 24 01:04:34 PM PDT 24
Peak memory 200068 kb
Host smart-cf7ca27f-a1b2-4c91-ba81-1159863ef4df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2088388991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2088388991
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3285920147
Short name T288
Test name
Test status
Simulation time 7839335226 ps
CPU time 108.25 seconds
Started Mar 24 01:03:07 PM PDT 24
Finished Mar 24 01:04:55 PM PDT 24
Peak memory 200104 kb
Host smart-41b2a948-4502-4d9c-9977-2c660054f627
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285920147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3285920147
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.2540518714
Short name T417
Test name
Test status
Simulation time 3560604176 ps
CPU time 25.91 seconds
Started Mar 24 01:03:07 PM PDT 24
Finished Mar 24 01:03:33 PM PDT 24
Peak memory 200084 kb
Host smart-521d6246-37db-45f7-8951-fef706b17952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540518714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2540518714
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2984704966
Short name T352
Test name
Test status
Simulation time 461424628 ps
CPU time 6.13 seconds
Started Mar 24 01:03:03 PM PDT 24
Finished Mar 24 01:03:09 PM PDT 24
Peak memory 200000 kb
Host smart-f4d637bb-2bc2-4f1f-bdf0-3e820188e5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984704966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2984704966
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3477349856
Short name T196
Test name
Test status
Simulation time 24029708756 ps
CPU time 707.54 seconds
Started Mar 24 01:03:05 PM PDT 24
Finished Mar 24 01:14:53 PM PDT 24
Peak memory 200068 kb
Host smart-cfbf5f7f-ec0d-440b-9dbc-1079863cf01e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477349856 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3477349856
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.2512031150
Short name T518
Test name
Test status
Simulation time 262580269 ps
CPU time 1.26 seconds
Started Mar 24 01:03:07 PM PDT 24
Finished Mar 24 01:03:08 PM PDT 24
Peak memory 199680 kb
Host smart-145c506c-2a2e-4da9-875e-594411a916d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512031150 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.2512031150
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.3729925938
Short name T491
Test name
Test status
Simulation time 31015548275 ps
CPU time 433.78 seconds
Started Mar 24 01:03:07 PM PDT 24
Finished Mar 24 01:10:21 PM PDT 24
Peak memory 200052 kb
Host smart-56b35b86-627d-4299-b56c-756e093f79da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729925938 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.3729925938
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_alert_test.393979023
Short name T409
Test name
Test status
Simulation time 20908056 ps
CPU time 0.58 seconds
Started Mar 24 01:03:07 PM PDT 24
Finished Mar 24 01:03:08 PM PDT 24
Peak memory 195520 kb
Host smart-008f6222-58db-462a-905c-ac8df3fd35d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393979023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.393979023
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1747965390
Short name T468
Test name
Test status
Simulation time 2114520466 ps
CPU time 52.33 seconds
Started Mar 24 01:03:07 PM PDT 24
Finished Mar 24 01:03:59 PM PDT 24
Peak memory 222908 kb
Host smart-9fd9a3cf-1ab8-487d-8798-ef612e227a24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1747965390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1747965390
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3756554270
Short name T41
Test name
Test status
Simulation time 6193708752 ps
CPU time 29.23 seconds
Started Mar 24 01:03:07 PM PDT 24
Finished Mar 24 01:03:36 PM PDT 24
Peak memory 200076 kb
Host smart-fe619634-8f1d-40fb-9874-dfb048e8ad00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756554270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3756554270
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.821607288
Short name T171
Test name
Test status
Simulation time 7473898891 ps
CPU time 113.07 seconds
Started Mar 24 01:03:03 PM PDT 24
Finished Mar 24 01:04:57 PM PDT 24
Peak memory 200036 kb
Host smart-ee9f8f6d-3a01-4731-89b9-ddf4a4f36f9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=821607288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.821607288
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3615525358
Short name T583
Test name
Test status
Simulation time 1505180331 ps
CPU time 41.39 seconds
Started Mar 24 01:03:07 PM PDT 24
Finished Mar 24 01:03:48 PM PDT 24
Peak memory 200008 kb
Host smart-3bcc333f-d53d-436d-8b9d-ec0f99de8d3c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615525358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3615525358
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3872656969
Short name T549
Test name
Test status
Simulation time 15645576759 ps
CPU time 116.19 seconds
Started Mar 24 01:03:04 PM PDT 24
Finished Mar 24 01:05:01 PM PDT 24
Peak memory 200068 kb
Host smart-9baaaa38-2559-4124-bda5-975b4a7ec053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872656969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3872656969
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2936493374
Short name T225
Test name
Test status
Simulation time 419380514 ps
CPU time 3.37 seconds
Started Mar 24 01:03:07 PM PDT 24
Finished Mar 24 01:03:11 PM PDT 24
Peak memory 199972 kb
Host smart-d80b21fd-e2a7-422d-b307-52e1cf0ca4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936493374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2936493374
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.2546752439
Short name T419
Test name
Test status
Simulation time 59307501667 ps
CPU time 320.75 seconds
Started Mar 24 01:03:07 PM PDT 24
Finished Mar 24 01:08:27 PM PDT 24
Peak memory 233912 kb
Host smart-5eee2c59-a640-44dc-bccb-da8d0f2121e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546752439 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2546752439
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.1298983975
Short name T328
Test name
Test status
Simulation time 78513563 ps
CPU time 1.08 seconds
Started Mar 24 01:03:07 PM PDT 24
Finished Mar 24 01:03:08 PM PDT 24
Peak memory 199512 kb
Host smart-f70e7e2a-96fd-40b2-b70e-6a4c64ac29aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298983975 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.1298983975
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.852562618
Short name T254
Test name
Test status
Simulation time 286456295783 ps
CPU time 460.5 seconds
Started Mar 24 01:03:06 PM PDT 24
Finished Mar 24 01:10:46 PM PDT 24
Peak memory 199996 kb
Host smart-7748235b-2e4a-4e0c-8c96-a4e8ba3734b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852562618 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.852562618
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3341571326
Short name T494
Test name
Test status
Simulation time 1006516853 ps
CPU time 14.95 seconds
Started Mar 24 01:03:07 PM PDT 24
Finished Mar 24 01:03:22 PM PDT 24
Peak memory 200008 kb
Host smart-d6596864-aa07-4a14-bb2f-64f03c54a06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341571326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3341571326
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3301087711
Short name T475
Test name
Test status
Simulation time 13373628 ps
CPU time 0.59 seconds
Started Mar 24 01:01:35 PM PDT 24
Finished Mar 24 01:01:36 PM PDT 24
Peak memory 195220 kb
Host smart-7ae40a7a-cc85-484a-9e36-64239d36f66e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301087711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3301087711
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1783901808
Short name T464
Test name
Test status
Simulation time 3068625743 ps
CPU time 52.37 seconds
Started Mar 24 01:01:42 PM PDT 24
Finished Mar 24 01:02:34 PM PDT 24
Peak memory 215540 kb
Host smart-45439c2a-38f1-4855-92ed-74b209119166
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1783901808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1783901808
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3931732614
Short name T335
Test name
Test status
Simulation time 2382623235 ps
CPU time 62.92 seconds
Started Mar 24 01:01:38 PM PDT 24
Finished Mar 24 01:02:41 PM PDT 24
Peak memory 200324 kb
Host smart-a1dd467d-b477-4bb4-bb2e-9b3d19fb8f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931732614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3931732614
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.3603446711
Short name T488
Test name
Test status
Simulation time 2427550396 ps
CPU time 66.95 seconds
Started Mar 24 01:01:32 PM PDT 24
Finished Mar 24 01:02:40 PM PDT 24
Peak memory 199964 kb
Host smart-6843d384-35b7-4aee-99f4-9a434f2f0907
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3603446711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.3603446711
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1900107227
Short name T253
Test name
Test status
Simulation time 4361966027 ps
CPU time 117.44 seconds
Started Mar 24 01:01:37 PM PDT 24
Finished Mar 24 01:03:34 PM PDT 24
Peak memory 200072 kb
Host smart-a36c2f2c-eb60-4a81-b0a3-acdad0a636f5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900107227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1900107227
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.908074895
Short name T249
Test name
Test status
Simulation time 3840466216 ps
CPU time 73.9 seconds
Started Mar 24 01:01:31 PM PDT 24
Finished Mar 24 01:02:45 PM PDT 24
Peak memory 200024 kb
Host smart-b370705d-9034-472b-be84-8776d1cbc2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908074895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.908074895
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_smoke.2981611234
Short name T252
Test name
Test status
Simulation time 867034922 ps
CPU time 5.02 seconds
Started Mar 24 01:01:31 PM PDT 24
Finished Mar 24 01:01:37 PM PDT 24
Peak memory 199976 kb
Host smart-b888cdbf-f4e1-4b45-b57f-1f3536bf43a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981611234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2981611234
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.801217525
Short name T514
Test name
Test status
Simulation time 3653203407 ps
CPU time 174.13 seconds
Started Mar 24 01:01:37 PM PDT 24
Finished Mar 24 01:04:31 PM PDT 24
Peak memory 233564 kb
Host smart-7ddf97e6-db2d-409a-89c6-3607cdef3a62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801217525 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.801217525
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.1759649166
Short name T522
Test name
Test status
Simulation time 106130435 ps
CPU time 1.28 seconds
Started Mar 24 01:01:38 PM PDT 24
Finished Mar 24 01:01:39 PM PDT 24
Peak memory 200024 kb
Host smart-016682be-c3f7-468e-8f0d-c79bbb4149fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759649166 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.1759649166
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.3575657320
Short name T436
Test name
Test status
Simulation time 39386738844 ps
CPU time 529.74 seconds
Started Mar 24 01:01:35 PM PDT 24
Finished Mar 24 01:10:25 PM PDT 24
Peak memory 199972 kb
Host smart-9d9fd682-a2e6-41df-bcef-e9c00b93447b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575657320 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.3575657320
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2372862903
Short name T130
Test name
Test status
Simulation time 931349211 ps
CPU time 18.06 seconds
Started Mar 24 01:01:36 PM PDT 24
Finished Mar 24 01:01:54 PM PDT 24
Peak memory 199964 kb
Host smart-a29ca5f8-b8cc-495d-b39f-8cf5eb45bdf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372862903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2372862903
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.622425145
Short name T266
Test name
Test status
Simulation time 10881240 ps
CPU time 0.58 seconds
Started Mar 24 01:03:09 PM PDT 24
Finished Mar 24 01:03:12 PM PDT 24
Peak memory 194500 kb
Host smart-4d25f80a-b4f3-488b-a937-a42024c79b86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622425145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.622425145
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1271935183
Short name T86
Test name
Test status
Simulation time 1219262624 ps
CPU time 30.15 seconds
Started Mar 24 01:03:08 PM PDT 24
Finished Mar 24 01:03:41 PM PDT 24
Peak memory 218340 kb
Host smart-0c7f9d83-4c41-46b6-a48d-4a5e456177ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1271935183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1271935183
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1195667027
Short name T33
Test name
Test status
Simulation time 2929031462 ps
CPU time 45.65 seconds
Started Mar 24 01:03:09 PM PDT 24
Finished Mar 24 01:03:57 PM PDT 24
Peak memory 199956 kb
Host smart-4f3bfa14-00a8-456b-90e3-4dcb3907e169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195667027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1195667027
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.4027679400
Short name T109
Test name
Test status
Simulation time 5995404507 ps
CPU time 66.59 seconds
Started Mar 24 01:03:09 PM PDT 24
Finished Mar 24 01:04:18 PM PDT 24
Peak memory 200072 kb
Host smart-1967e95e-c9bf-4488-bd2b-074244e8498a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4027679400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.4027679400
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.3831637483
Short name T540
Test name
Test status
Simulation time 408899760 ps
CPU time 22.79 seconds
Started Mar 24 01:03:09 PM PDT 24
Finished Mar 24 01:03:34 PM PDT 24
Peak memory 199964 kb
Host smart-d0eef899-d397-4a63-8373-97749a3273b3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831637483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3831637483
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.665915932
Short name T173
Test name
Test status
Simulation time 1870007335 ps
CPU time 19.25 seconds
Started Mar 24 01:03:11 PM PDT 24
Finished Mar 24 01:03:30 PM PDT 24
Peak memory 199988 kb
Host smart-0949616d-da1d-45aa-b394-cf3bfe31eb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665915932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.665915932
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.410264490
Short name T407
Test name
Test status
Simulation time 23283223 ps
CPU time 0.95 seconds
Started Mar 24 01:03:08 PM PDT 24
Finished Mar 24 01:03:09 PM PDT 24
Peak memory 198796 kb
Host smart-e66cea46-466b-4ceb-8edc-a0029ede8109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410264490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.410264490
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1887927391
Short name T68
Test name
Test status
Simulation time 57182551023 ps
CPU time 865.32 seconds
Started Mar 24 01:03:10 PM PDT 24
Finished Mar 24 01:17:36 PM PDT 24
Peak memory 208336 kb
Host smart-c24327a9-ce78-4d4d-bfcc-a7cf89af0fc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887927391 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1887927391
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.652808553
Short name T453
Test name
Test status
Simulation time 99811105 ps
CPU time 0.96 seconds
Started Mar 24 01:03:09 PM PDT 24
Finished Mar 24 01:03:12 PM PDT 24
Peak memory 198612 kb
Host smart-7bbce193-3b76-4132-bd34-fc3f28304f37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652808553 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_hmac_vectors.652808553
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.3483513313
Short name T513
Test name
Test status
Simulation time 16740739499 ps
CPU time 429.85 seconds
Started Mar 24 01:03:08 PM PDT 24
Finished Mar 24 01:10:21 PM PDT 24
Peak memory 200044 kb
Host smart-5d0056fa-81e8-4509-acc7-9bb91dc713b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483513313 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.3483513313
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.3288297202
Short name T87
Test name
Test status
Simulation time 4440252787 ps
CPU time 60.32 seconds
Started Mar 24 01:03:08 PM PDT 24
Finished Mar 24 01:04:08 PM PDT 24
Peak memory 199976 kb
Host smart-1ec073ad-e097-43ee-bd14-81c310de4d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288297202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.3288297202
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.326538157
Short name T576
Test name
Test status
Simulation time 40095820 ps
CPU time 0.58 seconds
Started Mar 24 01:03:15 PM PDT 24
Finished Mar 24 01:03:16 PM PDT 24
Peak memory 195444 kb
Host smart-20ce96a1-2eda-4570-965c-d75079681a6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326538157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.326538157
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1835688043
Short name T592
Test name
Test status
Simulation time 1077094115 ps
CPU time 49.62 seconds
Started Mar 24 01:03:22 PM PDT 24
Finished Mar 24 01:04:14 PM PDT 24
Peak memory 226524 kb
Host smart-1f83f57e-b57e-44cd-8edb-4d74701d4e1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1835688043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1835688043
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.4144833664
Short name T231
Test name
Test status
Simulation time 677206159 ps
CPU time 14.17 seconds
Started Mar 24 01:03:15 PM PDT 24
Finished Mar 24 01:03:29 PM PDT 24
Peak memory 199800 kb
Host smart-e6a3ee5e-50ff-4a1c-9d26-62db10582296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144833664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.4144833664
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2878112250
Short name T258
Test name
Test status
Simulation time 2351138498 ps
CPU time 118.29 seconds
Started Mar 24 01:03:17 PM PDT 24
Finished Mar 24 01:05:15 PM PDT 24
Peak memory 199900 kb
Host smart-30f0238d-5e80-4743-96d6-c49fcf48ceae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2878112250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2878112250
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2694190887
Short name T306
Test name
Test status
Simulation time 3447988530 ps
CPU time 48.93 seconds
Started Mar 24 01:03:16 PM PDT 24
Finished Mar 24 01:04:05 PM PDT 24
Peak memory 200128 kb
Host smart-b7c615cc-3e6a-4ad5-b325-c1f2d8343693
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694190887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2694190887
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.245397191
Short name T313
Test name
Test status
Simulation time 11618482132 ps
CPU time 39.63 seconds
Started Mar 24 01:03:14 PM PDT 24
Finished Mar 24 01:03:54 PM PDT 24
Peak memory 200020 kb
Host smart-85210ea0-75f9-4f43-a736-bf39a0900ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245397191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.245397191
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.3183701005
Short name T78
Test name
Test status
Simulation time 170741568 ps
CPU time 1.62 seconds
Started Mar 24 01:03:17 PM PDT 24
Finished Mar 24 01:03:19 PM PDT 24
Peak memory 199976 kb
Host smart-0ecb98f0-b111-44c7-a1fd-a2b69eeb3361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183701005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3183701005
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.1300314141
Short name T395
Test name
Test status
Simulation time 272558923 ps
CPU time 1.22 seconds
Started Mar 24 01:03:15 PM PDT 24
Finished Mar 24 01:03:16 PM PDT 24
Peak memory 199940 kb
Host smart-ca4d6d1f-ddab-471e-96bd-d3bf9a9e25e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300314141 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.1300314141
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.1074715847
Short name T123
Test name
Test status
Simulation time 14413519862 ps
CPU time 410.12 seconds
Started Mar 24 01:03:15 PM PDT 24
Finished Mar 24 01:10:06 PM PDT 24
Peak memory 200008 kb
Host smart-2b2acdd8-7b20-4e13-8b2c-ade8dc623b48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074715847 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.1074715847
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.67717896
Short name T189
Test name
Test status
Simulation time 3505890441 ps
CPU time 35.98 seconds
Started Mar 24 01:03:16 PM PDT 24
Finished Mar 24 01:03:52 PM PDT 24
Peak memory 200104 kb
Host smart-1edf373e-cff9-4dc0-b721-5cae0f4ddc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67717896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.67717896
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.4240055061
Short name T476
Test name
Test status
Simulation time 31244301 ps
CPU time 0.56 seconds
Started Mar 24 01:03:24 PM PDT 24
Finished Mar 24 01:03:26 PM PDT 24
Peak memory 194464 kb
Host smart-6d931c25-724e-4b71-8981-f1ef717911fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240055061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.4240055061
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2331306101
Short name T305
Test name
Test status
Simulation time 282896568 ps
CPU time 10.63 seconds
Started Mar 24 01:03:16 PM PDT 24
Finished Mar 24 01:03:27 PM PDT 24
Peak memory 208188 kb
Host smart-092ba277-a6dd-4994-9fb1-71f81c550daf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2331306101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2331306101
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.3288287735
Short name T396
Test name
Test status
Simulation time 3540966433 ps
CPU time 29.21 seconds
Started Mar 24 01:03:22 PM PDT 24
Finished Mar 24 01:03:54 PM PDT 24
Peak memory 200088 kb
Host smart-70dfdf30-e92f-40dc-819a-5671fe0aec6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288287735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3288287735
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.2533635111
Short name T451
Test name
Test status
Simulation time 632734975 ps
CPU time 34.24 seconds
Started Mar 24 01:03:16 PM PDT 24
Finished Mar 24 01:03:51 PM PDT 24
Peak memory 199924 kb
Host smart-c0ac9a32-84c5-4aff-9f8c-9a756511d0e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2533635111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2533635111
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3334592600
Short name T289
Test name
Test status
Simulation time 8743997159 ps
CPU time 153.29 seconds
Started Mar 24 01:03:23 PM PDT 24
Finished Mar 24 01:05:58 PM PDT 24
Peak memory 199920 kb
Host smart-e553c73e-e698-49c2-8bd3-07099631adb0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334592600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3334592600
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2215494790
Short name T322
Test name
Test status
Simulation time 6971707612 ps
CPU time 111.97 seconds
Started Mar 24 01:03:17 PM PDT 24
Finished Mar 24 01:05:09 PM PDT 24
Peak memory 200040 kb
Host smart-8a925b7b-bcaa-47c0-8ed0-9a4d3dda874f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215494790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2215494790
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.407345737
Short name T202
Test name
Test status
Simulation time 93997761 ps
CPU time 1.75 seconds
Started Mar 24 01:03:15 PM PDT 24
Finished Mar 24 01:03:17 PM PDT 24
Peak memory 200028 kb
Host smart-cc78aa05-f58b-42a6-9b33-5c700ac3102c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407345737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.407345737
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3117955161
Short name T492
Test name
Test status
Simulation time 102648055016 ps
CPU time 1425.89 seconds
Started Mar 24 01:03:21 PM PDT 24
Finished Mar 24 01:27:07 PM PDT 24
Peak memory 236884 kb
Host smart-f060905e-cac4-47c4-ab43-d1963ac57f32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117955161 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3117955161
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.1667555036
Short name T467
Test name
Test status
Simulation time 526327713 ps
CPU time 1.18 seconds
Started Mar 24 01:03:23 PM PDT 24
Finished Mar 24 01:03:26 PM PDT 24
Peak memory 198948 kb
Host smart-b6e33906-6d33-4da3-9563-5efa0ca36ef3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667555036 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.1667555036
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.775834932
Short name T127
Test name
Test status
Simulation time 26990397350 ps
CPU time 481.95 seconds
Started Mar 24 01:03:23 PM PDT 24
Finished Mar 24 01:11:27 PM PDT 24
Peak memory 200032 kb
Host smart-9fee7989-6f64-4b84-8ba6-12851aeebd81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775834932 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.775834932
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.139610677
Short name T344
Test name
Test status
Simulation time 7699051964 ps
CPU time 85.62 seconds
Started Mar 24 01:03:23 PM PDT 24
Finished Mar 24 01:04:51 PM PDT 24
Peak memory 200076 kb
Host smart-fa3d0287-834c-48e4-b20d-b13643e90d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139610677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.139610677
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1464288990
Short name T16
Test name
Test status
Simulation time 13460774 ps
CPU time 0.57 seconds
Started Mar 24 01:03:20 PM PDT 24
Finished Mar 24 01:03:21 PM PDT 24
Peak memory 195544 kb
Host smart-2d3884f1-9c52-4fc5-9ec3-ce4482f68388
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464288990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1464288990
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1854424056
Short name T51
Test name
Test status
Simulation time 992181119 ps
CPU time 9.07 seconds
Started Mar 24 01:03:21 PM PDT 24
Finished Mar 24 01:03:33 PM PDT 24
Peak memory 208168 kb
Host smart-2276c631-6e8f-40da-9753-489554cf110a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1854424056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1854424056
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3855769795
Short name T441
Test name
Test status
Simulation time 699190279 ps
CPU time 34.62 seconds
Started Mar 24 01:03:19 PM PDT 24
Finished Mar 24 01:03:55 PM PDT 24
Peak memory 199940 kb
Host smart-a1c4a183-9f43-451b-b22a-3e0393919133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855769795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3855769795
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.3896057637
Short name T303
Test name
Test status
Simulation time 3839995103 ps
CPU time 114.37 seconds
Started Mar 24 01:03:21 PM PDT 24
Finished Mar 24 01:05:19 PM PDT 24
Peak memory 200112 kb
Host smart-7b6ddf9c-3d88-41a6-8559-5039e738e5c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3896057637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.3896057637
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.380924739
Short name T408
Test name
Test status
Simulation time 1811868364 ps
CPU time 25.52 seconds
Started Mar 24 01:03:22 PM PDT 24
Finished Mar 24 01:03:50 PM PDT 24
Peak memory 199996 kb
Host smart-4eb4de2b-01fd-4d47-968b-69e1ef0b2d3a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380924739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.380924739
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.18494687
Short name T515
Test name
Test status
Simulation time 17988597893 ps
CPU time 135.63 seconds
Started Mar 24 01:03:24 PM PDT 24
Finished Mar 24 01:05:41 PM PDT 24
Peak memory 200048 kb
Host smart-162df65b-751c-4f74-acf6-479465c2bcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18494687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.18494687
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.482583921
Short name T40
Test name
Test status
Simulation time 426219214 ps
CPU time 5.49 seconds
Started Mar 24 01:03:23 PM PDT 24
Finished Mar 24 01:03:30 PM PDT 24
Peak memory 199844 kb
Host smart-63e2991e-b463-4770-839f-11562424c234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482583921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.482583921
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1872667900
Short name T244
Test name
Test status
Simulation time 147303597644 ps
CPU time 540.5 seconds
Started Mar 24 01:03:22 PM PDT 24
Finished Mar 24 01:12:25 PM PDT 24
Peak memory 224884 kb
Host smart-6e156d61-7e0a-4f24-b914-53efd727c483
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872667900 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1872667900
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.148369747
Short name T507
Test name
Test status
Simulation time 54893056 ps
CPU time 1.13 seconds
Started Mar 24 01:03:20 PM PDT 24
Finished Mar 24 01:03:22 PM PDT 24
Peak memory 199988 kb
Host smart-95a339de-d952-41b2-a749-bee1a9eeff4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148369747 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_hmac_vectors.148369747
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.4115042787
Short name T39
Test name
Test status
Simulation time 144585367978 ps
CPU time 476 seconds
Started Mar 24 01:03:24 PM PDT 24
Finished Mar 24 01:11:22 PM PDT 24
Peak memory 199844 kb
Host smart-57c8cada-d6ca-4825-b009-8e9b3d588bc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115042787 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.4115042787
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.993032975
Short name T459
Test name
Test status
Simulation time 7019331268 ps
CPU time 75.33 seconds
Started Mar 24 01:03:24 PM PDT 24
Finished Mar 24 01:04:41 PM PDT 24
Peak memory 199904 kb
Host smart-00ec10d2-ca72-4c65-86c6-baa173b87218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993032975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.993032975
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1760992255
Short name T18
Test name
Test status
Simulation time 34047853 ps
CPU time 0.57 seconds
Started Mar 24 01:03:25 PM PDT 24
Finished Mar 24 01:03:26 PM PDT 24
Peak memory 195416 kb
Host smart-f9c9ee02-694c-4e0d-a1af-ecee21dae1de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760992255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1760992255
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.4252291332
Short name T286
Test name
Test status
Simulation time 4144603614 ps
CPU time 40.6 seconds
Started Mar 24 01:03:21 PM PDT 24
Finished Mar 24 01:04:02 PM PDT 24
Peak memory 224164 kb
Host smart-df246353-b97e-4ed2-ae0f-7b2932d9635b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4252291332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.4252291332
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.2590251820
Short name T178
Test name
Test status
Simulation time 4764562171 ps
CPU time 15.85 seconds
Started Mar 24 01:03:24 PM PDT 24
Finished Mar 24 01:03:41 PM PDT 24
Peak memory 200020 kb
Host smart-c07520a0-5273-4577-99f1-be87fffa514c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590251820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2590251820
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1822672167
Short name T443
Test name
Test status
Simulation time 309552827 ps
CPU time 12.1 seconds
Started Mar 24 01:03:22 PM PDT 24
Finished Mar 24 01:03:37 PM PDT 24
Peak memory 200048 kb
Host smart-131b27cb-f75a-4a5e-85bc-0de7e9fa8d35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1822672167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1822672167
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.88411123
Short name T348
Test name
Test status
Simulation time 5666729490 ps
CPU time 18.07 seconds
Started Mar 24 01:03:22 PM PDT 24
Finished Mar 24 01:03:43 PM PDT 24
Peak memory 199984 kb
Host smart-68d9cf2c-f554-472b-b04c-ca7d9c471392
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88411123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.88411123
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.810721223
Short name T6
Test name
Test status
Simulation time 291701808 ps
CPU time 17.24 seconds
Started Mar 24 01:03:22 PM PDT 24
Finished Mar 24 01:03:42 PM PDT 24
Peak memory 200036 kb
Host smart-fc7c9a03-6947-4a4e-90d4-d9601cfd4724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810721223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.810721223
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2405747946
Short name T552
Test name
Test status
Simulation time 152469735 ps
CPU time 2.73 seconds
Started Mar 24 01:03:24 PM PDT 24
Finished Mar 24 01:03:28 PM PDT 24
Peak memory 199960 kb
Host smart-f56a3dbd-1495-4324-9286-95a9037cb5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405747946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2405747946
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2819324103
Short name T146
Test name
Test status
Simulation time 498127039 ps
CPU time 21.56 seconds
Started Mar 24 01:03:23 PM PDT 24
Finished Mar 24 01:03:47 PM PDT 24
Peak memory 199988 kb
Host smart-daf2ee60-be62-42f8-b45e-490401eecf97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819324103 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2819324103
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_stress_all_with_rand_reset.3644413286
Short name T65
Test name
Test status
Simulation time 3245761045 ps
CPU time 56.47 seconds
Started Mar 24 01:03:27 PM PDT 24
Finished Mar 24 01:04:24 PM PDT 24
Peak memory 216388 kb
Host smart-c014e7b1-6beb-45c1-a9cc-01bf6ec1c364
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3644413286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all_with_rand_reset.3644413286
Directory /workspace/44.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.1426451606
Short name T197
Test name
Test status
Simulation time 319855862 ps
CPU time 1.22 seconds
Started Mar 24 01:03:21 PM PDT 24
Finished Mar 24 01:03:22 PM PDT 24
Peak memory 199520 kb
Host smart-dbc59e37-972d-4386-b999-e81d4c6575f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426451606 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.1426451606
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.1039475156
Short name T167
Test name
Test status
Simulation time 8985087155 ps
CPU time 474.34 seconds
Started Mar 24 01:03:21 PM PDT 24
Finished Mar 24 01:11:15 PM PDT 24
Peak memory 199376 kb
Host smart-4fff113a-9669-485c-a1a9-d82eb7af9f54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039475156 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.1039475156
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.4263071552
Short name T425
Test name
Test status
Simulation time 2363594481 ps
CPU time 26.15 seconds
Started Mar 24 01:03:24 PM PDT 24
Finished Mar 24 01:03:51 PM PDT 24
Peak memory 200012 kb
Host smart-d4b40b3c-a89b-4b5f-ad4c-64757e9ba9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263071552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.4263071552
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.784201505
Short name T184
Test name
Test status
Simulation time 24363126 ps
CPU time 0.57 seconds
Started Mar 24 01:03:28 PM PDT 24
Finished Mar 24 01:03:29 PM PDT 24
Peak memory 195612 kb
Host smart-5ee3ceb6-b0fd-4e41-8339-0c24a21d46f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784201505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.784201505
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3101239966
Short name T154
Test name
Test status
Simulation time 641821598 ps
CPU time 20.9 seconds
Started Mar 24 01:03:26 PM PDT 24
Finished Mar 24 01:03:47 PM PDT 24
Peak memory 208172 kb
Host smart-be8cc101-aee1-45a3-a1e2-63c8bd00c668
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3101239966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3101239966
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2689427478
Short name T382
Test name
Test status
Simulation time 2420343282 ps
CPU time 48.57 seconds
Started Mar 24 01:03:26 PM PDT 24
Finished Mar 24 01:04:16 PM PDT 24
Peak memory 200076 kb
Host smart-9c021fd7-0800-4b2c-b798-0c04f3812abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689427478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2689427478
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1896797641
Short name T506
Test name
Test status
Simulation time 997297253 ps
CPU time 15.71 seconds
Started Mar 24 01:03:27 PM PDT 24
Finished Mar 24 01:03:43 PM PDT 24
Peak memory 200016 kb
Host smart-6eb9094d-1f78-4d38-88e3-ac5559697461
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1896797641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1896797641
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.708838048
Short name T571
Test name
Test status
Simulation time 3440832619 ps
CPU time 87.49 seconds
Started Mar 24 01:03:27 PM PDT 24
Finished Mar 24 01:04:55 PM PDT 24
Peak memory 199916 kb
Host smart-ecd66adb-fb9b-4621-a710-c9666f4bfc12
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708838048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.708838048
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.2271999659
Short name T595
Test name
Test status
Simulation time 5477132352 ps
CPU time 62.93 seconds
Started Mar 24 01:03:26 PM PDT 24
Finished Mar 24 01:04:29 PM PDT 24
Peak memory 199920 kb
Host smart-4300b801-55e5-4f7b-b600-fe6c92d9f96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271999659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.2271999659
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1056951629
Short name T191
Test name
Test status
Simulation time 389820551 ps
CPU time 3.65 seconds
Started Mar 24 01:03:26 PM PDT 24
Finished Mar 24 01:03:31 PM PDT 24
Peak memory 200012 kb
Host smart-65aa72a0-46d6-43ee-ba89-e5f1b843db76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056951629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1056951629
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.103033547
Short name T90
Test name
Test status
Simulation time 57478106970 ps
CPU time 771.07 seconds
Started Mar 24 01:03:27 PM PDT 24
Finished Mar 24 01:16:18 PM PDT 24
Peak memory 200048 kb
Host smart-6fb3a475-8c4b-4cf5-8fe4-17fce737f536
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103033547 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.103033547
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.675452720
Short name T285
Test name
Test status
Simulation time 40284981 ps
CPU time 1.05 seconds
Started Mar 24 01:03:25 PM PDT 24
Finished Mar 24 01:03:27 PM PDT 24
Peak memory 198520 kb
Host smart-ec0e6809-6920-4492-860e-3fbe00dd0a91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675452720 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_hmac_vectors.675452720
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.3026552996
Short name T159
Test name
Test status
Simulation time 41395891415 ps
CPU time 518.13 seconds
Started Mar 24 01:03:27 PM PDT 24
Finished Mar 24 01:12:06 PM PDT 24
Peak memory 200000 kb
Host smart-bec9ed62-e141-4641-ab14-7e175a83686a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026552996 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.3026552996
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3332416704
Short name T434
Test name
Test status
Simulation time 23415963872 ps
CPU time 87.19 seconds
Started Mar 24 01:03:28 PM PDT 24
Finished Mar 24 01:04:56 PM PDT 24
Peak memory 200096 kb
Host smart-b85132c7-0d08-4b4b-a9d8-26a9a46e14c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332416704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3332416704
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3771469417
Short name T224
Test name
Test status
Simulation time 42308492 ps
CPU time 0.66 seconds
Started Mar 24 01:03:31 PM PDT 24
Finished Mar 24 01:03:31 PM PDT 24
Peak memory 195552 kb
Host smart-4281436f-65e2-4276-9bd7-3c225256b0a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771469417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3771469417
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.2111763332
Short name T442
Test name
Test status
Simulation time 694180807 ps
CPU time 24.52 seconds
Started Mar 24 01:03:29 PM PDT 24
Finished Mar 24 01:03:53 PM PDT 24
Peak memory 208044 kb
Host smart-8177daa7-4ff0-4c73-9847-608a8cceeb87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2111763332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2111763332
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2742550023
Short name T365
Test name
Test status
Simulation time 28469260091 ps
CPU time 41.94 seconds
Started Mar 24 01:03:25 PM PDT 24
Finished Mar 24 01:04:07 PM PDT 24
Peak memory 199976 kb
Host smart-e6851ea1-b5a3-4c53-8468-74acf05a970e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742550023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2742550023
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.994581738
Short name T214
Test name
Test status
Simulation time 4560277468 ps
CPU time 66.08 seconds
Started Mar 24 01:03:27 PM PDT 24
Finished Mar 24 01:04:33 PM PDT 24
Peak memory 200108 kb
Host smart-fb603fed-093b-44f0-9166-962378cf8cbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=994581738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.994581738
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2801441499
Short name T163
Test name
Test status
Simulation time 1154847104 ps
CPU time 15.79 seconds
Started Mar 24 01:03:26 PM PDT 24
Finished Mar 24 01:03:43 PM PDT 24
Peak memory 200000 kb
Host smart-ad71bed7-3a73-4505-972b-8ebabf94ab14
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801441499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2801441499
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.818977093
Short name T151
Test name
Test status
Simulation time 2253375173 ps
CPU time 131.68 seconds
Started Mar 24 01:03:29 PM PDT 24
Finished Mar 24 01:05:41 PM PDT 24
Peak memory 200328 kb
Host smart-f9e3976c-da79-4a5f-968f-024b98b6ecee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818977093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.818977093
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.850941495
Short name T195
Test name
Test status
Simulation time 562923979 ps
CPU time 3.29 seconds
Started Mar 24 01:03:28 PM PDT 24
Finished Mar 24 01:03:32 PM PDT 24
Peak memory 200240 kb
Host smart-fedc68e8-d8b5-4750-9bf2-abafdea75d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850941495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.850941495
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.4294178057
Short name T333
Test name
Test status
Simulation time 16313548734 ps
CPU time 56.48 seconds
Started Mar 24 01:03:32 PM PDT 24
Finished Mar 24 01:04:28 PM PDT 24
Peak memory 199916 kb
Host smart-3e994331-11d7-4ee3-ba34-8d304de4daca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294178057 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.4294178057
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.391837826
Short name T493
Test name
Test status
Simulation time 97746942 ps
CPU time 1.17 seconds
Started Mar 24 01:03:32 PM PDT 24
Finished Mar 24 01:03:33 PM PDT 24
Peak memory 198636 kb
Host smart-46b8de40-c306-4781-ba45-12be765c447d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391837826 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_test_hmac_vectors.391837826
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.3300056321
Short name T119
Test name
Test status
Simulation time 9883420095 ps
CPU time 479.74 seconds
Started Mar 24 01:03:30 PM PDT 24
Finished Mar 24 01:11:30 PM PDT 24
Peak memory 200044 kb
Host smart-2826b455-bbd2-4bf4-addf-36b45a2313b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300056321 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.3300056321
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.2857749573
Short name T36
Test name
Test status
Simulation time 7092504555 ps
CPU time 34.83 seconds
Started Mar 24 01:03:33 PM PDT 24
Finished Mar 24 01:04:07 PM PDT 24
Peak memory 200080 kb
Host smart-98105a5c-f2cb-4251-90db-95c6602c47cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857749573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2857749573
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2131048328
Short name T179
Test name
Test status
Simulation time 73825608 ps
CPU time 0.61 seconds
Started Mar 24 01:03:31 PM PDT 24
Finished Mar 24 01:03:32 PM PDT 24
Peak memory 195532 kb
Host smart-a4522314-8dd6-456d-bb68-2d5bd911d485
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131048328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2131048328
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2054441030
Short name T405
Test name
Test status
Simulation time 1074647271 ps
CPU time 9.69 seconds
Started Mar 24 01:03:31 PM PDT 24
Finished Mar 24 01:03:41 PM PDT 24
Peak memory 199936 kb
Host smart-2efb9bc9-b27f-4408-978c-a051abdde314
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2054441030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2054441030
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1470892788
Short name T367
Test name
Test status
Simulation time 375833194 ps
CPU time 8.78 seconds
Started Mar 24 01:03:33 PM PDT 24
Finished Mar 24 01:03:42 PM PDT 24
Peak memory 200012 kb
Host smart-a2738f0c-fec4-453d-9b40-700b5724a8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470892788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1470892788
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.3550649309
Short name T428
Test name
Test status
Simulation time 49056486492 ps
CPU time 149.88 seconds
Started Mar 24 01:03:30 PM PDT 24
Finished Mar 24 01:06:00 PM PDT 24
Peak memory 200008 kb
Host smart-0694b03b-5de7-49f4-b43e-19810a82e5d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3550649309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3550649309
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.3544939789
Short name T298
Test name
Test status
Simulation time 30174661 ps
CPU time 0.75 seconds
Started Mar 24 01:03:31 PM PDT 24
Finished Mar 24 01:03:32 PM PDT 24
Peak memory 196208 kb
Host smart-ec6f990d-9cec-4c7e-a276-7dbc203a8b75
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544939789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3544939789
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.605596683
Short name T431
Test name
Test status
Simulation time 1359931009 ps
CPU time 75.65 seconds
Started Mar 24 01:03:32 PM PDT 24
Finished Mar 24 01:04:48 PM PDT 24
Peak memory 199988 kb
Host smart-bb35cb27-6885-4052-ac5d-fa76afb8f8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605596683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.605596683
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.886494175
Short name T308
Test name
Test status
Simulation time 484414863 ps
CPU time 4.11 seconds
Started Mar 24 01:03:30 PM PDT 24
Finished Mar 24 01:03:34 PM PDT 24
Peak memory 199984 kb
Host smart-34c3ab27-8554-4035-a20e-94741a3e0072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886494175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.886494175
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.2434572525
Short name T564
Test name
Test status
Simulation time 7822003561 ps
CPU time 436.85 seconds
Started Mar 24 01:03:31 PM PDT 24
Finished Mar 24 01:10:48 PM PDT 24
Peak memory 200088 kb
Host smart-f6121c5c-b514-4260-8dfa-af944ac62d42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434572525 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2434572525
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.1507779853
Short name T67
Test name
Test status
Simulation time 38172186 ps
CPU time 0.96 seconds
Started Mar 24 01:03:32 PM PDT 24
Finished Mar 24 01:03:33 PM PDT 24
Peak memory 198148 kb
Host smart-9e539eef-0d4f-46fe-aa2e-28c01a22e9e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507779853 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.1507779853
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.1674368401
Short name T82
Test name
Test status
Simulation time 332946025485 ps
CPU time 408.55 seconds
Started Mar 24 01:03:33 PM PDT 24
Finished Mar 24 01:10:23 PM PDT 24
Peak memory 199868 kb
Host smart-2ffbe4da-0bd3-4f06-b59b-a0dc9ef4b606
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674368401 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.1674368401
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.794753461
Short name T381
Test name
Test status
Simulation time 109498459271 ps
CPU time 102.52 seconds
Started Mar 24 01:03:32 PM PDT 24
Finished Mar 24 01:05:15 PM PDT 24
Peak memory 200040 kb
Host smart-17864564-d3d6-48f3-8e0f-f68291e55f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794753461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.794753461
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.461769168
Short name T478
Test name
Test status
Simulation time 37882513 ps
CPU time 0.65 seconds
Started Mar 24 01:03:44 PM PDT 24
Finished Mar 24 01:03:44 PM PDT 24
Peak memory 195612 kb
Host smart-412bddc3-8a34-497d-9936-d7f8c3530c54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461769168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.461769168
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.1866773565
Short name T454
Test name
Test status
Simulation time 913685041 ps
CPU time 37.59 seconds
Started Mar 24 01:03:37 PM PDT 24
Finished Mar 24 01:04:15 PM PDT 24
Peak memory 230764 kb
Host smart-a118a962-4474-495c-8843-1dc19489679c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1866773565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.1866773565
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.4096313528
Short name T215
Test name
Test status
Simulation time 4958047964 ps
CPU time 24.77 seconds
Started Mar 24 01:03:40 PM PDT 24
Finished Mar 24 01:04:04 PM PDT 24
Peak memory 200008 kb
Host smart-9e92c9ab-bdb0-4b53-8e01-066f069b8ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096313528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.4096313528
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.239413867
Short name T169
Test name
Test status
Simulation time 6412550741 ps
CPU time 85.02 seconds
Started Mar 24 01:03:38 PM PDT 24
Finished Mar 24 01:05:04 PM PDT 24
Peak memory 200012 kb
Host smart-24d56ed2-76c5-4752-9d58-be91d0761cbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=239413867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.239413867
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2399697274
Short name T198
Test name
Test status
Simulation time 3928842665 ps
CPU time 76.27 seconds
Started Mar 24 01:03:36 PM PDT 24
Finished Mar 24 01:04:53 PM PDT 24
Peak memory 200072 kb
Host smart-e13d67cc-ce19-4b50-bb13-e0f3320e5464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399697274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2399697274
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1653265707
Short name T221
Test name
Test status
Simulation time 171448714 ps
CPU time 2.99 seconds
Started Mar 24 01:03:37 PM PDT 24
Finished Mar 24 01:03:41 PM PDT 24
Peak memory 199892 kb
Host smart-4ce61482-7484-4603-81c3-9cc2d3821ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653265707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1653265707
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.1422158105
Short name T48
Test name
Test status
Simulation time 90413493845 ps
CPU time 1199.82 seconds
Started Mar 24 01:03:38 PM PDT 24
Finished Mar 24 01:23:38 PM PDT 24
Peak memory 216504 kb
Host smart-1171e8b5-821b-4096-a992-c12da7fe6d37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422158105 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1422158105
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.3648312781
Short name T35
Test name
Test status
Simulation time 320049136 ps
CPU time 1.27 seconds
Started Mar 24 01:03:37 PM PDT 24
Finished Mar 24 01:03:39 PM PDT 24
Peak memory 199968 kb
Host smart-393fd178-71f0-4c23-ade4-7f1585292bcd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648312781 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.3648312781
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.3321001338
Short name T129
Test name
Test status
Simulation time 65828137129 ps
CPU time 530.14 seconds
Started Mar 24 01:03:36 PM PDT 24
Finished Mar 24 01:12:27 PM PDT 24
Peak memory 199992 kb
Host smart-a06050ee-be3d-47f1-908d-56c36f2f4e14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321001338 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.3321001338
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.773808753
Short name T422
Test name
Test status
Simulation time 5795469241 ps
CPU time 60.21 seconds
Started Mar 24 01:03:37 PM PDT 24
Finished Mar 24 01:04:38 PM PDT 24
Peak memory 200044 kb
Host smart-f75439b1-8536-4011-be3e-4705b3f3dc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773808753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.773808753
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2090442201
Short name T458
Test name
Test status
Simulation time 16059420 ps
CPU time 0.59 seconds
Started Mar 24 01:03:43 PM PDT 24
Finished Mar 24 01:03:44 PM PDT 24
Peak memory 195544 kb
Host smart-67d5fb90-4db2-4d8f-a4ba-f297b03913f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090442201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2090442201
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1507548244
Short name T238
Test name
Test status
Simulation time 4536097005 ps
CPU time 46.86 seconds
Started Mar 24 01:03:43 PM PDT 24
Finished Mar 24 01:04:30 PM PDT 24
Peak memory 224636 kb
Host smart-362ebea7-9a88-4ab9-bb42-b100b04a3f2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1507548244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1507548244
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.803105740
Short name T585
Test name
Test status
Simulation time 1781013300 ps
CPU time 18.72 seconds
Started Mar 24 01:03:44 PM PDT 24
Finished Mar 24 01:04:03 PM PDT 24
Peak memory 200048 kb
Host smart-bc99a63d-57dd-4657-9156-1c3177bd466e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803105740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.803105740
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3523289342
Short name T479
Test name
Test status
Simulation time 8544420146 ps
CPU time 130.6 seconds
Started Mar 24 01:03:43 PM PDT 24
Finished Mar 24 01:05:54 PM PDT 24
Peak memory 200080 kb
Host smart-d057b333-7ce1-4146-b9e7-e8654b2332d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3523289342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3523289342
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.658531560
Short name T366
Test name
Test status
Simulation time 9682701528 ps
CPU time 122.71 seconds
Started Mar 24 01:03:41 PM PDT 24
Finished Mar 24 01:05:44 PM PDT 24
Peak memory 199980 kb
Host smart-51b5c130-b426-4abd-b520-a2a70a616791
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658531560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.658531560
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.1966680121
Short name T401
Test name
Test status
Simulation time 8007400162 ps
CPU time 30.19 seconds
Started Mar 24 01:03:42 PM PDT 24
Finished Mar 24 01:04:12 PM PDT 24
Peak memory 200060 kb
Host smart-50e38271-d1c7-47c4-b627-134e11a49d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966680121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1966680121
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.1962982381
Short name T217
Test name
Test status
Simulation time 340027820 ps
CPU time 4.01 seconds
Started Mar 24 01:03:42 PM PDT 24
Finished Mar 24 01:03:46 PM PDT 24
Peak memory 199980 kb
Host smart-0b03ba7f-b049-4a26-af72-9717e7ff80b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962982381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1962982381
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2126016532
Short name T3
Test name
Test status
Simulation time 13498922687 ps
CPU time 245.32 seconds
Started Mar 24 01:03:45 PM PDT 24
Finished Mar 24 01:07:51 PM PDT 24
Peak memory 200012 kb
Host smart-06bae4fa-eb7a-4104-a413-f6065637dff0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126016532 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2126016532
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.3007184556
Short name T376
Test name
Test status
Simulation time 82804414 ps
CPU time 1.43 seconds
Started Mar 24 01:03:43 PM PDT 24
Finished Mar 24 01:03:44 PM PDT 24
Peak memory 199788 kb
Host smart-54c45af3-8d2a-4da9-83c4-2bc55436d0c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007184556 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.3007184556
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.714832411
Short name T477
Test name
Test status
Simulation time 44676623086 ps
CPU time 468.85 seconds
Started Mar 24 01:03:42 PM PDT 24
Finished Mar 24 01:11:31 PM PDT 24
Peak memory 199968 kb
Host smart-954d39fd-a8d2-4117-b192-4c9273706695
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714832411 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.714832411
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.2602755847
Short name T230
Test name
Test status
Simulation time 5948605008 ps
CPU time 34.82 seconds
Started Mar 24 01:03:40 PM PDT 24
Finished Mar 24 01:04:15 PM PDT 24
Peak memory 200088 kb
Host smart-aee00b00-5e90-47da-ac0a-8392c1651496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602755847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.2602755847
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1199217044
Short name T497
Test name
Test status
Simulation time 46294448 ps
CPU time 0.57 seconds
Started Mar 24 01:01:41 PM PDT 24
Finished Mar 24 01:01:42 PM PDT 24
Peak memory 194528 kb
Host smart-b2af65db-4408-4d8e-85fc-f7b985e39298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199217044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1199217044
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.3595201609
Short name T53
Test name
Test status
Simulation time 84794776 ps
CPU time 3.1 seconds
Started Mar 24 01:01:36 PM PDT 24
Finished Mar 24 01:01:39 PM PDT 24
Peak memory 199976 kb
Host smart-7de9af74-b0dd-418b-bf91-d7d7d08eb2f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3595201609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3595201609
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.430437021
Short name T487
Test name
Test status
Simulation time 160781258 ps
CPU time 3.6 seconds
Started Mar 24 01:01:36 PM PDT 24
Finished Mar 24 01:01:40 PM PDT 24
Peak memory 200000 kb
Host smart-73c21082-288c-44dd-8df3-1d693289f2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430437021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.430437021
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1225537908
Short name T42
Test name
Test status
Simulation time 14811918046 ps
CPU time 154.06 seconds
Started Mar 24 01:01:36 PM PDT 24
Finished Mar 24 01:04:10 PM PDT 24
Peak memory 200052 kb
Host smart-3faa21f3-d398-4c1e-9579-46074002cd72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1225537908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1225537908
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1000006685
Short name T446
Test name
Test status
Simulation time 352052565 ps
CPU time 17.9 seconds
Started Mar 24 01:01:37 PM PDT 24
Finished Mar 24 01:01:55 PM PDT 24
Peak memory 199964 kb
Host smart-1fb4f0ef-d218-4a5e-add1-a58bfcbcca9d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000006685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1000006685
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.222090244
Short name T311
Test name
Test status
Simulation time 7868950022 ps
CPU time 77.56 seconds
Started Mar 24 01:01:36 PM PDT 24
Finished Mar 24 01:02:54 PM PDT 24
Peak memory 200096 kb
Host smart-38df0393-b152-4b45-8658-5616f6fba62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222090244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.222090244
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1094224135
Short name T354
Test name
Test status
Simulation time 351468953 ps
CPU time 3.62 seconds
Started Mar 24 01:01:35 PM PDT 24
Finished Mar 24 01:01:39 PM PDT 24
Peak memory 200012 kb
Host smart-b3895590-781f-47d3-9b4a-2f9e7a0236b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094224135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1094224135
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.4199009008
Short name T73
Test name
Test status
Simulation time 381131300477 ps
CPU time 1298.24 seconds
Started Mar 24 01:01:41 PM PDT 24
Finished Mar 24 01:23:19 PM PDT 24
Peak memory 200088 kb
Host smart-a7723d12-7c10-4746-b4f7-f00c90d2d146
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199009008 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.4199009008
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.2822671489
Short name T256
Test name
Test status
Simulation time 92265489 ps
CPU time 1.42 seconds
Started Mar 24 01:01:42 PM PDT 24
Finished Mar 24 01:01:44 PM PDT 24
Peak memory 199940 kb
Host smart-2fde8f55-8a42-4e25-9d8a-8e93e1f5d7ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822671489 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.2822671489
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.3712687664
Short name T437
Test name
Test status
Simulation time 105962804806 ps
CPU time 463.5 seconds
Started Mar 24 01:01:36 PM PDT 24
Finished Mar 24 01:09:19 PM PDT 24
Peak memory 199992 kb
Host smart-dc6b8cdc-a2b3-40a5-a3cb-21c42f7eb584
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712687664 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.3712687664
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.4039416908
Short name T261
Test name
Test status
Simulation time 1298471692 ps
CPU time 17.41 seconds
Started Mar 24 01:01:35 PM PDT 24
Finished Mar 24 01:01:53 PM PDT 24
Peak memory 200020 kb
Host smart-5e7fd8ce-97c1-498a-a849-2f163a90d65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039416908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.4039416908
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.486969589
Short name T338
Test name
Test status
Simulation time 22309390 ps
CPU time 0.6 seconds
Started Mar 24 01:01:43 PM PDT 24
Finished Mar 24 01:01:44 PM PDT 24
Peak memory 195556 kb
Host smart-517cdcdb-070d-400a-abd8-005cf5626d1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486969589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.486969589
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3718803999
Short name T342
Test name
Test status
Simulation time 1150261267 ps
CPU time 51.03 seconds
Started Mar 24 01:01:41 PM PDT 24
Finished Mar 24 01:02:32 PM PDT 24
Peak memory 229720 kb
Host smart-e1c8df97-c95c-4da5-8883-c8efdd5bee99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3718803999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3718803999
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.275000773
Short name T519
Test name
Test status
Simulation time 19892652754 ps
CPU time 74.02 seconds
Started Mar 24 01:01:40 PM PDT 24
Finished Mar 24 01:02:54 PM PDT 24
Peak memory 199968 kb
Host smart-75138d9b-df19-4e67-a644-319e388f03b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275000773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.275000773
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2872443180
Short name T83
Test name
Test status
Simulation time 5241658862 ps
CPU time 18.88 seconds
Started Mar 24 01:01:41 PM PDT 24
Finished Mar 24 01:02:00 PM PDT 24
Peak memory 200092 kb
Host smart-4f65ec20-bc11-41ba-b0e5-105cffe670c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2872443180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2872443180
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.2424814041
Short name T291
Test name
Test status
Simulation time 100473985970 ps
CPU time 138.53 seconds
Started Mar 24 01:01:41 PM PDT 24
Finished Mar 24 01:04:00 PM PDT 24
Peak memory 200084 kb
Host smart-1fa934ff-7f69-4da1-9d71-007a3b51bec2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424814041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2424814041
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1135981990
Short name T175
Test name
Test status
Simulation time 182513122 ps
CPU time 3.8 seconds
Started Mar 24 01:01:42 PM PDT 24
Finished Mar 24 01:01:46 PM PDT 24
Peak memory 199848 kb
Host smart-c9f004b5-b430-4f2a-bf0f-1e952bd8d146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135981990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1135981990
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3786827161
Short name T427
Test name
Test status
Simulation time 70950393 ps
CPU time 1.2 seconds
Started Mar 24 01:01:40 PM PDT 24
Finished Mar 24 01:01:41 PM PDT 24
Peak memory 200008 kb
Host smart-620236ed-15e2-4a49-84ac-94c914799b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786827161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3786827161
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.813799896
Short name T37
Test name
Test status
Simulation time 12538808147 ps
CPU time 702.3 seconds
Started Mar 24 01:01:41 PM PDT 24
Finished Mar 24 01:13:24 PM PDT 24
Peak memory 232340 kb
Host smart-c206459f-3c33-4b85-829b-093bc636cbff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813799896 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.813799896
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.3736180501
Short name T176
Test name
Test status
Simulation time 232836019 ps
CPU time 1.21 seconds
Started Mar 24 01:01:52 PM PDT 24
Finished Mar 24 01:01:53 PM PDT 24
Peak memory 199900 kb
Host smart-8b159cfb-4133-4ea9-b4e9-bdd37796fa1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736180501 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.3736180501
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.3475345373
Short name T223
Test name
Test status
Simulation time 129026435814 ps
CPU time 519.45 seconds
Started Mar 24 01:01:43 PM PDT 24
Finished Mar 24 01:10:22 PM PDT 24
Peak memory 199996 kb
Host smart-7e9f5462-3622-4ac8-b137-5038ea397b36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475345373 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.3475345373
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2566424637
Short name T362
Test name
Test status
Simulation time 240701176 ps
CPU time 9.24 seconds
Started Mar 24 01:01:43 PM PDT 24
Finished Mar 24 01:01:52 PM PDT 24
Peak memory 199988 kb
Host smart-b2211eab-d92f-4c31-b433-d649d02110c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566424637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2566424637
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/65.hmac_stress_all_with_rand_reset.2644855578
Short name T8
Test name
Test status
Simulation time 31086896235 ps
CPU time 1088.78 seconds
Started Mar 24 01:03:53 PM PDT 24
Finished Mar 24 01:22:02 PM PDT 24
Peak memory 248568 kb
Host smart-6ff23581-7fb9-4c8e-a4f6-d8649605caf8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2644855578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.hmac_stress_all_with_rand_reset.2644855578
Directory /workspace/65.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.hmac_stress_all_with_rand_reset.2272725799
Short name T24
Test name
Test status
Simulation time 27414929013 ps
CPU time 730.92 seconds
Started Mar 24 01:03:50 PM PDT 24
Finished Mar 24 01:16:02 PM PDT 24
Peak memory 208364 kb
Host smart-10514e80-5984-42b7-ba5d-6744485bbe65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2272725799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.hmac_stress_all_with_rand_reset.2272725799
Directory /workspace/67.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.4162550045
Short name T390
Test name
Test status
Simulation time 46742396 ps
CPU time 0.55 seconds
Started Mar 24 01:01:48 PM PDT 24
Finished Mar 24 01:01:48 PM PDT 24
Peak memory 194528 kb
Host smart-83837059-05f1-4537-aaa4-e99f15ef0b4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162550045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.4162550045
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2628867143
Short name T500
Test name
Test status
Simulation time 528142891 ps
CPU time 5.27 seconds
Started Mar 24 01:01:40 PM PDT 24
Finished Mar 24 01:01:45 PM PDT 24
Peak memory 208200 kb
Host smart-5c6ea00b-1246-40c7-b03c-b690bba54502
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2628867143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2628867143
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.759907835
Short name T168
Test name
Test status
Simulation time 317362610 ps
CPU time 7.68 seconds
Started Mar 24 01:01:42 PM PDT 24
Finished Mar 24 01:01:50 PM PDT 24
Peak memory 199908 kb
Host smart-d72fe65e-ef49-4b73-9d3d-f0cd31263ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759907835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.759907835
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2864002989
Short name T334
Test name
Test status
Simulation time 17399199 ps
CPU time 0.71 seconds
Started Mar 24 01:01:41 PM PDT 24
Finished Mar 24 01:01:42 PM PDT 24
Peak memory 197248 kb
Host smart-fff56f82-b4e1-4107-87f3-3556755f6f94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2864002989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2864002989
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.3360688669
Short name T345
Test name
Test status
Simulation time 43121676028 ps
CPU time 128.25 seconds
Started Mar 24 01:01:52 PM PDT 24
Finished Mar 24 01:04:00 PM PDT 24
Peak memory 199860 kb
Host smart-f7067ccc-1dcc-42ae-97bb-a2bb4e00bfdc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360688669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3360688669
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.4276446815
Short name T353
Test name
Test status
Simulation time 17813704024 ps
CPU time 120.65 seconds
Started Mar 24 01:01:42 PM PDT 24
Finished Mar 24 01:03:43 PM PDT 24
Peak memory 200044 kb
Host smart-e0aae5fb-17b3-465f-877f-74b7484fb176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276446815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.4276446815
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.553895635
Short name T79
Test name
Test status
Simulation time 233650554 ps
CPU time 2.13 seconds
Started Mar 24 01:01:42 PM PDT 24
Finished Mar 24 01:01:44 PM PDT 24
Peak memory 199944 kb
Host smart-1fa5917a-8a32-421e-90cb-28197391dbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553895635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.553895635
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.531454546
Short name T327
Test name
Test status
Simulation time 129461830842 ps
CPU time 1761.29 seconds
Started Mar 24 01:01:51 PM PDT 24
Finished Mar 24 01:31:12 PM PDT 24
Peak memory 208272 kb
Host smart-0cdf31a3-f33a-4362-94cf-c93601ea5d53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531454546 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.531454546
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.3311936686
Short name T187
Test name
Test status
Simulation time 114288346 ps
CPU time 1.03 seconds
Started Mar 24 01:01:43 PM PDT 24
Finished Mar 24 01:01:44 PM PDT 24
Peak memory 199496 kb
Host smart-1b5747e7-34ef-48ba-ad5c-2b34e8616eba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311936686 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.3311936686
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.2298450866
Short name T539
Test name
Test status
Simulation time 106957975652 ps
CPU time 476.35 seconds
Started Mar 24 01:01:43 PM PDT 24
Finished Mar 24 01:09:40 PM PDT 24
Peak memory 200016 kb
Host smart-a74b6247-6b1b-406a-a446-1f6f8cf0373d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298450866 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.2298450866
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1075183278
Short name T138
Test name
Test status
Simulation time 6072848513 ps
CPU time 31.91 seconds
Started Mar 24 01:01:41 PM PDT 24
Finished Mar 24 01:02:13 PM PDT 24
Peak memory 200088 kb
Host smart-18c1f90f-db17-4930-8a43-48d7e2ac2d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075183278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1075183278
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/78.hmac_stress_all_with_rand_reset.622438897
Short name T9
Test name
Test status
Simulation time 261353292183 ps
CPU time 1229.55 seconds
Started Mar 24 01:03:52 PM PDT 24
Finished Mar 24 01:24:22 PM PDT 24
Peak memory 224772 kb
Host smart-503641d1-d779-4b47-8c50-f8497f356a16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=622438897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.hmac_stress_all_with_rand_reset.622438897
Directory /workspace/78.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.969526804
Short name T445
Test name
Test status
Simulation time 53024979 ps
CPU time 0.59 seconds
Started Mar 24 01:01:50 PM PDT 24
Finished Mar 24 01:01:50 PM PDT 24
Peak memory 195528 kb
Host smart-f8772815-1694-486d-84ce-d8a8cc2d0c84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969526804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.969526804
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3950981706
Short name T466
Test name
Test status
Simulation time 5318171524 ps
CPU time 51.95 seconds
Started Mar 24 01:01:51 PM PDT 24
Finished Mar 24 01:02:43 PM PDT 24
Peak memory 231672 kb
Host smart-3ba1dbf1-915d-486f-9409-b998eadb643d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3950981706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3950981706
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.4041439388
Short name T388
Test name
Test status
Simulation time 376923842 ps
CPU time 18.57 seconds
Started Mar 24 01:01:48 PM PDT 24
Finished Mar 24 01:02:07 PM PDT 24
Peak memory 200012 kb
Host smart-7be27073-e026-4e08-8c1e-41bf4257b8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041439388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.4041439388
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.2142017056
Short name T586
Test name
Test status
Simulation time 4204531773 ps
CPU time 20.04 seconds
Started Mar 24 01:01:47 PM PDT 24
Finished Mar 24 01:02:08 PM PDT 24
Peak memory 200072 kb
Host smart-166b3ec2-c1ee-4af2-9d85-55adc6f91249
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2142017056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.2142017056
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.752765704
Short name T13
Test name
Test status
Simulation time 6430803420 ps
CPU time 80.76 seconds
Started Mar 24 01:01:48 PM PDT 24
Finished Mar 24 01:03:09 PM PDT 24
Peak memory 200092 kb
Host smart-16592c4a-daaa-4b9d-b628-e5396d9a78d5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752765704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.752765704
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3367364673
Short name T275
Test name
Test status
Simulation time 2302447318 ps
CPU time 32.3 seconds
Started Mar 24 01:01:49 PM PDT 24
Finished Mar 24 01:02:22 PM PDT 24
Peak memory 200132 kb
Host smart-1255e275-7aa3-491f-86fb-495fbe7342cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367364673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3367364673
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3461305248
Short name T461
Test name
Test status
Simulation time 2635053134 ps
CPU time 3.92 seconds
Started Mar 24 01:01:50 PM PDT 24
Finished Mar 24 01:01:54 PM PDT 24
Peak memory 200064 kb
Host smart-54e446bd-cab5-46eb-bb44-eda4a69195ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461305248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3461305248
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2198338201
Short name T355
Test name
Test status
Simulation time 18104963243 ps
CPU time 171.41 seconds
Started Mar 24 01:01:47 PM PDT 24
Finished Mar 24 01:04:39 PM PDT 24
Peak memory 226104 kb
Host smart-ba993834-fcd4-4244-bbc8-f8897406037c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198338201 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2198338201
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.4166846270
Short name T568
Test name
Test status
Simulation time 223727027 ps
CPU time 1.35 seconds
Started Mar 24 01:01:47 PM PDT 24
Finished Mar 24 01:01:49 PM PDT 24
Peak memory 199972 kb
Host smart-50bdc544-5e14-40e4-a4d8-bb0d2909ec82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166846270 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.4166846270
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.3642343375
Short name T273
Test name
Test status
Simulation time 103234683918 ps
CPU time 480.61 seconds
Started Mar 24 01:01:47 PM PDT 24
Finished Mar 24 01:09:48 PM PDT 24
Peak memory 199992 kb
Host smart-166cacc3-3eb4-4682-81df-a9bb799c5521
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642343375 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.3642343375
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.4200388413
Short name T210
Test name
Test status
Simulation time 8108633256 ps
CPU time 55.33 seconds
Started Mar 24 01:01:50 PM PDT 24
Finished Mar 24 01:02:46 PM PDT 24
Peak memory 200104 kb
Host smart-2ce10bd9-96c5-45da-9145-508473b5173a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200388413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.4200388413
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2092078487
Short name T562
Test name
Test status
Simulation time 35881750 ps
CPU time 0.61 seconds
Started Mar 24 01:01:52 PM PDT 24
Finished Mar 24 01:01:52 PM PDT 24
Peak memory 195212 kb
Host smart-f605c949-ebb0-43e0-b92a-758743d2dc44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092078487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2092078487
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1835608845
Short name T361
Test name
Test status
Simulation time 1774926035 ps
CPU time 30.59 seconds
Started Mar 24 01:01:49 PM PDT 24
Finished Mar 24 01:02:19 PM PDT 24
Peak memory 208156 kb
Host smart-33ea107b-0fa5-4a1f-a170-291c8f019fef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1835608845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1835608845
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2828851102
Short name T181
Test name
Test status
Simulation time 2014830378 ps
CPU time 26.1 seconds
Started Mar 24 01:01:50 PM PDT 24
Finished Mar 24 01:02:16 PM PDT 24
Peak memory 199976 kb
Host smart-7df4f524-0609-47cc-b4a5-8b9a3f03afc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828851102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2828851102
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3859106471
Short name T580
Test name
Test status
Simulation time 1905651114 ps
CPU time 103.56 seconds
Started Mar 24 01:01:51 PM PDT 24
Finished Mar 24 01:03:34 PM PDT 24
Peak memory 199836 kb
Host smart-a79d2793-d0bd-4046-89a5-6f99ef9de579
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3859106471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3859106471
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3639469116
Short name T370
Test name
Test status
Simulation time 1969199103 ps
CPU time 55.94 seconds
Started Mar 24 01:01:50 PM PDT 24
Finished Mar 24 01:02:47 PM PDT 24
Peak memory 199852 kb
Host smart-7788dde3-ef0f-4584-96f6-788c6a7eb546
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639469116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3639469116
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.669748581
Short name T426
Test name
Test status
Simulation time 8507337824 ps
CPU time 13.71 seconds
Started Mar 24 01:01:47 PM PDT 24
Finished Mar 24 01:02:01 PM PDT 24
Peak memory 200044 kb
Host smart-6a6f396e-8b4b-4109-8bc6-3b2502638887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669748581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.669748581
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.199818751
Short name T183
Test name
Test status
Simulation time 253442766 ps
CPU time 1.52 seconds
Started Mar 24 01:01:51 PM PDT 24
Finished Mar 24 01:01:52 PM PDT 24
Peak memory 199828 kb
Host smart-65aab774-2256-47aa-9fc1-3b806667c1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199818751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.199818751
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.176454554
Short name T545
Test name
Test status
Simulation time 12972302874 ps
CPU time 725.75 seconds
Started Mar 24 01:01:48 PM PDT 24
Finished Mar 24 01:13:55 PM PDT 24
Peak memory 222928 kb
Host smart-afd6fdf0-c4ef-4d2b-a077-df5758b360a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176454554 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.176454554
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.3782294823
Short name T139
Test name
Test status
Simulation time 666213371 ps
CPU time 0.94 seconds
Started Mar 24 01:01:48 PM PDT 24
Finished Mar 24 01:01:50 PM PDT 24
Peak memory 198276 kb
Host smart-56ce82fb-bfa2-41fe-a09f-5ddada278255
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782294823 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.3782294823
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.3019222300
Short name T346
Test name
Test status
Simulation time 26742268471 ps
CPU time 476.12 seconds
Started Mar 24 01:01:47 PM PDT 24
Finished Mar 24 01:09:44 PM PDT 24
Peak memory 200008 kb
Host smart-d50fbd1a-fdc4-4e8d-8c9a-5b3d3c2ce2ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019222300 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.3019222300
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3744464408
Short name T544
Test name
Test status
Simulation time 31246226103 ps
CPU time 94.25 seconds
Started Mar 24 01:01:49 PM PDT 24
Finished Mar 24 01:03:24 PM PDT 24
Peak memory 200044 kb
Host smart-ff2a3d46-0767-4d02-8bde-1e289b37fa90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744464408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3744464408
Directory /workspace/9.hmac_wipe_secret/latest

Test location /workspace/coverage/default/92.hmac_stress_all_with_rand_reset.1642056820
Short name T62
Test name
Test status
Simulation time 175942018435 ps
CPU time 1539.23 seconds
Started Mar 24 01:03:52 PM PDT 24
Finished Mar 24 01:29:31 PM PDT 24
Peak memory 249892 kb
Host smart-e61065e2-3e1f-45a8-946d-18c98b900c9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1642056820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.hmac_stress_all_with_rand_reset.1642056820
Directory /workspace/92.hmac_stress_all_with_rand_reset/latest
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