Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	11602589	1			T1	658		T2	6664		T3	58
all_values[1]	11602589	1			T1	658		T2	6664		T3	58
all_values[2]	11602589	1			T1	658		T2	6664		T3	58

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

99804

1

T1

17

T4

1022

T6

350

auto[1]

34707963

1

T1

1957

T2

19992

T3

174

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32917811

1

T1

1927

T2

14907

T3

162

auto[1]

1889956

1

T1

47

T2

5085

T3

12

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	40085	1			T1	15		T4	508		T27	515
all_values[0]	auto[0]	auto[1]	471	1			T1	2		T4	2		T27	2
all_values[0]	auto[1]	auto[0]	11522558	1			T1	596		T2	6660		T3	46
all_values[0]	auto[1]	auto[1]	39475	1			T1	45		T2	4		T3	12
all_values[1]	auto[0]	auto[0]	37076	1			T4	512		T19	4		T103	3
all_values[1]	auto[0]	auto[1]	184	1			T26	3		T17	1		T51	2
all_values[1]	auto[1]	auto[0]	11564988	1			T1	658		T2	6664		T3	58
all_values[1]	auto[1]	auto[1]	341	1			T19	1		T26	2		T17	2
all_values[2]	auto[0]	auto[0]	16564	1			T6	350		T19	10		T101	601
all_values[2]	auto[0]	auto[1]	5424	1			T26	3		T17	359		T121	1376
all_values[2]	auto[1]	auto[0]	9736540	1			T1	658		T2	1583		T3	58
all_values[2]	auto[1]	auto[1]	1844061	1			T2	5081		T8	8618		T19	2