Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5615398

1

T1

120

T2

1075

T3

467

auto[1]

2251126

1

T1

172

T2

499

T3

157

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2240081

1

T1

135

T2

1072

T3

471

auto[1]

5626443

1

T1

157

T2

502

T3

153

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4981245

1

T1

167

T2

500

T3

397

auto[1]

2885279

1

T1

125

T2

1074

T3

227

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	5137675	1			T1	192		T2	1438		T3	461
fifo_depth[1]	380848	1			T1	11		T2	72		T3	39
fifo_depth[2]	314341	1			T1	14		T2	42		T3	37
fifo_depth[3]	250661	1			T1	14		T2	14		T3	32
fifo_depth[4]	213555	1			T1	12		T2	6		T3	30
fifo_depth[5]	185989	1			T1	6		T2	1		T3	18
fifo_depth[6]	176505	1			T1	12		T2	1		T3	4
fifo_depth[7]	152889	1			T1	9		T3	1		T4	1015
fifo_depth[8]	140189	1			T1	5		T3	2		T4	854
fifo_depth[9]	94888	1			T1	1		T4	633		T5	2
fifo_depth[10]	72886	1			T1	5		T4	441		T5	3
fifo_depth[11]	44624	1			T1	4		T4	243		T5	3
fifo_depth[12]	45794	1			T1	7		T4	115		T5	3
fifo_depth[13]	23314	1			T4	56		T5	1		T27	32
fifo_depth[14]	29772	1			T4	31		T27	12		T100	8
fifo_depth[15]	19879	1			T4	6		T27	6		T100	2
fifo_depth[16]	84365	1			T4	3		T27	1		T101	4

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2838442

1

T1

100

T2

136

T3

163

auto[1]

5028082

1

T1

192

T2

1438

T3

461

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7756931

1

T1

292

T2

1574

T3

624

auto[1]

109593

1

T20

3

T21

1

T118

1022

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

178207

1

T3

47

T8

49

T7

179

auto[0]

auto[0]

auto[0]

auto[1]

177669

1

T3

13

T8

71

T7

260

auto[0]

auto[0]

auto[1]

auto[0]

934655

1

T3

48

T4

672

T6

111

auto[0]

auto[0]

auto[1]

auto[1]

189012

1

T2

32

T7

37

T4

1129

auto[0]

auto[1]

auto[0]

auto[0]

349297

1

T1

18

T2

104

T3

26

auto[0]

auto[1]

auto[0]

auto[1]

314430

1

T1

19

T3

29

T8

257

auto[0]

auto[1]

auto[1]

auto[0]

346960

1

T1

17

T7

67

T4

2351

auto[0]

auto[1]

auto[1]

auto[1]

348212

1

T1

46

T8

29

T7

126

auto[1]

auto[0]

auto[0]

auto[0]

230804

1

T1

33

T3

134

T8

296

auto[1]

auto[0]

auto[0]

auto[1]

229308

1

T1

59

T3

50

T8

2545

auto[1]

auto[0]

auto[1]

auto[0]

2801584

1

T1

46

T2

4

T3

105

auto[1]

auto[0]

auto[1]

auto[1]

240006

1

T1

29

T2

464

T8

73

auto[1]

auto[1]

auto[0]

auto[0]

373135

1

T1

4

T2

967

T3

107

auto[1]

auto[1]

auto[0]

auto[1]

387231

1

T1

2

T2

1

T3

65

auto[1]

auto[1]

auto[1]

auto[0]

400756

1

T1

2

T8

3

T7

933

auto[1]

auto[1]

auto[1]

auto[1]

365258

1

T1

17

T2

2

T8

296

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

395203

1

T1

33

T3

181

T8

345

auto[0]

auto[0]

auto[0]

auto[1]

394567

1

T1

59

T3

63

T8

2616

auto[0]

auto[0]

auto[1]

auto[0]

3723581

1

T1

46

T2

4

T3

153

auto[0]

auto[0]

auto[1]

auto[1]

414740

1

T1

29

T2

496

T8

73

auto[0]

auto[1]

auto[0]

auto[0]

710903

1

T1

22

T2

1071

T3

133

auto[0]

auto[1]

auto[0]

auto[1]

686973

1

T1

21

T2

1

T3

94

auto[0]

auto[1]

auto[1]

auto[0]

732304

1

T1

19

T8

3

T7

1000

auto[0]

auto[1]

auto[1]

auto[1]

698660

1

T1

63

T2

2

T8

325

auto[1]

auto[0]

auto[0]

auto[0]

13808

1

T21

1

T118

29

T122

867

auto[1]

auto[0]

auto[0]

auto[1]

12410

1

T118

69

T119

665

T53

1

auto[1]

auto[0]

auto[1]

auto[0]

12658

1

T118

53

T119

191

T120

475

auto[1]

auto[0]

auto[1]

auto[1]

14278

1

T20

3

T118

15

T119

25

auto[1]

auto[1]

auto[0]

auto[0]

11529

1

T118

48

T119

225

T120

26

auto[1]

auto[1]

auto[0]

auto[1]

14688

1

T118

336

T119

418

T120

55

auto[1]

auto[1]

auto[1]

auto[0]

15412

1

T118

68

T119

10

T120

136

auto[1]

auto[1]

auto[1]

auto[1]

14810

1

T118

404

T53

1

T122

116

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	244612	1			T1	33		T3	134		T8	296
fifo_depth[0]	auto[0]	auto[0]	auto[1]	241718	1			T1	59		T3	50		T8	2545
fifo_depth[0]	auto[0]	auto[1]	auto[0]	2814242	1			T1	46		T2	4		T3	105
fifo_depth[0]	auto[0]	auto[1]	auto[1]	254284	1			T1	29		T2	464		T8	73
fifo_depth[0]	auto[1]	auto[0]	auto[0]	384664	1			T1	4		T2	967		T3	107
fifo_depth[0]	auto[1]	auto[0]	auto[1]	401919	1			T1	2		T2	1		T3	65
fifo_depth[0]	auto[1]	auto[1]	auto[0]	416168	1			T1	2		T8	3		T7	933
fifo_depth[0]	auto[1]	auto[1]	auto[1]	380068	1			T1	17		T2	2		T8	296
fifo_depth[1]	auto[0]	auto[0]	auto[0]	16025	1			T3	14		T8	24		T7	114
fifo_depth[1]	auto[0]	auto[0]	auto[1]	16527	1			T3	2		T8	70		T7	173
fifo_depth[1]	auto[0]	auto[1]	auto[0]	185187	1			T3	9		T4	80		T6	60
fifo_depth[1]	auto[0]	auto[1]	auto[1]	17019	1			T2	21		T7	22		T4	128
fifo_depth[1]	auto[1]	auto[0]	auto[0]	37013	1			T1	4		T2	51		T3	8
fifo_depth[1]	auto[1]	auto[0]	auto[1]	35972	1			T1	3		T3	6		T8	120
fifo_depth[1]	auto[1]	auto[1]	auto[0]	37413	1			T1	2		T7	40		T4	240
fifo_depth[1]	auto[1]	auto[1]	auto[1]	35692	1			T1	2		T8	17		T7	79
fifo_depth[2]	auto[0]	auto[0]	auto[0]	12435	1			T3	11		T8	15		T7	50
fifo_depth[2]	auto[0]	auto[0]	auto[1]	12993	1			T3	1		T8	1		T7	55
fifo_depth[2]	auto[0]	auto[1]	auto[0]	151402	1			T3	8		T4	75		T6	33
fifo_depth[2]	auto[0]	auto[1]	auto[1]	13454	1			T2	9		T7	13		T4	147
fifo_depth[2]	auto[1]	auto[0]	auto[0]	31630	1			T1	2		T2	33		T3	11
fifo_depth[2]	auto[1]	auto[0]	auto[1]	30405	1			T1	4		T3	6		T8	67
fifo_depth[2]	auto[1]	auto[1]	auto[0]	31660	1			T1	1		T7	21		T4	249
fifo_depth[2]	auto[1]	auto[1]	auto[1]	30362	1			T1	7		T8	8		T7	38
fifo_depth[3]	auto[0]	auto[0]	auto[0]	9518	1			T3	10		T8	4		T7	13
fifo_depth[3]	auto[0]	auto[0]	auto[1]	10044	1			T3	1		T7	24		T28	8
fifo_depth[3]	auto[0]	auto[1]	auto[0]	116802	1			T3	12		T4	78		T6	14
fifo_depth[3]	auto[0]	auto[1]	auto[1]	9907	1			T2	1		T7	2		T4	133
fifo_depth[3]	auto[1]	auto[0]	auto[0]	27275	1			T1	2		T2	13		T3	5
fifo_depth[3]	auto[1]	auto[0]	auto[1]	24902	1			T1	1		T3	4		T8	52
fifo_depth[3]	auto[1]	auto[1]	auto[0]	26465	1			T1	1		T7	5		T4	272
fifo_depth[3]	auto[1]	auto[1]	auto[1]	25748	1			T1	10		T8	3		T7	7
fifo_depth[4]	auto[0]	auto[0]	auto[0]	8971	1			T3	7		T8	5		T7	2
fifo_depth[4]	auto[0]	auto[0]	auto[1]	9506	1			T3	7		T7	7		T28	5
fifo_depth[4]	auto[0]	auto[1]	auto[0]	86198	1			T3	9		T4	71		T6	2
fifo_depth[4]	auto[0]	auto[1]	auto[1]	9668	1			T2	1		T4	124		T6	5
fifo_depth[4]	auto[1]	auto[0]	auto[0]	25848	1			T1	2		T2	5		T3	2
fifo_depth[4]	auto[1]	auto[0]	auto[1]	23755	1			T1	2		T3	5		T8	15
fifo_depth[4]	auto[1]	auto[1]	auto[0]	24744	1			T1	4		T4	247		T5	6
fifo_depth[4]	auto[1]	auto[1]	auto[1]	24865	1			T1	4		T8	1		T7	2
fifo_depth[5]	auto[0]	auto[0]	auto[0]	7806	1			T3	4		T8	1		T4	52
fifo_depth[5]	auto[0]	auto[0]	auto[1]	8066	1			T3	2		T4	234		T6	2
fifo_depth[5]	auto[0]	auto[1]	auto[0]	70218	1			T3	6		T4	59		T6	1
fifo_depth[5]	auto[0]	auto[1]	auto[1]	8196	1			T4	128		T27	45		T19	28
fifo_depth[5]	auto[1]	auto[0]	auto[0]	24290	1			T2	1		T7	1		T4	144
fifo_depth[5]	auto[1]	auto[0]	auto[1]	21201	1			T3	6		T8	3		T28	4
fifo_depth[5]	auto[1]	auto[1]	auto[0]	23145	1			T1	4		T7	1		T4	268
fifo_depth[5]	auto[1]	auto[1]	auto[1]	23067	1			T1	2		T4	177		T5	3
fifo_depth[6]	auto[0]	auto[0]	auto[0]	7570	1			T3	1		T4	44		T27	36
fifo_depth[6]	auto[0]	auto[0]	auto[1]	7723	1			T7	1		T4	243		T27	119
fifo_depth[6]	auto[0]	auto[1]	auto[0]	61822	1			T3	2		T4	62		T6	1
fifo_depth[6]	auto[0]	auto[1]	auto[1]	8387	1			T4	114		T27	46		T19	14
fifo_depth[6]	auto[1]	auto[0]	auto[0]	23884	1			T1	1		T2	1		T4	134
fifo_depth[6]	auto[1]	auto[0]	auto[1]	21878	1			T1	3		T3	1		T28	1
fifo_depth[6]	auto[1]	auto[1]	auto[0]	22573	1			T1	1		T4	277		T5	2
fifo_depth[6]	auto[1]	auto[1]	auto[1]	22668	1			T1	7		T4	175		T5	1
fifo_depth[7]	auto[0]	auto[0]	auto[0]	6858	1			T4	47		T27	39		T19	9
fifo_depth[7]	auto[0]	auto[0]	auto[1]	7133	1			T4	215		T27	106		T19	13
fifo_depth[7]	auto[0]	auto[1]	auto[0]	48697	1			T3	1		T4	72		T27	54
fifo_depth[7]	auto[0]	auto[1]	auto[1]	7337	1			T4	111		T27	37		T19	9
fifo_depth[7]	auto[1]	auto[0]	auto[0]	21720	1			T1	2		T4	128		T27	104
fifo_depth[7]	auto[1]	auto[0]	auto[1]	19161	1			T1	1		T4	58		T27	79
fifo_depth[7]	auto[1]	auto[1]	auto[0]	21039	1			T1	1		T4	228		T5	5
fifo_depth[7]	auto[1]	auto[1]	auto[1]	20944	1			T1	5		T4	156		T5	1
fifo_depth[8]	auto[0]	auto[0]	auto[0]	7085	1			T4	33		T27	20		T19	17
fifo_depth[8]	auto[0]	auto[0]	auto[1]	7098	1			T4	163		T27	101		T19	4
fifo_depth[8]	auto[0]	auto[1]	auto[0]	39080	1			T3	1		T4	61		T27	65
fifo_depth[8]	auto[0]	auto[1]	auto[1]	8884	1			T4	101		T27	33		T19	22
fifo_depth[8]	auto[1]	auto[0]	auto[0]	19697	1			T1	1		T4	91		T27	86
fifo_depth[8]	auto[1]	auto[0]	auto[1]	18411	1			T3	1		T4	51		T5	1
fifo_depth[8]	auto[1]	auto[1]	auto[0]	20080	1			T1	1		T4	211		T5	1
fifo_depth[8]	auto[1]	auto[1]	auto[1]	19854	1			T1	3		T4	143		T27	69
fifo_depth[9]	auto[0]	auto[0]	auto[0]	4664	1			T4	29		T27	17		T19	2
fifo_depth[9]	auto[0]	auto[0]	auto[1]	4696	1			T4	127		T27	84		T19	3
fifo_depth[9]	auto[0]	auto[1]	auto[0]	25584	1			T4	52		T27	48		T19	3
fifo_depth[9]	auto[0]	auto[1]	auto[1]	5133	1			T4	59		T27	29		T100	22
fifo_depth[9]	auto[1]	auto[0]	auto[0]	14315	1			T4	94		T27	49		T19	4
fifo_depth[9]	auto[1]	auto[0]	auto[1]	12591	1			T4	39		T27	51		T99	4
fifo_depth[9]	auto[1]	auto[1]	auto[0]	13854	1			T4	136		T5	1		T27	45
fifo_depth[9]	auto[1]	auto[1]	auto[1]	14051	1			T1	1		T4	97		T5	1
fifo_depth[10]	auto[0]	auto[0]	auto[0]	4168	1			T4	16		T27	14		T19	1
fifo_depth[10]	auto[0]	auto[0]	auto[1]	3944	1			T4	84		T27	40		T99	2
fifo_depth[10]	auto[0]	auto[1]	auto[0]	18092	1			T4	24		T27	31		T100	30
fifo_depth[10]	auto[0]	auto[1]	auto[1]	4937	1			T4	39		T27	13		T19	3
fifo_depth[10]	auto[1]	auto[0]	auto[0]	10804	1			T1	1		T4	67		T5	1
fifo_depth[10]	auto[1]	auto[0]	auto[1]	9756	1			T1	2		T4	26		T27	37
fifo_depth[10]	auto[1]	auto[1]	auto[0]	10517	1			T4	110		T5	2		T27	34
fifo_depth[10]	auto[1]	auto[1]	auto[1]	10668	1			T1	2		T4	75		T27	40
fifo_depth[11]	auto[0]	auto[0]	auto[0]	2299	1			T4	10		T27	5		T19	1
fifo_depth[11]	auto[0]	auto[0]	auto[1]	2459	1			T4	54		T27	24		T19	1
fifo_depth[11]	auto[0]	auto[1]	auto[0]	10409	1			T4	23		T27	13		T100	17
fifo_depth[11]	auto[0]	auto[1]	auto[1]	3209	1			T4	28		T27	8		T19	1
fifo_depth[11]	auto[1]	auto[0]	auto[0]	6658	1			T1	2		T4	21		T27	18
fifo_depth[11]	auto[1]	auto[0]	auto[1]	5871	1			T4	8		T5	1		T27	23
fifo_depth[11]	auto[1]	auto[1]	auto[0]	6878	1			T1	1		T4	55		T5	2
fifo_depth[11]	auto[1]	auto[1]	auto[1]	6841	1			T1	1		T4	44		T27	21
fifo_depth[12]	auto[0]	auto[0]	auto[0]	3241	1			T4	7		T27	2		T19	2
fifo_depth[12]	auto[0]	auto[0]	auto[1]	3140	1			T4	16		T27	8		T100	5
fifo_depth[12]	auto[0]	auto[1]	auto[0]	8849	1			T4	10		T27	5		T19	1
fifo_depth[12]	auto[0]	auto[1]	auto[1]	5730	1			T4	8		T27	3		T100	7
fifo_depth[12]	auto[1]	auto[0]	auto[0]	5389	1			T1	1		T4	18		T27	8
fifo_depth[12]	auto[1]	auto[0]	auto[1]	5630	1			T1	3		T4	4		T5	2
fifo_depth[12]	auto[1]	auto[1]	auto[0]	6640	1			T1	1		T4	35		T5	1
fifo_depth[12]	auto[1]	auto[1]	auto[1]	7175	1			T1	2		T4	17		T27	7
fifo_depth[13]	auto[0]	auto[0]	auto[0]	1653	1			T4	2		T27	3		T101	12
fifo_depth[13]	auto[0]	auto[0]	auto[1]	1726	1			T4	8		T27	2		T100	3
fifo_depth[13]	auto[0]	auto[1]	auto[0]	4194	1			T4	2		T27	6		T100	3
fifo_depth[13]	auto[0]	auto[1]	auto[1]	2426	1			T4	5		T27	3		T19	1
fifo_depth[13]	auto[1]	auto[0]	auto[0]	2990	1			T4	10		T5	1		T27	5
fifo_depth[13]	auto[1]	auto[0]	auto[1]	2667	1			T4	1		T27	7		T100	2
fifo_depth[13]	auto[1]	auto[1]	auto[0]	3468	1			T4	14		T27	5		T100	2
fifo_depth[13]	auto[1]	auto[1]	auto[1]	4190	1			T4	14		T27	1		T100	1
fifo_depth[14]	auto[0]	auto[0]	auto[0]	2743	1			T101	3		T16	1		T119	24
fifo_depth[14]	auto[0]	auto[0]	auto[1]	2400	1			T4	8		T27	3		T100	2
fifo_depth[14]	auto[0]	auto[1]	auto[0]	5138	1			T4	3		T27	2		T100	1
fifo_depth[14]	auto[0]	auto[1]	auto[1]	3757	1			T4	3		T27	1		T100	2
fifo_depth[14]	auto[1]	auto[0]	auto[0]	3745	1			T4	3		T100	1		T103	8
fifo_depth[14]	auto[1]	auto[0]	auto[1]	3747	1			T27	3		T100	2		T101	3
fifo_depth[14]	auto[1]	auto[1]	auto[0]	3824	1			T4	8		T27	2		T101	1
fifo_depth[14]	auto[1]	auto[1]	auto[1]	4418	1			T4	6		T27	1		T101	2
fifo_depth[15]	auto[0]	auto[0]	auto[0]	1816	1			T101	2		T96	1		T118	1
fifo_depth[15]	auto[0]	auto[0]	auto[1]	1789	1			T96	1		T119	1		T120	23
fifo_depth[15]	auto[0]	auto[1]	auto[0]	3611	1			T100	1		T61	2		T65	8
fifo_depth[15]	auto[0]	auto[1]	auto[1]	2226	1			T101	2		T118	204		T119	50
fifo_depth[15]	auto[1]	auto[0]	auto[0]	2596	1			T4	1		T27	2		T103	1
fifo_depth[15]	auto[1]	auto[0]	auto[1]	2094	1			T27	2		T101	2		T119	18
fifo_depth[15]	auto[1]	auto[1]	auto[0]	2632	1			T4	1		T27	2		T100	1
fifo_depth[15]	auto[1]	auto[1]	auto[1]	3115	1			T4	4		T103	2		T117	1
fifo_depth[16]	auto[0]	auto[0]	auto[0]	14272	1			T119	1599		T122	192		T135	282
fifo_depth[16]	auto[0]	auto[0]	auto[1]	8849	1			T4	1		T101	1		T119	5
fifo_depth[16]	auto[0]	auto[1]	auto[0]	13494	1			T96	1		T61	3		T65	2
fifo_depth[16]	auto[0]	auto[1]	auto[1]	9793	1			T4	1		T101	2		T118	202
fifo_depth[16]	auto[1]	auto[0]	auto[0]	11234	1			T136	3		T118	238		T137	1
fifo_depth[16]	auto[1]	auto[0]	auto[1]	8317	1			T101	1		T118	1		T119	171
fifo_depth[16]	auto[1]	auto[1]	auto[0]	9505	1			T27	1		T117	3		T136	1
fifo_depth[16]	auto[1]	auto[1]	auto[1]	8901	1			T4	1		T103	1		T117	1