Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	11602589	1			T1	658		T2	6664		T3	58
all_pins[1]	11602589	1			T1	658		T2	6664		T3	58
all_pins[2]	11602589	1			T1	658		T2	6664		T3	58

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	32922775	1			T1	1925		T2	14907		T3	161
values[0x1]	1884992	1			T1	49		T2	5085		T3	13
transitions[0x0=>0x1]	1884838	1			T1	49		T2	5085		T3	13
transitions[0x1=>0x0]	1884848	1			T1	49		T2	5085		T3	13

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	11562022	1			T1	609		T2	6660		T3	45
all_pins[0]	values[0x1]	40567	1			T1	49		T2	4		T3	13
all_pins[0]	transitions[0x0=>0x1]	40503	1			T1	49		T2	4		T3	13
all_pins[0]	transitions[0x1=>0x0]	1844007	1			T2	5081		T8	8618		T19	2
all_pins[1]	values[0x0]	11602225	1			T1	658		T2	6664		T3	58
all_pins[1]	values[0x1]	364	1			T19	1		T26	2		T17	2
all_pins[1]	transitions[0x0=>0x1]	328	1			T19	1		T26	2		T17	2
all_pins[1]	transitions[0x1=>0x0]	40531	1			T1	49		T2	4		T3	13
all_pins[2]	values[0x0]	9758528	1			T1	658		T2	1583		T3	58
all_pins[2]	values[0x1]	1844061	1			T2	5081		T8	8618		T19	2
all_pins[2]	transitions[0x0=>0x1]	1844007	1			T2	5081		T8	8618		T19	2
all_pins[2]	transitions[0x1=>0x0]	310	1			T19	1		T26	2		T17	1