Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	18	0	18	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	18	0	18	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	900	1			T19	4		T26	10		T17	7
all_values[1]	900	1			T19	4		T26	10		T17	7
all_values[2]	900	1			T19	4		T26	10		T17	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1340

1

T19

4

T26

25

T17

11

auto[1]

1360

1

T19

8

T26

5

T17

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

953

1

T19

6

T26

10

T17

9

auto[1]

1747

1

T19

6

T26

20

T17

12

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1555

1

T19

7

T26

16

T17

12

auto[1]

1145

1

T19

5

T26

14

T17

9

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	18	0	18	100.00
Automatically Generated Cross Bins	18	0	18	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

161

1

T26

2

T17

2

T83

4

all_values[0]

auto[0]

auto[0]

auto[1]

94

1

T26

2

T83

2

T51

1

all_values[0]

auto[0]

auto[1]

auto[0]

191

1

T19

3

T26

1

T17

1

all_values[0]

auto[0]

auto[1]

auto[1]

83

1

T83

1

T122

2

T31

1

all_values[0]

auto[1]

auto[0]

auto[1]

193

1

T19

1

T26

5

T83

3

all_values[0]

auto[1]

auto[1]

auto[1]

178

1

T17

4

T83

1

T122

4

all_values[1]

auto[0]

auto[0]

auto[0]

148

1

T19

1

T26

3

T17

1

all_values[1]

auto[0]

auto[0]

auto[1]

94

1

T26

2

T17

1

T83

1

all_values[1]

auto[0]

auto[1]

auto[0]

145

1

T19

1

T83

2

T122

2

all_values[1]

auto[0]

auto[1]

auto[1]

133

1

T19

1

T17

2

T83

2

all_values[1]

auto[1]

auto[0]

auto[1]

188

1

T19

1

T26

4

T17

2

all_values[1]

auto[1]

auto[1]

auto[1]

192

1

T26

1

T17

1

T83

2

all_values[2]

auto[0]

auto[0]

auto[0]

172

1

T26

2

T17

4

T83

6

all_values[2]

auto[0]

auto[0]

auto[1]

93

1

T26

2

T122

2

T123

1

all_values[2]

auto[0]

auto[1]

auto[0]

136

1

T19

1

T26

2

T17

1

all_values[2]

auto[0]

auto[1]

auto[1]

105

1

T122

1

T31

3

T9

1

all_values[2]

auto[1]

auto[0]

auto[1]

197

1

T19

1

T26

3

T17

1

all_values[2]

auto[1]

auto[1]

auto[1]

197

1

T19

2

T26

1

T17

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal