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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.92 92.34 85.07 100.00 76.32 86.11 99.49 69.08


Total test records in report: 729
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T535 /workspace/coverage/default/44.hmac_datapath_stress.645833891 Mar 26 12:53:43 PM PDT 24 Mar 26 12:55:34 PM PDT 24 1805116007 ps
T536 /workspace/coverage/default/5.hmac_burst_wr.354120703 Mar 26 12:50:11 PM PDT 24 Mar 26 12:50:37 PM PDT 24 492856007 ps
T537 /workspace/coverage/default/24.hmac_alert_test.4094173715 Mar 26 12:51:45 PM PDT 24 Mar 26 12:51:46 PM PDT 24 40356789 ps
T538 /workspace/coverage/default/13.hmac_alert_test.2445892977 Mar 26 12:50:48 PM PDT 24 Mar 26 12:50:50 PM PDT 24 23217787 ps
T539 /workspace/coverage/default/35.hmac_datapath_stress.1774059894 Mar 26 12:52:55 PM PDT 24 Mar 26 12:52:56 PM PDT 24 28670957 ps
T540 /workspace/coverage/default/37.hmac_smoke.3079719719 Mar 26 12:52:56 PM PDT 24 Mar 26 12:52:59 PM PDT 24 605707953 ps
T541 /workspace/coverage/default/22.hmac_wipe_secret.4035513481 Mar 26 12:51:33 PM PDT 24 Mar 26 12:53:00 PM PDT 24 65418910953 ps
T542 /workspace/coverage/default/13.hmac_smoke.670139118 Mar 26 12:50:46 PM PDT 24 Mar 26 12:50:54 PM PDT 24 919001586 ps
T543 /workspace/coverage/default/14.hmac_alert_test.2493754389 Mar 26 12:50:47 PM PDT 24 Mar 26 12:50:50 PM PDT 24 53116910 ps
T544 /workspace/coverage/default/39.hmac_datapath_stress.1781811845 Mar 26 12:53:07 PM PDT 24 Mar 26 12:53:57 PM PDT 24 1891870396 ps
T545 /workspace/coverage/default/31.hmac_long_msg.1995894819 Mar 26 12:52:23 PM PDT 24 Mar 26 12:53:59 PM PDT 24 21025391894 ps
T546 /workspace/coverage/default/2.hmac_back_pressure.2514282325 Mar 26 12:49:56 PM PDT 24 Mar 26 12:50:37 PM PDT 24 3889426127 ps
T547 /workspace/coverage/default/22.hmac_long_msg.2488316158 Mar 26 12:51:33 PM PDT 24 Mar 26 12:52:52 PM PDT 24 8247870715 ps
T548 /workspace/coverage/default/48.hmac_error.3389513334 Mar 26 12:54:06 PM PDT 24 Mar 26 12:57:23 PM PDT 24 13423792501 ps
T549 /workspace/coverage/default/35.hmac_test_sha_vectors.39807789 Mar 26 12:52:56 PM PDT 24 Mar 26 01:00:44 PM PDT 24 16588609662 ps
T550 /workspace/coverage/default/33.hmac_back_pressure.411498867 Mar 26 12:52:30 PM PDT 24 Mar 26 12:52:34 PM PDT 24 400034780 ps
T551 /workspace/coverage/default/48.hmac_long_msg.2320079191 Mar 26 12:54:14 PM PDT 24 Mar 26 12:56:04 PM PDT 24 5857912792 ps
T14 /workspace/coverage/default/12.hmac_stress_all_with_rand_reset.365905191 Mar 26 12:50:53 PM PDT 24 Mar 26 01:29:19 PM PDT 24 63756811381 ps
T552 /workspace/coverage/default/42.hmac_wipe_secret.1596403836 Mar 26 12:53:33 PM PDT 24 Mar 26 12:53:50 PM PDT 24 1662891297 ps
T553 /workspace/coverage/default/30.hmac_back_pressure.2059673610 Mar 26 12:52:20 PM PDT 24 Mar 26 12:53:16 PM PDT 24 1438862911 ps
T554 /workspace/coverage/default/16.hmac_datapath_stress.1722701218 Mar 26 12:51:01 PM PDT 24 Mar 26 12:51:24 PM PDT 24 1549166931 ps
T555 /workspace/coverage/default/32.hmac_test_sha_vectors.939967020 Mar 26 12:52:33 PM PDT 24 Mar 26 01:00:21 PM PDT 24 15546850339 ps
T556 /workspace/coverage/default/8.hmac_long_msg.1665015949 Mar 26 12:50:10 PM PDT 24 Mar 26 12:51:38 PM PDT 24 16184508795 ps
T557 /workspace/coverage/default/13.hmac_test_sha_vectors.1568814345 Mar 26 12:50:49 PM PDT 24 Mar 26 12:58:45 PM PDT 24 32789144977 ps
T558 /workspace/coverage/default/17.hmac_alert_test.288852254 Mar 26 12:51:08 PM PDT 24 Mar 26 12:51:09 PM PDT 24 29878134 ps
T559 /workspace/coverage/default/14.hmac_long_msg.355003207 Mar 26 12:50:47 PM PDT 24 Mar 26 12:51:11 PM PDT 24 3082642947 ps
T560 /workspace/coverage/default/8.hmac_test_sha_vectors.3567461508 Mar 26 12:50:11 PM PDT 24 Mar 26 12:58:37 PM PDT 24 28385844751 ps
T561 /workspace/coverage/default/4.hmac_test_sha_vectors.744477410 Mar 26 12:50:12 PM PDT 24 Mar 26 12:58:54 PM PDT 24 55457125407 ps
T562 /workspace/coverage/default/16.hmac_back_pressure.1103669376 Mar 26 12:50:57 PM PDT 24 Mar 26 12:51:42 PM PDT 24 2047128155 ps
T563 /workspace/coverage/default/44.hmac_test_hmac_vectors.4028930042 Mar 26 12:53:49 PM PDT 24 Mar 26 12:53:50 PM PDT 24 74162723 ps
T564 /workspace/coverage/default/29.hmac_long_msg.2019672792 Mar 26 12:52:09 PM PDT 24 Mar 26 12:53:16 PM PDT 24 3961606665 ps
T565 /workspace/coverage/default/37.hmac_wipe_secret.151759904 Mar 26 12:52:57 PM PDT 24 Mar 26 12:54:17 PM PDT 24 3899352672 ps
T566 /workspace/coverage/default/40.hmac_back_pressure.3903917459 Mar 26 12:53:20 PM PDT 24 Mar 26 12:53:58 PM PDT 24 12360585394 ps
T567 /workspace/coverage/default/40.hmac_smoke.2644007234 Mar 26 12:53:23 PM PDT 24 Mar 26 12:53:24 PM PDT 24 90035654 ps
T568 /workspace/coverage/default/32.hmac_alert_test.4240138819 Mar 26 12:52:34 PM PDT 24 Mar 26 12:52:35 PM PDT 24 60063539 ps
T569 /workspace/coverage/default/27.hmac_stress_all.1336249 Mar 26 12:52:10 PM PDT 24 Mar 26 12:59:28 PM PDT 24 138013303963 ps
T570 /workspace/coverage/default/24.hmac_stress_all.52992786 Mar 26 12:51:46 PM PDT 24 Mar 26 01:12:10 PM PDT 24 27025051285 ps
T37 /workspace/coverage/default/0.hmac_sec_cm.187637481 Mar 26 12:49:55 PM PDT 24 Mar 26 12:49:56 PM PDT 24 374710494 ps
T571 /workspace/coverage/default/41.hmac_error.1153283597 Mar 26 12:53:22 PM PDT 24 Mar 26 12:55:10 PM PDT 24 28305718189 ps
T572 /workspace/coverage/default/17.hmac_smoke.2229293854 Mar 26 12:51:04 PM PDT 24 Mar 26 12:51:04 PM PDT 24 70761370 ps
T573 /workspace/coverage/default/5.hmac_stress_all.2268177296 Mar 26 12:50:14 PM PDT 24 Mar 26 12:59:19 PM PDT 24 188761861433 ps
T574 /workspace/coverage/default/6.hmac_smoke.1032188413 Mar 26 12:50:09 PM PDT 24 Mar 26 12:50:11 PM PDT 24 78657625 ps
T575 /workspace/coverage/default/9.hmac_wipe_secret.1959916028 Mar 26 12:50:23 PM PDT 24 Mar 26 12:51:26 PM PDT 24 1177630800 ps
T576 /workspace/coverage/default/5.hmac_datapath_stress.3663548186 Mar 26 12:50:13 PM PDT 24 Mar 26 12:52:30 PM PDT 24 22470728124 ps
T577 /workspace/coverage/default/6.hmac_stress_all.2458729551 Mar 26 12:50:13 PM PDT 24 Mar 26 01:04:17 PM PDT 24 17234001719 ps
T578 /workspace/coverage/default/17.hmac_datapath_stress.2277590306 Mar 26 12:51:10 PM PDT 24 Mar 26 12:51:56 PM PDT 24 772130386 ps
T73 /workspace/coverage/default/65.hmac_stress_all_with_rand_reset.3615910381 Mar 26 12:54:25 PM PDT 24 Mar 26 01:06:22 PM PDT 24 26273792875 ps
T579 /workspace/coverage/default/42.hmac_stress_all.2055290967 Mar 26 12:53:32 PM PDT 24 Mar 26 01:03:46 PM PDT 24 45238575026 ps
T580 /workspace/coverage/default/49.hmac_alert_test.351523878 Mar 26 12:54:23 PM PDT 24 Mar 26 12:54:24 PM PDT 24 34980531 ps
T581 /workspace/coverage/default/42.hmac_datapath_stress.3794772131 Mar 26 12:53:33 PM PDT 24 Mar 26 12:54:48 PM PDT 24 5462332475 ps
T582 /workspace/coverage/default/17.hmac_error.1959896371 Mar 26 12:51:08 PM PDT 24 Mar 26 12:54:45 PM PDT 24 46574784931 ps
T583 /workspace/coverage/default/41.hmac_smoke.2065478163 Mar 26 12:53:22 PM PDT 24 Mar 26 12:53:27 PM PDT 24 375440434 ps
T584 /workspace/coverage/default/24.hmac_long_msg.2996962078 Mar 26 12:51:44 PM PDT 24 Mar 26 12:52:36 PM PDT 24 30940220269 ps
T585 /workspace/coverage/default/46.hmac_back_pressure.2660392197 Mar 26 12:53:54 PM PDT 24 Mar 26 12:54:08 PM PDT 24 1350335972 ps
T586 /workspace/coverage/default/42.hmac_burst_wr.1869622851 Mar 26 12:53:32 PM PDT 24 Mar 26 12:53:54 PM PDT 24 3945373291 ps
T587 /workspace/coverage/default/7.hmac_test_sha_vectors.1811974251 Mar 26 12:50:11 PM PDT 24 Mar 26 12:59:43 PM PDT 24 45433095821 ps
T588 /workspace/coverage/default/3.hmac_test_sha_vectors.3505437933 Mar 26 12:49:54 PM PDT 24 Mar 26 12:57:46 PM PDT 24 26702615906 ps
T589 /workspace/coverage/default/5.hmac_test_sha_vectors.122568511 Mar 26 12:50:13 PM PDT 24 Mar 26 12:57:52 PM PDT 24 20243891702 ps
T590 /workspace/coverage/default/46.hmac_smoke.1852543237 Mar 26 12:53:54 PM PDT 24 Mar 26 12:53:57 PM PDT 24 51055498 ps
T591 /workspace/coverage/default/46.hmac_datapath_stress.330787772 Mar 26 12:53:53 PM PDT 24 Mar 26 12:55:24 PM PDT 24 3210149605 ps
T592 /workspace/coverage/default/39.hmac_long_msg.623481473 Mar 26 12:53:08 PM PDT 24 Mar 26 12:53:46 PM PDT 24 5135638288 ps
T593 /workspace/coverage/default/21.hmac_stress_all.1645731149 Mar 26 12:51:31 PM PDT 24 Mar 26 12:52:10 PM PDT 24 2065918547 ps
T594 /workspace/coverage/default/35.hmac_burst_wr.2450351433 Mar 26 12:52:56 PM PDT 24 Mar 26 12:53:43 PM PDT 24 2914969049 ps
T595 /workspace/coverage/default/15.hmac_smoke.897955054 Mar 26 12:50:59 PM PDT 24 Mar 26 12:51:00 PM PDT 24 115681983 ps
T596 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1014342668 Mar 26 12:37:18 PM PDT 24 Mar 26 12:37:19 PM PDT 24 17094117 ps
T69 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2476047495 Mar 26 12:37:01 PM PDT 24 Mar 26 12:37:02 PM PDT 24 221995117 ps
T70 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2526482516 Mar 26 12:36:48 PM PDT 24 Mar 26 12:36:57 PM PDT 24 457276007 ps
T71 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2681149441 Mar 26 12:37:00 PM PDT 24 Mar 26 12:37:02 PM PDT 24 45480145 ps
T597 /workspace/coverage/cover_reg_top/39.hmac_intr_test.2276522558 Mar 26 12:37:16 PM PDT 24 Mar 26 12:37:17 PM PDT 24 13593072 ps
T66 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1205721180 Mar 26 12:37:02 PM PDT 24 Mar 26 12:37:05 PM PDT 24 165597398 ps
T598 /workspace/coverage/cover_reg_top/15.hmac_intr_test.3974611767 Mar 26 12:37:01 PM PDT 24 Mar 26 12:37:03 PM PDT 24 30544508 ps
T104 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.124558619 Mar 26 12:36:36 PM PDT 24 Mar 26 12:36:51 PM PDT 24 1133327455 ps
T599 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2940876810 Mar 26 12:37:16 PM PDT 24 Mar 26 12:37:16 PM PDT 24 20989528 ps
T600 /workspace/coverage/cover_reg_top/38.hmac_intr_test.4031286700 Mar 26 12:37:17 PM PDT 24 Mar 26 12:37:18 PM PDT 24 19437901 ps
T105 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3393512294 Mar 26 12:36:52 PM PDT 24 Mar 26 12:36:53 PM PDT 24 20164151 ps
T601 /workspace/coverage/cover_reg_top/20.hmac_intr_test.692482533 Mar 26 12:37:18 PM PDT 24 Mar 26 12:37:19 PM PDT 24 29397891 ps
T67 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3291749396 Mar 26 12:36:59 PM PDT 24 Mar 26 12:37:03 PM PDT 24 714707988 ps
T602 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2993432988 Mar 26 12:37:36 PM PDT 24 Mar 26 12:37:38 PM PDT 24 219945440 ps
T603 /workspace/coverage/cover_reg_top/48.hmac_intr_test.878872263 Mar 26 12:37:18 PM PDT 24 Mar 26 12:37:19 PM PDT 24 108288708 ps
T604 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2138271146 Mar 26 12:37:17 PM PDT 24 Mar 26 12:37:17 PM PDT 24 11769208 ps
T605 /workspace/coverage/cover_reg_top/4.hmac_intr_test.1299642409 Mar 26 12:36:48 PM PDT 24 Mar 26 12:36:49 PM PDT 24 25223480 ps
T606 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2922045834 Mar 26 12:36:46 PM PDT 24 Mar 26 12:36:47 PM PDT 24 20069394 ps
T106 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1139946151 Mar 26 12:37:00 PM PDT 24 Mar 26 12:37:01 PM PDT 24 48107742 ps
T68 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3064498693 Mar 26 12:37:00 PM PDT 24 Mar 26 12:37:02 PM PDT 24 322764642 ps
T98 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.308629542 Mar 26 12:36:46 PM PDT 24 Mar 26 12:36:50 PM PDT 24 194665973 ps
T607 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.366148811 Mar 26 12:37:01 PM PDT 24 Mar 26 12:37:03 PM PDT 24 33464972 ps
T131 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.555580427 Mar 26 12:36:50 PM PDT 24 Mar 26 12:36:53 PM PDT 24 738670729 ps
T608 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.478552343 Mar 26 12:36:47 PM PDT 24 Mar 26 12:36:48 PM PDT 24 163157398 ps
T609 /workspace/coverage/cover_reg_top/5.hmac_intr_test.592421581 Mar 26 12:36:48 PM PDT 24 Mar 26 12:36:49 PM PDT 24 42642843 ps
T610 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3305633568 Mar 26 12:37:19 PM PDT 24 Mar 26 12:37:20 PM PDT 24 113051633 ps
T611 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1945335322 Mar 26 12:37:01 PM PDT 24 Mar 26 12:37:04 PM PDT 24 590031414 ps
T612 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2357246221 Mar 26 12:37:18 PM PDT 24 Mar 26 12:37:18 PM PDT 24 43960338 ps
T107 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.4105242418 Mar 26 12:36:48 PM PDT 24 Mar 26 12:36:53 PM PDT 24 106442604 ps
T108 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3811007088 Mar 26 12:36:51 PM PDT 24 Mar 26 12:36:52 PM PDT 24 29531785 ps
T613 /workspace/coverage/cover_reg_top/22.hmac_intr_test.4273075937 Mar 26 12:37:14 PM PDT 24 Mar 26 12:37:14 PM PDT 24 29990275 ps
T128 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.4043733615 Mar 26 12:36:44 PM PDT 24 Mar 26 12:36:48 PM PDT 24 273166932 ps
T614 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2311281636 Mar 26 12:36:34 PM PDT 24 Mar 26 12:36:34 PM PDT 24 26530861 ps
T615 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1310355681 Mar 26 12:36:46 PM PDT 24 Mar 26 12:36:48 PM PDT 24 100032885 ps
T616 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2618335665 Mar 26 12:36:44 PM PDT 24 Mar 26 12:41:10 PM PDT 24 48752121730 ps
T109 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.4022428594 Mar 26 12:36:51 PM PDT 24 Mar 26 12:36:52 PM PDT 24 57812559 ps
T617 /workspace/coverage/cover_reg_top/19.hmac_intr_test.4292379407 Mar 26 12:37:16 PM PDT 24 Mar 26 12:37:17 PM PDT 24 52231740 ps
T618 /workspace/coverage/cover_reg_top/26.hmac_intr_test.3626977773 Mar 26 12:37:16 PM PDT 24 Mar 26 12:37:16 PM PDT 24 48183000 ps
T619 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.551759034 Mar 26 12:37:01 PM PDT 24 Mar 26 12:37:04 PM PDT 24 119478586 ps
T620 /workspace/coverage/cover_reg_top/14.hmac_intr_test.594947605 Mar 26 12:37:05 PM PDT 24 Mar 26 12:37:06 PM PDT 24 24500918 ps
T621 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2362787090 Mar 26 12:37:02 PM PDT 24 Mar 26 12:37:05 PM PDT 24 902719121 ps
T622 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1012217010 Mar 26 12:37:01 PM PDT 24 Mar 26 12:37:03 PM PDT 24 39615798 ps
T623 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2988790418 Mar 26 12:36:49 PM PDT 24 Mar 26 12:36:51 PM PDT 24 413215272 ps
T124 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2569139326 Mar 26 12:36:46 PM PDT 24 Mar 26 12:36:51 PM PDT 24 1033085473 ps
T624 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1002960137 Mar 26 12:37:00 PM PDT 24 Mar 26 12:37:01 PM PDT 24 31562432 ps
T625 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2769021856 Mar 26 12:36:47 PM PDT 24 Mar 26 12:36:50 PM PDT 24 22633118 ps
T110 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2736622863 Mar 26 12:36:48 PM PDT 24 Mar 26 12:36:49 PM PDT 24 24669841 ps
T125 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.514124482 Mar 26 12:36:50 PM PDT 24 Mar 26 12:36:54 PM PDT 24 6104472425 ps
T626 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1461219262 Mar 26 12:36:35 PM PDT 24 Mar 26 12:36:41 PM PDT 24 1498860131 ps
T126 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3427109837 Mar 26 12:36:49 PM PDT 24 Mar 26 12:36:52 PM PDT 24 592496465 ps
T133 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1434599959 Mar 26 12:36:46 PM PDT 24 Mar 26 12:36:49 PM PDT 24 761101326 ps
T113 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.987607979 Mar 26 12:36:35 PM PDT 24 Mar 26 12:36:36 PM PDT 24 30570293 ps
T627 /workspace/coverage/cover_reg_top/31.hmac_intr_test.30017678 Mar 26 12:37:17 PM PDT 24 Mar 26 12:37:18 PM PDT 24 37372887 ps
T628 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2950757145 Mar 26 12:36:35 PM PDT 24 Mar 26 12:36:39 PM PDT 24 219080608 ps
T629 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.4163226544 Mar 26 12:36:51 PM PDT 24 Mar 26 12:36:56 PM PDT 24 897832630 ps
T630 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1493571844 Mar 26 12:37:01 PM PDT 24 Mar 26 12:37:05 PM PDT 24 46103608 ps
T631 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2436405328 Mar 26 12:36:48 PM PDT 24 Mar 26 12:36:50 PM PDT 24 60113864 ps
T632 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.354061861 Mar 26 12:37:00 PM PDT 24 Mar 26 12:37:02 PM PDT 24 281480731 ps
T633 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1539303897 Mar 26 12:36:48 PM PDT 24 Mar 26 12:36:55 PM PDT 24 432027794 ps
T634 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2114006423 Mar 26 12:36:35 PM PDT 24 Mar 26 12:36:36 PM PDT 24 149328818 ps
T635 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3443190544 Mar 26 12:36:47 PM PDT 24 Mar 26 12:36:50 PM PDT 24 35495694 ps
T636 /workspace/coverage/cover_reg_top/1.hmac_intr_test.285585682 Mar 26 12:36:35 PM PDT 24 Mar 26 12:36:35 PM PDT 24 13873918 ps
T637 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.4205159661 Mar 26 12:37:16 PM PDT 24 Mar 26 12:37:18 PM PDT 24 53660284 ps
T638 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3311080381 Mar 26 12:36:44 PM PDT 24 Mar 26 12:36:45 PM PDT 24 15088066 ps
T639 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3884945764 Mar 26 12:36:45 PM PDT 24 Mar 26 12:36:48 PM PDT 24 44984071 ps
T640 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2548524291 Mar 26 12:36:49 PM PDT 24 Mar 26 12:36:50 PM PDT 24 22181003 ps
T641 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3913354926 Mar 26 12:36:59 PM PDT 24 Mar 26 12:37:02 PM PDT 24 859147965 ps
T642 /workspace/coverage/cover_reg_top/28.hmac_intr_test.1819087116 Mar 26 12:37:19 PM PDT 24 Mar 26 12:37:20 PM PDT 24 51907089 ps
T111 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2206505177 Mar 26 12:36:48 PM PDT 24 Mar 26 12:36:49 PM PDT 24 16168354 ps
T643 /workspace/coverage/cover_reg_top/8.hmac_intr_test.1824576919 Mar 26 12:36:50 PM PDT 24 Mar 26 12:36:50 PM PDT 24 14101477 ps
T644 /workspace/coverage/cover_reg_top/42.hmac_intr_test.4075116789 Mar 26 12:37:18 PM PDT 24 Mar 26 12:37:19 PM PDT 24 50084799 ps
T645 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3382479853 Mar 26 12:36:46 PM PDT 24 Mar 26 12:43:26 PM PDT 24 105323307587 ps
T646 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.4252840575 Mar 26 12:36:36 PM PDT 24 Mar 26 12:52:32 PM PDT 24 388050310051 ps
T647 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1652978279 Mar 26 12:36:35 PM PDT 24 Mar 26 12:36:38 PM PDT 24 537962224 ps
T648 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.145229759 Mar 26 12:36:59 PM PDT 24 Mar 26 12:37:02 PM PDT 24 453145444 ps
T649 /workspace/coverage/cover_reg_top/9.hmac_intr_test.3913567487 Mar 26 12:36:50 PM PDT 24 Mar 26 12:36:50 PM PDT 24 20354321 ps
T112 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1570312219 Mar 26 12:36:36 PM PDT 24 Mar 26 12:36:37 PM PDT 24 133850724 ps
T650 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3613986456 Mar 26 12:36:35 PM PDT 24 Mar 26 12:36:37 PM PDT 24 278458618 ps
T651 /workspace/coverage/cover_reg_top/29.hmac_intr_test.4033442425 Mar 26 12:37:17 PM PDT 24 Mar 26 12:37:18 PM PDT 24 47157642 ps
T652 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3707281889 Mar 26 12:36:44 PM PDT 24 Mar 26 12:36:46 PM PDT 24 46718460 ps
T653 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.633879008 Mar 26 12:36:34 PM PDT 24 Mar 26 12:36:35 PM PDT 24 16665432 ps
T116 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3564351193 Mar 26 12:36:34 PM PDT 24 Mar 26 12:36:34 PM PDT 24 153303343 ps
T654 /workspace/coverage/cover_reg_top/46.hmac_intr_test.2497368053 Mar 26 12:37:20 PM PDT 24 Mar 26 12:37:21 PM PDT 24 17153063 ps
T655 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2601106689 Mar 26 12:37:18 PM PDT 24 Mar 26 12:37:18 PM PDT 24 23975654 ps
T134 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1637397155 Mar 26 12:36:36 PM PDT 24 Mar 26 12:36:39 PM PDT 24 501351894 ps
T656 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3221654224 Mar 26 12:36:37 PM PDT 24 Mar 26 12:36:39 PM PDT 24 1473171780 ps
T127 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1754960501 Mar 26 12:36:43 PM PDT 24 Mar 26 12:36:46 PM PDT 24 320070069 ps
T657 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2536603247 Mar 26 12:37:16 PM PDT 24 Mar 26 12:37:18 PM PDT 24 1438409499 ps
T658 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1921551588 Mar 26 12:36:59 PM PDT 24 Mar 26 12:36:59 PM PDT 24 31331650 ps
T659 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.587847936 Mar 26 12:36:48 PM PDT 24 Mar 26 12:36:51 PM PDT 24 95941230 ps
T114 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3707131501 Mar 26 12:36:47 PM PDT 24 Mar 26 12:36:48 PM PDT 24 17470914 ps
T660 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2868008672 Mar 26 12:37:02 PM PDT 24 Mar 26 12:37:05 PM PDT 24 499674819 ps
T130 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2946192103 Mar 26 12:36:59 PM PDT 24 Mar 26 12:37:02 PM PDT 24 846329369 ps
T661 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.553889405 Mar 26 12:37:00 PM PDT 24 Mar 26 12:37:02 PM PDT 24 37275285 ps
T662 /workspace/coverage/cover_reg_top/47.hmac_intr_test.883803161 Mar 26 12:37:19 PM PDT 24 Mar 26 12:37:20 PM PDT 24 41275034 ps
T663 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1335906335 Mar 26 12:37:01 PM PDT 24 Mar 26 12:37:04 PM PDT 24 86882733 ps
T664 /workspace/coverage/cover_reg_top/49.hmac_intr_test.1406716168 Mar 26 12:37:19 PM PDT 24 Mar 26 12:37:20 PM PDT 24 16600639 ps
T665 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3600543410 Mar 26 12:36:46 PM PDT 24 Mar 26 12:36:49 PM PDT 24 140983502 ps
T666 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2227742321 Mar 26 12:37:06 PM PDT 24 Mar 26 12:37:08 PM PDT 24 69737070 ps
T115 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.622843434 Mar 26 12:36:38 PM PDT 24 Mar 26 12:36:44 PM PDT 24 780469975 ps
T667 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.903634792 Mar 26 12:36:58 PM PDT 24 Mar 26 12:36:59 PM PDT 24 13656433 ps
T668 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2037857115 Mar 26 12:37:18 PM PDT 24 Mar 26 12:37:19 PM PDT 24 24284505 ps
T669 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3964418012 Mar 26 12:36:45 PM PDT 24 Mar 26 12:36:47 PM PDT 24 113903212 ps
T670 /workspace/coverage/cover_reg_top/30.hmac_intr_test.4048918107 Mar 26 12:37:17 PM PDT 24 Mar 26 12:37:18 PM PDT 24 17338835 ps
T132 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.156019763 Mar 26 12:37:17 PM PDT 24 Mar 26 12:37:21 PM PDT 24 365357579 ps
T671 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1542739554 Mar 26 12:37:16 PM PDT 24 Mar 26 12:37:17 PM PDT 24 75110622 ps
T672 /workspace/coverage/cover_reg_top/21.hmac_intr_test.2097064434 Mar 26 12:37:15 PM PDT 24 Mar 26 12:37:16 PM PDT 24 26044139 ps
T673 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.277651072 Mar 26 12:36:37 PM PDT 24 Mar 26 12:36:39 PM PDT 24 46118725 ps
T674 /workspace/coverage/cover_reg_top/7.hmac_intr_test.689300524 Mar 26 12:36:45 PM PDT 24 Mar 26 12:36:46 PM PDT 24 173006833 ps
T675 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1504775223 Mar 26 12:37:05 PM PDT 24 Mar 26 12:37:06 PM PDT 24 12214074 ps
T676 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.287836694 Mar 26 12:37:01 PM PDT 24 Mar 26 12:37:05 PM PDT 24 445517617 ps
T677 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.594580284 Mar 26 12:36:45 PM PDT 24 Mar 26 12:36:50 PM PDT 24 205310476 ps
T678 /workspace/coverage/cover_reg_top/3.hmac_intr_test.2448574344 Mar 26 12:36:44 PM PDT 24 Mar 26 12:36:45 PM PDT 24 18946820 ps
T679 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1004295433 Mar 26 12:37:01 PM PDT 24 Mar 26 12:37:06 PM PDT 24 126932999 ps
T680 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2360621244 Mar 26 12:36:46 PM PDT 24 Mar 26 12:50:09 PM PDT 24 463210229727 ps
T681 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.714091789 Mar 26 12:36:46 PM PDT 24 Mar 26 12:37:02 PM PDT 24 17563059279 ps
T682 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.677945984 Mar 26 12:36:50 PM PDT 24 Mar 26 12:36:54 PM PDT 24 48353750 ps
T683 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1155611068 Mar 26 12:36:47 PM PDT 24 Mar 26 12:36:48 PM PDT 24 58147848 ps
T684 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3359135157 Mar 26 12:37:16 PM PDT 24 Mar 26 12:37:19 PM PDT 24 329765156 ps
T685 /workspace/coverage/cover_reg_top/40.hmac_intr_test.2683508704 Mar 26 12:37:18 PM PDT 24 Mar 26 12:37:19 PM PDT 24 63661954 ps
T686 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1404111293 Mar 26 12:37:04 PM PDT 24 Mar 26 12:37:06 PM PDT 24 1157297382 ps
T687 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3996792774 Mar 26 12:37:00 PM PDT 24 Mar 26 12:37:01 PM PDT 24 24229189 ps
T688 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.647841716 Mar 26 12:37:00 PM PDT 24 Mar 26 12:37:03 PM PDT 24 239809513 ps
T689 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3268018583 Mar 26 12:36:45 PM PDT 24 Mar 26 12:36:47 PM PDT 24 60883101 ps
T690 /workspace/coverage/cover_reg_top/43.hmac_intr_test.1072379064 Mar 26 12:37:19 PM PDT 24 Mar 26 12:37:20 PM PDT 24 22988264 ps
T691 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.391294775 Mar 26 12:36:50 PM PDT 24 Mar 26 12:36:51 PM PDT 24 110083304 ps
T692 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2022066847 Mar 26 12:36:45 PM PDT 24 Mar 26 12:48:25 PM PDT 24 168455869789 ps
T693 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.197464634 Mar 26 12:36:59 PM PDT 24 Mar 26 12:36:59 PM PDT 24 81387588 ps
T694 /workspace/coverage/cover_reg_top/25.hmac_intr_test.1971129328 Mar 26 12:37:17 PM PDT 24 Mar 26 12:37:18 PM PDT 24 59677586 ps
T695 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3843812089 Mar 26 12:36:47 PM PDT 24 Mar 26 12:36:50 PM PDT 24 126616172 ps
T696 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3995793538 Mar 26 12:36:47 PM PDT 24 Mar 26 12:36:48 PM PDT 24 212419180 ps
T697 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.163605937 Mar 26 12:37:00 PM PDT 24 Mar 26 12:37:02 PM PDT 24 395013491 ps
T698 /workspace/coverage/cover_reg_top/27.hmac_intr_test.2053447968 Mar 26 12:37:15 PM PDT 24 Mar 26 12:37:15 PM PDT 24 13661138 ps
T699 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2217482257 Mar 26 12:37:19 PM PDT 24 Mar 26 12:37:20 PM PDT 24 162967118 ps
T700 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.326718535 Mar 26 12:36:59 PM PDT 24 Mar 26 12:37:02 PM PDT 24 585264715 ps
T701 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2332773261 Mar 26 12:36:59 PM PDT 24 Mar 26 12:37:00 PM PDT 24 69788740 ps
T702 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.248093749 Mar 26 12:36:59 PM PDT 24 Mar 26 12:37:02 PM PDT 24 169765041 ps
T703 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2070646654 Mar 26 12:36:45 PM PDT 24 Mar 26 12:36:51 PM PDT 24 1204500045 ps
T704 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.196476847 Mar 26 12:37:01 PM PDT 24 Mar 26 12:37:03 PM PDT 24 108090169 ps
T705 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.765558740 Mar 26 12:36:45 PM PDT 24 Mar 26 12:36:47 PM PDT 24 335198738 ps
T706 /workspace/coverage/cover_reg_top/24.hmac_intr_test.784280662 Mar 26 12:37:18 PM PDT 24 Mar 26 12:37:18 PM PDT 24 15821581 ps
T707 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.4162860789 Mar 26 12:36:39 PM PDT 24 Mar 26 12:36:41 PM PDT 24 22191958 ps
T708 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2036939534 Mar 26 12:36:59 PM PDT 24 Mar 26 12:37:00 PM PDT 24 251852037 ps
T709 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1063129184 Mar 26 12:37:02 PM PDT 24 Mar 26 12:37:05 PM PDT 24 231378530 ps
T710 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1075817667 Mar 26 12:36:35 PM PDT 24 Mar 26 12:36:41 PM PDT 24 3670242264 ps
T129 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3415381124 Mar 26 12:36:34 PM PDT 24 Mar 26 12:36:37 PM PDT 24 246486824 ps
T711 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3635384378 Mar 26 12:36:37 PM PDT 24 Mar 26 12:36:54 PM PDT 24 8776865856 ps
T712 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.252728358 Mar 26 12:36:46 PM PDT 24 Mar 26 12:36:49 PM PDT 24 152886731 ps
T713 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1059008100 Mar 26 12:37:00 PM PDT 24 Mar 26 12:37:02 PM PDT 24 173814916 ps
T714 /workspace/coverage/cover_reg_top/45.hmac_intr_test.3796459557 Mar 26 12:37:23 PM PDT 24 Mar 26 12:37:26 PM PDT 24 46739115 ps
T715 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1900592023 Mar 26 12:36:35 PM PDT 24 Mar 26 12:36:36 PM PDT 24 39109737 ps
T716 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.48127936 Mar 26 12:37:04 PM PDT 24 Mar 26 12:37:06 PM PDT 24 128442794 ps
T717 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.583255538 Mar 26 12:36:35 PM PDT 24 Mar 26 12:36:38 PM PDT 24 437764365 ps
T718 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1055769925 Mar 26 12:36:58 PM PDT 24 Mar 26 12:36:59 PM PDT 24 37317855 ps
T719 /workspace/coverage/cover_reg_top/35.hmac_intr_test.3843622476 Mar 26 12:37:17 PM PDT 24 Mar 26 12:37:17 PM PDT 24 16453928 ps
T720 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.4282182134 Mar 26 12:36:47 PM PDT 24 Mar 26 12:36:50 PM PDT 24 317514381 ps
T721 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1067061148 Mar 26 12:37:17 PM PDT 24 Mar 26 12:37:17 PM PDT 24 13396493 ps
T722 /workspace/coverage/cover_reg_top/10.hmac_intr_test.2967621058 Mar 26 12:36:49 PM PDT 24 Mar 26 12:36:50 PM PDT 24 36824674 ps
T723 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1342064616 Mar 26 12:37:06 PM PDT 24 Mar 26 12:37:10 PM PDT 24 458770566 ps
T724 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1928418800 Mar 26 12:37:02 PM PDT 24 Mar 26 12:37:04 PM PDT 24 322075191 ps
T725 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2240631152 Mar 26 12:37:17 PM PDT 24 Mar 26 12:37:18 PM PDT 24 146946789 ps
T726 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2726858552 Mar 26 12:37:17 PM PDT 24 Mar 26 12:37:18 PM PDT 24 56781924 ps
T727 /workspace/coverage/cover_reg_top/17.hmac_intr_test.34511339 Mar 26 12:37:06 PM PDT 24 Mar 26 12:37:07 PM PDT 24 12993421 ps
T728 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2317927537 Mar 26 12:37:04 PM PDT 24 Mar 26 12:37:07 PM PDT 24 98477395 ps
T729 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2046885902 Mar 26 12:36:46 PM PDT 24 Mar 26 12:36:50 PM PDT 24 808921370 ps

Test location /workspace/coverage/default/2.hmac_wipe_secret.2697858043
Short name T27
Test name
Test status
Simulation time 2638296187 ps
CPU time 61.01 seconds
Started Mar 26 12:49:54 PM PDT 24
Finished Mar 26 12:50:55 PM PDT 24
Peak memory 199996 kb
Host smart-4376b427-3ed0-4ef6-8c95-7b09dae7696f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697858043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2697858043
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/178.hmac_stress_all_with_rand_reset.2902739994
Short name T9
Test name
Test status
Simulation time 58981291803 ps
CPU time 2050.33 seconds
Started Mar 26 12:55:36 PM PDT 24
Finished Mar 26 01:29:48 PM PDT 24
Peak memory 244900 kb
Host smart-a43566a5-be85-4c3f-b56e-15eda9f4ab85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2902739994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.hmac_stress_all_with_rand_reset.2902739994
Directory /workspace/178.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.hmac_stress_all.445765824
Short name T17
Test name
Test status
Simulation time 40890370013 ps
CPU time 575.37 seconds
Started Mar 26 12:52:08 PM PDT 24
Finished Mar 26 01:01:43 PM PDT 24
Peak memory 216344 kb
Host smart-b5fb3c9e-413e-49b5-948f-293ab9b92def
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445765824 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.445765824
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.187637481
Short name T37
Test name
Test status
Simulation time 374710494 ps
CPU time 0.95 seconds
Started Mar 26 12:49:55 PM PDT 24
Finished Mar 26 12:49:56 PM PDT 24
Peak memory 219068 kb
Host smart-8d257020-00cf-4ecb-acae-27be4489cac1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187637481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.187637481
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.1799515693
Short name T13
Test name
Test status
Simulation time 129976975338 ps
CPU time 567.71 seconds
Started Mar 26 12:49:53 PM PDT 24
Finished Mar 26 12:59:21 PM PDT 24
Peak memory 224752 kb
Host smart-a6cc75fc-1374-4d09-9e16-f2c0e2fb4228
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1799515693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.1799515693
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1205721180
Short name T66
Test name
Test status
Simulation time 165597398 ps
CPU time 2.85 seconds
Started Mar 26 12:37:02 PM PDT 24
Finished Mar 26 12:37:05 PM PDT 24
Peak memory 199056 kb
Host smart-485a78ff-c174-4096-8a96-21f5096ec4d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205721180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.1205721180
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.hmac_stress_all.495160535
Short name T31
Test name
Test status
Simulation time 78148475568 ps
CPU time 1112.92 seconds
Started Mar 26 12:49:54 PM PDT 24
Finished Mar 26 01:08:27 PM PDT 24
Peak memory 232396 kb
Host smart-755ea28e-92e7-4620-a6d4-dabb69cb468f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495160535 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.495160535
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.2954011908
Short name T12
Test name
Test status
Simulation time 15037487081 ps
CPU time 432.55 seconds
Started Mar 26 12:50:12 PM PDT 24
Finished Mar 26 12:57:25 PM PDT 24
Peak memory 215904 kb
Host smart-95020648-ea80-4a9b-b2c7-1382592dca34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2954011908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.2954011908
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3819984690
Short name T144
Test name
Test status
Simulation time 17937140 ps
CPU time 0.56 seconds
Started Mar 26 12:49:54 PM PDT 24
Finished Mar 26 12:49:55 PM PDT 24
Peak memory 194408 kb
Host smart-9b2515c5-7625-435a-bbcd-e5df4e6c1214
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819984690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3819984690
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_error.1776326847
Short name T286
Test name
Test status
Simulation time 2011268353 ps
CPU time 109.73 seconds
Started Mar 26 12:52:32 PM PDT 24
Finished Mar 26 12:54:22 PM PDT 24
Peak memory 199892 kb
Host smart-0acc1e4a-04bc-47fe-a6d0-a87ac773c90f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776326847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1776326847
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.124558619
Short name T104
Test name
Test status
Simulation time 1133327455 ps
CPU time 14.5 seconds
Started Mar 26 12:36:36 PM PDT 24
Finished Mar 26 12:36:51 PM PDT 24
Peak memory 199020 kb
Host smart-df5e37c1-7c32-409b-825a-eb120ad2f4fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124558619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.124558619
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.645044753
Short name T118
Test name
Test status
Simulation time 392871374 ps
CPU time 19.96 seconds
Started Mar 26 12:49:56 PM PDT 24
Finished Mar 26 12:50:16 PM PDT 24
Peak memory 199928 kb
Host smart-60311495-b494-4b16-a15e-2c36a369408c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645044753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.645044753
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_error.1924999942
Short name T15
Test name
Test status
Simulation time 21054384233 ps
CPU time 181.89 seconds
Started Mar 26 12:51:21 PM PDT 24
Finished Mar 26 12:54:23 PM PDT 24
Peak memory 199964 kb
Host smart-c795c118-2dae-4188-9915-23d80cb11b2d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924999942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1924999942
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3415381124
Short name T129
Test name
Test status
Simulation time 246486824 ps
CPU time 2.84 seconds
Started Mar 26 12:36:34 PM PDT 24
Finished Mar 26 12:36:37 PM PDT 24
Peak memory 199120 kb
Host smart-cb4197bc-bd6f-41ac-9e2b-df1b4a5d9dd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415381124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3415381124
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1004295433
Short name T679
Test name
Test status
Simulation time 126932999 ps
CPU time 3.73 seconds
Started Mar 26 12:37:01 PM PDT 24
Finished Mar 26 12:37:06 PM PDT 24
Peak memory 199152 kb
Host smart-8024cb2b-0bf7-4a66-9217-93849f7c5509
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004295433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1004295433
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.196809818
Short name T103
Test name
Test status
Simulation time 605444165 ps
CPU time 36.28 seconds
Started Mar 26 12:50:28 PM PDT 24
Finished Mar 26 12:51:04 PM PDT 24
Peak memory 200224 kb
Host smart-adf12758-f8c9-4dcf-81bf-c8afa0a20a72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=196809818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.196809818
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2134706184
Short name T51
Test name
Test status
Simulation time 228828659984 ps
CPU time 1040.72 seconds
Started Mar 26 12:51:09 PM PDT 24
Finished Mar 26 01:08:30 PM PDT 24
Peak memory 215620 kb
Host smart-95a10381-666c-41f9-9f3c-fe27af0356af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134706184 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2134706184
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1075817667
Short name T710
Test name
Test status
Simulation time 3670242264 ps
CPU time 6.25 seconds
Started Mar 26 12:36:35 PM PDT 24
Finished Mar 26 12:36:41 PM PDT 24
Peak memory 198928 kb
Host smart-50acc2d0-f8d6-4158-9534-8c504597b9ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075817667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1075817667
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1900592023
Short name T715
Test name
Test status
Simulation time 39109737 ps
CPU time 0.92 seconds
Started Mar 26 12:36:35 PM PDT 24
Finished Mar 26 12:36:36 PM PDT 24
Peak memory 198972 kb
Host smart-31ed639f-6c76-4f80-ba30-6ff9dfca5189
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900592023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1900592023
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3613986456
Short name T650
Test name
Test status
Simulation time 278458618 ps
CPU time 2.29 seconds
Started Mar 26 12:36:35 PM PDT 24
Finished Mar 26 12:36:37 PM PDT 24
Peak memory 199304 kb
Host smart-11e6a8d1-d927-4590-a7e4-f9fb68fb1286
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613986456 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.3613986456
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3564351193
Short name T116
Test name
Test status
Simulation time 153303343 ps
CPU time 0.77 seconds
Started Mar 26 12:36:34 PM PDT 24
Finished Mar 26 12:36:34 PM PDT 24
Peak memory 198364 kb
Host smart-0d267de9-884a-48a9-9437-d14d210b7d44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564351193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3564351193
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2311281636
Short name T614
Test name
Test status
Simulation time 26530861 ps
CPU time 0.61 seconds
Started Mar 26 12:36:34 PM PDT 24
Finished Mar 26 12:36:34 PM PDT 24
Peak memory 193904 kb
Host smart-a2f0d863-8dc1-438a-af5d-c8cf4f34bc76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311281636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2311281636
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3221654224
Short name T656
Test name
Test status
Simulation time 1473171780 ps
CPU time 1.66 seconds
Started Mar 26 12:36:37 PM PDT 24
Finished Mar 26 12:36:39 PM PDT 24
Peak memory 199200 kb
Host smart-f806bee3-482e-4205-b468-1deb0585a6d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221654224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3221654224
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1652978279
Short name T647
Test name
Test status
Simulation time 537962224 ps
CPU time 2.63 seconds
Started Mar 26 12:36:35 PM PDT 24
Finished Mar 26 12:36:38 PM PDT 24
Peak memory 199188 kb
Host smart-ceda9f0b-6be6-4306-9776-4a0c9bfe79a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652978279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1652978279
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.622843434
Short name T115
Test name
Test status
Simulation time 780469975 ps
CPU time 5.95 seconds
Started Mar 26 12:36:38 PM PDT 24
Finished Mar 26 12:36:44 PM PDT 24
Peak memory 199056 kb
Host smart-cf1e4425-b4b7-4e24-9ae4-d0f6974e59c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622843434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.622843434
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1461219262
Short name T626
Test name
Test status
Simulation time 1498860131 ps
CPU time 6.18 seconds
Started Mar 26 12:36:35 PM PDT 24
Finished Mar 26 12:36:41 PM PDT 24
Peak memory 197708 kb
Host smart-f435391b-2cfe-4f2c-b8ab-02e8341e742f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461219262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1461219262
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.633879008
Short name T653
Test name
Test status
Simulation time 16665432 ps
CPU time 0.83 seconds
Started Mar 26 12:36:34 PM PDT 24
Finished Mar 26 12:36:35 PM PDT 24
Peak memory 198220 kb
Host smart-98b3a9a9-cc51-46d2-b514-8cc5355e17a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633879008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.633879008
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.4252840575
Short name T646
Test name
Test status
Simulation time 388050310051 ps
CPU time 955.93 seconds
Started Mar 26 12:36:36 PM PDT 24
Finished Mar 26 12:52:32 PM PDT 24
Peak memory 215792 kb
Host smart-7d116271-a01b-47d7-aed9-78b7a0388310
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252840575 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.4252840575
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.987607979
Short name T113
Test name
Test status
Simulation time 30570293 ps
CPU time 0.69 seconds
Started Mar 26 12:36:35 PM PDT 24
Finished Mar 26 12:36:36 PM PDT 24
Peak memory 197056 kb
Host smart-d01f35ba-e744-4151-a0ff-b78a692a60a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987607979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.987607979
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.285585682
Short name T636
Test name
Test status
Simulation time 13873918 ps
CPU time 0.58 seconds
Started Mar 26 12:36:35 PM PDT 24
Finished Mar 26 12:36:35 PM PDT 24
Peak memory 193800 kb
Host smart-d513ec09-7bc8-476b-a070-bf3a4ef4361b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285585682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.285585682
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.277651072
Short name T673
Test name
Test status
Simulation time 46118725 ps
CPU time 1.13 seconds
Started Mar 26 12:36:37 PM PDT 24
Finished Mar 26 12:36:39 PM PDT 24
Peak memory 197232 kb
Host smart-76470d45-099e-4413-abe6-174b1720958e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277651072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.277651072
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2950757145
Short name T628
Test name
Test status
Simulation time 219080608 ps
CPU time 4.15 seconds
Started Mar 26 12:36:35 PM PDT 24
Finished Mar 26 12:36:39 PM PDT 24
Peak memory 199512 kb
Host smart-428dd3b5-5862-4a25-8fca-13802018dcda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950757145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2950757145
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1637397155
Short name T134
Test name
Test status
Simulation time 501351894 ps
CPU time 2.69 seconds
Started Mar 26 12:36:36 PM PDT 24
Finished Mar 26 12:36:39 PM PDT 24
Peak memory 199136 kb
Host smart-54bcdc38-b62e-4a90-b678-54d89d146e1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637397155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1637397155
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.163605937
Short name T697
Test name
Test status
Simulation time 395013491 ps
CPU time 1.3 seconds
Started Mar 26 12:37:00 PM PDT 24
Finished Mar 26 12:37:02 PM PDT 24
Peak memory 199244 kb
Host smart-9a2555db-6675-44a8-984c-422bbab660d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163605937 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.163605937
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3393512294
Short name T105
Test name
Test status
Simulation time 20164151 ps
CPU time 0.89 seconds
Started Mar 26 12:36:52 PM PDT 24
Finished Mar 26 12:36:53 PM PDT 24
Peak memory 198608 kb
Host smart-4bfc58aa-7476-48ce-9eba-29bd3b1789b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393512294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3393512294
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.2967621058
Short name T722
Test name
Test status
Simulation time 36824674 ps
CPU time 0.57 seconds
Started Mar 26 12:36:49 PM PDT 24
Finished Mar 26 12:36:50 PM PDT 24
Peak memory 193772 kb
Host smart-269769c5-b2bc-4ab4-bc8f-917b58bc9ec2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967621058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2967621058
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2362787090
Short name T621
Test name
Test status
Simulation time 902719121 ps
CPU time 2.3 seconds
Started Mar 26 12:37:02 PM PDT 24
Finished Mar 26 12:37:05 PM PDT 24
Peak memory 198796 kb
Host smart-4e1532ae-d5e2-44c3-a9c3-641c86116f22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362787090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2362787090
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.4282182134
Short name T720
Test name
Test status
Simulation time 317514381 ps
CPU time 3.09 seconds
Started Mar 26 12:36:47 PM PDT 24
Finished Mar 26 12:36:50 PM PDT 24
Peak memory 199268 kb
Host smart-1aecce58-af70-436b-9653-dd8ed91d4792
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282182134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.4282182134
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3427109837
Short name T126
Test name
Test status
Simulation time 592496465 ps
CPU time 3 seconds
Started Mar 26 12:36:49 PM PDT 24
Finished Mar 26 12:36:52 PM PDT 24
Peak memory 199164 kb
Host smart-763a11bc-44e2-478e-b0b0-9a3b32e20352
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427109837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3427109837
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1493571844
Short name T630
Test name
Test status
Simulation time 46103608 ps
CPU time 2.71 seconds
Started Mar 26 12:37:01 PM PDT 24
Finished Mar 26 12:37:05 PM PDT 24
Peak memory 199204 kb
Host smart-33a65ff1-3732-408f-8189-4c5f14a81477
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493571844 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1493571844
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.197464634
Short name T693
Test name
Test status
Simulation time 81387588 ps
CPU time 0.9 seconds
Started Mar 26 12:36:59 PM PDT 24
Finished Mar 26 12:36:59 PM PDT 24
Peak memory 198164 kb
Host smart-f127165b-9b48-4d82-96a8-63564cd33b24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197464634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.197464634
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1002960137
Short name T624
Test name
Test status
Simulation time 31562432 ps
CPU time 0.61 seconds
Started Mar 26 12:37:00 PM PDT 24
Finished Mar 26 12:37:01 PM PDT 24
Peak memory 193804 kb
Host smart-b5633ad9-ae00-4da0-97b1-03b3a23cd090
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002960137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1002960137
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1945335322
Short name T611
Test name
Test status
Simulation time 590031414 ps
CPU time 1.83 seconds
Started Mar 26 12:37:01 PM PDT 24
Finished Mar 26 12:37:04 PM PDT 24
Peak memory 199060 kb
Host smart-2438647b-ca64-4932-b8cb-6071ab122494
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945335322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.1945335322
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.551759034
Short name T619
Test name
Test status
Simulation time 119478586 ps
CPU time 2.98 seconds
Started Mar 26 12:37:01 PM PDT 24
Finished Mar 26 12:37:04 PM PDT 24
Peak memory 199204 kb
Host smart-29857bb4-f996-43f6-85d8-77a0a2451ae9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551759034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.551759034
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3913354926
Short name T641
Test name
Test status
Simulation time 859147965 ps
CPU time 3.04 seconds
Started Mar 26 12:36:59 PM PDT 24
Finished Mar 26 12:37:02 PM PDT 24
Peak memory 199168 kb
Host smart-20725540-225b-4f41-9006-d7c1f656cdb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913354926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3913354926
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.366148811
Short name T607
Test name
Test status
Simulation time 33464972 ps
CPU time 2.12 seconds
Started Mar 26 12:37:01 PM PDT 24
Finished Mar 26 12:37:03 PM PDT 24
Peak memory 199260 kb
Host smart-c5899486-413a-4b03-829e-d43c99eddd62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366148811 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.366148811
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2332773261
Short name T701
Test name
Test status
Simulation time 69788740 ps
CPU time 0.69 seconds
Started Mar 26 12:36:59 PM PDT 24
Finished Mar 26 12:37:00 PM PDT 24
Peak memory 196884 kb
Host smart-70cbd797-5249-4fac-b005-65fbe1191626
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332773261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2332773261
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1055769925
Short name T718
Test name
Test status
Simulation time 37317855 ps
CPU time 0.55 seconds
Started Mar 26 12:36:58 PM PDT 24
Finished Mar 26 12:36:59 PM PDT 24
Peak memory 193788 kb
Host smart-7ccd0e7a-eed5-45b1-8bec-382e52221416
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055769925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1055769925
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.553889405
Short name T661
Test name
Test status
Simulation time 37275285 ps
CPU time 1.68 seconds
Started Mar 26 12:37:00 PM PDT 24
Finished Mar 26 12:37:02 PM PDT 24
Peak memory 198848 kb
Host smart-2e36157d-2941-4ebf-82f8-9efd9f8641a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553889405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.553889405
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2036939534
Short name T708
Test name
Test status
Simulation time 251852037 ps
CPU time 1.56 seconds
Started Mar 26 12:36:59 PM PDT 24
Finished Mar 26 12:37:00 PM PDT 24
Peak memory 199268 kb
Host smart-24c2d487-f8af-4eb3-a7b2-977ec959d626
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036939534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2036939534
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.354061861
Short name T632
Test name
Test status
Simulation time 281480731 ps
CPU time 1.8 seconds
Started Mar 26 12:37:00 PM PDT 24
Finished Mar 26 12:37:02 PM PDT 24
Peak memory 199216 kb
Host smart-63259008-e143-4345-b8c5-f0f4ba2bd319
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354061861 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.354061861
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1012217010
Short name T622
Test name
Test status
Simulation time 39615798 ps
CPU time 0.81 seconds
Started Mar 26 12:37:01 PM PDT 24
Finished Mar 26 12:37:03 PM PDT 24
Peak memory 198192 kb
Host smart-46071d47-391e-49b2-bca1-ebc3c2ed7dda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012217010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1012217010
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3996792774
Short name T687
Test name
Test status
Simulation time 24229189 ps
CPU time 0.55 seconds
Started Mar 26 12:37:00 PM PDT 24
Finished Mar 26 12:37:01 PM PDT 24
Peak memory 193712 kb
Host smart-2114c0b9-241a-4e24-83f2-2462a93a9ed4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996792774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3996792774
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.48127936
Short name T716
Test name
Test status
Simulation time 128442794 ps
CPU time 1.63 seconds
Started Mar 26 12:37:04 PM PDT 24
Finished Mar 26 12:37:06 PM PDT 24
Peak memory 199132 kb
Host smart-5750442c-863e-49c9-872f-fb045c625d90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48127936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr_
outstanding.48127936
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1335906335
Short name T663
Test name
Test status
Simulation time 86882733 ps
CPU time 2.05 seconds
Started Mar 26 12:37:01 PM PDT 24
Finished Mar 26 12:37:04 PM PDT 24
Peak memory 199168 kb
Host smart-cd2e3d7b-2693-41d5-b520-17acccb8f367
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335906335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1335906335
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3064498693
Short name T68
Test name
Test status
Simulation time 322764642 ps
CPU time 1.83 seconds
Started Mar 26 12:37:00 PM PDT 24
Finished Mar 26 12:37:02 PM PDT 24
Peak memory 199136 kb
Host smart-e83ca940-6e54-4b68-b94f-b3b4caf6fb2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064498693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3064498693
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2227742321
Short name T666
Test name
Test status
Simulation time 69737070 ps
CPU time 2.07 seconds
Started Mar 26 12:37:06 PM PDT 24
Finished Mar 26 12:37:08 PM PDT 24
Peak memory 199216 kb
Host smart-b9e19d48-9a09-4b1a-a48e-7dcf878c1d5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227742321 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2227742321
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.196476847
Short name T704
Test name
Test status
Simulation time 108090169 ps
CPU time 0.98 seconds
Started Mar 26 12:37:01 PM PDT 24
Finished Mar 26 12:37:03 PM PDT 24
Peak memory 198700 kb
Host smart-5e58e314-5859-45a4-8999-eb408fca4533
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196476847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.196476847
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.594947605
Short name T620
Test name
Test status
Simulation time 24500918 ps
CPU time 0.6 seconds
Started Mar 26 12:37:05 PM PDT 24
Finished Mar 26 12:37:06 PM PDT 24
Peak memory 193828 kb
Host smart-81c59393-e864-436d-8a13-183abf2db662
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594947605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.594947605
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.145229759
Short name T648
Test name
Test status
Simulation time 453145444 ps
CPU time 2.33 seconds
Started Mar 26 12:36:59 PM PDT 24
Finished Mar 26 12:37:02 PM PDT 24
Peak memory 198352 kb
Host smart-e31b231a-3034-4d25-b618-cc88c85519a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145229759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr
_outstanding.145229759
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1928418800
Short name T724
Test name
Test status
Simulation time 322075191 ps
CPU time 1.66 seconds
Started Mar 26 12:37:02 PM PDT 24
Finished Mar 26 12:37:04 PM PDT 24
Peak memory 199232 kb
Host smart-a4ceb24c-6e4d-4d7c-955b-7e023f81d964
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928418800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1928418800
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.326718535
Short name T700
Test name
Test status
Simulation time 585264715 ps
CPU time 2.8 seconds
Started Mar 26 12:36:59 PM PDT 24
Finished Mar 26 12:37:02 PM PDT 24
Peak memory 199484 kb
Host smart-97bcc67c-3ad5-4f66-8207-ffe540687583
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326718535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.326718535
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2868008672
Short name T660
Test name
Test status
Simulation time 499674819 ps
CPU time 2.73 seconds
Started Mar 26 12:37:02 PM PDT 24
Finished Mar 26 12:37:05 PM PDT 24
Peak memory 207368 kb
Host smart-518526ef-6541-4d23-8ec7-3fe3816affb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868008672 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2868008672
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1921551588
Short name T658
Test name
Test status
Simulation time 31331650 ps
CPU time 0.69 seconds
Started Mar 26 12:36:59 PM PDT 24
Finished Mar 26 12:36:59 PM PDT 24
Peak memory 196792 kb
Host smart-59d8f49b-7569-44e2-8c8d-02e07566f639
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921551588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1921551588
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.3974611767
Short name T598
Test name
Test status
Simulation time 30544508 ps
CPU time 0.62 seconds
Started Mar 26 12:37:01 PM PDT 24
Finished Mar 26 12:37:03 PM PDT 24
Peak memory 194020 kb
Host smart-b1d0fe16-83e2-440c-9aa4-3ed2e9225602
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974611767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.3974611767
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2681149441
Short name T71
Test name
Test status
Simulation time 45480145 ps
CPU time 1.16 seconds
Started Mar 26 12:37:00 PM PDT 24
Finished Mar 26 12:37:02 PM PDT 24
Peak memory 197400 kb
Host smart-3bc03f5b-f61a-4def-8394-6d1a00fede1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681149441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2681149441
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2317927537
Short name T728
Test name
Test status
Simulation time 98477395 ps
CPU time 2.93 seconds
Started Mar 26 12:37:04 PM PDT 24
Finished Mar 26 12:37:07 PM PDT 24
Peak memory 199200 kb
Host smart-5152ab1c-5452-421f-bfb8-53659a6c46c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317927537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.2317927537
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2946192103
Short name T130
Test name
Test status
Simulation time 846329369 ps
CPU time 1.84 seconds
Started Mar 26 12:36:59 PM PDT 24
Finished Mar 26 12:37:02 PM PDT 24
Peak memory 199124 kb
Host smart-686463fc-ca29-4297-b96f-4ccb2b9f3b8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946192103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2946192103
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1404111293
Short name T686
Test name
Test status
Simulation time 1157297382 ps
CPU time 2.32 seconds
Started Mar 26 12:37:04 PM PDT 24
Finished Mar 26 12:37:06 PM PDT 24
Peak memory 199188 kb
Host smart-3638491a-2603-4064-aa15-34a544ee2d92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404111293 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.1404111293
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.903634792
Short name T667
Test name
Test status
Simulation time 13656433 ps
CPU time 0.7 seconds
Started Mar 26 12:36:58 PM PDT 24
Finished Mar 26 12:36:59 PM PDT 24
Peak memory 196696 kb
Host smart-2db03afa-8b4a-41c2-acf8-3125902bd63d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903634792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.903634792
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.1504775223
Short name T675
Test name
Test status
Simulation time 12214074 ps
CPU time 0.58 seconds
Started Mar 26 12:37:05 PM PDT 24
Finished Mar 26 12:37:06 PM PDT 24
Peak memory 193880 kb
Host smart-ff4ec107-a7fd-4fa5-af29-76110e19a1c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504775223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1504775223
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2476047495
Short name T69
Test name
Test status
Simulation time 221995117 ps
CPU time 1.21 seconds
Started Mar 26 12:37:01 PM PDT 24
Finished Mar 26 12:37:02 PM PDT 24
Peak memory 197316 kb
Host smart-62ec9fe0-425a-4539-93cd-4972594ef07b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476047495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.2476047495
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.248093749
Short name T702
Test name
Test status
Simulation time 169765041 ps
CPU time 3.14 seconds
Started Mar 26 12:36:59 PM PDT 24
Finished Mar 26 12:37:02 PM PDT 24
Peak memory 199248 kb
Host smart-55ef6001-cf1e-40bb-b0d0-3fc0feff1185
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248093749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.248093749
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3291749396
Short name T67
Test name
Test status
Simulation time 714707988 ps
CPU time 3.09 seconds
Started Mar 26 12:36:59 PM PDT 24
Finished Mar 26 12:37:03 PM PDT 24
Peak memory 199108 kb
Host smart-fd8ca98b-c54f-447d-a972-badba8431638
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291749396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3291749396
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.647841716
Short name T688
Test name
Test status
Simulation time 239809513 ps
CPU time 3.12 seconds
Started Mar 26 12:37:00 PM PDT 24
Finished Mar 26 12:37:03 PM PDT 24
Peak memory 199264 kb
Host smart-d309ea1f-a494-4275-9ebb-a60da5989ff1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647841716 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.647841716
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1139946151
Short name T106
Test name
Test status
Simulation time 48107742 ps
CPU time 0.86 seconds
Started Mar 26 12:37:00 PM PDT 24
Finished Mar 26 12:37:01 PM PDT 24
Peak memory 198332 kb
Host smart-4cb82f7c-efc0-41ae-9eac-d6bb2498c196
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139946151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1139946151
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.34511339
Short name T727
Test name
Test status
Simulation time 12993421 ps
CPU time 0.6 seconds
Started Mar 26 12:37:06 PM PDT 24
Finished Mar 26 12:37:07 PM PDT 24
Peak memory 193756 kb
Host smart-f2b78c58-2293-415b-98f4-0a5b7d92d9d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34511339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.34511339
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1063129184
Short name T709
Test name
Test status
Simulation time 231378530 ps
CPU time 2.35 seconds
Started Mar 26 12:37:02 PM PDT 24
Finished Mar 26 12:37:05 PM PDT 24
Peak memory 198728 kb
Host smart-8752b4db-b120-4954-9acb-bbe60ce2a750
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063129184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.1063129184
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.287836694
Short name T676
Test name
Test status
Simulation time 445517617 ps
CPU time 2.6 seconds
Started Mar 26 12:37:01 PM PDT 24
Finished Mar 26 12:37:05 PM PDT 24
Peak memory 199308 kb
Host smart-1c13017c-c05e-480a-8a98-1bb896ca44d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287836694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.287836694
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1342064616
Short name T723
Test name
Test status
Simulation time 458770566 ps
CPU time 3.86 seconds
Started Mar 26 12:37:06 PM PDT 24
Finished Mar 26 12:37:10 PM PDT 24
Peak memory 199176 kb
Host smart-048632b0-00bc-4379-bcdb-453d3467cbc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342064616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1342064616
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2240631152
Short name T725
Test name
Test status
Simulation time 146946789 ps
CPU time 1.39 seconds
Started Mar 26 12:37:17 PM PDT 24
Finished Mar 26 12:37:18 PM PDT 24
Peak memory 199272 kb
Host smart-606321f6-42ae-4038-9f65-f8dd8ee5563e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240631152 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2240631152
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2037857115
Short name T668
Test name
Test status
Simulation time 24284505 ps
CPU time 0.85 seconds
Started Mar 26 12:37:18 PM PDT 24
Finished Mar 26 12:37:19 PM PDT 24
Peak memory 198944 kb
Host smart-3e14c048-1c00-4312-8ffc-383b0f05019b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037857115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2037857115
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2940876810
Short name T599
Test name
Test status
Simulation time 20989528 ps
CPU time 0.58 seconds
Started Mar 26 12:37:16 PM PDT 24
Finished Mar 26 12:37:16 PM PDT 24
Peak memory 193704 kb
Host smart-809f4e7a-512c-4945-8b2d-7b810d3eb1cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940876810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2940876810
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2536603247
Short name T657
Test name
Test status
Simulation time 1438409499 ps
CPU time 2.46 seconds
Started Mar 26 12:37:16 PM PDT 24
Finished Mar 26 12:37:18 PM PDT 24
Peak memory 199160 kb
Host smart-8050e297-ef09-4039-ad61-662dd833cbb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536603247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.2536603247
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1059008100
Short name T713
Test name
Test status
Simulation time 173814916 ps
CPU time 1.69 seconds
Started Mar 26 12:37:00 PM PDT 24
Finished Mar 26 12:37:02 PM PDT 24
Peak memory 199272 kb
Host smart-0492896a-f750-4ab8-bc7e-f91890cfb4da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059008100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1059008100
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.4205159661
Short name T637
Test name
Test status
Simulation time 53660284 ps
CPU time 1.64 seconds
Started Mar 26 12:37:16 PM PDT 24
Finished Mar 26 12:37:18 PM PDT 24
Peak memory 199236 kb
Host smart-2a9b4542-84e5-4745-af0c-7b17acb49121
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205159661 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.4205159661
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1542739554
Short name T671
Test name
Test status
Simulation time 75110622 ps
CPU time 0.84 seconds
Started Mar 26 12:37:16 PM PDT 24
Finished Mar 26 12:37:17 PM PDT 24
Peak memory 198100 kb
Host smart-54934664-f0e8-4779-ac7a-fc84b7e5370a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542739554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1542739554
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.4292379407
Short name T617
Test name
Test status
Simulation time 52231740 ps
CPU time 0.59 seconds
Started Mar 26 12:37:16 PM PDT 24
Finished Mar 26 12:37:17 PM PDT 24
Peak memory 194028 kb
Host smart-50fe20b1-c5d1-47a6-af1a-e5897865dff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292379407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.4292379407
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2993432988
Short name T602
Test name
Test status
Simulation time 219945440 ps
CPU time 2.26 seconds
Started Mar 26 12:37:36 PM PDT 24
Finished Mar 26 12:37:38 PM PDT 24
Peak memory 199160 kb
Host smart-8bd579d0-9d4d-4c3f-9f97-ce0e1aa0781e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993432988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.2993432988
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3359135157
Short name T684
Test name
Test status
Simulation time 329765156 ps
CPU time 3.3 seconds
Started Mar 26 12:37:16 PM PDT 24
Finished Mar 26 12:37:19 PM PDT 24
Peak memory 199180 kb
Host smart-2b2aab6a-6611-4738-aa45-c0e4199a2f4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359135157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3359135157
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.156019763
Short name T132
Test name
Test status
Simulation time 365357579 ps
CPU time 4.27 seconds
Started Mar 26 12:37:17 PM PDT 24
Finished Mar 26 12:37:21 PM PDT 24
Peak memory 199132 kb
Host smart-822669f1-56e1-4f69-a5fb-005116d43248
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156019763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.156019763
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.4105242418
Short name T107
Test name
Test status
Simulation time 106442604 ps
CPU time 5.36 seconds
Started Mar 26 12:36:48 PM PDT 24
Finished Mar 26 12:36:53 PM PDT 24
Peak memory 199084 kb
Host smart-414f3111-15e9-4aa0-b2af-1157e6073950
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105242418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.4105242418
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3635384378
Short name T711
Test name
Test status
Simulation time 8776865856 ps
CPU time 16.17 seconds
Started Mar 26 12:36:37 PM PDT 24
Finished Mar 26 12:36:54 PM PDT 24
Peak memory 199236 kb
Host smart-2a544e94-7bee-4818-96af-0c2614fc0418
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635384378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3635384378
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1570312219
Short name T112
Test name
Test status
Simulation time 133850724 ps
CPU time 0.98 seconds
Started Mar 26 12:36:36 PM PDT 24
Finished Mar 26 12:36:37 PM PDT 24
Peak memory 199020 kb
Host smart-791ce461-cbc6-4f41-bee7-e78b25ea7213
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570312219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1570312219
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2022066847
Short name T692
Test name
Test status
Simulation time 168455869789 ps
CPU time 699.63 seconds
Started Mar 26 12:36:45 PM PDT 24
Finished Mar 26 12:48:25 PM PDT 24
Peak memory 209120 kb
Host smart-cafcb602-36cf-4cc4-b759-03cc116c2513
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022066847 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2022066847
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.4162860789
Short name T707
Test name
Test status
Simulation time 22191958 ps
CPU time 0.69 seconds
Started Mar 26 12:36:39 PM PDT 24
Finished Mar 26 12:36:41 PM PDT 24
Peak memory 196480 kb
Host smart-f3e7361b-a98c-439d-b586-5b71a3bac516
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162860789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.4162860789
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2114006423
Short name T634
Test name
Test status
Simulation time 149328818 ps
CPU time 0.57 seconds
Started Mar 26 12:36:35 PM PDT 24
Finished Mar 26 12:36:36 PM PDT 24
Peak memory 194028 kb
Host smart-8ac3da71-66f4-49ae-9296-386faa6bfc98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114006423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2114006423
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3884945764
Short name T639
Test name
Test status
Simulation time 44984071 ps
CPU time 2.28 seconds
Started Mar 26 12:36:45 PM PDT 24
Finished Mar 26 12:36:48 PM PDT 24
Peak memory 198976 kb
Host smart-eb904f6d-df5a-4d4d-a256-4eb9884d1869
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884945764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3884945764
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.583255538
Short name T717
Test name
Test status
Simulation time 437764365 ps
CPU time 2.25 seconds
Started Mar 26 12:36:35 PM PDT 24
Finished Mar 26 12:36:38 PM PDT 24
Peak memory 199260 kb
Host smart-d6a7ee98-e997-4b46-a10b-e721f12dc642
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583255538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.583255538
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1754960501
Short name T127
Test name
Test status
Simulation time 320070069 ps
CPU time 3.11 seconds
Started Mar 26 12:36:43 PM PDT 24
Finished Mar 26 12:36:46 PM PDT 24
Peak memory 199124 kb
Host smart-250811ec-bcdd-4686-b5c3-08bdca8ddb52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754960501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.1754960501
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.692482533
Short name T601
Test name
Test status
Simulation time 29397891 ps
CPU time 0.58 seconds
Started Mar 26 12:37:18 PM PDT 24
Finished Mar 26 12:37:19 PM PDT 24
Peak memory 193828 kb
Host smart-fea7dc5c-ed0f-4f06-b106-9ce7704392e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692482533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.692482533
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2097064434
Short name T672
Test name
Test status
Simulation time 26044139 ps
CPU time 0.62 seconds
Started Mar 26 12:37:15 PM PDT 24
Finished Mar 26 12:37:16 PM PDT 24
Peak memory 194088 kb
Host smart-0c604b3a-d010-41a9-9fcc-82cf91122f5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097064434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2097064434
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.4273075937
Short name T613
Test name
Test status
Simulation time 29990275 ps
CPU time 0.57 seconds
Started Mar 26 12:37:14 PM PDT 24
Finished Mar 26 12:37:14 PM PDT 24
Peak memory 193820 kb
Host smart-1ab0c000-6419-47d4-a459-c7855a729372
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273075937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.4273075937
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2357246221
Short name T612
Test name
Test status
Simulation time 43960338 ps
CPU time 0.56 seconds
Started Mar 26 12:37:18 PM PDT 24
Finished Mar 26 12:37:18 PM PDT 24
Peak memory 194100 kb
Host smart-2f869134-c7a8-4de8-b1f6-360f5b5c5046
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357246221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2357246221
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.784280662
Short name T706
Test name
Test status
Simulation time 15821581 ps
CPU time 0.56 seconds
Started Mar 26 12:37:18 PM PDT 24
Finished Mar 26 12:37:18 PM PDT 24
Peak memory 193768 kb
Host smart-011aa1a0-3926-4938-958e-94f070b15d33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784280662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.784280662
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1971129328
Short name T694
Test name
Test status
Simulation time 59677586 ps
CPU time 0.63 seconds
Started Mar 26 12:37:17 PM PDT 24
Finished Mar 26 12:37:18 PM PDT 24
Peak memory 193836 kb
Host smart-db853341-5456-4955-89a2-785dd11b50bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971129328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1971129328
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3626977773
Short name T618
Test name
Test status
Simulation time 48183000 ps
CPU time 0.59 seconds
Started Mar 26 12:37:16 PM PDT 24
Finished Mar 26 12:37:16 PM PDT 24
Peak memory 193824 kb
Host smart-86550c3c-5fe9-4a1b-a652-0ff18ef499de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626977773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3626977773
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2053447968
Short name T698
Test name
Test status
Simulation time 13661138 ps
CPU time 0.57 seconds
Started Mar 26 12:37:15 PM PDT 24
Finished Mar 26 12:37:15 PM PDT 24
Peak memory 193724 kb
Host smart-0bc636bd-aaa1-4b01-b729-5c7aa1a375cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053447968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2053447968
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1819087116
Short name T642
Test name
Test status
Simulation time 51907089 ps
CPU time 0.6 seconds
Started Mar 26 12:37:19 PM PDT 24
Finished Mar 26 12:37:20 PM PDT 24
Peak memory 193816 kb
Host smart-36e6b146-b01c-452d-9dac-977d21f15636
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819087116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1819087116
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.4033442425
Short name T651
Test name
Test status
Simulation time 47157642 ps
CPU time 0.61 seconds
Started Mar 26 12:37:17 PM PDT 24
Finished Mar 26 12:37:18 PM PDT 24
Peak memory 193804 kb
Host smart-15fe4cdc-4509-4072-8819-071920881a36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033442425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.4033442425
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2526482516
Short name T70
Test name
Test status
Simulation time 457276007 ps
CPU time 8.62 seconds
Started Mar 26 12:36:48 PM PDT 24
Finished Mar 26 12:36:57 PM PDT 24
Peak memory 198784 kb
Host smart-fe97e3ee-d794-4d5c-9ed8-d1e4a482be1c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526482516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2526482516
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2070646654
Short name T703
Test name
Test status
Simulation time 1204500045 ps
CPU time 4.92 seconds
Started Mar 26 12:36:45 PM PDT 24
Finished Mar 26 12:36:51 PM PDT 24
Peak memory 197672 kb
Host smart-bb525abd-0904-426a-a9ea-899f85c5782a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070646654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2070646654
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3268018583
Short name T689
Test name
Test status
Simulation time 60883101 ps
CPU time 0.85 seconds
Started Mar 26 12:36:45 PM PDT 24
Finished Mar 26 12:36:47 PM PDT 24
Peak memory 197916 kb
Host smart-7f6e40f9-99a7-4bc4-bece-a0b4c0ea91fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268018583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3268018583
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1310355681
Short name T615
Test name
Test status
Simulation time 100032885 ps
CPU time 2.24 seconds
Started Mar 26 12:36:46 PM PDT 24
Finished Mar 26 12:36:48 PM PDT 24
Peak memory 199200 kb
Host smart-a6603fba-8255-46ae-9ee1-45c7f768cbfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310355681 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1310355681
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2736622863
Short name T110
Test name
Test status
Simulation time 24669841 ps
CPU time 0.66 seconds
Started Mar 26 12:36:48 PM PDT 24
Finished Mar 26 12:36:49 PM PDT 24
Peak memory 196812 kb
Host smart-b275ddf0-06b8-4b57-94e0-da19a18eb0ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736622863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2736622863
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2448574344
Short name T678
Test name
Test status
Simulation time 18946820 ps
CPU time 0.62 seconds
Started Mar 26 12:36:44 PM PDT 24
Finished Mar 26 12:36:45 PM PDT 24
Peak memory 193760 kb
Host smart-437a4002-1fd3-4f60-89a6-86f8bb16b153
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448574344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2448574344
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.677945984
Short name T682
Test name
Test status
Simulation time 48353750 ps
CPU time 2.09 seconds
Started Mar 26 12:36:50 PM PDT 24
Finished Mar 26 12:36:54 PM PDT 24
Peak memory 198868 kb
Host smart-ec0342f5-b27e-46d6-8182-3e251372b872
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677945984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.677945984
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2988790418
Short name T623
Test name
Test status
Simulation time 413215272 ps
CPU time 2.12 seconds
Started Mar 26 12:36:49 PM PDT 24
Finished Mar 26 12:36:51 PM PDT 24
Peak memory 199176 kb
Host smart-da79f8e1-300a-4de1-8f9d-04085130e635
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988790418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2988790418
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.252728358
Short name T712
Test name
Test status
Simulation time 152886731 ps
CPU time 3.11 seconds
Started Mar 26 12:36:46 PM PDT 24
Finished Mar 26 12:36:49 PM PDT 24
Peak memory 199188 kb
Host smart-09540ec2-1738-4e60-8cd9-acff92f6d0de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252728358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.252728358
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.4048918107
Short name T670
Test name
Test status
Simulation time 17338835 ps
CPU time 0.61 seconds
Started Mar 26 12:37:17 PM PDT 24
Finished Mar 26 12:37:18 PM PDT 24
Peak memory 194084 kb
Host smart-67676b4c-0127-4806-bd14-474dc603680b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048918107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.4048918107
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.30017678
Short name T627
Test name
Test status
Simulation time 37372887 ps
CPU time 0.58 seconds
Started Mar 26 12:37:17 PM PDT 24
Finished Mar 26 12:37:18 PM PDT 24
Peak memory 193748 kb
Host smart-a7b3fbcc-2148-4603-9be1-d492249858cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30017678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.30017678
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3305633568
Short name T610
Test name
Test status
Simulation time 113051633 ps
CPU time 0.58 seconds
Started Mar 26 12:37:19 PM PDT 24
Finished Mar 26 12:37:20 PM PDT 24
Peak memory 194044 kb
Host smart-fd96d0ca-af64-4263-8306-9f37fa4e81c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305633568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3305633568
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2138271146
Short name T604
Test name
Test status
Simulation time 11769208 ps
CPU time 0.6 seconds
Started Mar 26 12:37:17 PM PDT 24
Finished Mar 26 12:37:17 PM PDT 24
Peak memory 193788 kb
Host smart-b00250f8-9edd-4104-90aa-16455b239f46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138271146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2138271146
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1067061148
Short name T721
Test name
Test status
Simulation time 13396493 ps
CPU time 0.63 seconds
Started Mar 26 12:37:17 PM PDT 24
Finished Mar 26 12:37:17 PM PDT 24
Peak memory 194012 kb
Host smart-7447dd54-f46a-47dd-9a53-fa2f7c7a0b70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067061148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1067061148
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.3843622476
Short name T719
Test name
Test status
Simulation time 16453928 ps
CPU time 0.58 seconds
Started Mar 26 12:37:17 PM PDT 24
Finished Mar 26 12:37:17 PM PDT 24
Peak memory 193792 kb
Host smart-98c87ac2-0a3c-4d14-b0bd-b0b26a856c4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843622476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3843622476
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2217482257
Short name T699
Test name
Test status
Simulation time 162967118 ps
CPU time 0.57 seconds
Started Mar 26 12:37:19 PM PDT 24
Finished Mar 26 12:37:20 PM PDT 24
Peak memory 194052 kb
Host smart-0099f941-d876-4f1e-8f7f-583981d0cc4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217482257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2217482257
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2726858552
Short name T726
Test name
Test status
Simulation time 56781924 ps
CPU time 0.55 seconds
Started Mar 26 12:37:17 PM PDT 24
Finished Mar 26 12:37:18 PM PDT 24
Peak memory 193972 kb
Host smart-38a1eb8f-f290-4d85-8b0c-bc5ebab17462
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726858552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2726858552
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.4031286700
Short name T600
Test name
Test status
Simulation time 19437901 ps
CPU time 0.61 seconds
Started Mar 26 12:37:17 PM PDT 24
Finished Mar 26 12:37:18 PM PDT 24
Peak memory 193880 kb
Host smart-80541213-6d63-45ce-9801-a82a5657d2c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031286700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.4031286700
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.2276522558
Short name T597
Test name
Test status
Simulation time 13593072 ps
CPU time 0.57 seconds
Started Mar 26 12:37:16 PM PDT 24
Finished Mar 26 12:37:17 PM PDT 24
Peak memory 194096 kb
Host smart-7cca8d45-6996-4dc7-bd6c-723d9907a62e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276522558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.2276522558
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1539303897
Short name T633
Test name
Test status
Simulation time 432027794 ps
CPU time 6.23 seconds
Started Mar 26 12:36:48 PM PDT 24
Finished Mar 26 12:36:55 PM PDT 24
Peak memory 199008 kb
Host smart-a5e9b8fd-2fdf-44f0-b9d1-1748413bd70f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539303897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1539303897
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.714091789
Short name T681
Test name
Test status
Simulation time 17563059279 ps
CPU time 16.11 seconds
Started Mar 26 12:36:46 PM PDT 24
Finished Mar 26 12:37:02 PM PDT 24
Peak memory 198308 kb
Host smart-3a0a5822-74b2-46ca-9ab3-1c621e355471
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714091789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.714091789
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2922045834
Short name T606
Test name
Test status
Simulation time 20069394 ps
CPU time 0.75 seconds
Started Mar 26 12:36:46 PM PDT 24
Finished Mar 26 12:36:47 PM PDT 24
Peak memory 196824 kb
Host smart-65814c28-3d38-40e7-bf51-a90784733275
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922045834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2922045834
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2618335665
Short name T616
Test name
Test status
Simulation time 48752121730 ps
CPU time 265 seconds
Started Mar 26 12:36:44 PM PDT 24
Finished Mar 26 12:41:10 PM PDT 24
Peak memory 208616 kb
Host smart-9d8e2fb3-9c76-430d-af3c-bdcf0c102a3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618335665 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.2618335665
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3707131501
Short name T114
Test name
Test status
Simulation time 17470914 ps
CPU time 0.89 seconds
Started Mar 26 12:36:47 PM PDT 24
Finished Mar 26 12:36:48 PM PDT 24
Peak memory 198648 kb
Host smart-de68018b-1580-4620-ba47-1db4a9d9f6f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707131501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3707131501
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.1299642409
Short name T605
Test name
Test status
Simulation time 25223480 ps
CPU time 0.55 seconds
Started Mar 26 12:36:48 PM PDT 24
Finished Mar 26 12:36:49 PM PDT 24
Peak memory 193788 kb
Host smart-9200917c-03cd-47a0-ae01-5b2a64f8a04f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299642409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1299642409
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1155611068
Short name T683
Test name
Test status
Simulation time 58147848 ps
CPU time 1.21 seconds
Started Mar 26 12:36:47 PM PDT 24
Finished Mar 26 12:36:48 PM PDT 24
Peak memory 197392 kb
Host smart-e59a6f07-72f1-49db-975c-3d2fccf8608f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155611068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1155611068
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.4163226544
Short name T629
Test name
Test status
Simulation time 897832630 ps
CPU time 4.32 seconds
Started Mar 26 12:36:51 PM PDT 24
Finished Mar 26 12:36:56 PM PDT 24
Peak memory 199168 kb
Host smart-dccbb955-94e2-4fbb-8133-be3f55dead0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163226544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.4163226544
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.765558740
Short name T705
Test name
Test status
Simulation time 335198738 ps
CPU time 1.65 seconds
Started Mar 26 12:36:45 PM PDT 24
Finished Mar 26 12:36:47 PM PDT 24
Peak memory 199148 kb
Host smart-7dd723ee-25d6-4124-bfa1-ae1e9c146eb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765558740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.765558740
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.2683508704
Short name T685
Test name
Test status
Simulation time 63661954 ps
CPU time 0.63 seconds
Started Mar 26 12:37:18 PM PDT 24
Finished Mar 26 12:37:19 PM PDT 24
Peak memory 193880 kb
Host smart-9e4c8057-10e6-4c57-bedb-a0c176a6ac9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683508704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2683508704
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1014342668
Short name T596
Test name
Test status
Simulation time 17094117 ps
CPU time 0.6 seconds
Started Mar 26 12:37:18 PM PDT 24
Finished Mar 26 12:37:19 PM PDT 24
Peak memory 193780 kb
Host smart-fd92a608-5526-4b1f-9e01-10577de08583
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014342668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1014342668
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.4075116789
Short name T644
Test name
Test status
Simulation time 50084799 ps
CPU time 0.62 seconds
Started Mar 26 12:37:18 PM PDT 24
Finished Mar 26 12:37:19 PM PDT 24
Peak memory 193844 kb
Host smart-e7e4ae79-ddfb-42f6-a3ea-5dac358e4af4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075116789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.4075116789
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.1072379064
Short name T690
Test name
Test status
Simulation time 22988264 ps
CPU time 0.6 seconds
Started Mar 26 12:37:19 PM PDT 24
Finished Mar 26 12:37:20 PM PDT 24
Peak memory 194088 kb
Host smart-078daf22-0b70-442a-8ab3-2f417c8dc87b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072379064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1072379064
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2601106689
Short name T655
Test name
Test status
Simulation time 23975654 ps
CPU time 0.57 seconds
Started Mar 26 12:37:18 PM PDT 24
Finished Mar 26 12:37:18 PM PDT 24
Peak memory 193804 kb
Host smart-2f1c801d-5352-40f5-974a-69289e7b605d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601106689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2601106689
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3796459557
Short name T714
Test name
Test status
Simulation time 46739115 ps
CPU time 0.57 seconds
Started Mar 26 12:37:23 PM PDT 24
Finished Mar 26 12:37:26 PM PDT 24
Peak memory 194052 kb
Host smart-ea122990-9ac1-4e91-97d9-eac59e7efe6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796459557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3796459557
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.2497368053
Short name T654
Test name
Test status
Simulation time 17153063 ps
CPU time 0.62 seconds
Started Mar 26 12:37:20 PM PDT 24
Finished Mar 26 12:37:21 PM PDT 24
Peak memory 193848 kb
Host smart-df941295-18d8-42be-a478-50636b084cdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497368053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2497368053
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.883803161
Short name T662
Test name
Test status
Simulation time 41275034 ps
CPU time 0.58 seconds
Started Mar 26 12:37:19 PM PDT 24
Finished Mar 26 12:37:20 PM PDT 24
Peak memory 193804 kb
Host smart-25959c18-abc3-45b0-a36c-ceda0944beef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883803161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.883803161
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.878872263
Short name T603
Test name
Test status
Simulation time 108288708 ps
CPU time 0.58 seconds
Started Mar 26 12:37:18 PM PDT 24
Finished Mar 26 12:37:19 PM PDT 24
Peak memory 193812 kb
Host smart-7c4bd491-d3f2-4f64-bf38-623527a2e970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878872263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.878872263
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1406716168
Short name T664
Test name
Test status
Simulation time 16600639 ps
CPU time 0.58 seconds
Started Mar 26 12:37:19 PM PDT 24
Finished Mar 26 12:37:20 PM PDT 24
Peak memory 193812 kb
Host smart-74efd232-642e-4869-9fdf-6bbefe2dc88e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406716168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1406716168
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2769021856
Short name T625
Test name
Test status
Simulation time 22633118 ps
CPU time 1.43 seconds
Started Mar 26 12:36:47 PM PDT 24
Finished Mar 26 12:36:50 PM PDT 24
Peak memory 199268 kb
Host smart-01fac4f9-69d7-4fe3-a9f2-438ebe389ac3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769021856 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2769021856
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3707281889
Short name T652
Test name
Test status
Simulation time 46718460 ps
CPU time 0.87 seconds
Started Mar 26 12:36:44 PM PDT 24
Finished Mar 26 12:36:46 PM PDT 24
Peak memory 198120 kb
Host smart-813abae9-de97-42aa-b479-2ca0f72277ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707281889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3707281889
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.592421581
Short name T609
Test name
Test status
Simulation time 42642843 ps
CPU time 0.57 seconds
Started Mar 26 12:36:48 PM PDT 24
Finished Mar 26 12:36:49 PM PDT 24
Peak memory 193932 kb
Host smart-c3470896-c29a-4ae1-8dcf-a3a3b187783e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592421581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.592421581
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3843812089
Short name T695
Test name
Test status
Simulation time 126616172 ps
CPU time 1.64 seconds
Started Mar 26 12:36:47 PM PDT 24
Finished Mar 26 12:36:50 PM PDT 24
Peak memory 198880 kb
Host smart-55374cbe-2cb2-4df5-92f8-2eef575099cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843812089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3843812089
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.308629542
Short name T98
Test name
Test status
Simulation time 194665973 ps
CPU time 3.6 seconds
Started Mar 26 12:36:46 PM PDT 24
Finished Mar 26 12:36:50 PM PDT 24
Peak memory 199276 kb
Host smart-5551c19f-12fe-43ca-b8b4-a5300e9014ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308629542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.308629542
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1434599959
Short name T133
Test name
Test status
Simulation time 761101326 ps
CPU time 3.16 seconds
Started Mar 26 12:36:46 PM PDT 24
Finished Mar 26 12:36:49 PM PDT 24
Peak memory 199144 kb
Host smart-1671736e-b4a2-4ebf-a492-b5394169f87d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434599959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1434599959
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.587847936
Short name T659
Test name
Test status
Simulation time 95941230 ps
CPU time 2.15 seconds
Started Mar 26 12:36:48 PM PDT 24
Finished Mar 26 12:36:51 PM PDT 24
Peak memory 199236 kb
Host smart-9bb6d817-f250-40bf-b3c3-d268574f2d0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587847936 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.587847936
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2206505177
Short name T111
Test name
Test status
Simulation time 16168354 ps
CPU time 0.81 seconds
Started Mar 26 12:36:48 PM PDT 24
Finished Mar 26 12:36:49 PM PDT 24
Peak memory 198200 kb
Host smart-0769f256-4b7c-4491-acf7-93c2166bbc3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206505177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2206505177
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3311080381
Short name T638
Test name
Test status
Simulation time 15088066 ps
CPU time 0.59 seconds
Started Mar 26 12:36:44 PM PDT 24
Finished Mar 26 12:36:45 PM PDT 24
Peak memory 194020 kb
Host smart-a264ba1e-b996-44f1-92fb-67bb37e32df4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311080381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3311080381
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3964418012
Short name T669
Test name
Test status
Simulation time 113903212 ps
CPU time 2.19 seconds
Started Mar 26 12:36:45 PM PDT 24
Finished Mar 26 12:36:47 PM PDT 24
Peak memory 199188 kb
Host smart-a858c840-0670-4e97-9d5e-635f3502ea17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964418012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.3964418012
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2046885902
Short name T729
Test name
Test status
Simulation time 808921370 ps
CPU time 3.58 seconds
Started Mar 26 12:36:46 PM PDT 24
Finished Mar 26 12:36:50 PM PDT 24
Peak memory 199212 kb
Host smart-ea56ee80-ec85-41e5-b655-b8d1ad64d5db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046885902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2046885902
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.4043733615
Short name T128
Test name
Test status
Simulation time 273166932 ps
CPU time 4.12 seconds
Started Mar 26 12:36:44 PM PDT 24
Finished Mar 26 12:36:48 PM PDT 24
Peak memory 199160 kb
Host smart-63f1bcfa-f2f7-43b8-96d4-d7de75c8defe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043733615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.4043733615
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2360621244
Short name T680
Test name
Test status
Simulation time 463210229727 ps
CPU time 802.28 seconds
Started Mar 26 12:36:46 PM PDT 24
Finished Mar 26 12:50:09 PM PDT 24
Peak memory 215724 kb
Host smart-d89bee8a-27ed-407e-b85d-f42eb339f7a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360621244 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.2360621244
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2548524291
Short name T640
Test name
Test status
Simulation time 22181003 ps
CPU time 0.66 seconds
Started Mar 26 12:36:49 PM PDT 24
Finished Mar 26 12:36:50 PM PDT 24
Peak memory 196824 kb
Host smart-4cd89657-3a3d-4a05-8558-8d7fb7cc2afd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548524291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2548524291
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.689300524
Short name T674
Test name
Test status
Simulation time 173006833 ps
CPU time 0.55 seconds
Started Mar 26 12:36:45 PM PDT 24
Finished Mar 26 12:36:46 PM PDT 24
Peak memory 194012 kb
Host smart-5bc1571f-3009-4995-b634-57ed603b1432
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689300524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.689300524
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3443190544
Short name T635
Test name
Test status
Simulation time 35495694 ps
CPU time 1.67 seconds
Started Mar 26 12:36:47 PM PDT 24
Finished Mar 26 12:36:50 PM PDT 24
Peak memory 198800 kb
Host smart-6ef79c17-164e-4d61-a08c-8f67546d51a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443190544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3443190544
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.391294775
Short name T691
Test name
Test status
Simulation time 110083304 ps
CPU time 1.76 seconds
Started Mar 26 12:36:50 PM PDT 24
Finished Mar 26 12:36:51 PM PDT 24
Peak memory 199208 kb
Host smart-27c9f657-6a91-420b-b0ff-3391b1d8d2cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391294775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.391294775
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2569139326
Short name T124
Test name
Test status
Simulation time 1033085473 ps
CPU time 4.8 seconds
Started Mar 26 12:36:46 PM PDT 24
Finished Mar 26 12:36:51 PM PDT 24
Peak memory 199092 kb
Host smart-9fd9a80e-fa1b-44f8-9269-073ccdc6b304
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569139326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2569139326
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3382479853
Short name T645
Test name
Test status
Simulation time 105323307587 ps
CPU time 398.95 seconds
Started Mar 26 12:36:46 PM PDT 24
Finished Mar 26 12:43:26 PM PDT 24
Peak memory 215240 kb
Host smart-ead3a68a-526f-4a09-98b1-85eac1bc4c60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382479853 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3382479853
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3811007088
Short name T108
Test name
Test status
Simulation time 29531785 ps
CPU time 0.9 seconds
Started Mar 26 12:36:51 PM PDT 24
Finished Mar 26 12:36:52 PM PDT 24
Peak memory 198268 kb
Host smart-f3bac1eb-f1f9-484b-b2f3-f2a7badcaa68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811007088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3811007088
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.1824576919
Short name T643
Test name
Test status
Simulation time 14101477 ps
CPU time 0.59 seconds
Started Mar 26 12:36:50 PM PDT 24
Finished Mar 26 12:36:50 PM PDT 24
Peak memory 193800 kb
Host smart-fa8fa193-6912-4d7d-a920-0c692ac1157b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824576919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.1824576919
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3600543410
Short name T665
Test name
Test status
Simulation time 140983502 ps
CPU time 2 seconds
Started Mar 26 12:36:46 PM PDT 24
Finished Mar 26 12:36:49 PM PDT 24
Peak memory 199028 kb
Host smart-3ce0df9b-3f56-4b53-86fc-c83869dcfe2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600543410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3600543410
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3995793538
Short name T696
Test name
Test status
Simulation time 212419180 ps
CPU time 1.66 seconds
Started Mar 26 12:36:47 PM PDT 24
Finished Mar 26 12:36:48 PM PDT 24
Peak memory 199192 kb
Host smart-4f7e5bc2-0098-4942-9d7c-06fbe853c058
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995793538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3995793538
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.555580427
Short name T131
Test name
Test status
Simulation time 738670729 ps
CPU time 3.11 seconds
Started Mar 26 12:36:50 PM PDT 24
Finished Mar 26 12:36:53 PM PDT 24
Peak memory 199172 kb
Host smart-38775bac-131e-48e7-a42d-2dbadb47e9d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555580427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.555580427
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2436405328
Short name T631
Test name
Test status
Simulation time 60113864 ps
CPU time 1.73 seconds
Started Mar 26 12:36:48 PM PDT 24
Finished Mar 26 12:36:50 PM PDT 24
Peak memory 199288 kb
Host smart-0e916580-747b-43d8-b418-3b3176ea67e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436405328 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2436405328
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.4022428594
Short name T109
Test name
Test status
Simulation time 57812559 ps
CPU time 0.81 seconds
Started Mar 26 12:36:51 PM PDT 24
Finished Mar 26 12:36:52 PM PDT 24
Peak memory 197928 kb
Host smart-5d87dc7c-ff87-43a4-bafc-07f0aea9d8dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022428594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.4022428594
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.3913567487
Short name T649
Test name
Test status
Simulation time 20354321 ps
CPU time 0.62 seconds
Started Mar 26 12:36:50 PM PDT 24
Finished Mar 26 12:36:50 PM PDT 24
Peak memory 193800 kb
Host smart-50005007-b5b9-4bbf-9b07-04ce7027f70e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913567487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3913567487
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.478552343
Short name T608
Test name
Test status
Simulation time 163157398 ps
CPU time 1.17 seconds
Started Mar 26 12:36:47 PM PDT 24
Finished Mar 26 12:36:48 PM PDT 24
Peak memory 197236 kb
Host smart-d5a45242-8e9f-413d-b50b-1b2ccc1c3b33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478552343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.478552343
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.594580284
Short name T677
Test name
Test status
Simulation time 205310476 ps
CPU time 4.35 seconds
Started Mar 26 12:36:45 PM PDT 24
Finished Mar 26 12:36:50 PM PDT 24
Peak memory 199164 kb
Host smart-1aba8274-3fb9-4fc8-90a2-a7f06366dd3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594580284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.594580284
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.514124482
Short name T125
Test name
Test status
Simulation time 6104472425 ps
CPU time 4.22 seconds
Started Mar 26 12:36:50 PM PDT 24
Finished Mar 26 12:36:54 PM PDT 24
Peak memory 199232 kb
Host smart-4e85740a-fda5-4c05-b658-87598255f7ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514124482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.514124482
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.585727349
Short name T54
Test name
Test status
Simulation time 12293268066 ps
CPU time 24.89 seconds
Started Mar 26 12:49:34 PM PDT 24
Finished Mar 26 12:49:59 PM PDT 24
Peak memory 224640 kb
Host smart-af4a780e-73d2-4963-8987-6bb73e7501aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=585727349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.585727349
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.919761003
Short name T220
Test name
Test status
Simulation time 1835283061 ps
CPU time 46.42 seconds
Started Mar 26 12:49:56 PM PDT 24
Finished Mar 26 12:50:43 PM PDT 24
Peak memory 199904 kb
Host smart-71a09502-c9d3-4afe-9125-41e94e9f38f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919761003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.919761003
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.505148960
Short name T237
Test name
Test status
Simulation time 475438416 ps
CPU time 27 seconds
Started Mar 26 12:49:38 PM PDT 24
Finished Mar 26 12:50:05 PM PDT 24
Peak memory 199872 kb
Host smart-e648f397-f511-46c0-a2b1-a70578d519dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=505148960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.505148960
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2340863657
Short name T290
Test name
Test status
Simulation time 85152167 ps
CPU time 0.66 seconds
Started Mar 26 12:49:56 PM PDT 24
Finished Mar 26 12:49:57 PM PDT 24
Peak memory 195736 kb
Host smart-4260d1d0-f15a-4e0c-9675-f7d9a4c32035
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340863657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2340863657
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.448265989
Short name T92
Test name
Test status
Simulation time 6118694956 ps
CPU time 122.91 seconds
Started Mar 26 12:49:36 PM PDT 24
Finished Mar 26 12:51:39 PM PDT 24
Peak memory 199944 kb
Host smart-c2249f3b-2270-4f5f-96b5-6c5477f74980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448265989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.448265989
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.4042546515
Short name T167
Test name
Test status
Simulation time 994624396 ps
CPU time 6.25 seconds
Started Mar 26 12:49:36 PM PDT 24
Finished Mar 26 12:49:42 PM PDT 24
Peak memory 199916 kb
Host smart-eb961653-1bff-4218-b0a3-3d0be43381b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042546515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.4042546515
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.661530503
Short name T26
Test name
Test status
Simulation time 59545124108 ps
CPU time 425.22 seconds
Started Mar 26 12:49:58 PM PDT 24
Finished Mar 26 12:57:03 PM PDT 24
Peak memory 215952 kb
Host smart-ec120e2f-fd18-4b74-a084-5efacb991542
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661530503 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.661530503
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.3850437765
Short name T423
Test name
Test status
Simulation time 51630303 ps
CPU time 1.01 seconds
Started Mar 26 12:49:57 PM PDT 24
Finished Mar 26 12:49:58 PM PDT 24
Peak memory 199424 kb
Host smart-35059bb1-834c-42bb-b625-cb1895248b30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850437765 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.3850437765
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.339171308
Short name T487
Test name
Test status
Simulation time 30400499743 ps
CPU time 487.76 seconds
Started Mar 26 12:49:56 PM PDT 24
Finished Mar 26 12:58:04 PM PDT 24
Peak memory 199892 kb
Host smart-70ea0a1f-0be4-4331-881d-b3153fcb0669
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339171308 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.339171308
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1254564853
Short name T462
Test name
Test status
Simulation time 5344793227 ps
CPU time 53.71 seconds
Started Mar 26 12:49:55 PM PDT 24
Finished Mar 26 12:50:49 PM PDT 24
Peak memory 199972 kb
Host smart-45e1da4d-9f74-44bf-a42c-75351c1e8795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254564853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1254564853
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3369427189
Short name T25
Test name
Test status
Simulation time 37295852 ps
CPU time 0.58 seconds
Started Mar 26 12:49:54 PM PDT 24
Finished Mar 26 12:49:55 PM PDT 24
Peak memory 194472 kb
Host smart-e8c114bc-41f4-4cc1-9b6e-9cfe9b54aac5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369427189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3369427189
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.1723905025
Short name T362
Test name
Test status
Simulation time 1522533716 ps
CPU time 54.29 seconds
Started Mar 26 12:49:54 PM PDT 24
Finished Mar 26 12:50:48 PM PDT 24
Peak memory 222828 kb
Host smart-7089bd6c-3a7b-456f-a1d8-95bff6520683
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1723905025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.1723905025
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3185525890
Short name T370
Test name
Test status
Simulation time 52820327930 ps
CPU time 43.93 seconds
Started Mar 26 12:49:55 PM PDT 24
Finished Mar 26 12:50:39 PM PDT 24
Peak memory 199928 kb
Host smart-56d7d262-478a-453e-ba38-6251f050e295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185525890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3185525890
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1267320611
Short name T447
Test name
Test status
Simulation time 2197829772 ps
CPU time 133.72 seconds
Started Mar 26 12:49:57 PM PDT 24
Finished Mar 26 12:52:10 PM PDT 24
Peak memory 199920 kb
Host smart-d3ecfe87-14de-4461-b7ac-0ae590e3a623
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1267320611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1267320611
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3142883716
Short name T16
Test name
Test status
Simulation time 2966087793 ps
CPU time 121.11 seconds
Started Mar 26 12:49:55 PM PDT 24
Finished Mar 26 12:51:57 PM PDT 24
Peak memory 199916 kb
Host smart-512c2347-931b-4a2a-9b00-dfc09bc860a1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142883716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3142883716
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.1611039986
Short name T318
Test name
Test status
Simulation time 3444355282 ps
CPU time 102.01 seconds
Started Mar 26 12:49:53 PM PDT 24
Finished Mar 26 12:51:35 PM PDT 24
Peak memory 200076 kb
Host smart-c919c575-84ed-471d-b9b9-86a5bbf44c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611039986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.1611039986
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.4009232593
Short name T34
Test name
Test status
Simulation time 234022645 ps
CPU time 0.84 seconds
Started Mar 26 12:49:54 PM PDT 24
Finished Mar 26 12:49:54 PM PDT 24
Peak memory 218056 kb
Host smart-7ca9389a-9c42-49fa-a741-429c462166f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009232593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.4009232593
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3010020615
Short name T416
Test name
Test status
Simulation time 210856695 ps
CPU time 6.1 seconds
Started Mar 26 12:49:54 PM PDT 24
Finished Mar 26 12:50:01 PM PDT 24
Peak memory 199920 kb
Host smart-bbd52774-a28c-4c6e-b347-4b5838ff169c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010020615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3010020615
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.4069783981
Short name T326
Test name
Test status
Simulation time 70905560 ps
CPU time 1.23 seconds
Started Mar 26 12:49:55 PM PDT 24
Finished Mar 26 12:49:57 PM PDT 24
Peak memory 199808 kb
Host smart-284f3ec0-49c3-4838-be52-0fed67a3704e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069783981 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.4069783981
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.1653673102
Short name T486
Test name
Test status
Simulation time 17673399932 ps
CPU time 504.22 seconds
Started Mar 26 12:49:52 PM PDT 24
Finished Mar 26 12:58:17 PM PDT 24
Peak memory 199876 kb
Host smart-9a40f5e1-a6f1-4186-a69c-2a91117114f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653673102 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.1653673102
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3406457160
Short name T338
Test name
Test status
Simulation time 667475237 ps
CPU time 27.73 seconds
Started Mar 26 12:49:57 PM PDT 24
Finished Mar 26 12:50:26 PM PDT 24
Peak memory 199916 kb
Host smart-26dd5416-f241-49c7-8f6f-e66afb323649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406457160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3406457160
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3311446229
Short name T419
Test name
Test status
Simulation time 14611269 ps
CPU time 0.57 seconds
Started Mar 26 12:50:22 PM PDT 24
Finished Mar 26 12:50:23 PM PDT 24
Peak memory 195548 kb
Host smart-f92ee3d3-314d-4ffc-9a08-977a6cb73b96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311446229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3311446229
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.766149760
Short name T446
Test name
Test status
Simulation time 2681119615 ps
CPU time 24.29 seconds
Started Mar 26 12:50:21 PM PDT 24
Finished Mar 26 12:50:46 PM PDT 24
Peak memory 216224 kb
Host smart-5c6cfd87-f74e-4c40-b248-f4c04d3f9774
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=766149760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.766149760
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.4051983982
Short name T291
Test name
Test status
Simulation time 448210436 ps
CPU time 9.03 seconds
Started Mar 26 12:50:20 PM PDT 24
Finished Mar 26 12:50:30 PM PDT 24
Peak memory 199928 kb
Host smart-55a479a6-a8c9-4c24-b46f-48a20446dcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051983982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.4051983982
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_error.2684362286
Short name T48
Test name
Test status
Simulation time 75542263521 ps
CPU time 227.67 seconds
Started Mar 26 12:50:21 PM PDT 24
Finished Mar 26 12:54:09 PM PDT 24
Peak memory 199964 kb
Host smart-526dd785-ba3d-4fa1-a323-507aa573d327
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684362286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2684362286
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.102199504
Short name T159
Test name
Test status
Simulation time 3954558591 ps
CPU time 72.47 seconds
Started Mar 26 12:50:22 PM PDT 24
Finished Mar 26 12:51:34 PM PDT 24
Peak memory 199964 kb
Host smart-f639e100-4f1f-4364-9ace-e8a5870fb98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102199504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.102199504
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1269704963
Short name T328
Test name
Test status
Simulation time 1977144693 ps
CPU time 6.77 seconds
Started Mar 26 12:50:23 PM PDT 24
Finished Mar 26 12:50:30 PM PDT 24
Peak memory 200056 kb
Host smart-b8d68af6-57f8-4c97-bc4a-5210ad769b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269704963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1269704963
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.430051164
Short name T19
Test name
Test status
Simulation time 33274852389 ps
CPU time 176.69 seconds
Started Mar 26 12:50:24 PM PDT 24
Finished Mar 26 12:53:21 PM PDT 24
Peak memory 199976 kb
Host smart-be5ca9f9-b82f-40e4-b3f6-0dee6c941a92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430051164 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.430051164
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.3978504323
Short name T317
Test name
Test status
Simulation time 303925454 ps
CPU time 1.38 seconds
Started Mar 26 12:50:22 PM PDT 24
Finished Mar 26 12:50:24 PM PDT 24
Peak memory 199668 kb
Host smart-cc775623-37a9-4934-a659-493026dc272e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978504323 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.3978504323
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.2529246708
Short name T274
Test name
Test status
Simulation time 7336945060 ps
CPU time 419.25 seconds
Started Mar 26 12:50:21 PM PDT 24
Finished Mar 26 12:57:20 PM PDT 24
Peak memory 199948 kb
Host smart-77fb1b11-2636-44d4-83dd-6b6d3fe84cc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529246708 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.2529246708
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.1269702485
Short name T100
Test name
Test status
Simulation time 792972827 ps
CPU time 30.72 seconds
Started Mar 26 12:50:20 PM PDT 24
Finished Mar 26 12:50:51 PM PDT 24
Peak memory 199844 kb
Host smart-c1cfd36f-e402-4297-a22c-1d6498f9475b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269702485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1269702485
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/100.hmac_stress_all_with_rand_reset.3109391782
Short name T47
Test name
Test status
Simulation time 76762981864 ps
CPU time 1515.89 seconds
Started Mar 26 12:54:47 PM PDT 24
Finished Mar 26 01:20:03 PM PDT 24
Peak memory 232692 kb
Host smart-863971fb-03f5-46b8-9a6a-30b409394ac4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3109391782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.hmac_stress_all_with_rand_reset.3109391782
Directory /workspace/100.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3940085144
Short name T306
Test name
Test status
Simulation time 21477463 ps
CPU time 0.56 seconds
Started Mar 26 12:50:35 PM PDT 24
Finished Mar 26 12:50:36 PM PDT 24
Peak memory 194384 kb
Host smart-3e2e4660-4f11-426e-901c-3f71d92d9b12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940085144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3940085144
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.538405077
Short name T22
Test name
Test status
Simulation time 620491040 ps
CPU time 16.06 seconds
Started Mar 26 12:50:35 PM PDT 24
Finished Mar 26 12:50:51 PM PDT 24
Peak memory 208088 kb
Host smart-2d562d3d-6e34-421a-98a8-c1e6f8e3a381
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=538405077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.538405077
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3334068749
Short name T485
Test name
Test status
Simulation time 1293050959 ps
CPU time 5.02 seconds
Started Mar 26 12:50:33 PM PDT 24
Finished Mar 26 12:50:38 PM PDT 24
Peak memory 199908 kb
Host smart-b919159d-fa17-40d0-836c-190fe3cb64d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334068749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3334068749
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.3893898674
Short name T221
Test name
Test status
Simulation time 2209230305 ps
CPU time 137.23 seconds
Started Mar 26 12:50:36 PM PDT 24
Finished Mar 26 12:52:53 PM PDT 24
Peak memory 199968 kb
Host smart-713f2584-9c68-4564-82ae-5afa973ee5a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3893898674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3893898674
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.3446972378
Short name T375
Test name
Test status
Simulation time 900673367 ps
CPU time 51.74 seconds
Started Mar 26 12:50:33 PM PDT 24
Finished Mar 26 12:51:24 PM PDT 24
Peak memory 199972 kb
Host smart-db07cfa6-5de1-4568-9d8e-7d44158e8ec6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446972378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.3446972378
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3717053549
Short name T389
Test name
Test status
Simulation time 19345076075 ps
CPU time 70.46 seconds
Started Mar 26 12:50:35 PM PDT 24
Finished Mar 26 12:51:45 PM PDT 24
Peak memory 199976 kb
Host smart-b39ab118-c8d9-4bb7-ba93-160b9e57460c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717053549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3717053549
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1556163820
Short name T174
Test name
Test status
Simulation time 43742898 ps
CPU time 1.16 seconds
Started Mar 26 12:50:24 PM PDT 24
Finished Mar 26 12:50:26 PM PDT 24
Peak memory 199652 kb
Host smart-9f60724d-18c8-44d5-8230-e73d32468864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556163820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1556163820
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.2284149155
Short name T445
Test name
Test status
Simulation time 55326410755 ps
CPU time 1216.39 seconds
Started Mar 26 12:50:34 PM PDT 24
Finished Mar 26 01:10:50 PM PDT 24
Peak memory 199896 kb
Host smart-3f7de5ca-5eda-4011-bac9-989aa929ca46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284149155 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2284149155
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.1744793960
Short name T218
Test name
Test status
Simulation time 33206123 ps
CPU time 1.29 seconds
Started Mar 26 12:50:41 PM PDT 24
Finished Mar 26 12:50:44 PM PDT 24
Peak memory 199868 kb
Host smart-2e4d919c-f45a-48c7-8610-e2779b1aa54c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744793960 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.1744793960
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.3838250108
Short name T432
Test name
Test status
Simulation time 57637264618 ps
CPU time 497.17 seconds
Started Mar 26 12:50:42 PM PDT 24
Finished Mar 26 12:59:00 PM PDT 24
Peak memory 199892 kb
Host smart-947ced64-ded8-4121-8814-5d0eb2eea055
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838250108 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.3838250108
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.1214699707
Short name T28
Test name
Test status
Simulation time 1577520689 ps
CPU time 8.01 seconds
Started Mar 26 12:50:34 PM PDT 24
Finished Mar 26 12:50:43 PM PDT 24
Peak memory 199992 kb
Host smart-4322d8c2-bdfe-4a7a-8978-d01fee9c0574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214699707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1214699707
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.3163250976
Short name T303
Test name
Test status
Simulation time 21268735 ps
CPU time 0.59 seconds
Started Mar 26 12:50:53 PM PDT 24
Finished Mar 26 12:50:55 PM PDT 24
Peak memory 195540 kb
Host smart-df9fd17b-6781-46a3-9541-78741c542d5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163250976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3163250976
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1309538648
Short name T498
Test name
Test status
Simulation time 2738350392 ps
CPU time 21.31 seconds
Started Mar 26 12:50:41 PM PDT 24
Finished Mar 26 12:51:04 PM PDT 24
Peak memory 203024 kb
Host smart-c4c3baec-b5e0-4a10-8d0a-16e255b21b7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1309538648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1309538648
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1900648718
Short name T471
Test name
Test status
Simulation time 20511189993 ps
CPU time 53.74 seconds
Started Mar 26 12:50:42 PM PDT 24
Finished Mar 26 12:51:36 PM PDT 24
Peak memory 199916 kb
Host smart-02621c7d-47ef-458c-9604-b32c0146d119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900648718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1900648718
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.4070553192
Short name T371
Test name
Test status
Simulation time 1666536925 ps
CPU time 27.2 seconds
Started Mar 26 12:50:42 PM PDT 24
Finished Mar 26 12:51:10 PM PDT 24
Peak memory 199896 kb
Host smart-2a22fd79-928c-4488-9dc8-9fa20b060bcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4070553192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.4070553192
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.3298037379
Short name T8
Test name
Test status
Simulation time 23044675718 ps
CPU time 114.22 seconds
Started Mar 26 12:50:47 PM PDT 24
Finished Mar 26 12:52:44 PM PDT 24
Peak memory 199988 kb
Host smart-2c982b6b-ab4d-4099-b2a3-9876e23c3f26
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298037379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3298037379
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.2427958166
Short name T242
Test name
Test status
Simulation time 165871222 ps
CPU time 9.61 seconds
Started Mar 26 12:50:35 PM PDT 24
Finished Mar 26 12:50:45 PM PDT 24
Peak memory 200264 kb
Host smart-5569344a-a4a1-4060-ab7c-8a190b8e3d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427958166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2427958166
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1977039215
Short name T463
Test name
Test status
Simulation time 828250713 ps
CPU time 5.94 seconds
Started Mar 26 12:50:35 PM PDT 24
Finished Mar 26 12:50:42 PM PDT 24
Peak memory 200024 kb
Host smart-509bebac-3392-46b3-bad9-fb43bd7b1ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977039215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1977039215
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.2642704518
Short name T87
Test name
Test status
Simulation time 89444191879 ps
CPU time 304.13 seconds
Started Mar 26 12:50:47 PM PDT 24
Finished Mar 26 12:55:53 PM PDT 24
Peak memory 220488 kb
Host smart-3935f154-e2b6-4110-b565-ab6f95a55993
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642704518 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2642704518
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_stress_all_with_rand_reset.365905191
Short name T14
Test name
Test status
Simulation time 63756811381 ps
CPU time 2305.19 seconds
Started Mar 26 12:50:53 PM PDT 24
Finished Mar 26 01:29:19 PM PDT 24
Peak memory 242140 kb
Host smart-7f5aedc8-d57e-48d9-9a81-1c8ff8ea358a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=365905191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all_with_rand_reset.365905191
Directory /workspace/12.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.2460595693
Short name T477
Test name
Test status
Simulation time 54240293 ps
CPU time 1.1 seconds
Started Mar 26 12:50:46 PM PDT 24
Finished Mar 26 12:50:49 PM PDT 24
Peak memory 199276 kb
Host smart-3aabe6bc-43df-4684-80be-51c8522f3132
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460595693 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.2460595693
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.3056107702
Short name T184
Test name
Test status
Simulation time 11689816524 ps
CPU time 502.34 seconds
Started Mar 26 12:50:49 PM PDT 24
Finished Mar 26 12:59:13 PM PDT 24
Peak memory 199912 kb
Host smart-665e76ce-f187-4ebf-8eef-2bdaea611782
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056107702 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.3056107702
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.1753602009
Short name T178
Test name
Test status
Simulation time 1632055272 ps
CPU time 24.4 seconds
Started Mar 26 12:50:46 PM PDT 24
Finished Mar 26 12:51:12 PM PDT 24
Peak memory 199908 kb
Host smart-36ae43ea-82e8-4159-9560-7fc32ccc5712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753602009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1753602009
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2445892977
Short name T538
Test name
Test status
Simulation time 23217787 ps
CPU time 0.56 seconds
Started Mar 26 12:50:48 PM PDT 24
Finished Mar 26 12:50:50 PM PDT 24
Peak memory 195136 kb
Host smart-ed6bc334-3fb9-4085-9f97-0f0c9b2c7c73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445892977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2445892977
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1230905799
Short name T289
Test name
Test status
Simulation time 731165293 ps
CPU time 28.34 seconds
Started Mar 26 12:50:49 PM PDT 24
Finished Mar 26 12:51:19 PM PDT 24
Peak memory 248444 kb
Host smart-d7166ff0-f056-440a-8c58-ed0e4f606555
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1230905799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1230905799
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2090544703
Short name T216
Test name
Test status
Simulation time 102623216 ps
CPU time 2.58 seconds
Started Mar 26 12:50:45 PM PDT 24
Finished Mar 26 12:50:48 PM PDT 24
Peak memory 199928 kb
Host smart-e1b3afce-074b-4d40-8143-c06e401e9235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090544703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2090544703
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1782300161
Short name T137
Test name
Test status
Simulation time 1536109107 ps
CPU time 93.45 seconds
Started Mar 26 12:50:48 PM PDT 24
Finished Mar 26 12:52:23 PM PDT 24
Peak memory 200044 kb
Host smart-f5fdc554-5a25-43b2-91ea-1bdf70002960
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1782300161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1782300161
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2922666763
Short name T271
Test name
Test status
Simulation time 4223305779 ps
CPU time 71.8 seconds
Started Mar 26 12:50:47 PM PDT 24
Finished Mar 26 12:52:01 PM PDT 24
Peak memory 199964 kb
Host smart-19bebd87-cdc7-464e-ad71-baf6aa8fefd1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922666763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2922666763
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.519368886
Short name T228
Test name
Test status
Simulation time 21042300912 ps
CPU time 79.69 seconds
Started Mar 26 12:50:53 PM PDT 24
Finished Mar 26 12:52:14 PM PDT 24
Peak memory 200084 kb
Host smart-e641557a-ecc2-4d11-a487-22542ae03e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519368886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.519368886
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.670139118
Short name T542
Test name
Test status
Simulation time 919001586 ps
CPU time 4.28 seconds
Started Mar 26 12:50:46 PM PDT 24
Finished Mar 26 12:50:54 PM PDT 24
Peak memory 200008 kb
Host smart-f385ab12-3f0e-4f8d-a743-5a7464ffccc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670139118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.670139118
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.3892532215
Short name T193
Test name
Test status
Simulation time 7888523735 ps
CPU time 178.47 seconds
Started Mar 26 12:50:48 PM PDT 24
Finished Mar 26 12:53:48 PM PDT 24
Peak memory 227740 kb
Host smart-5e2f6338-ce72-40d3-9405-744cf43da5fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892532215 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3892532215
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.2074669079
Short name T293
Test name
Test status
Simulation time 60858645 ps
CPU time 1.34 seconds
Started Mar 26 12:50:48 PM PDT 24
Finished Mar 26 12:50:51 PM PDT 24
Peak memory 199996 kb
Host smart-d9acbfd2-a333-449d-ae31-55056aa226fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074669079 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.2074669079
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.1568814345
Short name T557
Test name
Test status
Simulation time 32789144977 ps
CPU time 473.87 seconds
Started Mar 26 12:50:49 PM PDT 24
Finished Mar 26 12:58:45 PM PDT 24
Peak memory 199892 kb
Host smart-26903cb7-b687-4681-8536-2121a214c60d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568814345 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.1568814345
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3063669373
Short name T358
Test name
Test status
Simulation time 851663935 ps
CPU time 42.09 seconds
Started Mar 26 12:50:49 PM PDT 24
Finished Mar 26 12:51:33 PM PDT 24
Peak memory 199952 kb
Host smart-60f9817e-8537-4ffa-9338-38e9695c678a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063669373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3063669373
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2493754389
Short name T543
Test name
Test status
Simulation time 53116910 ps
CPU time 0.6 seconds
Started Mar 26 12:50:47 PM PDT 24
Finished Mar 26 12:50:50 PM PDT 24
Peak memory 195528 kb
Host smart-84fa42a6-aded-472f-b377-617f0bc28186
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493754389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2493754389
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1132977890
Short name T450
Test name
Test status
Simulation time 40344534 ps
CPU time 1.68 seconds
Started Mar 26 12:50:48 PM PDT 24
Finished Mar 26 12:50:52 PM PDT 24
Peak memory 199936 kb
Host smart-3fa5f8c0-9b1d-452a-a7df-35f0a676c498
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1132977890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1132977890
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.304876646
Short name T490
Test name
Test status
Simulation time 1766392836 ps
CPU time 6.54 seconds
Started Mar 26 12:50:47 PM PDT 24
Finished Mar 26 12:50:56 PM PDT 24
Peak memory 199884 kb
Host smart-ebe31421-e473-4655-af74-90ec65ca1b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304876646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.304876646
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.2758673743
Short name T158
Test name
Test status
Simulation time 2215062686 ps
CPU time 31.19 seconds
Started Mar 26 12:50:47 PM PDT 24
Finished Mar 26 12:51:20 PM PDT 24
Peak memory 200064 kb
Host smart-7852a722-9e1d-416c-9337-6d93503cfaf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2758673743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2758673743
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.514219875
Short name T52
Test name
Test status
Simulation time 4609527149 ps
CPU time 78 seconds
Started Mar 26 12:50:45 PM PDT 24
Finished Mar 26 12:52:03 PM PDT 24
Peak memory 199972 kb
Host smart-862d7809-63fc-4884-be50-c4f66011772d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514219875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.514219875
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.355003207
Short name T559
Test name
Test status
Simulation time 3082642947 ps
CPU time 21.58 seconds
Started Mar 26 12:50:47 PM PDT 24
Finished Mar 26 12:51:11 PM PDT 24
Peak memory 199992 kb
Host smart-2f340337-5dfd-45a5-9eb7-61c7ea24f766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355003207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.355003207
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3818170582
Short name T156
Test name
Test status
Simulation time 456605626 ps
CPU time 5.45 seconds
Started Mar 26 12:50:48 PM PDT 24
Finished Mar 26 12:50:53 PM PDT 24
Peak memory 200008 kb
Host smart-12e9aec6-dc1e-4519-8823-1c2c0affcb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818170582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3818170582
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.3638705843
Short name T474
Test name
Test status
Simulation time 118617951451 ps
CPU time 1610.38 seconds
Started Mar 26 12:50:48 PM PDT 24
Finished Mar 26 01:17:41 PM PDT 24
Peak memory 199972 kb
Host smart-5274e324-92c8-4159-b8b1-ab19c3ce25bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638705843 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3638705843
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.566866171
Short name T501
Test name
Test status
Simulation time 251728913 ps
CPU time 1.26 seconds
Started Mar 26 12:50:48 PM PDT 24
Finished Mar 26 12:50:51 PM PDT 24
Peak memory 199552 kb
Host smart-13aa9aa8-bdc7-4891-bb0c-7e45d4253563
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566866171 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_test_hmac_vectors.566866171
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.499163309
Short name T324
Test name
Test status
Simulation time 47981334176 ps
CPU time 453.1 seconds
Started Mar 26 12:50:46 PM PDT 24
Finished Mar 26 12:58:21 PM PDT 24
Peak memory 199936 kb
Host smart-32d590c2-441f-489e-bd6a-6cc294679671
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499163309 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.499163309
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.349062431
Short name T171
Test name
Test status
Simulation time 2440317915 ps
CPU time 28.27 seconds
Started Mar 26 12:50:49 PM PDT 24
Finished Mar 26 12:51:19 PM PDT 24
Peak memory 200076 kb
Host smart-ff417fe4-e320-48ab-ba8e-f7449a536fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349062431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.349062431
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.299305760
Short name T201
Test name
Test status
Simulation time 14569087 ps
CPU time 0.54 seconds
Started Mar 26 12:50:59 PM PDT 24
Finished Mar 26 12:51:00 PM PDT 24
Peak memory 194400 kb
Host smart-15b813a8-ee2c-4738-9e36-e5cfa67da9ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299305760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.299305760
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.2718635005
Short name T53
Test name
Test status
Simulation time 445680170 ps
CPU time 18.79 seconds
Started Mar 26 12:50:58 PM PDT 24
Finished Mar 26 12:51:17 PM PDT 24
Peak memory 215696 kb
Host smart-3ead0f6c-850a-49c2-8076-1467ce052fcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2718635005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2718635005
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.4293530643
Short name T395
Test name
Test status
Simulation time 568974659 ps
CPU time 7.88 seconds
Started Mar 26 12:50:57 PM PDT 24
Finished Mar 26 12:51:06 PM PDT 24
Peak memory 199852 kb
Host smart-b16f22d5-5bc2-41ba-837f-35673206d2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293530643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.4293530643
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.542719583
Short name T407
Test name
Test status
Simulation time 15430670 ps
CPU time 0.68 seconds
Started Mar 26 12:51:01 PM PDT 24
Finished Mar 26 12:51:02 PM PDT 24
Peak memory 197276 kb
Host smart-deb037ff-9515-43ea-b924-085b277b20e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=542719583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.542719583
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2459921275
Short name T82
Test name
Test status
Simulation time 7803008742 ps
CPU time 75.29 seconds
Started Mar 26 12:50:58 PM PDT 24
Finished Mar 26 12:52:14 PM PDT 24
Peak memory 199960 kb
Host smart-56b6d9d7-5cff-4001-ae8a-c0aa36ef2fa1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459921275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2459921275
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3254882287
Short name T517
Test name
Test status
Simulation time 359076793 ps
CPU time 5.07 seconds
Started Mar 26 12:50:58 PM PDT 24
Finished Mar 26 12:51:03 PM PDT 24
Peak memory 199828 kb
Host smart-c8a78c68-9542-49e3-8b32-f7f0c6b0636e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254882287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3254882287
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.897955054
Short name T595
Test name
Test status
Simulation time 115681983 ps
CPU time 0.74 seconds
Started Mar 26 12:50:59 PM PDT 24
Finished Mar 26 12:51:00 PM PDT 24
Peak memory 197048 kb
Host smart-3cf6ad7f-4e14-454f-9df1-6a574d2dc7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897955054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.897955054
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1634389002
Short name T504
Test name
Test status
Simulation time 148584963040 ps
CPU time 240.46 seconds
Started Mar 26 12:50:56 PM PDT 24
Finished Mar 26 12:54:57 PM PDT 24
Peak memory 200060 kb
Host smart-7d3282c3-fc37-4fa1-a426-2d99f23af21c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634389002 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1634389002
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.1327409882
Short name T396
Test name
Test status
Simulation time 503152762 ps
CPU time 1.37 seconds
Started Mar 26 12:50:57 PM PDT 24
Finished Mar 26 12:50:59 PM PDT 24
Peak memory 199976 kb
Host smart-7632b00b-d7e6-460a-a6ab-dac98885983e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327409882 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.1327409882
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.2799089496
Short name T198
Test name
Test status
Simulation time 30071506827 ps
CPU time 486.35 seconds
Started Mar 26 12:50:58 PM PDT 24
Finished Mar 26 12:59:05 PM PDT 24
Peak memory 200012 kb
Host smart-d9586a76-c9f8-47b2-93b2-e5e60460b6cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799089496 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.2799089496
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3833510206
Short name T421
Test name
Test status
Simulation time 30161892389 ps
CPU time 79.85 seconds
Started Mar 26 12:50:58 PM PDT 24
Finished Mar 26 12:52:18 PM PDT 24
Peak memory 199952 kb
Host smart-40f73665-adc4-4502-b0c3-cb8aed64fd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833510206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3833510206
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2682879069
Short name T523
Test name
Test status
Simulation time 13094096 ps
CPU time 0.58 seconds
Started Mar 26 12:51:00 PM PDT 24
Finished Mar 26 12:51:01 PM PDT 24
Peak memory 195428 kb
Host smart-23044bc0-96d2-4319-b24e-5ea0a2a0fb27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682879069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2682879069
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1103669376
Short name T562
Test name
Test status
Simulation time 2047128155 ps
CPU time 44.24 seconds
Started Mar 26 12:50:57 PM PDT 24
Finished Mar 26 12:51:42 PM PDT 24
Peak memory 233656 kb
Host smart-8f68d9bb-26bb-46fe-b4db-de73a88763d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1103669376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1103669376
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.4175752455
Short name T347
Test name
Test status
Simulation time 7307699694 ps
CPU time 74.52 seconds
Started Mar 26 12:51:02 PM PDT 24
Finished Mar 26 12:52:16 PM PDT 24
Peak memory 200080 kb
Host smart-cbb9c4d8-bd32-434e-be3a-94fe5de7e73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175752455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.4175752455
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.1722701218
Short name T554
Test name
Test status
Simulation time 1549166931 ps
CPU time 23.2 seconds
Started Mar 26 12:51:01 PM PDT 24
Finished Mar 26 12:51:24 PM PDT 24
Peak memory 199932 kb
Host smart-2a476be0-3d6f-47b4-bd26-a9f2ddfba134
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1722701218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1722701218
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.883411960
Short name T422
Test name
Test status
Simulation time 255404525 ps
CPU time 4.56 seconds
Started Mar 26 12:51:00 PM PDT 24
Finished Mar 26 12:51:04 PM PDT 24
Peak memory 199800 kb
Host smart-9375b142-eace-4ade-977e-af7619440776
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883411960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.883411960
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1546077264
Short name T44
Test name
Test status
Simulation time 1424261647 ps
CPU time 80.24 seconds
Started Mar 26 12:50:57 PM PDT 24
Finished Mar 26 12:52:18 PM PDT 24
Peak memory 199848 kb
Host smart-128a6be4-d994-422b-aab7-cfc91712f036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546077264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1546077264
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.2695636188
Short name T267
Test name
Test status
Simulation time 996343714 ps
CPU time 3.03 seconds
Started Mar 26 12:50:58 PM PDT 24
Finished Mar 26 12:51:01 PM PDT 24
Peak memory 200024 kb
Host smart-5da5d214-c1ed-4f6f-85c9-a9b24364099f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695636188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2695636188
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3140378139
Short name T275
Test name
Test status
Simulation time 84178938684 ps
CPU time 429.06 seconds
Started Mar 26 12:50:57 PM PDT 24
Finished Mar 26 12:58:07 PM PDT 24
Peak memory 199960 kb
Host smart-f68880c7-2dcb-4b2c-95d5-3be510c93fee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140378139 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3140378139
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.2689478437
Short name T458
Test name
Test status
Simulation time 513588269 ps
CPU time 1.12 seconds
Started Mar 26 12:50:57 PM PDT 24
Finished Mar 26 12:50:59 PM PDT 24
Peak memory 199352 kb
Host smart-3618a059-3ed9-4d83-a57b-216d13b4eff9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689478437 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.2689478437
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.1599317231
Short name T403
Test name
Test status
Simulation time 89019139427 ps
CPU time 556.25 seconds
Started Mar 26 12:50:58 PM PDT 24
Finished Mar 26 01:00:14 PM PDT 24
Peak memory 200044 kb
Host smart-61208212-cdcf-4d20-a386-45bf7be4415c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599317231 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.1599317231
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2653587760
Short name T382
Test name
Test status
Simulation time 14158477907 ps
CPU time 34.99 seconds
Started Mar 26 12:50:57 PM PDT 24
Finished Mar 26 12:51:33 PM PDT 24
Peak memory 199904 kb
Host smart-00284bbf-1b35-4e1d-b3ea-1dac76bb9084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653587760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2653587760
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.288852254
Short name T558
Test name
Test status
Simulation time 29878134 ps
CPU time 0.59 seconds
Started Mar 26 12:51:08 PM PDT 24
Finished Mar 26 12:51:09 PM PDT 24
Peak memory 195512 kb
Host smart-010d289a-9eff-4142-a625-daca605de074
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288852254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.288852254
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.807862440
Short name T284
Test name
Test status
Simulation time 83261044 ps
CPU time 3.03 seconds
Started Mar 26 12:50:58 PM PDT 24
Finished Mar 26 12:51:01 PM PDT 24
Peak memory 200012 kb
Host smart-d7e1801b-9713-48df-8b76-18213005d2e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=807862440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.807862440
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2013333393
Short name T527
Test name
Test status
Simulation time 1402793625 ps
CPU time 17.86 seconds
Started Mar 26 12:51:08 PM PDT 24
Finished Mar 26 12:51:26 PM PDT 24
Peak memory 199840 kb
Host smart-9246ea16-77eb-498a-931b-10b4406ac520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013333393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2013333393
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2277590306
Short name T578
Test name
Test status
Simulation time 772130386 ps
CPU time 46.31 seconds
Started Mar 26 12:51:10 PM PDT 24
Finished Mar 26 12:51:56 PM PDT 24
Peak memory 199936 kb
Host smart-66d3aa79-b69b-4607-aca6-45b972038f56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2277590306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2277590306
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1959896371
Short name T582
Test name
Test status
Simulation time 46574784931 ps
CPU time 217.51 seconds
Started Mar 26 12:51:08 PM PDT 24
Finished Mar 26 12:54:45 PM PDT 24
Peak memory 200020 kb
Host smart-91cde3f9-d4b5-4221-81fd-3aeeecbeff63
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959896371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1959896371
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2441893006
Short name T415
Test name
Test status
Simulation time 5272378440 ps
CPU time 78.63 seconds
Started Mar 26 12:51:01 PM PDT 24
Finished Mar 26 12:52:20 PM PDT 24
Peak memory 200104 kb
Host smart-6603289c-ff25-40d1-95d9-6c0f1594525f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441893006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2441893006
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2229293854
Short name T572
Test name
Test status
Simulation time 70761370 ps
CPU time 0.81 seconds
Started Mar 26 12:51:04 PM PDT 24
Finished Mar 26 12:51:04 PM PDT 24
Peak memory 198340 kb
Host smart-d7cdabc0-5259-4681-b683-6d607206a85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229293854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2229293854
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.1784466991
Short name T93
Test name
Test status
Simulation time 64203568 ps
CPU time 1.3 seconds
Started Mar 26 12:51:11 PM PDT 24
Finished Mar 26 12:51:13 PM PDT 24
Peak memory 199636 kb
Host smart-f59df8fb-778e-4f85-a504-bdf8a249c2b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784466991 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.1784466991
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.1519244235
Short name T311
Test name
Test status
Simulation time 23643594831 ps
CPU time 384.54 seconds
Started Mar 26 12:51:07 PM PDT 24
Finished Mar 26 12:57:32 PM PDT 24
Peak memory 200004 kb
Host smart-896b6818-32b2-4bd8-966f-771b52aef0e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519244235 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.1519244235
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3368518926
Short name T519
Test name
Test status
Simulation time 5767634038 ps
CPU time 77.85 seconds
Started Mar 26 12:51:08 PM PDT 24
Finished Mar 26 12:52:26 PM PDT 24
Peak memory 199988 kb
Host smart-77ac0994-dd8d-468d-b9c7-01e643fa4a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368518926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3368518926
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1940966830
Short name T185
Test name
Test status
Simulation time 23855659 ps
CPU time 0.64 seconds
Started Mar 26 12:51:09 PM PDT 24
Finished Mar 26 12:51:10 PM PDT 24
Peak memory 195068 kb
Host smart-1e23ac0d-4bed-4656-84e9-3b84bca0bf4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940966830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1940966830
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2954423623
Short name T239
Test name
Test status
Simulation time 1207951087 ps
CPU time 49.86 seconds
Started Mar 26 12:51:08 PM PDT 24
Finished Mar 26 12:51:58 PM PDT 24
Peak memory 216368 kb
Host smart-1bed4390-bdf2-4324-8916-9ebf9bb9ddb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2954423623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2954423623
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.160379870
Short name T240
Test name
Test status
Simulation time 1425821134 ps
CPU time 7.74 seconds
Started Mar 26 12:51:11 PM PDT 24
Finished Mar 26 12:51:19 PM PDT 24
Peak memory 200012 kb
Host smart-7e1980f5-241b-4fed-b0ae-e2b723d30717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160379870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.160379870
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2460124164
Short name T250
Test name
Test status
Simulation time 2921167139 ps
CPU time 43.2 seconds
Started Mar 26 12:51:07 PM PDT 24
Finished Mar 26 12:51:51 PM PDT 24
Peak memory 200116 kb
Host smart-12f46b2d-8b72-411f-8618-3687359316bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2460124164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2460124164
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.1531143768
Short name T410
Test name
Test status
Simulation time 1595738144 ps
CPU time 95.04 seconds
Started Mar 26 12:51:08 PM PDT 24
Finished Mar 26 12:52:44 PM PDT 24
Peak memory 200020 kb
Host smart-8479d3f8-fa77-40cd-9394-ba1653bbeb84
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531143768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1531143768
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.2006399069
Short name T270
Test name
Test status
Simulation time 21272995441 ps
CPU time 124.92 seconds
Started Mar 26 12:51:07 PM PDT 24
Finished Mar 26 12:53:12 PM PDT 24
Peak memory 199948 kb
Host smart-871f76be-98a5-4094-937e-025f3dbfe379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006399069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2006399069
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2961607742
Short name T164
Test name
Test status
Simulation time 1436489630 ps
CPU time 5.36 seconds
Started Mar 26 12:51:08 PM PDT 24
Finished Mar 26 12:51:13 PM PDT 24
Peak memory 199912 kb
Host smart-506c2bc6-fde1-4dfa-b3c0-ad7ceca67729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961607742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2961607742
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.4186833132
Short name T90
Test name
Test status
Simulation time 502661708346 ps
CPU time 1377.65 seconds
Started Mar 26 12:51:09 PM PDT 24
Finished Mar 26 01:14:07 PM PDT 24
Peak memory 226628 kb
Host smart-192572ef-9df3-45a5-b9af-747449d33cdb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186833132 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.4186833132
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.2754630299
Short name T507
Test name
Test status
Simulation time 33111203 ps
CPU time 1.15 seconds
Started Mar 26 12:51:07 PM PDT 24
Finished Mar 26 12:51:08 PM PDT 24
Peak memory 199864 kb
Host smart-634081ba-83b3-4fc0-a8da-d3e0c72126c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754630299 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.2754630299
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.3354598961
Short name T65
Test name
Test status
Simulation time 15616447579 ps
CPU time 429.41 seconds
Started Mar 26 12:51:08 PM PDT 24
Finished Mar 26 12:58:17 PM PDT 24
Peak memory 199944 kb
Host smart-2b8cbed5-66ae-429e-a60c-f75da450d6cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354598961 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.3354598961
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.1535627404
Short name T466
Test name
Test status
Simulation time 622142923 ps
CPU time 12.17 seconds
Started Mar 26 12:51:08 PM PDT 24
Finished Mar 26 12:51:21 PM PDT 24
Peak memory 200028 kb
Host smart-f59d09db-f8ab-4388-8687-ec13e0e390a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535627404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1535627404
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.3899743420
Short name T165
Test name
Test status
Simulation time 43726305 ps
CPU time 0.59 seconds
Started Mar 26 12:51:21 PM PDT 24
Finished Mar 26 12:51:22 PM PDT 24
Peak memory 195452 kb
Host smart-60c2b70a-8034-4680-919d-6c90ec2a2f7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899743420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3899743420
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3745904859
Short name T196
Test name
Test status
Simulation time 119968949 ps
CPU time 6.38 seconds
Started Mar 26 12:51:07 PM PDT 24
Finished Mar 26 12:51:13 PM PDT 24
Peak memory 216304 kb
Host smart-1aa61e51-3952-475e-9366-b359a4309ca7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3745904859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3745904859
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1172779321
Short name T378
Test name
Test status
Simulation time 8213367481 ps
CPU time 32.58 seconds
Started Mar 26 12:51:22 PM PDT 24
Finished Mar 26 12:51:54 PM PDT 24
Peak memory 199936 kb
Host smart-81364fad-3f82-4832-b002-9f179e3b5249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172779321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1172779321
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.4130105130
Short name T295
Test name
Test status
Simulation time 348182099 ps
CPU time 17.78 seconds
Started Mar 26 12:51:22 PM PDT 24
Finished Mar 26 12:51:40 PM PDT 24
Peak memory 199952 kb
Host smart-d51f21c8-8d12-4558-a40d-1f9551f0a9ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4130105130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.4130105130
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.431829471
Short name T192
Test name
Test status
Simulation time 6659420947 ps
CPU time 18.73 seconds
Started Mar 26 12:51:25 PM PDT 24
Finished Mar 26 12:51:44 PM PDT 24
Peak memory 200024 kb
Host smart-b380cfc7-0be3-4ab9-8307-cedc4b85a191
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431829471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.431829471
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1547127672
Short name T359
Test name
Test status
Simulation time 35407592538 ps
CPU time 125.88 seconds
Started Mar 26 12:51:08 PM PDT 24
Finished Mar 26 12:53:14 PM PDT 24
Peak memory 200000 kb
Host smart-f7a4943b-56fe-4ad6-8736-497630128c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547127672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1547127672
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.2579733640
Short name T515
Test name
Test status
Simulation time 87669628 ps
CPU time 2.74 seconds
Started Mar 26 12:51:09 PM PDT 24
Finished Mar 26 12:51:12 PM PDT 24
Peak memory 199940 kb
Host smart-f15780c2-16a9-4369-b21a-ef9bca51da6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579733640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2579733640
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1031918103
Short name T123
Test name
Test status
Simulation time 11533969516 ps
CPU time 593.8 seconds
Started Mar 26 12:51:23 PM PDT 24
Finished Mar 26 01:01:17 PM PDT 24
Peak memory 199956 kb
Host smart-a0b3e68b-1e73-41b9-87f4-9cdf2880332d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031918103 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1031918103
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.981560930
Short name T496
Test name
Test status
Simulation time 43883630 ps
CPU time 1.08 seconds
Started Mar 26 12:51:25 PM PDT 24
Finished Mar 26 12:51:27 PM PDT 24
Peak memory 199460 kb
Host smart-afbb89da-bceb-4bb5-9bb8-4566d72295ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981560930 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_hmac_vectors.981560930
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.2942246007
Short name T142
Test name
Test status
Simulation time 34101785511 ps
CPU time 485.38 seconds
Started Mar 26 12:51:24 PM PDT 24
Finished Mar 26 12:59:30 PM PDT 24
Peak memory 200024 kb
Host smart-7b312141-0abb-4aa5-befe-12c44c8a4b39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942246007 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.2942246007
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1175376392
Short name T522
Test name
Test status
Simulation time 9075854950 ps
CPU time 43.97 seconds
Started Mar 26 12:51:21 PM PDT 24
Finished Mar 26 12:52:06 PM PDT 24
Peak memory 199960 kb
Host smart-c55a0c0b-8ce8-41fc-b185-3a81f14f7e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175376392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1175376392
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.3160180854
Short name T525
Test name
Test status
Simulation time 13593512 ps
CPU time 0.58 seconds
Started Mar 26 12:49:56 PM PDT 24
Finished Mar 26 12:49:57 PM PDT 24
Peak memory 194496 kb
Host smart-82a8e9d9-ab80-4564-9b20-0ce1126117e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160180854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3160180854
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.2514282325
Short name T546
Test name
Test status
Simulation time 3889426127 ps
CPU time 41.11 seconds
Started Mar 26 12:49:56 PM PDT 24
Finished Mar 26 12:50:37 PM PDT 24
Peak memory 240308 kb
Host smart-b06a20a3-7581-4bb9-ac10-333f9e890099
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2514282325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.2514282325
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.1619593277
Short name T448
Test name
Test status
Simulation time 369939044 ps
CPU time 23.28 seconds
Started Mar 26 12:49:54 PM PDT 24
Finished Mar 26 12:50:18 PM PDT 24
Peak memory 200036 kb
Host smart-0c84de03-e859-4158-8312-74705d5c0ec9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1619593277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1619593277
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.1714151328
Short name T121
Test name
Test status
Simulation time 9122314368 ps
CPU time 140.36 seconds
Started Mar 26 12:49:56 PM PDT 24
Finished Mar 26 12:52:16 PM PDT 24
Peak memory 199868 kb
Host smart-80a1e552-b045-442f-a374-d5bb43231809
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714151328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.1714151328
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.1702300736
Short name T205
Test name
Test status
Simulation time 2405069468 ps
CPU time 24.27 seconds
Started Mar 26 12:49:56 PM PDT 24
Finished Mar 26 12:50:21 PM PDT 24
Peak memory 199920 kb
Host smart-40259035-79e5-4a6d-b339-d9dbe002e2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702300736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1702300736
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2154201327
Short name T33
Test name
Test status
Simulation time 56989175 ps
CPU time 0.85 seconds
Started Mar 26 12:49:55 PM PDT 24
Finished Mar 26 12:49:56 PM PDT 24
Peak memory 218132 kb
Host smart-72be673c-672c-404e-9522-a029db98c94f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154201327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2154201327
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2141532336
Short name T102
Test name
Test status
Simulation time 495430403 ps
CPU time 5.66 seconds
Started Mar 26 12:49:56 PM PDT 24
Finished Mar 26 12:50:02 PM PDT 24
Peak memory 199872 kb
Host smart-1a9a9503-31c6-44e3-93e2-ae6630d2c952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141532336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2141532336
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.1710749699
Short name T215
Test name
Test status
Simulation time 66514721886 ps
CPU time 1235.33 seconds
Started Mar 26 12:49:53 PM PDT 24
Finished Mar 26 01:10:29 PM PDT 24
Peak memory 199960 kb
Host smart-92661ca9-7951-4bf1-bd16-86381cced628
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710749699 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.1710749699
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.1268550034
Short name T427
Test name
Test status
Simulation time 72916624 ps
CPU time 1.08 seconds
Started Mar 26 12:49:55 PM PDT 24
Finished Mar 26 12:49:57 PM PDT 24
Peak memory 198660 kb
Host smart-4a664fd6-cac9-4e5f-a711-a338870f3f07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268550034 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.1268550034
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.589386619
Short name T143
Test name
Test status
Simulation time 30684017219 ps
CPU time 465.4 seconds
Started Mar 26 12:49:54 PM PDT 24
Finished Mar 26 12:57:40 PM PDT 24
Peak memory 199852 kb
Host smart-8ac0c0d3-3866-4c66-8f5e-64851b8dbb2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589386619 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.589386619
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1142601
Short name T406
Test name
Test status
Simulation time 36235766 ps
CPU time 0.59 seconds
Started Mar 26 12:51:32 PM PDT 24
Finished Mar 26 12:51:33 PM PDT 24
Peak memory 195524 kb
Host smart-e27d68c3-9bc4-43e2-8e25-0a46a98e71f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1142601
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1370746716
Short name T405
Test name
Test status
Simulation time 1805568310 ps
CPU time 65.15 seconds
Started Mar 26 12:51:24 PM PDT 24
Finished Mar 26 12:52:30 PM PDT 24
Peak memory 229508 kb
Host smart-b56774cb-388e-491b-80f2-9d8f1fb8b001
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1370746716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1370746716
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2821875979
Short name T530
Test name
Test status
Simulation time 1019259365 ps
CPU time 48.22 seconds
Started Mar 26 12:51:20 PM PDT 24
Finished Mar 26 12:52:08 PM PDT 24
Peak memory 199884 kb
Host smart-33aca55f-8093-44f5-b474-5bcd7f208950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821875979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2821875979
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.399526726
Short name T153
Test name
Test status
Simulation time 488637290 ps
CPU time 27.64 seconds
Started Mar 26 12:51:22 PM PDT 24
Finished Mar 26 12:51:49 PM PDT 24
Peak memory 199932 kb
Host smart-9a1b7ea9-9c64-4756-b0c3-a7329685a6f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=399526726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.399526726
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_long_msg.426952482
Short name T206
Test name
Test status
Simulation time 2492261882 ps
CPU time 75.42 seconds
Started Mar 26 12:51:21 PM PDT 24
Finished Mar 26 12:52:37 PM PDT 24
Peak memory 200040 kb
Host smart-0ae48002-d95b-4c1f-9902-174be168a360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426952482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.426952482
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1844931547
Short name T364
Test name
Test status
Simulation time 263709323 ps
CPU time 2.32 seconds
Started Mar 26 12:51:21 PM PDT 24
Finished Mar 26 12:51:23 PM PDT 24
Peak memory 200032 kb
Host smart-cc78ad8d-b8ea-4e46-a6e2-6a4fbd3e2dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844931547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1844931547
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.1566870429
Short name T86
Test name
Test status
Simulation time 78208056620 ps
CPU time 254.73 seconds
Started Mar 26 12:51:30 PM PDT 24
Finished Mar 26 12:55:45 PM PDT 24
Peak memory 199992 kb
Host smart-4a3d1d83-6e71-4ab5-832b-eb091c3eaa47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566870429 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1566870429
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.3818302347
Short name T204
Test name
Test status
Simulation time 30635188 ps
CPU time 1.02 seconds
Started Mar 26 12:51:32 PM PDT 24
Finished Mar 26 12:51:33 PM PDT 24
Peak memory 198732 kb
Host smart-1a638488-6b55-49c4-870d-bbc9313796e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818302347 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.3818302347
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.911273187
Short name T285
Test name
Test status
Simulation time 51007131557 ps
CPU time 458.58 seconds
Started Mar 26 12:51:32 PM PDT 24
Finished Mar 26 12:59:11 PM PDT 24
Peak memory 200072 kb
Host smart-612c49fb-eaa9-4e41-ab1a-7949b292c16e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911273187 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.911273187
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.4235526560
Short name T214
Test name
Test status
Simulation time 4469108867 ps
CPU time 66.08 seconds
Started Mar 26 12:51:32 PM PDT 24
Finished Mar 26 12:52:39 PM PDT 24
Peak memory 199996 kb
Host smart-bca7d3ab-a0b9-4a0e-8f00-06bf187bcdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235526560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.4235526560
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2719450049
Short name T373
Test name
Test status
Simulation time 42909361 ps
CPU time 0.64 seconds
Started Mar 26 12:51:35 PM PDT 24
Finished Mar 26 12:51:35 PM PDT 24
Peak memory 195516 kb
Host smart-b4d46d95-23ba-42df-99d7-29ea4e8516f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719450049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2719450049
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1235779357
Short name T413
Test name
Test status
Simulation time 4316025447 ps
CPU time 16.19 seconds
Started Mar 26 12:51:32 PM PDT 24
Finished Mar 26 12:51:48 PM PDT 24
Peak memory 215948 kb
Host smart-9ea3f78f-f040-4c6b-bbd3-e9828de6d0df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1235779357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1235779357
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.353664392
Short name T264
Test name
Test status
Simulation time 1159529977 ps
CPU time 29.05 seconds
Started Mar 26 12:51:33 PM PDT 24
Finished Mar 26 12:52:02 PM PDT 24
Peak memory 200036 kb
Host smart-15dc9287-c398-4a43-97fb-7fa1d887abdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353664392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.353664392
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.505342284
Short name T149
Test name
Test status
Simulation time 1497561376 ps
CPU time 90.97 seconds
Started Mar 26 12:51:32 PM PDT 24
Finished Mar 26 12:53:03 PM PDT 24
Peak memory 200012 kb
Host smart-e77d2fa3-fd2c-47ae-8599-c2999af3c156
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=505342284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.505342284
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1478908820
Short name T467
Test name
Test status
Simulation time 2603824087 ps
CPU time 144.78 seconds
Started Mar 26 12:51:33 PM PDT 24
Finished Mar 26 12:53:58 PM PDT 24
Peak memory 199980 kb
Host smart-0f409b20-d3c3-4a59-a707-2b8a7d9e6f38
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478908820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1478908820
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.4063555570
Short name T7
Test name
Test status
Simulation time 26659916262 ps
CPU time 92.95 seconds
Started Mar 26 12:51:35 PM PDT 24
Finished Mar 26 12:53:08 PM PDT 24
Peak memory 200068 kb
Host smart-c55cd729-9756-4ef9-afa9-95ca560b7581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063555570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.4063555570
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.4181229956
Short name T140
Test name
Test status
Simulation time 882359418 ps
CPU time 2.84 seconds
Started Mar 26 12:51:31 PM PDT 24
Finished Mar 26 12:51:34 PM PDT 24
Peak memory 199888 kb
Host smart-cc074d21-7fd3-44bc-b84f-794ed7f824a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181229956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.4181229956
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1645731149
Short name T593
Test name
Test status
Simulation time 2065918547 ps
CPU time 38.51 seconds
Started Mar 26 12:51:31 PM PDT 24
Finished Mar 26 12:52:10 PM PDT 24
Peak memory 199996 kb
Host smart-cb377d4a-aa59-4c4e-b053-51769a71bb5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645731149 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1645731149
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.2730899538
Short name T146
Test name
Test status
Simulation time 163244760 ps
CPU time 1 seconds
Started Mar 26 12:51:31 PM PDT 24
Finished Mar 26 12:51:32 PM PDT 24
Peak memory 198932 kb
Host smart-3395b03d-5105-4b67-8799-500fe4120deb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730899538 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.2730899538
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.2636497444
Short name T169
Test name
Test status
Simulation time 29194708410 ps
CPU time 415.09 seconds
Started Mar 26 12:51:31 PM PDT 24
Finished Mar 26 12:58:26 PM PDT 24
Peak memory 199888 kb
Host smart-94180960-2014-469d-a89d-8d28a2262bc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636497444 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.2636497444
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.1055044488
Short name T505
Test name
Test status
Simulation time 1608289875 ps
CPU time 60.35 seconds
Started Mar 26 12:51:32 PM PDT 24
Finished Mar 26 12:52:32 PM PDT 24
Peak memory 199944 kb
Host smart-abf5fcef-f097-4b89-9f0e-9707359b45b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055044488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1055044488
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.879731962
Short name T23
Test name
Test status
Simulation time 38087407 ps
CPU time 0.57 seconds
Started Mar 26 12:51:31 PM PDT 24
Finished Mar 26 12:51:31 PM PDT 24
Peak memory 195452 kb
Host smart-dbf05874-3ec0-48e9-9e4f-3c0d2292ccca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879731962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.879731962
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3700126874
Short name T180
Test name
Test status
Simulation time 2631479182 ps
CPU time 26.65 seconds
Started Mar 26 12:51:31 PM PDT 24
Finished Mar 26 12:51:57 PM PDT 24
Peak memory 224640 kb
Host smart-dbc1a512-4c9a-4ad8-985e-ce2e1e5d7e58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3700126874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3700126874
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1974184391
Short name T213
Test name
Test status
Simulation time 920326785 ps
CPU time 48.58 seconds
Started Mar 26 12:51:32 PM PDT 24
Finished Mar 26 12:52:21 PM PDT 24
Peak memory 199924 kb
Host smart-594b3f89-4da8-4e58-9616-b413773e7a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974184391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1974184391
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1772323984
Short name T150
Test name
Test status
Simulation time 1672886513 ps
CPU time 96.95 seconds
Started Mar 26 12:51:33 PM PDT 24
Finished Mar 26 12:53:10 PM PDT 24
Peak memory 199892 kb
Host smart-264c7923-d61a-4a5d-99ee-0b4aa5b8cbbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1772323984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1772323984
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.276459851
Short name T18
Test name
Test status
Simulation time 20649417237 ps
CPU time 96.54 seconds
Started Mar 26 12:51:32 PM PDT 24
Finished Mar 26 12:53:08 PM PDT 24
Peak memory 200064 kb
Host smart-8d7247cb-6eb4-4f48-960b-8b61ed8ead89
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276459851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.276459851
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2488316158
Short name T547
Test name
Test status
Simulation time 8247870715 ps
CPU time 79.34 seconds
Started Mar 26 12:51:33 PM PDT 24
Finished Mar 26 12:52:52 PM PDT 24
Peak memory 199900 kb
Host smart-52def868-1b56-4b59-ba84-f71b00ceb84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488316158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2488316158
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2137478215
Short name T177
Test name
Test status
Simulation time 1074038761 ps
CPU time 3.72 seconds
Started Mar 26 12:51:34 PM PDT 24
Finished Mar 26 12:51:38 PM PDT 24
Peak memory 200016 kb
Host smart-240bbb60-7caf-4b3c-b7a8-031edc3b16d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137478215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2137478215
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.548374152
Short name T457
Test name
Test status
Simulation time 138505516238 ps
CPU time 1038.07 seconds
Started Mar 26 12:51:33 PM PDT 24
Finished Mar 26 01:08:51 PM PDT 24
Peak memory 222988 kb
Host smart-55d3806c-9c6a-4bce-9dba-fef06d0d8590
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548374152 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.548374152
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.1067084565
Short name T75
Test name
Test status
Simulation time 123792910 ps
CPU time 1.26 seconds
Started Mar 26 12:51:31 PM PDT 24
Finished Mar 26 12:51:32 PM PDT 24
Peak memory 199652 kb
Host smart-b856fbb2-3094-40e6-b31f-c033daad95e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067084565 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.1067084565
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.2916789416
Short name T420
Test name
Test status
Simulation time 156846504189 ps
CPU time 501.14 seconds
Started Mar 26 12:51:32 PM PDT 24
Finished Mar 26 12:59:54 PM PDT 24
Peak memory 199944 kb
Host smart-689749a1-d8aa-4abd-9181-0250395eb175
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916789416 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.2916789416
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.4035513481
Short name T541
Test name
Test status
Simulation time 65418910953 ps
CPU time 86.27 seconds
Started Mar 26 12:51:33 PM PDT 24
Finished Mar 26 12:53:00 PM PDT 24
Peak memory 199920 kb
Host smart-e6106247-7bcd-40a3-b514-28f3d4041ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035513481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.4035513481
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.528305607
Short name T302
Test name
Test status
Simulation time 13093637 ps
CPU time 0.59 seconds
Started Mar 26 12:51:45 PM PDT 24
Finished Mar 26 12:51:46 PM PDT 24
Peak memory 195640 kb
Host smart-bafd1b7d-a19b-4dc4-a287-896a45b2de35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528305607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.528305607
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1559628619
Short name T233
Test name
Test status
Simulation time 3411341863 ps
CPU time 35.01 seconds
Started Mar 26 12:51:45 PM PDT 24
Finished Mar 26 12:52:21 PM PDT 24
Peak memory 241284 kb
Host smart-0f02037d-3b45-4846-ae4b-87f10bbfca1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1559628619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1559628619
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1852487969
Short name T241
Test name
Test status
Simulation time 3265207325 ps
CPU time 46.92 seconds
Started Mar 26 12:51:46 PM PDT 24
Finished Mar 26 12:52:34 PM PDT 24
Peak memory 199972 kb
Host smart-d9ce9b64-6015-4fb4-8376-86473dfc3fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852487969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1852487969
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2139986622
Short name T429
Test name
Test status
Simulation time 1972559408 ps
CPU time 122.12 seconds
Started Mar 26 12:51:45 PM PDT 24
Finished Mar 26 12:53:47 PM PDT 24
Peak memory 200044 kb
Host smart-26a59dfb-e828-4219-bc51-707f5bf54f7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2139986622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2139986622
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3074185219
Short name T189
Test name
Test status
Simulation time 1354619213 ps
CPU time 26.06 seconds
Started Mar 26 12:51:46 PM PDT 24
Finished Mar 26 12:52:14 PM PDT 24
Peak memory 200020 kb
Host smart-759b5eba-5d14-4a4b-a059-fed17fb6ddb5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074185219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3074185219
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3700170001
Short name T334
Test name
Test status
Simulation time 7896749532 ps
CPU time 49.94 seconds
Started Mar 26 12:51:32 PM PDT 24
Finished Mar 26 12:52:22 PM PDT 24
Peak memory 200080 kb
Host smart-52b72594-daae-4a8c-9638-15c017cf5385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700170001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3700170001
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2738995496
Short name T246
Test name
Test status
Simulation time 882167489 ps
CPU time 3.22 seconds
Started Mar 26 12:51:30 PM PDT 24
Finished Mar 26 12:51:34 PM PDT 24
Peak memory 199868 kb
Host smart-2f1cc23c-a340-4b7c-9898-99dbd9b95d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738995496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2738995496
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.1612193282
Short name T339
Test name
Test status
Simulation time 40605500042 ps
CPU time 545.63 seconds
Started Mar 26 12:51:46 PM PDT 24
Finished Mar 26 01:00:54 PM PDT 24
Peak memory 199944 kb
Host smart-864ffb30-5a20-47a7-8892-257113813525
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612193282 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1612193282
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.4036984484
Short name T351
Test name
Test status
Simulation time 40460011 ps
CPU time 0.98 seconds
Started Mar 26 12:51:47 PM PDT 24
Finished Mar 26 12:51:49 PM PDT 24
Peak memory 198804 kb
Host smart-2e32f0d4-d765-4a44-b670-7174a913affb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036984484 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.4036984484
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.917249965
Short name T200
Test name
Test status
Simulation time 8220787479 ps
CPU time 494.23 seconds
Started Mar 26 12:51:46 PM PDT 24
Finished Mar 26 01:00:02 PM PDT 24
Peak memory 199872 kb
Host smart-51a27d96-8e62-430d-a18c-1678b102afd4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917249965 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.917249965
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.459539724
Short name T39
Test name
Test status
Simulation time 1431201519 ps
CPU time 27.03 seconds
Started Mar 26 12:51:43 PM PDT 24
Finished Mar 26 12:52:11 PM PDT 24
Peak memory 199896 kb
Host smart-dddf4084-b1ac-485c-b1bf-fe9f41ef4cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459539724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.459539724
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.4094173715
Short name T537
Test name
Test status
Simulation time 40356789 ps
CPU time 0.59 seconds
Started Mar 26 12:51:45 PM PDT 24
Finished Mar 26 12:51:46 PM PDT 24
Peak memory 195136 kb
Host smart-4260876a-5528-4072-984f-4dfd875fc1fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094173715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.4094173715
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.4202761343
Short name T502
Test name
Test status
Simulation time 2866070399 ps
CPU time 16.62 seconds
Started Mar 26 12:51:46 PM PDT 24
Finished Mar 26 12:52:04 PM PDT 24
Peak memory 208092 kb
Host smart-4e933d67-d303-4595-a240-217afe5dc089
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4202761343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.4202761343
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2934691324
Short name T393
Test name
Test status
Simulation time 4718587210 ps
CPU time 55.56 seconds
Started Mar 26 12:51:43 PM PDT 24
Finished Mar 26 12:52:38 PM PDT 24
Peak memory 200080 kb
Host smart-d5faa444-b3ce-41e1-a398-9406c4e3fa7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934691324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2934691324
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.183051202
Short name T387
Test name
Test status
Simulation time 4294589714 ps
CPU time 130.27 seconds
Started Mar 26 12:51:47 PM PDT 24
Finished Mar 26 12:53:58 PM PDT 24
Peak memory 200056 kb
Host smart-21e87228-2cc4-4293-b6f0-756f7b99a896
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=183051202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.183051202
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.1525063916
Short name T59
Test name
Test status
Simulation time 7738790549 ps
CPU time 97.56 seconds
Started Mar 26 12:51:45 PM PDT 24
Finished Mar 26 12:53:23 PM PDT 24
Peak memory 199892 kb
Host smart-86b02c53-fef4-4b4e-8d3c-2b33028e855a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525063916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1525063916
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2996962078
Short name T584
Test name
Test status
Simulation time 30940220269 ps
CPU time 51.6 seconds
Started Mar 26 12:51:44 PM PDT 24
Finished Mar 26 12:52:36 PM PDT 24
Peak memory 199892 kb
Host smart-04b12a51-d6c0-487d-86b8-534e15da0018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996962078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2996962078
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1241513207
Short name T45
Test name
Test status
Simulation time 165811007 ps
CPU time 5.01 seconds
Started Mar 26 12:51:43 PM PDT 24
Finished Mar 26 12:51:49 PM PDT 24
Peak memory 199996 kb
Host smart-2d2bcee9-5d69-484b-b632-ac946e2bb094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241513207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1241513207
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.52992786
Short name T570
Test name
Test status
Simulation time 27025051285 ps
CPU time 1222.04 seconds
Started Mar 26 12:51:46 PM PDT 24
Finished Mar 26 01:12:10 PM PDT 24
Peak memory 236476 kb
Host smart-46468939-1123-4b5a-9763-70ecca383774
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52992786 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.52992786
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.888155892
Short name T247
Test name
Test status
Simulation time 291714543 ps
CPU time 1.24 seconds
Started Mar 26 12:51:47 PM PDT 24
Finished Mar 26 12:51:49 PM PDT 24
Peak memory 199964 kb
Host smart-8c628265-d3cc-438d-ac4b-6304951cb8d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888155892 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.hmac_test_hmac_vectors.888155892
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.3119402517
Short name T430
Test name
Test status
Simulation time 13571558561 ps
CPU time 384.98 seconds
Started Mar 26 12:51:46 PM PDT 24
Finished Mar 26 12:58:13 PM PDT 24
Peak memory 199916 kb
Host smart-d364ee35-e7fd-4512-99e0-d9f90d07644d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119402517 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.3119402517
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.1292862465
Short name T418
Test name
Test status
Simulation time 1667885980 ps
CPU time 30.74 seconds
Started Mar 26 12:51:47 PM PDT 24
Finished Mar 26 12:52:18 PM PDT 24
Peak memory 199944 kb
Host smart-5abeeda9-ffca-46fb-a3c9-8699e9e846c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292862465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1292862465
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.546171674
Short name T259
Test name
Test status
Simulation time 145455073 ps
CPU time 0.6 seconds
Started Mar 26 12:51:57 PM PDT 24
Finished Mar 26 12:51:59 PM PDT 24
Peak memory 195524 kb
Host smart-36cdd195-3688-49a8-a9f0-49b46560955c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546171674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.546171674
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.4288142289
Short name T42
Test name
Test status
Simulation time 15984562473 ps
CPU time 43.47 seconds
Started Mar 26 12:51:46 PM PDT 24
Finished Mar 26 12:52:31 PM PDT 24
Peak memory 216060 kb
Host smart-d35d0076-6151-4a7e-8c39-0617ab164a81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4288142289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.4288142289
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3266944317
Short name T120
Test name
Test status
Simulation time 786224587 ps
CPU time 19.48 seconds
Started Mar 26 12:51:46 PM PDT 24
Finished Mar 26 12:52:07 PM PDT 24
Peak memory 199916 kb
Host smart-b06fc749-6203-4a48-840b-f322f68370dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266944317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3266944317
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.2032706933
Short name T451
Test name
Test status
Simulation time 7235571907 ps
CPU time 90.39 seconds
Started Mar 26 12:51:46 PM PDT 24
Finished Mar 26 12:53:18 PM PDT 24
Peak memory 200044 kb
Host smart-c612f246-094a-43e7-8e60-8a2904cdd7be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2032706933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2032706933
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.863440228
Short name T32
Test name
Test status
Simulation time 1531832412 ps
CPU time 20.21 seconds
Started Mar 26 12:51:46 PM PDT 24
Finished Mar 26 12:52:08 PM PDT 24
Peak memory 199848 kb
Host smart-13808625-b1ae-4815-b558-0eefeed0cd08
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863440228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.863440228
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2871022510
Short name T43
Test name
Test status
Simulation time 5213985057 ps
CPU time 81.11 seconds
Started Mar 26 12:51:47 PM PDT 24
Finished Mar 26 12:53:09 PM PDT 24
Peak memory 200080 kb
Host smart-385a332a-8232-452f-982d-8382655011da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871022510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2871022510
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.1716063522
Short name T186
Test name
Test status
Simulation time 607861964 ps
CPU time 4.87 seconds
Started Mar 26 12:51:45 PM PDT 24
Finished Mar 26 12:51:50 PM PDT 24
Peak memory 199920 kb
Host smart-07f1e59c-1f07-4bbd-9c8f-42aae94dcdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716063522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1716063522
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.1185776148
Short name T245
Test name
Test status
Simulation time 11688096956 ps
CPU time 43.26 seconds
Started Mar 26 12:51:58 PM PDT 24
Finished Mar 26 12:52:42 PM PDT 24
Peak memory 216024 kb
Host smart-d90959f1-3cb0-4b60-9b5a-1c2c8ffe1b80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185776148 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1185776148
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_stress_all_with_rand_reset.1220485189
Short name T11
Test name
Test status
Simulation time 87202680930 ps
CPU time 1179.5 seconds
Started Mar 26 12:51:56 PM PDT 24
Finished Mar 26 01:11:36 PM PDT 24
Peak memory 248940 kb
Host smart-d32b0f8a-c364-4de3-943f-88fa43843ed3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1220485189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all_with_rand_reset.1220485189
Directory /workspace/25.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.511272856
Short name T385
Test name
Test status
Simulation time 102137873 ps
CPU time 1.04 seconds
Started Mar 26 12:51:56 PM PDT 24
Finished Mar 26 12:51:57 PM PDT 24
Peak memory 199300 kb
Host smart-16b7406b-ffeb-4e9e-b9a6-cb85a1b011b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511272856 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.hmac_test_hmac_vectors.511272856
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.2354982364
Short name T473
Test name
Test status
Simulation time 41874944139 ps
CPU time 491.73 seconds
Started Mar 26 12:51:47 PM PDT 24
Finished Mar 26 12:59:59 PM PDT 24
Peak memory 200008 kb
Host smart-5704533e-b200-48f8-b762-660a94b64828
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354982364 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.2354982364
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.780663273
Short name T372
Test name
Test status
Simulation time 2516159257 ps
CPU time 49.6 seconds
Started Mar 26 12:51:47 PM PDT 24
Finished Mar 26 12:52:38 PM PDT 24
Peak memory 200076 kb
Host smart-b11407f4-1b34-4de7-b328-bbc0a7436969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780663273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.780663273
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.4292852551
Short name T287
Test name
Test status
Simulation time 101572774 ps
CPU time 0.6 seconds
Started Mar 26 12:51:55 PM PDT 24
Finished Mar 26 12:51:56 PM PDT 24
Peak memory 195404 kb
Host smart-cab4cf55-f6f8-4dee-9baa-1b6ae9a12268
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292852551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.4292852551
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.1213061038
Short name T265
Test name
Test status
Simulation time 210059416 ps
CPU time 7.65 seconds
Started Mar 26 12:51:58 PM PDT 24
Finished Mar 26 12:52:06 PM PDT 24
Peak memory 199868 kb
Host smart-00f2ec50-bc53-4b74-8cd8-939a4811ca8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1213061038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1213061038
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1718070314
Short name T361
Test name
Test status
Simulation time 247285957 ps
CPU time 1.6 seconds
Started Mar 26 12:51:56 PM PDT 24
Finished Mar 26 12:51:58 PM PDT 24
Peak memory 200184 kb
Host smart-6109fc46-c41e-4a2a-9ca0-84befb5880e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718070314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1718070314
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3487795959
Short name T514
Test name
Test status
Simulation time 2611289589 ps
CPU time 149.59 seconds
Started Mar 26 12:51:57 PM PDT 24
Finished Mar 26 12:54:28 PM PDT 24
Peak memory 200084 kb
Host smart-b2463420-2f1e-4dd7-9efc-32f78f9aaed5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3487795959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3487795959
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.185312574
Short name T323
Test name
Test status
Simulation time 6499627109 ps
CPU time 88.09 seconds
Started Mar 26 12:51:55 PM PDT 24
Finished Mar 26 12:53:23 PM PDT 24
Peak memory 200016 kb
Host smart-1088bbe0-893a-4a6a-abc8-fcb0cf6e5238
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185312574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.185312574
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.105385584
Short name T352
Test name
Test status
Simulation time 7973766754 ps
CPU time 41.71 seconds
Started Mar 26 12:51:55 PM PDT 24
Finished Mar 26 12:52:37 PM PDT 24
Peak memory 199988 kb
Host smart-20217b7a-c18e-4e5b-ac5c-2e2f5ec5e42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105385584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.105385584
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.1150526932
Short name T343
Test name
Test status
Simulation time 803196117 ps
CPU time 6.49 seconds
Started Mar 26 12:51:55 PM PDT 24
Finished Mar 26 12:52:02 PM PDT 24
Peak memory 199992 kb
Host smart-2b69e305-6c76-467d-ab54-07068a88989d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150526932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1150526932
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.2831085223
Short name T85
Test name
Test status
Simulation time 111189200291 ps
CPU time 477.27 seconds
Started Mar 26 12:51:58 PM PDT 24
Finished Mar 26 12:59:56 PM PDT 24
Peak memory 230724 kb
Host smart-9d5710a6-4af9-45ac-92e8-fff8e0a71720
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831085223 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.2831085223
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.3760549462
Short name T425
Test name
Test status
Simulation time 101684938 ps
CPU time 0.99 seconds
Started Mar 26 12:51:56 PM PDT 24
Finished Mar 26 12:51:57 PM PDT 24
Peak memory 199288 kb
Host smart-19a1ebf1-ec5d-4777-b3a8-a1e49565c6a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760549462 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.3760549462
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.3672537847
Short name T147
Test name
Test status
Simulation time 8253438519 ps
CPU time 456.2 seconds
Started Mar 26 12:51:57 PM PDT 24
Finished Mar 26 12:59:33 PM PDT 24
Peak memory 199932 kb
Host smart-98e376c3-f006-445b-a536-7a0005f58b70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672537847 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.3672537847
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3040588337
Short name T191
Test name
Test status
Simulation time 6605003348 ps
CPU time 98.79 seconds
Started Mar 26 12:51:58 PM PDT 24
Finished Mar 26 12:53:38 PM PDT 24
Peak memory 200052 kb
Host smart-8b64c4af-2e30-4e1c-8509-a27d072d60c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040588337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3040588337
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1039690932
Short name T261
Test name
Test status
Simulation time 91811068 ps
CPU time 0.56 seconds
Started Mar 26 12:52:09 PM PDT 24
Finished Mar 26 12:52:10 PM PDT 24
Peak memory 194400 kb
Host smart-bcb1923c-0c01-4337-825f-ae76717385a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039690932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1039690932
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.381686901
Short name T21
Test name
Test status
Simulation time 5931422673 ps
CPU time 39.82 seconds
Started Mar 26 12:51:55 PM PDT 24
Finished Mar 26 12:52:35 PM PDT 24
Peak memory 224404 kb
Host smart-4c7ec209-d5d4-4339-a1e2-b0afbded93ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=381686901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.381686901
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3174996893
Short name T272
Test name
Test status
Simulation time 4861547247 ps
CPU time 63.47 seconds
Started Mar 26 12:51:56 PM PDT 24
Finished Mar 26 12:53:00 PM PDT 24
Peak memory 199948 kb
Host smart-fa168fe1-2347-4ffa-9c91-5193853d3a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174996893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3174996893
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1070603763
Short name T300
Test name
Test status
Simulation time 9971093213 ps
CPU time 70.41 seconds
Started Mar 26 12:51:55 PM PDT 24
Finished Mar 26 12:53:06 PM PDT 24
Peak memory 200004 kb
Host smart-0a6da917-350d-4763-bee8-51949b726410
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1070603763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1070603763
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.33242363
Short name T417
Test name
Test status
Simulation time 9534518900 ps
CPU time 130.35 seconds
Started Mar 26 12:51:57 PM PDT 24
Finished Mar 26 12:54:09 PM PDT 24
Peak memory 199988 kb
Host smart-1784ae1e-9689-4a64-a943-cbfe8b846242
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33242363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.33242363
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.503304282
Short name T148
Test name
Test status
Simulation time 25626948285 ps
CPU time 54.77 seconds
Started Mar 26 12:51:58 PM PDT 24
Finished Mar 26 12:52:54 PM PDT 24
Peak memory 200000 kb
Host smart-128e8380-3d23-45a8-9d4a-dcf8f673559a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503304282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.503304282
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.3723129771
Short name T348
Test name
Test status
Simulation time 383094269 ps
CPU time 4.51 seconds
Started Mar 26 12:51:55 PM PDT 24
Finished Mar 26 12:52:00 PM PDT 24
Peak memory 199920 kb
Host smart-d9d7ffd1-c0c4-40a2-aa86-87e3d3ecb5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723129771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3723129771
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.1336249
Short name T569
Test name
Test status
Simulation time 138013303963 ps
CPU time 437.66 seconds
Started Mar 26 12:52:10 PM PDT 24
Finished Mar 26 12:59:28 PM PDT 24
Peak memory 200100 kb
Host smart-f49253a5-0277-4fe1-b8a5-6f0584dded01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336249 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.1336249
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.3616628512
Short name T163
Test name
Test status
Simulation time 41426247 ps
CPU time 1.03 seconds
Started Mar 26 12:52:10 PM PDT 24
Finished Mar 26 12:52:11 PM PDT 24
Peak memory 199232 kb
Host smart-0a190242-d32e-4fb3-8a07-76eb5eeda464
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616628512 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.3616628512
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.2590153506
Short name T455
Test name
Test status
Simulation time 304377253001 ps
CPU time 459.83 seconds
Started Mar 26 12:52:09 PM PDT 24
Finished Mar 26 12:59:49 PM PDT 24
Peak memory 199944 kb
Host smart-db1c290b-db21-4c86-ac61-b00a9c408116
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590153506 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.2590153506
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.314716120
Short name T386
Test name
Test status
Simulation time 5320181659 ps
CPU time 76.68 seconds
Started Mar 26 12:52:10 PM PDT 24
Finished Mar 26 12:53:27 PM PDT 24
Peak memory 200076 kb
Host smart-85c14b25-76b5-4a5a-acf8-417da7a43a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314716120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.314716120
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1093393088
Short name T390
Test name
Test status
Simulation time 28187538 ps
CPU time 0.57 seconds
Started Mar 26 12:52:11 PM PDT 24
Finished Mar 26 12:52:11 PM PDT 24
Peak memory 195380 kb
Host smart-b429a856-2d36-4c56-8a9b-53e0128e135a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093393088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1093393088
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3255282998
Short name T327
Test name
Test status
Simulation time 3100682532 ps
CPU time 23.21 seconds
Started Mar 26 12:52:10 PM PDT 24
Finished Mar 26 12:52:33 PM PDT 24
Peak memory 208204 kb
Host smart-2e043243-aa86-4ab5-9b67-966d8ecd321b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3255282998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3255282998
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1625017143
Short name T207
Test name
Test status
Simulation time 476992540 ps
CPU time 24.57 seconds
Started Mar 26 12:52:08 PM PDT 24
Finished Mar 26 12:52:33 PM PDT 24
Peak memory 199956 kb
Host smart-909265ae-1513-46bb-85ec-f9aabc96e948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625017143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1625017143
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3213849690
Short name T506
Test name
Test status
Simulation time 14935963927 ps
CPU time 52.26 seconds
Started Mar 26 12:52:08 PM PDT 24
Finished Mar 26 12:53:00 PM PDT 24
Peak memory 200008 kb
Host smart-f2070f87-0635-4961-ae72-0c33ea600134
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3213849690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3213849690
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.2120488244
Short name T252
Test name
Test status
Simulation time 2078339494 ps
CPU time 31.3 seconds
Started Mar 26 12:52:09 PM PDT 24
Finished Mar 26 12:52:40 PM PDT 24
Peak memory 200036 kb
Host smart-547da480-80a2-4bd6-8b57-d81b416d9b8a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120488244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.2120488244
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1489191780
Short name T439
Test name
Test status
Simulation time 1191568176 ps
CPU time 67 seconds
Started Mar 26 12:52:09 PM PDT 24
Finished Mar 26 12:53:16 PM PDT 24
Peak memory 199856 kb
Host smart-feeb99b7-36ed-4b42-a1a2-797bf46e44e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489191780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1489191780
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3616867231
Short name T315
Test name
Test status
Simulation time 528702945 ps
CPU time 4.1 seconds
Started Mar 26 12:52:09 PM PDT 24
Finished Mar 26 12:52:14 PM PDT 24
Peak memory 199924 kb
Host smart-eda196f8-6459-40fb-b0ee-1f4499600101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616867231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3616867231
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.1651021060
Short name T46
Test name
Test status
Simulation time 26844353 ps
CPU time 1.02 seconds
Started Mar 26 12:52:09 PM PDT 24
Finished Mar 26 12:52:10 PM PDT 24
Peak memory 199160 kb
Host smart-9a1a8d51-95dd-4cfb-8a27-ca1b9140dc2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651021060 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.1651021060
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.950582101
Short name T61
Test name
Test status
Simulation time 35173205659 ps
CPU time 488.69 seconds
Started Mar 26 12:52:10 PM PDT 24
Finished Mar 26 01:00:19 PM PDT 24
Peak memory 200044 kb
Host smart-b0d6c083-afe0-469f-881b-235fa46bd682
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950582101 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.950582101
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.642621505
Short name T452
Test name
Test status
Simulation time 309292459 ps
CPU time 15.79 seconds
Started Mar 26 12:52:08 PM PDT 24
Finished Mar 26 12:52:24 PM PDT 24
Peak memory 200016 kb
Host smart-d078ca5d-38d2-4759-bc68-46bc0d2d247e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642621505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.642621505
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.455022916
Short name T489
Test name
Test status
Simulation time 35470371 ps
CPU time 0.54 seconds
Started Mar 26 12:52:20 PM PDT 24
Finished Mar 26 12:52:22 PM PDT 24
Peak memory 194516 kb
Host smart-fceef368-21ba-4ac5-a603-678251da0df4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455022916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.455022916
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2551499180
Short name T341
Test name
Test status
Simulation time 881809291 ps
CPU time 7.79 seconds
Started Mar 26 12:52:09 PM PDT 24
Finished Mar 26 12:52:16 PM PDT 24
Peak memory 200016 kb
Host smart-560068f9-a80b-4f65-9e50-52f70ea813c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2551499180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2551499180
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.912551955
Short name T304
Test name
Test status
Simulation time 1090991326 ps
CPU time 13.69 seconds
Started Mar 26 12:52:20 PM PDT 24
Finished Mar 26 12:52:36 PM PDT 24
Peak memory 199996 kb
Host smart-0f9da262-7842-4454-ad38-29b08f52e604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912551955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.912551955
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1591204889
Short name T182
Test name
Test status
Simulation time 2258441690 ps
CPU time 15.62 seconds
Started Mar 26 12:52:08 PM PDT 24
Finished Mar 26 12:52:24 PM PDT 24
Peak memory 199960 kb
Host smart-bba77cc8-bf5b-4fb0-9336-972f4ed07f28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1591204889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1591204889
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.1457366392
Short name T253
Test name
Test status
Simulation time 6170131429 ps
CPU time 42.33 seconds
Started Mar 26 12:52:22 PM PDT 24
Finished Mar 26 12:53:05 PM PDT 24
Peak memory 200004 kb
Host smart-328c0b52-46f6-4ab8-b6d1-dc72e2885df7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457366392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1457366392
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2019672792
Short name T564
Test name
Test status
Simulation time 3961606665 ps
CPU time 66.64 seconds
Started Mar 26 12:52:09 PM PDT 24
Finished Mar 26 12:53:16 PM PDT 24
Peak memory 199932 kb
Host smart-96245d4d-fe01-4f79-b287-077637089be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019672792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2019672792
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2482207024
Short name T380
Test name
Test status
Simulation time 3575421313 ps
CPU time 6.97 seconds
Started Mar 26 12:52:09 PM PDT 24
Finished Mar 26 12:52:16 PM PDT 24
Peak memory 199920 kb
Host smart-8a618c5e-0d54-409c-b9fa-b6dcf8cbed64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482207024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2482207024
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.567849043
Short name T96
Test name
Test status
Simulation time 574445551 ps
CPU time 33.24 seconds
Started Mar 26 12:52:21 PM PDT 24
Finished Mar 26 12:52:55 PM PDT 24
Peak memory 200008 kb
Host smart-23f00855-6030-4623-8066-ea351a9c1c26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567849043 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.567849043
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.2300472579
Short name T469
Test name
Test status
Simulation time 119915105 ps
CPU time 1.41 seconds
Started Mar 26 12:52:21 PM PDT 24
Finished Mar 26 12:52:24 PM PDT 24
Peak memory 199944 kb
Host smart-620693fa-bcaa-4d05-b1d5-403461706b98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300472579 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.2300472579
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.13276229
Short name T278
Test name
Test status
Simulation time 8953543797 ps
CPU time 475.6 seconds
Started Mar 26 12:52:21 PM PDT 24
Finished Mar 26 01:00:18 PM PDT 24
Peak memory 199932 kb
Host smart-32716381-5ff8-4376-97a8-4529b7083999
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13276229 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.13276229
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.3612700537
Short name T266
Test name
Test status
Simulation time 11378014944 ps
CPU time 99.29 seconds
Started Mar 26 12:52:19 PM PDT 24
Finished Mar 26 12:53:59 PM PDT 24
Peak memory 200008 kb
Host smart-d1f98352-3427-42f2-8569-da02124c583f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612700537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3612700537
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.1744153311
Short name T139
Test name
Test status
Simulation time 65266000 ps
CPU time 0.6 seconds
Started Mar 26 12:49:53 PM PDT 24
Finished Mar 26 12:49:54 PM PDT 24
Peak memory 195520 kb
Host smart-7dafe02a-d27f-4c7a-aa7d-ed1e84c65b79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744153311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1744153311
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.2392533478
Short name T508
Test name
Test status
Simulation time 8495320972 ps
CPU time 41.42 seconds
Started Mar 26 12:49:53 PM PDT 24
Finished Mar 26 12:50:35 PM PDT 24
Peak memory 224612 kb
Host smart-a2075f79-4379-4f70-8d88-18a32fe59c70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2392533478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2392533478
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1996047504
Short name T481
Test name
Test status
Simulation time 1996219635 ps
CPU time 48.34 seconds
Started Mar 26 12:49:55 PM PDT 24
Finished Mar 26 12:50:43 PM PDT 24
Peak memory 199940 kb
Host smart-bae5bece-1ea9-414e-bca4-0b567d3ebc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996047504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1996047504
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2977399913
Short name T516
Test name
Test status
Simulation time 26653608728 ps
CPU time 113.31 seconds
Started Mar 26 12:49:58 PM PDT 24
Finished Mar 26 12:51:52 PM PDT 24
Peak memory 200068 kb
Host smart-5243911d-5d4d-424e-83e4-b336f26171a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2977399913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2977399913
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2580425406
Short name T94
Test name
Test status
Simulation time 3471078709 ps
CPU time 15.01 seconds
Started Mar 26 12:49:54 PM PDT 24
Finished Mar 26 12:50:09 PM PDT 24
Peak memory 199968 kb
Host smart-ee0199de-5764-4573-ad50-1ded6a3906a6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580425406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2580425406
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3339678123
Short name T209
Test name
Test status
Simulation time 3423234771 ps
CPU time 68.04 seconds
Started Mar 26 12:49:56 PM PDT 24
Finished Mar 26 12:51:04 PM PDT 24
Peak memory 199976 kb
Host smart-bdbcc919-0866-44ab-bce1-1b08bb64006f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339678123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3339678123
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2715118081
Short name T36
Test name
Test status
Simulation time 142109889 ps
CPU time 0.92 seconds
Started Mar 26 12:49:56 PM PDT 24
Finished Mar 26 12:49:57 PM PDT 24
Peak memory 219172 kb
Host smart-e686d73a-b295-4620-a35a-e5e0c383cc22
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715118081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2715118081
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.2883915335
Short name T138
Test name
Test status
Simulation time 1575317003 ps
CPU time 3.09 seconds
Started Mar 26 12:49:55 PM PDT 24
Finished Mar 26 12:49:58 PM PDT 24
Peak memory 199920 kb
Host smart-0ef3f7ea-3505-4800-8786-01fae1f1e646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883915335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.2883915335
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.2695055015
Short name T464
Test name
Test status
Simulation time 25800141166 ps
CPU time 133.81 seconds
Started Mar 26 12:49:56 PM PDT 24
Finished Mar 26 12:52:10 PM PDT 24
Peak memory 199920 kb
Host smart-c15fe20b-60ac-4b4c-88a1-bf5e61dde043
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695055015 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.2695055015
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.3905520461
Short name T476
Test name
Test status
Simulation time 316503743 ps
CPU time 1.14 seconds
Started Mar 26 12:49:55 PM PDT 24
Finished Mar 26 12:49:56 PM PDT 24
Peak memory 198852 kb
Host smart-a5bda9ff-ffdc-48ad-9529-bc960b251c5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905520461 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.3905520461
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.3505437933
Short name T588
Test name
Test status
Simulation time 26702615906 ps
CPU time 472.27 seconds
Started Mar 26 12:49:54 PM PDT 24
Finished Mar 26 12:57:46 PM PDT 24
Peak memory 199904 kb
Host smart-83237e3c-7b4b-4cba-af2a-c81d27650056
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505437933 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.3505437933
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1460938374
Short name T41
Test name
Test status
Simulation time 4973885139 ps
CPU time 82.23 seconds
Started Mar 26 12:49:55 PM PDT 24
Finished Mar 26 12:51:17 PM PDT 24
Peak memory 199944 kb
Host smart-421187f3-fa01-4ec7-bbba-58c3a21538af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460938374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1460938374
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.3499720171
Short name T273
Test name
Test status
Simulation time 63620025 ps
CPU time 0.58 seconds
Started Mar 26 12:52:19 PM PDT 24
Finished Mar 26 12:52:20 PM PDT 24
Peak memory 194372 kb
Host smart-dd1d3eb8-94c2-41c8-b896-cf076789fc98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499720171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.3499720171
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2059673610
Short name T553
Test name
Test status
Simulation time 1438862911 ps
CPU time 55.13 seconds
Started Mar 26 12:52:20 PM PDT 24
Finished Mar 26 12:53:16 PM PDT 24
Peak memory 222600 kb
Host smart-7dd0fb2a-fc04-4f88-ae1e-2e968042d02d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2059673610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2059673610
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.2132696499
Short name T314
Test name
Test status
Simulation time 2314335067 ps
CPU time 31.98 seconds
Started Mar 26 12:52:19 PM PDT 24
Finished Mar 26 12:52:52 PM PDT 24
Peak memory 199968 kb
Host smart-848aa070-bcb2-46f4-9537-37e38fa383b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132696499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.2132696499
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2408739544
Short name T442
Test name
Test status
Simulation time 1344053379 ps
CPU time 38.81 seconds
Started Mar 26 12:52:21 PM PDT 24
Finished Mar 26 12:53:01 PM PDT 24
Peak memory 200048 kb
Host smart-74eedca6-9336-4fa1-b561-a4cb0330d905
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2408739544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2408739544
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.658286420
Short name T534
Test name
Test status
Simulation time 15403060658 ps
CPU time 204.16 seconds
Started Mar 26 12:52:21 PM PDT 24
Finished Mar 26 12:55:47 PM PDT 24
Peak memory 199984 kb
Host smart-1651cad9-a210-4c60-8ad1-bed594e1e03a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658286420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.658286420
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2705770854
Short name T211
Test name
Test status
Simulation time 2393725141 ps
CPU time 33.19 seconds
Started Mar 26 12:52:20 PM PDT 24
Finished Mar 26 12:52:54 PM PDT 24
Peak memory 200128 kb
Host smart-1226445c-a2ef-492c-8008-36f130669ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705770854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2705770854
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3513266600
Short name T78
Test name
Test status
Simulation time 577310518 ps
CPU time 2.03 seconds
Started Mar 26 12:52:21 PM PDT 24
Finished Mar 26 12:52:24 PM PDT 24
Peak memory 199860 kb
Host smart-2e70f167-38d4-4e51-9c7b-5d34a6678e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513266600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3513266600
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1617035515
Short name T503
Test name
Test status
Simulation time 54503345869 ps
CPU time 1015.72 seconds
Started Mar 26 12:52:22 PM PDT 24
Finished Mar 26 01:09:18 PM PDT 24
Peak memory 239356 kb
Host smart-f8bca266-8fed-46fc-907f-8cd4d3f6c492
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617035515 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1617035515
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.3839605123
Short name T475
Test name
Test status
Simulation time 271011057 ps
CPU time 1.26 seconds
Started Mar 26 12:52:21 PM PDT 24
Finished Mar 26 12:52:24 PM PDT 24
Peak memory 199696 kb
Host smart-0a18857e-c862-4cb4-a431-757eb0d0ba40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839605123 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.3839605123
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.4194144084
Short name T227
Test name
Test status
Simulation time 29597304496 ps
CPU time 487.07 seconds
Started Mar 26 12:52:22 PM PDT 24
Finished Mar 26 01:00:30 PM PDT 24
Peak memory 199944 kb
Host smart-6fb46e3a-cac8-46a4-a487-3e5c0a6d14da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194144084 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.4194144084
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3732674015
Short name T170
Test name
Test status
Simulation time 8356312600 ps
CPU time 83.37 seconds
Started Mar 26 12:52:22 PM PDT 24
Finished Mar 26 12:53:46 PM PDT 24
Peak memory 199988 kb
Host smart-75bc24d4-e663-4307-90cd-3b9569340b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732674015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3732674015
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3204067110
Short name T74
Test name
Test status
Simulation time 13713706 ps
CPU time 0.58 seconds
Started Mar 26 12:52:32 PM PDT 24
Finished Mar 26 12:52:33 PM PDT 24
Peak memory 195452 kb
Host smart-82de89e1-86a9-4696-8506-aae096c5623f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204067110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3204067110
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1776602084
Short name T188
Test name
Test status
Simulation time 150581186 ps
CPU time 3.41 seconds
Started Mar 26 12:52:21 PM PDT 24
Finished Mar 26 12:52:26 PM PDT 24
Peak memory 208032 kb
Host smart-c2feb828-39bb-4d23-a7de-962ca87169a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1776602084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1776602084
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.278838250
Short name T152
Test name
Test status
Simulation time 1219401794 ps
CPU time 19.48 seconds
Started Mar 26 12:52:20 PM PDT 24
Finished Mar 26 12:52:42 PM PDT 24
Peak memory 199896 kb
Host smart-8d663f9d-3a3d-43fb-868a-8224a3f486ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278838250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.278838250
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.4209299529
Short name T384
Test name
Test status
Simulation time 1621772843 ps
CPU time 93.82 seconds
Started Mar 26 12:52:21 PM PDT 24
Finished Mar 26 12:53:56 PM PDT 24
Peak memory 199964 kb
Host smart-3ab0e66a-c27d-483e-b8e0-064f18e2f267
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4209299529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.4209299529
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.4076754254
Short name T397
Test name
Test status
Simulation time 14153267 ps
CPU time 0.64 seconds
Started Mar 26 12:52:22 PM PDT 24
Finished Mar 26 12:52:23 PM PDT 24
Peak memory 195804 kb
Host smart-7a8d9e05-9865-425f-9ec0-d403771478ce
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076754254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.4076754254
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1995894819
Short name T545
Test name
Test status
Simulation time 21025391894 ps
CPU time 94.62 seconds
Started Mar 26 12:52:23 PM PDT 24
Finished Mar 26 12:53:59 PM PDT 24
Peak memory 199920 kb
Host smart-ccb54e04-5adc-41fd-bf1b-d417865dbfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995894819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1995894819
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1359837684
Short name T354
Test name
Test status
Simulation time 29486675 ps
CPU time 0.78 seconds
Started Mar 26 12:52:20 PM PDT 24
Finished Mar 26 12:52:23 PM PDT 24
Peak memory 197020 kb
Host smart-0d038962-4d88-4a07-a9ba-e5567afcb13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359837684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1359837684
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.616954628
Short name T461
Test name
Test status
Simulation time 9394540167 ps
CPU time 175.02 seconds
Started Mar 26 12:52:32 PM PDT 24
Finished Mar 26 12:55:28 PM PDT 24
Peak memory 199964 kb
Host smart-48254859-9e4b-4c70-97cf-5b1c63d559c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616954628 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.616954628
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.3105894841
Short name T453
Test name
Test status
Simulation time 99827478 ps
CPU time 1.02 seconds
Started Mar 26 12:52:32 PM PDT 24
Finished Mar 26 12:52:34 PM PDT 24
Peak memory 199288 kb
Host smart-79529189-b54c-4f23-81d8-797edf438105
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105894841 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.3105894841
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.1477233623
Short name T330
Test name
Test status
Simulation time 7117744867 ps
CPU time 416.41 seconds
Started Mar 26 12:52:32 PM PDT 24
Finished Mar 26 12:59:29 PM PDT 24
Peak memory 199904 kb
Host smart-4cffea35-d276-4ab7-8a0f-870ab093be0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477233623 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.1477233623
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.552266747
Short name T257
Test name
Test status
Simulation time 2622892506 ps
CPU time 34 seconds
Started Mar 26 12:52:21 PM PDT 24
Finished Mar 26 12:52:57 PM PDT 24
Peak memory 200040 kb
Host smart-a1cefc8f-e564-4813-9f95-d32dc122d89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552266747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.552266747
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.4240138819
Short name T568
Test name
Test status
Simulation time 60063539 ps
CPU time 0.58 seconds
Started Mar 26 12:52:34 PM PDT 24
Finished Mar 26 12:52:35 PM PDT 24
Peak memory 195312 kb
Host smart-56807aa4-8a07-4505-b300-df513f06ada7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240138819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.4240138819
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3143993897
Short name T296
Test name
Test status
Simulation time 3258300243 ps
CPU time 61.44 seconds
Started Mar 26 12:52:29 PM PDT 24
Finished Mar 26 12:53:31 PM PDT 24
Peak memory 226644 kb
Host smart-545d3972-4d37-47f1-9fb1-19ce65260d0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3143993897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3143993897
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.2400354909
Short name T336
Test name
Test status
Simulation time 146636533 ps
CPU time 6.59 seconds
Started Mar 26 12:52:30 PM PDT 24
Finished Mar 26 12:52:36 PM PDT 24
Peak memory 199892 kb
Host smart-8f67aea5-31dd-470c-b728-48545f88f4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400354909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2400354909
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.1828714771
Short name T383
Test name
Test status
Simulation time 1282910080 ps
CPU time 75.72 seconds
Started Mar 26 12:52:32 PM PDT 24
Finished Mar 26 12:53:48 PM PDT 24
Peak memory 200052 kb
Host smart-d179de15-d10c-4470-9bbe-1d37d823b0c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1828714771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1828714771
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2676370442
Short name T6
Test name
Test status
Simulation time 42522354935 ps
CPU time 138.93 seconds
Started Mar 26 12:52:33 PM PDT 24
Finished Mar 26 12:54:52 PM PDT 24
Peak memory 200068 kb
Host smart-017444e9-d06f-475c-8b32-a060e024a6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676370442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2676370442
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1937829405
Short name T409
Test name
Test status
Simulation time 100847377 ps
CPU time 1.54 seconds
Started Mar 26 12:52:32 PM PDT 24
Finished Mar 26 12:52:34 PM PDT 24
Peak memory 199908 kb
Host smart-0aa968bf-8362-4dad-aaf1-299255bd482c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937829405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1937829405
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.3458625429
Short name T468
Test name
Test status
Simulation time 61488236443 ps
CPU time 894.08 seconds
Started Mar 26 12:52:32 PM PDT 24
Finished Mar 26 01:07:27 PM PDT 24
Peak memory 216220 kb
Host smart-1243ef8c-f025-47da-b509-084a937802d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458625429 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.3458625429
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.36696952
Short name T64
Test name
Test status
Simulation time 80168996 ps
CPU time 1.24 seconds
Started Mar 26 12:52:33 PM PDT 24
Finished Mar 26 12:52:35 PM PDT 24
Peak memory 199656 kb
Host smart-04545cee-0357-4d1f-b767-7cdf683c6160
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36696952 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.hmac_test_hmac_vectors.36696952
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.939967020
Short name T555
Test name
Test status
Simulation time 15546850339 ps
CPU time 467.18 seconds
Started Mar 26 12:52:33 PM PDT 24
Finished Mar 26 01:00:21 PM PDT 24
Peak memory 199940 kb
Host smart-840158aa-d7b8-4570-aecd-f60de9ad0b19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939967020 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.939967020
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3051565917
Short name T235
Test name
Test status
Simulation time 13533394191 ps
CPU time 64.8 seconds
Started Mar 26 12:52:31 PM PDT 24
Finished Mar 26 12:53:36 PM PDT 24
Peak memory 199980 kb
Host smart-e6186e71-1eab-4bb2-9377-bb031f3a4f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051565917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3051565917
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.3112460318
Short name T76
Test name
Test status
Simulation time 13646249 ps
CPU time 0.58 seconds
Started Mar 26 12:52:43 PM PDT 24
Finished Mar 26 12:52:43 PM PDT 24
Peak memory 194360 kb
Host smart-91198b81-5a52-4891-b1b2-19c339f3520e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112460318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3112460318
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.411498867
Short name T550
Test name
Test status
Simulation time 400034780 ps
CPU time 4.28 seconds
Started Mar 26 12:52:30 PM PDT 24
Finished Mar 26 12:52:34 PM PDT 24
Peak memory 208124 kb
Host smart-5a427fb3-3ea4-4dc7-8361-af3d381f49de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=411498867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.411498867
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.2756998164
Short name T197
Test name
Test status
Simulation time 7806655571 ps
CPU time 57.25 seconds
Started Mar 26 12:52:32 PM PDT 24
Finished Mar 26 12:53:30 PM PDT 24
Peak memory 199928 kb
Host smart-e5ac15c0-e1ed-4fd3-9c29-dbbf298bdd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756998164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2756998164
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.4180139346
Short name T117
Test name
Test status
Simulation time 862507339 ps
CPU time 45.52 seconds
Started Mar 26 12:52:34 PM PDT 24
Finished Mar 26 12:53:20 PM PDT 24
Peak memory 199920 kb
Host smart-3d0b1157-38f8-4165-9caa-cea5f4dc31c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4180139346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.4180139346
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.293836568
Short name T470
Test name
Test status
Simulation time 47070436711 ps
CPU time 151.77 seconds
Started Mar 26 12:52:44 PM PDT 24
Finished Mar 26 12:55:16 PM PDT 24
Peak memory 200092 kb
Host smart-cd5d17cf-f4a1-41ed-8ae7-7fc02c7b7475
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293836568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.293836568
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.4241392905
Short name T333
Test name
Test status
Simulation time 1822711630 ps
CPU time 39.29 seconds
Started Mar 26 12:52:31 PM PDT 24
Finished Mar 26 12:53:10 PM PDT 24
Peak memory 200244 kb
Host smart-7540d923-da8e-4055-9076-f9d5c740709f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241392905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.4241392905
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3714401561
Short name T310
Test name
Test status
Simulation time 179806236 ps
CPU time 5.2 seconds
Started Mar 26 12:52:31 PM PDT 24
Finished Mar 26 12:52:36 PM PDT 24
Peak memory 199912 kb
Host smart-4dee79ed-84a5-42d9-9b9e-c975d4616334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714401561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3714401561
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.750753340
Short name T84
Test name
Test status
Simulation time 84711607237 ps
CPU time 1101.16 seconds
Started Mar 26 12:52:44 PM PDT 24
Finished Mar 26 01:11:05 PM PDT 24
Peak memory 199988 kb
Host smart-db1e5ac3-eb3e-4f04-8ad1-2240c28f75d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750753340 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.750753340
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.1890845333
Short name T363
Test name
Test status
Simulation time 718937632 ps
CPU time 1.1 seconds
Started Mar 26 12:52:43 PM PDT 24
Finished Mar 26 12:52:44 PM PDT 24
Peak memory 199704 kb
Host smart-74b90ca7-6c45-46e7-9cb1-4af9cdf3e8bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890845333 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.1890845333
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.2745152950
Short name T456
Test name
Test status
Simulation time 31963894132 ps
CPU time 455.91 seconds
Started Mar 26 12:52:45 PM PDT 24
Finished Mar 26 01:00:21 PM PDT 24
Peak memory 199892 kb
Host smart-633bd146-7de8-427c-a90b-5bd285cce374
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745152950 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.2745152950
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.4146756881
Short name T449
Test name
Test status
Simulation time 2595421643 ps
CPU time 22.52 seconds
Started Mar 26 12:52:43 PM PDT 24
Finished Mar 26 12:53:06 PM PDT 24
Peak memory 199988 kb
Host smart-75d9091a-470f-45ef-b6b6-3584027471d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146756881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.4146756881
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2949711281
Short name T222
Test name
Test status
Simulation time 16384634 ps
CPU time 0.59 seconds
Started Mar 26 12:52:45 PM PDT 24
Finished Mar 26 12:52:46 PM PDT 24
Peak memory 195440 kb
Host smart-c02feef3-ec58-48d2-9cc9-1c809bfd6058
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949711281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2949711281
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.2664575734
Short name T342
Test name
Test status
Simulation time 3854986900 ps
CPU time 39.41 seconds
Started Mar 26 12:52:42 PM PDT 24
Finished Mar 26 12:53:21 PM PDT 24
Peak memory 213052 kb
Host smart-00593a11-62c4-4412-8ec3-97595d09a014
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2664575734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2664575734
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.218249827
Short name T183
Test name
Test status
Simulation time 669284731 ps
CPU time 17.95 seconds
Started Mar 26 12:52:43 PM PDT 24
Finished Mar 26 12:53:01 PM PDT 24
Peak memory 199904 kb
Host smart-5fe7412b-01e0-48bf-9185-89f580753de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218249827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.218249827
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.1819994842
Short name T136
Test name
Test status
Simulation time 1290692450 ps
CPU time 75.9 seconds
Started Mar 26 12:52:45 PM PDT 24
Finished Mar 26 12:54:00 PM PDT 24
Peak memory 199976 kb
Host smart-97410712-0b02-47a7-8915-9e2a86e3a4ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1819994842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1819994842
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.979812795
Short name T29
Test name
Test status
Simulation time 50041161476 ps
CPU time 249.89 seconds
Started Mar 26 12:52:44 PM PDT 24
Finished Mar 26 12:56:54 PM PDT 24
Peak memory 200056 kb
Host smart-dd897560-b5f4-4153-a7cc-6ebc82ab017a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979812795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.979812795
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.2739328701
Short name T299
Test name
Test status
Simulation time 28363271985 ps
CPU time 145.25 seconds
Started Mar 26 12:52:48 PM PDT 24
Finished Mar 26 12:55:13 PM PDT 24
Peak memory 199944 kb
Host smart-5360a79e-adfa-4e13-b065-37ab29343bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739328701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.2739328701
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2652053621
Short name T5
Test name
Test status
Simulation time 468968427 ps
CPU time 4.11 seconds
Started Mar 26 12:52:44 PM PDT 24
Finished Mar 26 12:52:48 PM PDT 24
Peak memory 199868 kb
Host smart-f8b3b0ae-3667-4b90-a52b-ab6eff1448e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652053621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2652053621
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.2218470538
Short name T483
Test name
Test status
Simulation time 5752376625 ps
CPU time 106.54 seconds
Started Mar 26 12:52:43 PM PDT 24
Finished Mar 26 12:54:30 PM PDT 24
Peak memory 232828 kb
Host smart-e1a9bd26-153b-4a47-a430-dd0027aa8c09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218470538 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2218470538
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.3645178353
Short name T357
Test name
Test status
Simulation time 151928552 ps
CPU time 1.41 seconds
Started Mar 26 12:52:43 PM PDT 24
Finished Mar 26 12:52:45 PM PDT 24
Peak memory 199952 kb
Host smart-87844302-0f08-4dbd-88f6-5ee08d532d21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645178353 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.3645178353
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.1935973625
Short name T38
Test name
Test status
Simulation time 273224872463 ps
CPU time 473.14 seconds
Started Mar 26 12:52:44 PM PDT 24
Finished Mar 26 01:00:37 PM PDT 24
Peak memory 199948 kb
Host smart-b618721a-2cef-4a92-86ae-70b769846f70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935973625 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.1935973625
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1577306535
Short name T529
Test name
Test status
Simulation time 66287138518 ps
CPU time 73.53 seconds
Started Mar 26 12:52:47 PM PDT 24
Finished Mar 26 12:54:01 PM PDT 24
Peak memory 200012 kb
Host smart-11cc10d6-fd39-4500-a36e-457952980d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577306535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1577306535
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.834339934
Short name T424
Test name
Test status
Simulation time 11422590 ps
CPU time 0.6 seconds
Started Mar 26 12:52:55 PM PDT 24
Finished Mar 26 12:52:56 PM PDT 24
Peak memory 195124 kb
Host smart-85120573-69fa-42c4-8cab-00b5d916b882
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834339934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.834339934
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.2338721014
Short name T57
Test name
Test status
Simulation time 254287511 ps
CPU time 13.38 seconds
Started Mar 26 12:52:43 PM PDT 24
Finished Mar 26 12:52:57 PM PDT 24
Peak memory 230564 kb
Host smart-ce65e2fa-179f-4517-bc70-bb2ad8e5c8cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2338721014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2338721014
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2450351433
Short name T594
Test name
Test status
Simulation time 2914969049 ps
CPU time 47.21 seconds
Started Mar 26 12:52:56 PM PDT 24
Finished Mar 26 12:53:43 PM PDT 24
Peak memory 200060 kb
Host smart-c7095be5-9b75-44e8-b7f4-b6f3220de4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450351433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2450351433
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1774059894
Short name T539
Test name
Test status
Simulation time 28670957 ps
CPU time 0.77 seconds
Started Mar 26 12:52:55 PM PDT 24
Finished Mar 26 12:52:56 PM PDT 24
Peak memory 197740 kb
Host smart-765525c3-6ea1-4583-979a-0a7c46fd0c8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1774059894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1774059894
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.149575793
Short name T528
Test name
Test status
Simulation time 3905897235 ps
CPU time 53.42 seconds
Started Mar 26 12:52:58 PM PDT 24
Finished Mar 26 12:53:52 PM PDT 24
Peak memory 200000 kb
Host smart-700e8d14-5077-43f7-9d40-5d5286d1613c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149575793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.149575793
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1572791767
Short name T157
Test name
Test status
Simulation time 22536193943 ps
CPU time 76.31 seconds
Started Mar 26 12:52:45 PM PDT 24
Finished Mar 26 12:54:01 PM PDT 24
Peak memory 199952 kb
Host smart-017a439a-3cfe-485e-af23-1aa102b6acab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572791767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1572791767
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.1025730310
Short name T187
Test name
Test status
Simulation time 1701821959 ps
CPU time 6.4 seconds
Started Mar 26 12:52:45 PM PDT 24
Finished Mar 26 12:52:51 PM PDT 24
Peak memory 199836 kb
Host smart-f297c050-24e1-4554-a76f-3ce48ac80620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025730310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.1025730310
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3435197035
Short name T62
Test name
Test status
Simulation time 6710531684 ps
CPU time 98.41 seconds
Started Mar 26 12:52:55 PM PDT 24
Finished Mar 26 12:54:34 PM PDT 24
Peak memory 223068 kb
Host smart-1c48f06b-e9f6-475c-9c35-be786570d2e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435197035 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3435197035
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.2137979801
Short name T391
Test name
Test status
Simulation time 28932177 ps
CPU time 0.98 seconds
Started Mar 26 12:52:55 PM PDT 24
Finished Mar 26 12:52:56 PM PDT 24
Peak memory 199500 kb
Host smart-148f0b83-3f8a-4549-a6b0-f3796b9f24b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137979801 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.2137979801
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.39807789
Short name T549
Test name
Test status
Simulation time 16588609662 ps
CPU time 467.36 seconds
Started Mar 26 12:52:56 PM PDT 24
Finished Mar 26 01:00:44 PM PDT 24
Peak memory 199944 kb
Host smart-ddf37c35-e250-44d1-bbaf-603f978ffa70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39807789 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.39807789
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.993412234
Short name T500
Test name
Test status
Simulation time 8176832291 ps
CPU time 71.8 seconds
Started Mar 26 12:52:55 PM PDT 24
Finished Mar 26 12:54:07 PM PDT 24
Peak memory 200004 kb
Host smart-7fa79a3e-44b2-4778-8bc8-d1516b29c315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993412234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.993412234
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2248149038
Short name T24
Test name
Test status
Simulation time 35992242 ps
CPU time 0.6 seconds
Started Mar 26 12:52:57 PM PDT 24
Finished Mar 26 12:52:57 PM PDT 24
Peak memory 195548 kb
Host smart-c76f5ad6-6424-4fe3-b8fa-ac7706b652b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248149038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2248149038
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1998293045
Short name T58
Test name
Test status
Simulation time 6289449504 ps
CPU time 34.65 seconds
Started Mar 26 12:52:56 PM PDT 24
Finished Mar 26 12:53:30 PM PDT 24
Peak memory 229152 kb
Host smart-998d5c34-976f-42a0-ac0e-cbf82bb16d9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1998293045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1998293045
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1527385855
Short name T365
Test name
Test status
Simulation time 690016580 ps
CPU time 11.57 seconds
Started Mar 26 12:52:57 PM PDT 24
Finished Mar 26 12:53:09 PM PDT 24
Peak memory 200200 kb
Host smart-bbe78434-069a-4b67-af61-aaf3154def19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527385855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1527385855
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.443046954
Short name T443
Test name
Test status
Simulation time 2562658013 ps
CPU time 152.31 seconds
Started Mar 26 12:52:55 PM PDT 24
Finished Mar 26 12:55:27 PM PDT 24
Peak memory 199952 kb
Host smart-b908bdad-c287-4b3f-af7a-b2f79ff00e3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=443046954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.443046954
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.4194500745
Short name T495
Test name
Test status
Simulation time 11732667900 ps
CPU time 128.2 seconds
Started Mar 26 12:52:56 PM PDT 24
Finished Mar 26 12:55:04 PM PDT 24
Peak memory 199976 kb
Host smart-5a05d4e3-d3b7-43af-894e-8929bccb2324
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194500745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.4194500745
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.959219641
Short name T251
Test name
Test status
Simulation time 1134424410 ps
CPU time 35.01 seconds
Started Mar 26 12:52:56 PM PDT 24
Finished Mar 26 12:53:31 PM PDT 24
Peak memory 199916 kb
Host smart-d458fa41-b2de-4235-ad1d-0f94be59e94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959219641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.959219641
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.502731884
Short name T340
Test name
Test status
Simulation time 373479299 ps
CPU time 6.06 seconds
Started Mar 26 12:52:56 PM PDT 24
Finished Mar 26 12:53:02 PM PDT 24
Peak memory 200016 kb
Host smart-76eb1719-5569-44a2-9740-05decdded603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502731884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.502731884
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.2882961013
Short name T533
Test name
Test status
Simulation time 25314772156 ps
CPU time 692.24 seconds
Started Mar 26 12:52:59 PM PDT 24
Finished Mar 26 01:04:31 PM PDT 24
Peak memory 208152 kb
Host smart-58bcf247-c5d8-44bf-a3ce-599ff12fdc10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882961013 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2882961013
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.3638530871
Short name T494
Test name
Test status
Simulation time 252427012 ps
CPU time 1.22 seconds
Started Mar 26 12:52:57 PM PDT 24
Finished Mar 26 12:52:59 PM PDT 24
Peak memory 199704 kb
Host smart-f69c0fb0-7d5f-44a2-a0d1-30c907845818
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638530871 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.3638530871
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.794818034
Short name T232
Test name
Test status
Simulation time 27325218009 ps
CPU time 480.18 seconds
Started Mar 26 12:52:56 PM PDT 24
Finished Mar 26 01:00:57 PM PDT 24
Peak memory 199908 kb
Host smart-135054d2-67e7-47f6-b207-8928ad934f22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794818034 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.794818034
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1546931182
Short name T411
Test name
Test status
Simulation time 11987030895 ps
CPU time 79.99 seconds
Started Mar 26 12:52:56 PM PDT 24
Finished Mar 26 12:54:16 PM PDT 24
Peak memory 200096 kb
Host smart-fe0895b4-47de-4aa2-9a2a-8adc732b8101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546931182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1546931182
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.1734992023
Short name T231
Test name
Test status
Simulation time 22918529 ps
CPU time 0.6 seconds
Started Mar 26 12:53:09 PM PDT 24
Finished Mar 26 12:53:09 PM PDT 24
Peak memory 195628 kb
Host smart-72198bc5-b70c-4263-86e1-030f37289bad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734992023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.1734992023
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.98891040
Short name T301
Test name
Test status
Simulation time 1758147421 ps
CPU time 57.23 seconds
Started Mar 26 12:52:54 PM PDT 24
Finished Mar 26 12:53:52 PM PDT 24
Peak memory 231992 kb
Host smart-2190b23b-aa6a-463b-8391-b4a68cc64932
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=98891040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.98891040
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3792116517
Short name T329
Test name
Test status
Simulation time 2250185755 ps
CPU time 34.68 seconds
Started Mar 26 12:52:57 PM PDT 24
Finished Mar 26 12:53:32 PM PDT 24
Peak memory 199956 kb
Host smart-35d83a6f-87bf-47cc-88e8-c358bd538903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792116517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3792116517
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3098318362
Short name T223
Test name
Test status
Simulation time 14882023024 ps
CPU time 46.35 seconds
Started Mar 26 12:52:56 PM PDT 24
Finished Mar 26 12:53:42 PM PDT 24
Peak memory 199968 kb
Host smart-d7aa6f60-8be7-49b5-ac4e-b6226a8542da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3098318362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3098318362
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1763763383
Short name T2
Test name
Test status
Simulation time 2784672935 ps
CPU time 41.65 seconds
Started Mar 26 12:52:56 PM PDT 24
Finished Mar 26 12:53:38 PM PDT 24
Peak memory 199924 kb
Host smart-8e5360c1-59fb-42d0-9829-24362328b894
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763763383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1763763383
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1024477466
Short name T256
Test name
Test status
Simulation time 409488508 ps
CPU time 23.71 seconds
Started Mar 26 12:52:57 PM PDT 24
Finished Mar 26 12:53:21 PM PDT 24
Peak memory 199984 kb
Host smart-35ef51fd-db66-4849-bf21-43f119fdb1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024477466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1024477466
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3079719719
Short name T540
Test name
Test status
Simulation time 605707953 ps
CPU time 2.67 seconds
Started Mar 26 12:52:56 PM PDT 24
Finished Mar 26 12:52:59 PM PDT 24
Peak memory 199836 kb
Host smart-a2e4ee75-852d-4fe8-a6e6-d452b5bc4187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079719719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3079719719
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.3986768064
Short name T499
Test name
Test status
Simulation time 110101906 ps
CPU time 1.66 seconds
Started Mar 26 12:53:08 PM PDT 24
Finished Mar 26 12:53:09 PM PDT 24
Peak memory 199888 kb
Host smart-45f052a9-6a78-4926-b70c-fcf62f43546c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986768064 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3986768064
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.3020603421
Short name T312
Test name
Test status
Simulation time 299180337 ps
CPU time 1.45 seconds
Started Mar 26 12:53:10 PM PDT 24
Finished Mar 26 12:53:12 PM PDT 24
Peak memory 199756 kb
Host smart-e1c86788-bfed-4a11-a8c7-64b6530c36bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020603421 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.3020603421
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.11913249
Short name T141
Test name
Test status
Simulation time 25617478107 ps
CPU time 464.02 seconds
Started Mar 26 12:52:58 PM PDT 24
Finished Mar 26 01:00:43 PM PDT 24
Peak memory 199916 kb
Host smart-b1322bea-e7a7-4fe8-9f13-dedb91a6337f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11913249 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.11913249
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.151759904
Short name T565
Test name
Test status
Simulation time 3899352672 ps
CPU time 79.89 seconds
Started Mar 26 12:52:57 PM PDT 24
Finished Mar 26 12:54:17 PM PDT 24
Peak memory 199968 kb
Host smart-f75fe9a9-be6d-4f74-80bf-f1d57db4b595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151759904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.151759904
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3110807299
Short name T412
Test name
Test status
Simulation time 35069493 ps
CPU time 0.58 seconds
Started Mar 26 12:53:09 PM PDT 24
Finished Mar 26 12:53:09 PM PDT 24
Peak memory 195548 kb
Host smart-010103a8-a46e-4257-8f1f-d5c357bca053
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110807299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3110807299
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.54374514
Short name T277
Test name
Test status
Simulation time 1485620354 ps
CPU time 14.32 seconds
Started Mar 26 12:53:08 PM PDT 24
Finished Mar 26 12:53:23 PM PDT 24
Peak memory 208128 kb
Host smart-3e6ebf38-72c3-4804-8cd2-bfbe3249d0bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=54374514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.54374514
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.906009881
Short name T236
Test name
Test status
Simulation time 2086093668 ps
CPU time 7.84 seconds
Started Mar 26 12:53:09 PM PDT 24
Finished Mar 26 12:53:17 PM PDT 24
Peak memory 200040 kb
Host smart-b0a04629-6bc1-41d6-a5ab-d0c71746f787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906009881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.906009881
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2713798843
Short name T292
Test name
Test status
Simulation time 2141298893 ps
CPU time 59.85 seconds
Started Mar 26 12:53:10 PM PDT 24
Finished Mar 26 12:54:10 PM PDT 24
Peak memory 199904 kb
Host smart-75b3dd24-265b-4a9e-be6e-1ee37431f985
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2713798843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2713798843
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.1863618775
Short name T30
Test name
Test status
Simulation time 685164728 ps
CPU time 42.16 seconds
Started Mar 26 12:53:09 PM PDT 24
Finished Mar 26 12:53:51 PM PDT 24
Peak memory 199916 kb
Host smart-3a47badf-93d2-4f1f-894b-bcb3a8922804
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863618775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.1863618775
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3152315821
Short name T431
Test name
Test status
Simulation time 4738744551 ps
CPU time 72.02 seconds
Started Mar 26 12:53:08 PM PDT 24
Finished Mar 26 12:54:21 PM PDT 24
Peak memory 200052 kb
Host smart-c5e4bebe-bcc6-47bd-af37-cabeeed6e709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152315821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3152315821
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.775928788
Short name T1
Test name
Test status
Simulation time 345366728 ps
CPU time 5.5 seconds
Started Mar 26 12:53:11 PM PDT 24
Finished Mar 26 12:53:16 PM PDT 24
Peak memory 200036 kb
Host smart-6646385d-9f86-45a2-a8c5-a3da2e09c9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775928788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.775928788
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1203101097
Short name T322
Test name
Test status
Simulation time 248340684980 ps
CPU time 1227.24 seconds
Started Mar 26 12:53:09 PM PDT 24
Finished Mar 26 01:13:37 PM PDT 24
Peak memory 232632 kb
Host smart-91f09d40-05ef-4853-ad2b-eb99911ef6d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203101097 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1203101097
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.3409443949
Short name T510
Test name
Test status
Simulation time 54759306 ps
CPU time 0.98 seconds
Started Mar 26 12:53:10 PM PDT 24
Finished Mar 26 12:53:11 PM PDT 24
Peak memory 198112 kb
Host smart-800ee6ff-1408-4e77-9418-a61a6d9b53bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409443949 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.3409443949
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.3815609334
Short name T394
Test name
Test status
Simulation time 8458176969 ps
CPU time 485.47 seconds
Started Mar 26 12:53:10 PM PDT 24
Finished Mar 26 01:01:15 PM PDT 24
Peak memory 200044 kb
Host smart-6ac86a88-638e-4497-9206-1a882c639d1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815609334 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.3815609334
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.2213670194
Short name T521
Test name
Test status
Simulation time 4811354427 ps
CPU time 94.13 seconds
Started Mar 26 12:53:07 PM PDT 24
Finished Mar 26 12:54:42 PM PDT 24
Peak memory 200068 kb
Host smart-36604456-e956-4925-ac31-f12f979d6e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213670194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2213670194
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1871032271
Short name T210
Test name
Test status
Simulation time 13193442 ps
CPU time 0.58 seconds
Started Mar 26 12:53:20 PM PDT 24
Finished Mar 26 12:53:21 PM PDT 24
Peak memory 195236 kb
Host smart-2365d25e-a017-4d22-be59-b5372b1494b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871032271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1871032271
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.475409059
Short name T20
Test name
Test status
Simulation time 6434125747 ps
CPU time 59.05 seconds
Started Mar 26 12:53:08 PM PDT 24
Finished Mar 26 12:54:08 PM PDT 24
Peak memory 232396 kb
Host smart-6849f99c-6f14-4674-99e5-8a4c3ffc1542
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=475409059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.475409059
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1273771871
Short name T119
Test name
Test status
Simulation time 1957996390 ps
CPU time 25.97 seconds
Started Mar 26 12:53:09 PM PDT 24
Finished Mar 26 12:53:35 PM PDT 24
Peak memory 199864 kb
Host smart-48a75642-560d-4981-82cc-70b608d92513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273771871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1273771871
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1781811845
Short name T544
Test name
Test status
Simulation time 1891870396 ps
CPU time 50.37 seconds
Started Mar 26 12:53:07 PM PDT 24
Finished Mar 26 12:53:57 PM PDT 24
Peak memory 199944 kb
Host smart-84607386-f207-4cfa-bf46-4cf4ce164dca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1781811845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1781811845
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.2023286803
Short name T229
Test name
Test status
Simulation time 10913143582 ps
CPU time 151.08 seconds
Started Mar 26 12:53:11 PM PDT 24
Finished Mar 26 12:55:42 PM PDT 24
Peak memory 199996 kb
Host smart-ab582f4d-c2ed-473e-9ebe-01384ec24ef4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023286803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.2023286803
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.623481473
Short name T592
Test name
Test status
Simulation time 5135638288 ps
CPU time 38.04 seconds
Started Mar 26 12:53:08 PM PDT 24
Finished Mar 26 12:53:46 PM PDT 24
Peak memory 199992 kb
Host smart-fe1beb19-a857-44e8-a077-f62ef769dc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623481473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.623481473
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3436459523
Short name T279
Test name
Test status
Simulation time 82629142 ps
CPU time 2.88 seconds
Started Mar 26 12:53:10 PM PDT 24
Finished Mar 26 12:53:13 PM PDT 24
Peak memory 200044 kb
Host smart-fc8ce422-2458-455c-9086-9cee086816bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436459523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3436459523
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3109174062
Short name T88
Test name
Test status
Simulation time 167251296517 ps
CPU time 1195.95 seconds
Started Mar 26 12:53:20 PM PDT 24
Finished Mar 26 01:13:17 PM PDT 24
Peak memory 240004 kb
Host smart-5bac2426-16cf-44e6-906b-2a3f3bb165e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109174062 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3109174062
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.2404792659
Short name T95
Test name
Test status
Simulation time 94668987 ps
CPU time 1.06 seconds
Started Mar 26 12:53:10 PM PDT 24
Finished Mar 26 12:53:11 PM PDT 24
Peak memory 199408 kb
Host smart-d9e84ec7-326b-4693-8a09-da2d7e613d63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404792659 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.2404792659
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.1672971126
Short name T435
Test name
Test status
Simulation time 8028182422 ps
CPU time 481.98 seconds
Started Mar 26 12:53:08 PM PDT 24
Finished Mar 26 01:01:10 PM PDT 24
Peak memory 199928 kb
Host smart-d40dd1d0-3a9a-4f65-9878-a0097c05dbdf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672971126 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.1672971126
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.310728649
Short name T181
Test name
Test status
Simulation time 19533852555 ps
CPU time 75.66 seconds
Started Mar 26 12:53:10 PM PDT 24
Finished Mar 26 12:54:26 PM PDT 24
Peak memory 200072 kb
Host smart-9c703a42-74b7-4873-bdaa-5220da12df97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310728649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.310728649
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2590832696
Short name T79
Test name
Test status
Simulation time 43787126 ps
CPU time 0.57 seconds
Started Mar 26 12:50:10 PM PDT 24
Finished Mar 26 12:50:11 PM PDT 24
Peak memory 195036 kb
Host smart-e88c6cae-1c02-4b71-b191-77cb58a7a8f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590832696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2590832696
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.2346789117
Short name T56
Test name
Test status
Simulation time 382821685 ps
CPU time 14.56 seconds
Started Mar 26 12:50:10 PM PDT 24
Finished Mar 26 12:50:25 PM PDT 24
Peak memory 208072 kb
Host smart-c9726407-8ba0-4e3f-97c8-de4ab04d6862
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2346789117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2346789117
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3004230425
Short name T154
Test name
Test status
Simulation time 18731734163 ps
CPU time 38.63 seconds
Started Mar 26 12:50:09 PM PDT 24
Finished Mar 26 12:50:49 PM PDT 24
Peak memory 199976 kb
Host smart-58d96906-5613-478b-8985-2588e80f4daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004230425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3004230425
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2598802202
Short name T392
Test name
Test status
Simulation time 1942576406 ps
CPU time 118 seconds
Started Mar 26 12:50:09 PM PDT 24
Finished Mar 26 12:52:07 PM PDT 24
Peak memory 199888 kb
Host smart-c97ad697-f1b7-4994-8d08-94e14fcc368f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2598802202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2598802202
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1987658193
Short name T479
Test name
Test status
Simulation time 6889183371 ps
CPU time 89.27 seconds
Started Mar 26 12:50:13 PM PDT 24
Finished Mar 26 12:51:43 PM PDT 24
Peak memory 199968 kb
Host smart-ce952fe8-c3bf-4f70-923e-79db214c978f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987658193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1987658193
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.181650852
Short name T243
Test name
Test status
Simulation time 25146131758 ps
CPU time 143.25 seconds
Started Mar 26 12:50:11 PM PDT 24
Finished Mar 26 12:52:35 PM PDT 24
Peak memory 200080 kb
Host smart-9d517054-759a-42a0-a132-38d4bae63f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181650852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.181650852
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.893590388
Short name T35
Test name
Test status
Simulation time 115464597 ps
CPU time 0.89 seconds
Started Mar 26 12:50:14 PM PDT 24
Finished Mar 26 12:50:15 PM PDT 24
Peak memory 218108 kb
Host smart-8ff62ca7-d436-4248-a886-32466ee38547
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893590388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.893590388
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.557169644
Short name T160
Test name
Test status
Simulation time 891092534 ps
CPU time 6.31 seconds
Started Mar 26 12:50:09 PM PDT 24
Finished Mar 26 12:50:16 PM PDT 24
Peak memory 200004 kb
Host smart-6999435a-ee5a-4847-b234-721a98315798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557169644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.557169644
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1257159372
Short name T320
Test name
Test status
Simulation time 52694836037 ps
CPU time 785.37 seconds
Started Mar 26 12:50:13 PM PDT 24
Finished Mar 26 01:03:18 PM PDT 24
Peak memory 232744 kb
Host smart-9f08a1cd-e0a0-4d39-a143-9905134f8bee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257159372 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1257159372
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.2875590461
Short name T459
Test name
Test status
Simulation time 102828232 ps
CPU time 0.95 seconds
Started Mar 26 12:50:09 PM PDT 24
Finished Mar 26 12:50:10 PM PDT 24
Peak memory 198064 kb
Host smart-663aac12-cfc4-4c05-b613-89c2185235e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875590461 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.2875590461
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.744477410
Short name T561
Test name
Test status
Simulation time 55457125407 ps
CPU time 521.53 seconds
Started Mar 26 12:50:12 PM PDT 24
Finished Mar 26 12:58:54 PM PDT 24
Peak memory 199964 kb
Host smart-180604d8-7abe-4566-b93a-dfc73c19e240
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744477410 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.744477410
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2029611100
Short name T497
Test name
Test status
Simulation time 21837805329 ps
CPU time 65.04 seconds
Started Mar 26 12:50:13 PM PDT 24
Finished Mar 26 12:51:19 PM PDT 24
Peak memory 200020 kb
Host smart-e67a705b-0dbf-4998-8f13-3d47b9f9c07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029611100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2029611100
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.1094902837
Short name T398
Test name
Test status
Simulation time 13947451 ps
CPU time 0.58 seconds
Started Mar 26 12:53:21 PM PDT 24
Finished Mar 26 12:53:23 PM PDT 24
Peak memory 195492 kb
Host smart-9cb04d9b-ee4d-4505-a9a4-3caee2ab2fa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094902837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1094902837
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.3903917459
Short name T566
Test name
Test status
Simulation time 12360585394 ps
CPU time 38.26 seconds
Started Mar 26 12:53:20 PM PDT 24
Finished Mar 26 12:53:58 PM PDT 24
Peak memory 226296 kb
Host smart-aaafd5e1-3564-442e-bbcb-dbadf0450fa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3903917459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3903917459
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1114242730
Short name T524
Test name
Test status
Simulation time 744894595 ps
CPU time 12.09 seconds
Started Mar 26 12:53:25 PM PDT 24
Finished Mar 26 12:53:38 PM PDT 24
Peak memory 199832 kb
Host smart-1313c9ab-6422-4aa3-836a-d13366805bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114242730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1114242730
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.662898103
Short name T511
Test name
Test status
Simulation time 804293019 ps
CPU time 23.97 seconds
Started Mar 26 12:53:20 PM PDT 24
Finished Mar 26 12:53:44 PM PDT 24
Peak memory 199972 kb
Host smart-e755e2a4-02c2-4c90-85e8-bb26121d4d23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=662898103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.662898103
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2722152056
Short name T49
Test name
Test status
Simulation time 9673935279 ps
CPU time 123.96 seconds
Started Mar 26 12:53:21 PM PDT 24
Finished Mar 26 12:55:26 PM PDT 24
Peak memory 200084 kb
Host smart-223fdd21-2041-4e3b-97f1-539c428d37d2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722152056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2722152056
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3102162294
Short name T276
Test name
Test status
Simulation time 6214826034 ps
CPU time 96.27 seconds
Started Mar 26 12:53:20 PM PDT 24
Finished Mar 26 12:54:57 PM PDT 24
Peak memory 199976 kb
Host smart-86fd111f-7bb8-462d-b30d-6e2660022812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102162294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3102162294
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2644007234
Short name T567
Test name
Test status
Simulation time 90035654 ps
CPU time 1.77 seconds
Started Mar 26 12:53:23 PM PDT 24
Finished Mar 26 12:53:24 PM PDT 24
Peak memory 199872 kb
Host smart-ecdd17a8-2d9b-4eb8-bbbb-509e3de146a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644007234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2644007234
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.6869998
Short name T297
Test name
Test status
Simulation time 10130891613 ps
CPU time 437.64 seconds
Started Mar 26 12:53:21 PM PDT 24
Finished Mar 26 01:00:39 PM PDT 24
Peak memory 240816 kb
Host smart-d75ec56b-f8b4-4583-8c85-a3b0022becc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6869998 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.6869998
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.3147814124
Short name T40
Test name
Test status
Simulation time 64021775 ps
CPU time 1.06 seconds
Started Mar 26 12:53:21 PM PDT 24
Finished Mar 26 12:53:23 PM PDT 24
Peak memory 197892 kb
Host smart-53613cef-01cd-4975-a1d4-2873e7838e54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147814124 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.3147814124
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.2099191992
Short name T77
Test name
Test status
Simulation time 41105248435 ps
CPU time 528.4 seconds
Started Mar 26 12:53:21 PM PDT 24
Finished Mar 26 01:02:11 PM PDT 24
Peak memory 200024 kb
Host smart-a6099a82-889e-45b1-b705-0a03d23f7987
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099191992 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.2099191992
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2824593519
Short name T91
Test name
Test status
Simulation time 2532036066 ps
CPU time 49.12 seconds
Started Mar 26 12:53:21 PM PDT 24
Finished Mar 26 12:54:11 PM PDT 24
Peak memory 200100 kb
Host smart-b41a36b3-c02c-4175-869d-64e8fd8a17d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824593519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2824593519
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.3921663976
Short name T80
Test name
Test status
Simulation time 14318484 ps
CPU time 0.6 seconds
Started Mar 26 12:53:26 PM PDT 24
Finished Mar 26 12:53:27 PM PDT 24
Peak memory 195396 kb
Host smart-c97a9c65-1844-4040-9fb9-6b1241681724
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921663976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3921663976
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.832328938
Short name T526
Test name
Test status
Simulation time 338401922 ps
CPU time 11.93 seconds
Started Mar 26 12:53:23 PM PDT 24
Finished Mar 26 12:53:35 PM PDT 24
Peak memory 208116 kb
Host smart-4ba1e5ca-488b-45b6-94eb-dc2a8f8bf50b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=832328938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.832328938
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3269580032
Short name T355
Test name
Test status
Simulation time 69147701 ps
CPU time 2.46 seconds
Started Mar 26 12:53:20 PM PDT 24
Finished Mar 26 12:53:23 PM PDT 24
Peak memory 199844 kb
Host smart-4b595212-4c09-4a02-87a6-01d5c46f95d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269580032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3269580032
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2950340631
Short name T249
Test name
Test status
Simulation time 624643618 ps
CPU time 36.09 seconds
Started Mar 26 12:53:20 PM PDT 24
Finished Mar 26 12:53:57 PM PDT 24
Peak memory 200024 kb
Host smart-626cc731-2f9b-4066-96a2-de9afc208dee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2950340631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2950340631
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1153283597
Short name T571
Test name
Test status
Simulation time 28305718189 ps
CPU time 107.54 seconds
Started Mar 26 12:53:22 PM PDT 24
Finished Mar 26 12:55:10 PM PDT 24
Peak memory 199984 kb
Host smart-14644132-3697-43c1-acbc-7a67d471e4fa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153283597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1153283597
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.2516892772
Short name T255
Test name
Test status
Simulation time 2412197320 ps
CPU time 48.69 seconds
Started Mar 26 12:53:23 PM PDT 24
Finished Mar 26 12:54:12 PM PDT 24
Peak memory 200032 kb
Host smart-079db015-d1ed-49c5-b1d9-eadaf463d28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516892772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.2516892772
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.2065478163
Short name T583
Test name
Test status
Simulation time 375440434 ps
CPU time 5 seconds
Started Mar 26 12:53:22 PM PDT 24
Finished Mar 26 12:53:27 PM PDT 24
Peak memory 199952 kb
Host smart-0cf30966-19a9-44ab-b58d-b5af3338e4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065478163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.2065478163
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.3903878859
Short name T83
Test name
Test status
Simulation time 47160683433 ps
CPU time 782.64 seconds
Started Mar 26 12:53:21 PM PDT 24
Finished Mar 26 01:06:25 PM PDT 24
Peak memory 244012 kb
Host smart-9577212e-a8bc-4402-a1f7-d37fde8c2903
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903878859 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3903878859
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_stress_all_with_rand_reset.1442905422
Short name T72
Test name
Test status
Simulation time 255446998599 ps
CPU time 312.87 seconds
Started Mar 26 12:53:21 PM PDT 24
Finished Mar 26 12:58:34 PM PDT 24
Peak memory 224656 kb
Host smart-75852f34-fa0b-43c0-9b0f-b80bba5d10dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1442905422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all_with_rand_reset.1442905422
Directory /workspace/41.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.2091846594
Short name T305
Test name
Test status
Simulation time 118765955 ps
CPU time 1.24 seconds
Started Mar 26 12:53:22 PM PDT 24
Finished Mar 26 12:53:24 PM PDT 24
Peak memory 200172 kb
Host smart-be8d90b0-72bc-4cb1-a1dc-8c32d19e6392
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091846594 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.2091846594
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.1304046632
Short name T194
Test name
Test status
Simulation time 28747565150 ps
CPU time 400.47 seconds
Started Mar 26 12:53:26 PM PDT 24
Finished Mar 26 01:00:07 PM PDT 24
Peak memory 199864 kb
Host smart-435cfc91-ecaa-4c25-aaac-95951e676615
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304046632 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.1304046632
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.1863124509
Short name T97
Test name
Test status
Simulation time 27151295612 ps
CPU time 96.85 seconds
Started Mar 26 12:53:23 PM PDT 24
Finished Mar 26 12:55:00 PM PDT 24
Peak memory 199988 kb
Host smart-f07621aa-c9f2-43cf-973c-0d26768658ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863124509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1863124509
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3169770849
Short name T203
Test name
Test status
Simulation time 11702855 ps
CPU time 0.58 seconds
Started Mar 26 12:53:35 PM PDT 24
Finished Mar 26 12:53:36 PM PDT 24
Peak memory 195436 kb
Host smart-7c767e6d-1fa5-4d1a-81e8-f62eba9fe638
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169770849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3169770849
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.677252175
Short name T374
Test name
Test status
Simulation time 448880962 ps
CPU time 15.98 seconds
Started Mar 26 12:53:35 PM PDT 24
Finished Mar 26 12:53:51 PM PDT 24
Peak memory 215436 kb
Host smart-4c38b06c-43b2-4145-94e8-7942cac1b5a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=677252175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.677252175
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1869622851
Short name T586
Test name
Test status
Simulation time 3945373291 ps
CPU time 21.6 seconds
Started Mar 26 12:53:32 PM PDT 24
Finished Mar 26 12:53:54 PM PDT 24
Peak memory 200072 kb
Host smart-1974daf8-9edf-4ede-9795-6ea2a7d4a53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869622851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1869622851
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.3794772131
Short name T581
Test name
Test status
Simulation time 5462332475 ps
CPU time 75.06 seconds
Started Mar 26 12:53:33 PM PDT 24
Finished Mar 26 12:54:48 PM PDT 24
Peak memory 199984 kb
Host smart-6d556c05-6bbf-4426-8a2d-4d22b437ff69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3794772131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3794772131
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3789420222
Short name T335
Test name
Test status
Simulation time 117345139 ps
CPU time 2.26 seconds
Started Mar 26 12:53:33 PM PDT 24
Finished Mar 26 12:53:35 PM PDT 24
Peak memory 199780 kb
Host smart-69b160c0-fba1-4bf4-85cd-499af9629a92
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789420222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3789420222
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.161990029
Short name T166
Test name
Test status
Simulation time 2655940989 ps
CPU time 20.14 seconds
Started Mar 26 12:53:21 PM PDT 24
Finished Mar 26 12:53:43 PM PDT 24
Peak memory 200080 kb
Host smart-c5b16286-19a7-4143-a050-cb1b0cc172cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161990029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.161990029
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1050162807
Short name T346
Test name
Test status
Simulation time 1577044137 ps
CPU time 4.84 seconds
Started Mar 26 12:53:23 PM PDT 24
Finished Mar 26 12:53:28 PM PDT 24
Peak memory 199840 kb
Host smart-0dd99230-42ee-4c93-b6f5-b5fdba97047c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050162807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1050162807
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2055290967
Short name T579
Test name
Test status
Simulation time 45238575026 ps
CPU time 612.81 seconds
Started Mar 26 12:53:32 PM PDT 24
Finished Mar 26 01:03:46 PM PDT 24
Peak memory 199996 kb
Host smart-ac4fc959-d8a0-493d-9abf-b0f98a6b1aa7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055290967 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2055290967
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.2258817149
Short name T492
Test name
Test status
Simulation time 82818966 ps
CPU time 1.31 seconds
Started Mar 26 12:53:32 PM PDT 24
Finished Mar 26 12:53:33 PM PDT 24
Peak memory 199908 kb
Host smart-851494da-77e1-4717-afef-61b19f837d2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258817149 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.2258817149
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.1222353487
Short name T225
Test name
Test status
Simulation time 50104492656 ps
CPU time 473.77 seconds
Started Mar 26 12:53:31 PM PDT 24
Finished Mar 26 01:01:25 PM PDT 24
Peak memory 199880 kb
Host smart-846f2afe-a444-49ed-9a7b-e2d08a372530
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222353487 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.1222353487
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.1596403836
Short name T552
Test name
Test status
Simulation time 1662891297 ps
CPU time 17.03 seconds
Started Mar 26 12:53:33 PM PDT 24
Finished Mar 26 12:53:50 PM PDT 24
Peak memory 199908 kb
Host smart-a1a350fc-3349-4893-8087-a90c8239572c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596403836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1596403836
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.774644952
Short name T208
Test name
Test status
Simulation time 14336292 ps
CPU time 0.6 seconds
Started Mar 26 12:53:49 PM PDT 24
Finished Mar 26 12:53:50 PM PDT 24
Peak memory 195236 kb
Host smart-3bf81815-c79d-4391-a924-8c306f8b4cc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774644952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.774644952
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1433165071
Short name T176
Test name
Test status
Simulation time 500108226 ps
CPU time 9.73 seconds
Started Mar 26 12:53:33 PM PDT 24
Finished Mar 26 12:53:43 PM PDT 24
Peak memory 199900 kb
Host smart-4f59e8cd-805c-46da-b237-236def487f8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1433165071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1433165071
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.1576052978
Short name T309
Test name
Test status
Simulation time 5164910262 ps
CPU time 39.91 seconds
Started Mar 26 12:53:43 PM PDT 24
Finished Mar 26 12:54:24 PM PDT 24
Peak memory 199988 kb
Host smart-d60274a1-ff41-4dee-a8bd-0cc5db1c7156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576052978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1576052978
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.1752648557
Short name T325
Test name
Test status
Simulation time 3106576644 ps
CPU time 28.6 seconds
Started Mar 26 12:53:34 PM PDT 24
Finished Mar 26 12:54:03 PM PDT 24
Peak memory 199972 kb
Host smart-83b9a6c2-c4b8-4378-9a92-dfa4012df2fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1752648557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.1752648557
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.1503972483
Short name T260
Test name
Test status
Simulation time 22585696284 ps
CPU time 159.13 seconds
Started Mar 26 12:53:45 PM PDT 24
Finished Mar 26 12:56:24 PM PDT 24
Peak memory 199908 kb
Host smart-d67de7c8-305b-4006-bf31-eebd60fb3673
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503972483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1503972483
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3184959429
Short name T175
Test name
Test status
Simulation time 2175600729 ps
CPU time 33.55 seconds
Started Mar 26 12:53:31 PM PDT 24
Finished Mar 26 12:54:05 PM PDT 24
Peak memory 200052 kb
Host smart-f48f6ee1-9015-42ba-bd76-eefaee7309d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184959429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3184959429
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.884160236
Short name T63
Test name
Test status
Simulation time 499423272 ps
CPU time 4.21 seconds
Started Mar 26 12:53:33 PM PDT 24
Finished Mar 26 12:53:37 PM PDT 24
Peak memory 199864 kb
Host smart-4998e506-a67b-4a4c-8260-0b308a4541cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884160236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.884160236
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.3502999310
Short name T426
Test name
Test status
Simulation time 45201709522 ps
CPU time 195.71 seconds
Started Mar 26 12:53:44 PM PDT 24
Finished Mar 26 12:57:00 PM PDT 24
Peak memory 199984 kb
Host smart-f16e0161-3b7e-4e8a-8002-8b12055ba527
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502999310 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3502999310
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.1658280434
Short name T428
Test name
Test status
Simulation time 207894083 ps
CPU time 1.23 seconds
Started Mar 26 12:53:44 PM PDT 24
Finished Mar 26 12:53:45 PM PDT 24
Peak memory 199976 kb
Host smart-2ad1ea63-0001-45b8-b016-667006fff7bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658280434 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.1658280434
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.3425953675
Short name T313
Test name
Test status
Simulation time 11123582169 ps
CPU time 443.75 seconds
Started Mar 26 12:53:44 PM PDT 24
Finished Mar 26 01:01:08 PM PDT 24
Peak memory 199916 kb
Host smart-1a62ba13-d847-48d7-81c3-f826271684cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425953675 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.3425953675
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1722668774
Short name T168
Test name
Test status
Simulation time 6079592843 ps
CPU time 29.88 seconds
Started Mar 26 12:53:47 PM PDT 24
Finished Mar 26 12:54:17 PM PDT 24
Peak memory 199920 kb
Host smart-cbe0c20a-7d31-44aa-afc6-210ec7b079f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722668774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1722668774
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3847288084
Short name T388
Test name
Test status
Simulation time 117769345 ps
CPU time 0.55 seconds
Started Mar 26 12:53:44 PM PDT 24
Finished Mar 26 12:53:45 PM PDT 24
Peak memory 195360 kb
Host smart-ee29a206-cbee-423e-b13b-104a768cd5de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847288084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3847288084
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.1742020290
Short name T55
Test name
Test status
Simulation time 130531550 ps
CPU time 1.41 seconds
Started Mar 26 12:53:45 PM PDT 24
Finished Mar 26 12:53:47 PM PDT 24
Peak memory 199992 kb
Host smart-adcf28ba-70fd-40cc-bb77-7c0d484ef481
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1742020290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.1742020290
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3261462136
Short name T248
Test name
Test status
Simulation time 1311836890 ps
CPU time 60.05 seconds
Started Mar 26 12:53:48 PM PDT 24
Finished Mar 26 12:54:48 PM PDT 24
Peak memory 199820 kb
Host smart-c6a7ae46-0b09-4ee4-83be-19d460f0a8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261462136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3261462136
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.645833891
Short name T535
Test name
Test status
Simulation time 1805116007 ps
CPU time 111.52 seconds
Started Mar 26 12:53:43 PM PDT 24
Finished Mar 26 12:55:34 PM PDT 24
Peak memory 199964 kb
Host smart-d74e3c47-cf6e-442e-8fa3-ccc18b766f90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=645833891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.645833891
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3223454888
Short name T294
Test name
Test status
Simulation time 17111567508 ps
CPU time 154.39 seconds
Started Mar 26 12:53:45 PM PDT 24
Finished Mar 26 12:56:20 PM PDT 24
Peak memory 200060 kb
Host smart-ddb67100-4a87-4e70-90c8-29f13629cc68
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223454888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3223454888
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2225315842
Short name T400
Test name
Test status
Simulation time 2939975973 ps
CPU time 61.48 seconds
Started Mar 26 12:53:45 PM PDT 24
Finished Mar 26 12:54:46 PM PDT 24
Peak memory 199880 kb
Host smart-4f73abae-abdd-46ba-b66e-dd0832e7dc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225315842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2225315842
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.1065163050
Short name T345
Test name
Test status
Simulation time 64018138 ps
CPU time 2.13 seconds
Started Mar 26 12:53:43 PM PDT 24
Finished Mar 26 12:53:45 PM PDT 24
Peak memory 199904 kb
Host smart-0f23e3e7-e8ae-41c6-93d3-5ee6e19e4ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065163050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1065163050
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3687352374
Short name T401
Test name
Test status
Simulation time 304544037473 ps
CPU time 1118.02 seconds
Started Mar 26 12:53:45 PM PDT 24
Finished Mar 26 01:12:23 PM PDT 24
Peak memory 208084 kb
Host smart-8aed6e25-2ae5-41ba-910c-0e64414359b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687352374 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3687352374
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.4028930042
Short name T563
Test name
Test status
Simulation time 74162723 ps
CPU time 1.02 seconds
Started Mar 26 12:53:49 PM PDT 24
Finished Mar 26 12:53:50 PM PDT 24
Peak memory 198052 kb
Host smart-4a940bb1-3168-451d-9b07-9853acb57ef3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028930042 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.4028930042
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.3913710581
Short name T488
Test name
Test status
Simulation time 49899490308 ps
CPU time 451.24 seconds
Started Mar 26 12:53:44 PM PDT 24
Finished Mar 26 01:01:16 PM PDT 24
Peak memory 199944 kb
Host smart-3abc2c0f-edba-4327-8ec7-497ef9e65809
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913710581 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.3913710581
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2029014574
Short name T234
Test name
Test status
Simulation time 813897706 ps
CPU time 12.97 seconds
Started Mar 26 12:53:43 PM PDT 24
Finished Mar 26 12:53:57 PM PDT 24
Peak memory 200028 kb
Host smart-79874514-2522-4046-b257-67d99c712517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029014574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2029014574
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2386113393
Short name T465
Test name
Test status
Simulation time 17946774 ps
CPU time 0.54 seconds
Started Mar 26 12:53:54 PM PDT 24
Finished Mar 26 12:53:54 PM PDT 24
Peak memory 195084 kb
Host smart-00d37501-64bd-4bc0-bbf8-364788070a82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386113393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2386113393
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.2745382866
Short name T454
Test name
Test status
Simulation time 15583654540 ps
CPU time 76.89 seconds
Started Mar 26 12:53:45 PM PDT 24
Finished Mar 26 12:55:02 PM PDT 24
Peak memory 231920 kb
Host smart-65f94d69-2947-45ff-a3bc-36a6d3fd4f64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2745382866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.2745382866
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3375660135
Short name T99
Test name
Test status
Simulation time 4644610407 ps
CPU time 21.07 seconds
Started Mar 26 12:53:56 PM PDT 24
Finished Mar 26 12:54:19 PM PDT 24
Peak memory 199992 kb
Host smart-081f4c54-1813-4aff-b1e6-e589daf0df78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375660135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3375660135
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2270232092
Short name T433
Test name
Test status
Simulation time 4603686973 ps
CPU time 65.25 seconds
Started Mar 26 12:53:47 PM PDT 24
Finished Mar 26 12:54:53 PM PDT 24
Peak memory 199916 kb
Host smart-a04d38de-4469-4ac0-8b30-40e4ea9aa002
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2270232092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2270232092
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1326660373
Short name T518
Test name
Test status
Simulation time 202095265102 ps
CPU time 190.54 seconds
Started Mar 26 12:53:54 PM PDT 24
Finished Mar 26 12:57:06 PM PDT 24
Peak memory 199964 kb
Host smart-ce9f9950-0c95-4d53-9dbf-9a6418c2fbd2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326660373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1326660373
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.22720461
Short name T444
Test name
Test status
Simulation time 1369995387 ps
CPU time 7.73 seconds
Started Mar 26 12:53:47 PM PDT 24
Finished Mar 26 12:53:55 PM PDT 24
Peak memory 199848 kb
Host smart-8e92db4c-d767-4d2b-b596-f12e7f18de3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22720461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.22720461
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2171474463
Short name T190
Test name
Test status
Simulation time 679143293 ps
CPU time 3.2 seconds
Started Mar 26 12:53:44 PM PDT 24
Finished Mar 26 12:53:47 PM PDT 24
Peak memory 199928 kb
Host smart-b9caf817-9b1e-41a4-84c0-dacf46d358e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171474463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2171474463
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2238337226
Short name T89
Test name
Test status
Simulation time 39140507467 ps
CPU time 395.45 seconds
Started Mar 26 12:53:53 PM PDT 24
Finished Mar 26 01:00:29 PM PDT 24
Peak memory 216356 kb
Host smart-bd040826-38bd-46fe-8c57-132928a6e2b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238337226 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2238337226
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.3058155246
Short name T244
Test name
Test status
Simulation time 55077629 ps
CPU time 1.22 seconds
Started Mar 26 12:53:56 PM PDT 24
Finished Mar 26 12:53:57 PM PDT 24
Peak memory 200004 kb
Host smart-c59870a1-d7b1-4b92-b759-918be96e224d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058155246 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.3058155246
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.2844856283
Short name T195
Test name
Test status
Simulation time 240099675608 ps
CPU time 539.39 seconds
Started Mar 26 12:53:59 PM PDT 24
Finished Mar 26 01:02:59 PM PDT 24
Peak memory 199828 kb
Host smart-ca6368c5-287d-417f-8d7b-1e225531e2d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844856283 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.2844856283
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1709343029
Short name T349
Test name
Test status
Simulation time 6971766587 ps
CPU time 72.96 seconds
Started Mar 26 12:53:51 PM PDT 24
Finished Mar 26 12:55:04 PM PDT 24
Peak memory 200004 kb
Host smart-85b70bee-7172-4ff0-a6b2-81619f175eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709343029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1709343029
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3595275727
Short name T460
Test name
Test status
Simulation time 12963657 ps
CPU time 0.57 seconds
Started Mar 26 12:53:51 PM PDT 24
Finished Mar 26 12:53:52 PM PDT 24
Peak memory 194436 kb
Host smart-47ff6538-fe62-4464-acad-f643f0a2e228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595275727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3595275727
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.2660392197
Short name T585
Test name
Test status
Simulation time 1350335972 ps
CPU time 12.75 seconds
Started Mar 26 12:53:54 PM PDT 24
Finished Mar 26 12:54:08 PM PDT 24
Peak memory 216168 kb
Host smart-220c5017-09ca-4743-86c2-3b2d4d8672e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2660392197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2660392197
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2633947791
Short name T437
Test name
Test status
Simulation time 719647559 ps
CPU time 35.12 seconds
Started Mar 26 12:53:53 PM PDT 24
Finished Mar 26 12:54:29 PM PDT 24
Peak memory 199888 kb
Host smart-e988ae00-3cb9-42c3-8e88-414a6b629e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633947791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2633947791
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.330787772
Short name T591
Test name
Test status
Simulation time 3210149605 ps
CPU time 90.53 seconds
Started Mar 26 12:53:53 PM PDT 24
Finished Mar 26 12:55:24 PM PDT 24
Peak memory 199936 kb
Host smart-e2137bac-8590-4542-af21-e75e2dd42e40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=330787772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.330787772
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2679196266
Short name T230
Test name
Test status
Simulation time 11396992652 ps
CPU time 213.53 seconds
Started Mar 26 12:53:53 PM PDT 24
Finished Mar 26 12:57:27 PM PDT 24
Peak memory 200084 kb
Host smart-c269cf4c-604d-4c71-b3de-a46438bbb49f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679196266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2679196266
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.2369809846
Short name T4
Test name
Test status
Simulation time 1820855651 ps
CPU time 105.42 seconds
Started Mar 26 12:53:57 PM PDT 24
Finished Mar 26 12:55:44 PM PDT 24
Peak memory 199884 kb
Host smart-3115ee21-21ca-431b-9c6b-6b838ab67b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369809846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2369809846
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.1852543237
Short name T590
Test name
Test status
Simulation time 51055498 ps
CPU time 1.01 seconds
Started Mar 26 12:53:54 PM PDT 24
Finished Mar 26 12:53:57 PM PDT 24
Peak memory 198636 kb
Host smart-ff1b72f7-d2e9-430e-9b67-350069103c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852543237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1852543237
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3704119353
Short name T151
Test name
Test status
Simulation time 358107481645 ps
CPU time 1247.36 seconds
Started Mar 26 12:53:55 PM PDT 24
Finished Mar 26 01:14:43 PM PDT 24
Peak memory 215508 kb
Host smart-cc3060ad-9de9-43be-8281-53e7304fd0fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704119353 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3704119353
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.3294181051
Short name T381
Test name
Test status
Simulation time 43995721 ps
CPU time 1.15 seconds
Started Mar 26 12:53:57 PM PDT 24
Finished Mar 26 12:54:00 PM PDT 24
Peak memory 199408 kb
Host smart-5ca90619-0b60-4a9d-bad4-040b2a21dcd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294181051 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.3294181051
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.3436011306
Short name T478
Test name
Test status
Simulation time 32685275069 ps
CPU time 463.02 seconds
Started Mar 26 12:53:57 PM PDT 24
Finished Mar 26 01:01:41 PM PDT 24
Peak memory 200024 kb
Host smart-153c2d13-5930-4b1b-82c4-f117e6b649d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436011306 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.3436011306
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1318729421
Short name T155
Test name
Test status
Simulation time 641448160 ps
CPU time 23.19 seconds
Started Mar 26 12:53:53 PM PDT 24
Finished Mar 26 12:54:16 PM PDT 24
Peak memory 199864 kb
Host smart-8ba6020b-41b8-4c8a-856b-31a2ebb9d161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318729421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1318729421
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3437889920
Short name T263
Test name
Test status
Simulation time 34876369 ps
CPU time 0.58 seconds
Started Mar 26 12:54:07 PM PDT 24
Finished Mar 26 12:54:08 PM PDT 24
Peak memory 194400 kb
Host smart-67ce4c7d-21e2-4fb9-adc7-71cdac6970d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437889920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3437889920
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2483656873
Short name T368
Test name
Test status
Simulation time 211658043 ps
CPU time 2.07 seconds
Started Mar 26 12:53:54 PM PDT 24
Finished Mar 26 12:53:58 PM PDT 24
Peak memory 199940 kb
Host smart-fd9f49f6-f9ea-46f4-956a-637550887312
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2483656873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2483656873
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3655202827
Short name T135
Test name
Test status
Simulation time 5634636215 ps
CPU time 53.66 seconds
Started Mar 26 12:53:53 PM PDT 24
Finished Mar 26 12:54:47 PM PDT 24
Peak memory 199900 kb
Host smart-1d9de1f5-bebd-4c6e-9a51-295b934795aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655202827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3655202827
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.3284930376
Short name T179
Test name
Test status
Simulation time 1602180751 ps
CPU time 88.21 seconds
Started Mar 26 12:53:52 PM PDT 24
Finished Mar 26 12:55:21 PM PDT 24
Peak memory 200300 kb
Host smart-cdc84084-5aad-4cb0-8de4-1607a5c9dc25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3284930376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3284930376
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2854521149
Short name T50
Test name
Test status
Simulation time 31927217959 ps
CPU time 111.77 seconds
Started Mar 26 12:53:58 PM PDT 24
Finished Mar 26 12:55:50 PM PDT 24
Peak memory 199892 kb
Host smart-a03e6d9a-4f8f-4849-91c8-2d98227c8e7f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854521149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2854521149
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1249151665
Short name T367
Test name
Test status
Simulation time 579555204 ps
CPU time 34.38 seconds
Started Mar 26 12:53:53 PM PDT 24
Finished Mar 26 12:54:28 PM PDT 24
Peak memory 200016 kb
Host smart-991a5cf4-4282-43f4-80e4-befeef47a0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249151665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1249151665
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.226787218
Short name T436
Test name
Test status
Simulation time 417767499 ps
CPU time 3.19 seconds
Started Mar 26 12:53:54 PM PDT 24
Finished Mar 26 12:53:59 PM PDT 24
Peak memory 199884 kb
Host smart-e0269f23-919c-417c-bfdc-ba140ff5e987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226787218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.226787218
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.4256753703
Short name T122
Test name
Test status
Simulation time 7008497100 ps
CPU time 409.98 seconds
Started Mar 26 12:53:53 PM PDT 24
Finished Mar 26 01:00:43 PM PDT 24
Peak memory 200104 kb
Host smart-311b35e5-1810-4818-aa8e-bdd387fc2976
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256753703 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.4256753703
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.970026245
Short name T513
Test name
Test status
Simulation time 30115284 ps
CPU time 1.01 seconds
Started Mar 26 12:53:55 PM PDT 24
Finished Mar 26 12:53:57 PM PDT 24
Peak memory 199412 kb
Host smart-9a9d6cab-1bc1-4bc7-8a1b-c77273017a7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970026245 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.hmac_test_hmac_vectors.970026245
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.426281302
Short name T366
Test name
Test status
Simulation time 212809735598 ps
CPU time 539.05 seconds
Started Mar 26 12:53:54 PM PDT 24
Finished Mar 26 01:02:54 PM PDT 24
Peak memory 199932 kb
Host smart-f509207d-da4c-4487-81f8-70254dd7cb3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426281302 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.426281302
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1983737708
Short name T350
Test name
Test status
Simulation time 7672772707 ps
CPU time 33.55 seconds
Started Mar 26 12:53:53 PM PDT 24
Finished Mar 26 12:54:27 PM PDT 24
Peak memory 199972 kb
Host smart-065493ec-7d03-435d-b12c-7aa5568fae32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983737708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1983737708
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3162982572
Short name T441
Test name
Test status
Simulation time 30279600 ps
CPU time 0.58 seconds
Started Mar 26 12:54:06 PM PDT 24
Finished Mar 26 12:54:07 PM PDT 24
Peak memory 195460 kb
Host smart-e9a50c12-48bc-47e2-8bc3-9a1fe5b10319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162982572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3162982572
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.242698705
Short name T402
Test name
Test status
Simulation time 8156847673 ps
CPU time 56.47 seconds
Started Mar 26 12:54:08 PM PDT 24
Finished Mar 26 12:55:05 PM PDT 24
Peak memory 245888 kb
Host smart-1695f2f5-7dde-4b1e-bb37-f203f64d4b2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=242698705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.242698705
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.2702136217
Short name T399
Test name
Test status
Simulation time 2407200813 ps
CPU time 10.1 seconds
Started Mar 26 12:54:13 PM PDT 24
Finished Mar 26 12:54:23 PM PDT 24
Peak memory 200304 kb
Host smart-33921b80-ba9d-4922-87eb-9611e11d2cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702136217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2702136217
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3726974212
Short name T307
Test name
Test status
Simulation time 10621064881 ps
CPU time 157.31 seconds
Started Mar 26 12:54:14 PM PDT 24
Finished Mar 26 12:56:51 PM PDT 24
Peak memory 200288 kb
Host smart-abf408cd-c4e5-4174-80fe-e2976e616643
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3726974212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3726974212
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.3389513334
Short name T548
Test name
Test status
Simulation time 13423792501 ps
CPU time 196.06 seconds
Started Mar 26 12:54:06 PM PDT 24
Finished Mar 26 12:57:23 PM PDT 24
Peak memory 199896 kb
Host smart-4f85aeeb-f2e0-4fc1-a020-61bfdb221258
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389513334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3389513334
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2320079191
Short name T551
Test name
Test status
Simulation time 5857912792 ps
CPU time 110.48 seconds
Started Mar 26 12:54:14 PM PDT 24
Finished Mar 26 12:56:04 PM PDT 24
Peak memory 200328 kb
Host smart-1b5b8f3e-738b-4a11-8de4-d3358392d9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320079191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2320079191
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3345456787
Short name T258
Test name
Test status
Simulation time 187813002 ps
CPU time 3.13 seconds
Started Mar 26 12:54:14 PM PDT 24
Finished Mar 26 12:54:17 PM PDT 24
Peak memory 200204 kb
Host smart-35a176a0-a54f-475e-863b-1d99eacb4778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345456787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3345456787
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.3451976423
Short name T319
Test name
Test status
Simulation time 60461171102 ps
CPU time 847.38 seconds
Started Mar 26 12:54:07 PM PDT 24
Finished Mar 26 01:08:15 PM PDT 24
Peak memory 240892 kb
Host smart-d2009ca9-0abb-4c12-bdbf-0758a853be05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451976423 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3451976423
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.1281551378
Short name T408
Test name
Test status
Simulation time 59202231 ps
CPU time 1.33 seconds
Started Mar 26 12:54:13 PM PDT 24
Finished Mar 26 12:54:15 PM PDT 24
Peak memory 200060 kb
Host smart-d22d82dd-5fe0-4364-8ad8-b8c18adc3f38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281551378 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.1281551378
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.3501397369
Short name T283
Test name
Test status
Simulation time 284743982799 ps
CPU time 481.69 seconds
Started Mar 26 12:54:06 PM PDT 24
Finished Mar 26 01:02:08 PM PDT 24
Peak memory 199900 kb
Host smart-cad53baf-bcee-48ef-86ec-8e39efc8f48c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501397369 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.3501397369
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.7602930
Short name T217
Test name
Test status
Simulation time 5666563136 ps
CPU time 39.59 seconds
Started Mar 26 12:54:05 PM PDT 24
Finished Mar 26 12:54:45 PM PDT 24
Peak memory 199992 kb
Host smart-8fec8d78-44d0-4129-83fb-f24b4d3e71e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7602930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.7602930
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.351523878
Short name T580
Test name
Test status
Simulation time 34980531 ps
CPU time 0.6 seconds
Started Mar 26 12:54:23 PM PDT 24
Finished Mar 26 12:54:24 PM PDT 24
Peak memory 195440 kb
Host smart-28784ab5-f453-4f05-a296-495d8b8704a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351523878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.351523878
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1165993624
Short name T480
Test name
Test status
Simulation time 379334118 ps
CPU time 3.37 seconds
Started Mar 26 12:54:05 PM PDT 24
Finished Mar 26 12:54:09 PM PDT 24
Peak memory 215996 kb
Host smart-7db0ce9b-07bb-4553-b74e-0b1b91f3cce8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1165993624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1165993624
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.132357450
Short name T321
Test name
Test status
Simulation time 2508059188 ps
CPU time 44.28 seconds
Started Mar 26 12:54:05 PM PDT 24
Finished Mar 26 12:54:50 PM PDT 24
Peak memory 199972 kb
Host smart-1ec8ae6d-a72b-47b0-84b1-17b47b54a40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132357450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.132357450
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2244486821
Short name T238
Test name
Test status
Simulation time 1333056798 ps
CPU time 72.16 seconds
Started Mar 26 12:54:06 PM PDT 24
Finished Mar 26 12:55:19 PM PDT 24
Peak memory 199940 kb
Host smart-fa0b368e-ad0c-43f6-b7cc-b81a7e5a5b32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2244486821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2244486821
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3163664282
Short name T60
Test name
Test status
Simulation time 14160119111 ps
CPU time 65.44 seconds
Started Mar 26 12:54:14 PM PDT 24
Finished Mar 26 12:55:19 PM PDT 24
Peak memory 200284 kb
Host smart-5875e28e-ed10-4760-a448-b3b4444acfe1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163664282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3163664282
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.3794265142
Short name T532
Test name
Test status
Simulation time 2092328786 ps
CPU time 29.28 seconds
Started Mar 26 12:54:05 PM PDT 24
Finished Mar 26 12:54:35 PM PDT 24
Peak memory 199868 kb
Host smart-5d43c6f3-ed70-4b61-ac1f-876e5dd0ce57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794265142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3794265142
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3365770717
Short name T162
Test name
Test status
Simulation time 198696772 ps
CPU time 1.16 seconds
Started Mar 26 12:54:09 PM PDT 24
Finished Mar 26 12:54:10 PM PDT 24
Peak memory 199848 kb
Host smart-1f78527f-68f0-43dd-b431-72dc06185081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365770717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3365770717
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.627022505
Short name T472
Test name
Test status
Simulation time 4691480087 ps
CPU time 31.34 seconds
Started Mar 26 12:54:22 PM PDT 24
Finished Mar 26 12:54:54 PM PDT 24
Peak memory 203060 kb
Host smart-26d7a262-2ed8-4f44-a87f-e6ea8d6b0552
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627022505 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.627022505
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.3502997862
Short name T172
Test name
Test status
Simulation time 49456231 ps
CPU time 1.05 seconds
Started Mar 26 12:54:24 PM PDT 24
Finished Mar 26 12:54:25 PM PDT 24
Peak memory 199772 kb
Host smart-cbc82c26-6cb4-43f7-9fe9-9b20b9b85e99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502997862 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.3502997862
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.251214223
Short name T379
Test name
Test status
Simulation time 251824297135 ps
CPU time 510.75 seconds
Started Mar 26 12:54:05 PM PDT 24
Finished Mar 26 01:02:37 PM PDT 24
Peak memory 199900 kb
Host smart-13b43542-b1cc-4271-a597-baf43db75e5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251214223 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.251214223
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.2894941945
Short name T81
Test name
Test status
Simulation time 3004251168 ps
CPU time 26.19 seconds
Started Mar 26 12:54:05 PM PDT 24
Finished Mar 26 12:54:33 PM PDT 24
Peak memory 200084 kb
Host smart-4851dd6e-6ca7-4fa5-9d5d-291a3bdb661a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894941945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.2894941945
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.2812874011
Short name T531
Test name
Test status
Simulation time 121346293 ps
CPU time 0.55 seconds
Started Mar 26 12:50:12 PM PDT 24
Finished Mar 26 12:50:13 PM PDT 24
Peak memory 194480 kb
Host smart-d72285d8-a95b-4e6d-a83f-81865327239b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812874011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.2812874011
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1896138095
Short name T376
Test name
Test status
Simulation time 2966108456 ps
CPU time 59.71 seconds
Started Mar 26 12:50:11 PM PDT 24
Finished Mar 26 12:51:11 PM PDT 24
Peak memory 223444 kb
Host smart-327237e9-702a-4c65-8e7b-21990cb0d9e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1896138095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1896138095
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.354120703
Short name T536
Test name
Test status
Simulation time 492856007 ps
CPU time 25.31 seconds
Started Mar 26 12:50:11 PM PDT 24
Finished Mar 26 12:50:37 PM PDT 24
Peak memory 200012 kb
Host smart-9c67451b-faa9-4d30-b96f-d75eebb0c2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354120703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.354120703
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.3663548186
Short name T576
Test name
Test status
Simulation time 22470728124 ps
CPU time 136.96 seconds
Started Mar 26 12:50:13 PM PDT 24
Finished Mar 26 12:52:30 PM PDT 24
Peak memory 199952 kb
Host smart-31f48930-2ebf-4b09-867f-3f8a5e4c3e3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3663548186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3663548186
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.2127537095
Short name T434
Test name
Test status
Simulation time 158928482768 ps
CPU time 120.93 seconds
Started Mar 26 12:50:09 PM PDT 24
Finished Mar 26 12:52:10 PM PDT 24
Peak memory 199944 kb
Host smart-3e586371-bba8-4abb-b80b-ee39d22983a7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127537095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.2127537095
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3170230091
Short name T219
Test name
Test status
Simulation time 16333958168 ps
CPU time 19.28 seconds
Started Mar 26 12:50:09 PM PDT 24
Finished Mar 26 12:50:29 PM PDT 24
Peak memory 199984 kb
Host smart-e52704b8-669d-4593-8e5a-e565d8985dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170230091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3170230091
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.2174450015
Short name T254
Test name
Test status
Simulation time 3073982400 ps
CPU time 7.72 seconds
Started Mar 26 12:50:13 PM PDT 24
Finished Mar 26 12:50:21 PM PDT 24
Peak memory 199956 kb
Host smart-8452bca0-78b2-43c2-9926-4c991fc23ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174450015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2174450015
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.2268177296
Short name T573
Test name
Test status
Simulation time 188761861433 ps
CPU time 544.79 seconds
Started Mar 26 12:50:14 PM PDT 24
Finished Mar 26 12:59:19 PM PDT 24
Peak memory 200004 kb
Host smart-b72054cc-4d74-42c1-9cd4-2d6bab821856
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268177296 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.2268177296
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.2023068314
Short name T353
Test name
Test status
Simulation time 162182165 ps
CPU time 1.05 seconds
Started Mar 26 12:50:14 PM PDT 24
Finished Mar 26 12:50:15 PM PDT 24
Peak memory 199428 kb
Host smart-9738f35d-787a-4f7c-a847-6e7b341dd310
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023068314 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.2023068314
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.122568511
Short name T589
Test name
Test status
Simulation time 20243891702 ps
CPU time 457.99 seconds
Started Mar 26 12:50:13 PM PDT 24
Finished Mar 26 12:57:52 PM PDT 24
Peak memory 199928 kb
Host smart-d12915ca-2130-46f7-85e5-2c7670bdd18a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122568511 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.122568511
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.1416508484
Short name T202
Test name
Test status
Simulation time 643316604 ps
CPU time 7.93 seconds
Started Mar 26 12:50:13 PM PDT 24
Finished Mar 26 12:50:21 PM PDT 24
Peak memory 199548 kb
Host smart-4fde2011-ebdb-493f-b475-c83bfaebf27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416508484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.1416508484
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/56.hmac_stress_all_with_rand_reset.2568661460
Short name T10
Test name
Test status
Simulation time 27878271778 ps
CPU time 408.76 seconds
Started Mar 26 12:54:25 PM PDT 24
Finished Mar 26 01:01:14 PM PDT 24
Peak memory 224592 kb
Host smart-7423e562-a5cd-4822-b1f8-87d465a3f2b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2568661460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.hmac_stress_all_with_rand_reset.2568661460
Directory /workspace/56.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_alert_test.3422865682
Short name T440
Test name
Test status
Simulation time 14907403 ps
CPU time 0.56 seconds
Started Mar 26 12:50:11 PM PDT 24
Finished Mar 26 12:50:12 PM PDT 24
Peak memory 195344 kb
Host smart-f4bf8508-cbbf-406d-9ce7-4eb0ef9ca113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422865682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.3422865682
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3171302948
Short name T316
Test name
Test status
Simulation time 1948728495 ps
CPU time 47.74 seconds
Started Mar 26 12:50:09 PM PDT 24
Finished Mar 26 12:50:57 PM PDT 24
Peak memory 223516 kb
Host smart-6ba1d88d-0cae-4ab3-85ac-04edcf2ccc1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3171302948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3171302948
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.932031659
Short name T337
Test name
Test status
Simulation time 1077912900 ps
CPU time 15.63 seconds
Started Mar 26 12:50:12 PM PDT 24
Finished Mar 26 12:50:29 PM PDT 24
Peak memory 199900 kb
Host smart-04ece23c-e71f-4932-97df-5d69b5e56587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932031659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.932031659
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2643474815
Short name T482
Test name
Test status
Simulation time 579729766 ps
CPU time 33.58 seconds
Started Mar 26 12:50:12 PM PDT 24
Finished Mar 26 12:50:46 PM PDT 24
Peak memory 199984 kb
Host smart-e40efe64-bce6-40e8-a190-e5c9440833e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2643474815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2643474815
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3592841626
Short name T356
Test name
Test status
Simulation time 4466687213 ps
CPU time 43.52 seconds
Started Mar 26 12:50:10 PM PDT 24
Finished Mar 26 12:50:54 PM PDT 24
Peak memory 199912 kb
Host smart-0eb60e1d-d8b9-4afc-b3ac-b1c7b3e70e39
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592841626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3592841626
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1675887676
Short name T101
Test name
Test status
Simulation time 2310420785 ps
CPU time 70.65 seconds
Started Mar 26 12:50:12 PM PDT 24
Finished Mar 26 12:51:24 PM PDT 24
Peak memory 199936 kb
Host smart-15480d75-726f-492a-afd9-ff88f05fe38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675887676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1675887676
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.1032188413
Short name T574
Test name
Test status
Simulation time 78657625 ps
CPU time 1.06 seconds
Started Mar 26 12:50:09 PM PDT 24
Finished Mar 26 12:50:11 PM PDT 24
Peak memory 199692 kb
Host smart-01f50b7f-dba3-4b04-a6ce-9b1f6e89231c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032188413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1032188413
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.2458729551
Short name T577
Test name
Test status
Simulation time 17234001719 ps
CPU time 843.02 seconds
Started Mar 26 12:50:13 PM PDT 24
Finished Mar 26 01:04:17 PM PDT 24
Peak memory 235816 kb
Host smart-e6f11a96-e77e-46ed-9638-a3863aad3d71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458729551 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2458729551
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.709637492
Short name T331
Test name
Test status
Simulation time 114550695 ps
CPU time 1.35 seconds
Started Mar 26 12:50:14 PM PDT 24
Finished Mar 26 12:50:16 PM PDT 24
Peak memory 199772 kb
Host smart-73dc4a41-edb6-4fe4-96e2-3f401352b5af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709637492 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_hmac_vectors.709637492
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.1243475640
Short name T145
Test name
Test status
Simulation time 17213227238 ps
CPU time 453.21 seconds
Started Mar 26 12:50:12 PM PDT 24
Finished Mar 26 12:57:47 PM PDT 24
Peak memory 199948 kb
Host smart-a52de1fb-2988-4f54-9ef5-06cfa06aa6e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243475640 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.1243475640
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.4274113118
Short name T268
Test name
Test status
Simulation time 6250412384 ps
CPU time 52.22 seconds
Started Mar 26 12:50:10 PM PDT 24
Finished Mar 26 12:51:03 PM PDT 24
Peak memory 199956 kb
Host smart-b91d2296-2881-42ca-820f-62ef6bf18c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274113118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.4274113118
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/65.hmac_stress_all_with_rand_reset.3615910381
Short name T73
Test name
Test status
Simulation time 26273792875 ps
CPU time 715.98 seconds
Started Mar 26 12:54:25 PM PDT 24
Finished Mar 26 01:06:22 PM PDT 24
Peak memory 216392 kb
Host smart-531faf72-0ce1-48bc-8903-f58020874c2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3615910381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.hmac_stress_all_with_rand_reset.3615910381
Directory /workspace/65.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.506608531
Short name T512
Test name
Test status
Simulation time 17551734 ps
CPU time 0.59 seconds
Started Mar 26 12:50:13 PM PDT 24
Finished Mar 26 12:50:14 PM PDT 24
Peak memory 195088 kb
Host smart-f56965b4-1ad4-403c-96e3-e8f7b0154b14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506608531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.506608531
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.434195834
Short name T269
Test name
Test status
Simulation time 911572169 ps
CPU time 36.83 seconds
Started Mar 26 12:50:14 PM PDT 24
Finished Mar 26 12:50:52 PM PDT 24
Peak memory 221520 kb
Host smart-a28bcecd-6626-4ab4-ba2a-bbe2f35f08d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=434195834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.434195834
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2476539046
Short name T3
Test name
Test status
Simulation time 935253702 ps
CPU time 14.19 seconds
Started Mar 26 12:50:10 PM PDT 24
Finished Mar 26 12:50:24 PM PDT 24
Peak memory 199836 kb
Host smart-40a998aa-b107-40ac-9964-f20844307a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476539046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2476539046
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.3775136975
Short name T332
Test name
Test status
Simulation time 1657487526 ps
CPU time 51.8 seconds
Started Mar 26 12:50:09 PM PDT 24
Finished Mar 26 12:51:01 PM PDT 24
Peak memory 199856 kb
Host smart-ff6bcfc3-9073-4c8c-88df-2179b3b1567b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3775136975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3775136975
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1094547176
Short name T414
Test name
Test status
Simulation time 5352445208 ps
CPU time 114.99 seconds
Started Mar 26 12:50:12 PM PDT 24
Finished Mar 26 12:52:08 PM PDT 24
Peak memory 199980 kb
Host smart-bd49672f-7e15-4223-8125-c9baaae8d33f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094547176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1094547176
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2089031146
Short name T344
Test name
Test status
Simulation time 828614458 ps
CPU time 12.12 seconds
Started Mar 26 12:50:12 PM PDT 24
Finished Mar 26 12:50:25 PM PDT 24
Peak memory 199904 kb
Host smart-8b172e7a-0262-434e-85c8-1b3ecc7a2401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089031146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2089031146
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.3798372467
Short name T298
Test name
Test status
Simulation time 988752212 ps
CPU time 6.09 seconds
Started Mar 26 12:50:09 PM PDT 24
Finished Mar 26 12:50:15 PM PDT 24
Peak memory 199840 kb
Host smart-061a2f43-fcf6-4a32-91e7-4c4488ad7480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798372467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3798372467
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.2409972394
Short name T491
Test name
Test status
Simulation time 85741699139 ps
CPU time 1196.57 seconds
Started Mar 26 12:50:10 PM PDT 24
Finished Mar 26 01:10:08 PM PDT 24
Peak memory 232124 kb
Host smart-8475d67d-fdb0-41d9-a771-ad68999d3eef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409972394 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.2409972394
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.3307329934
Short name T199
Test name
Test status
Simulation time 99569784 ps
CPU time 1.08 seconds
Started Mar 26 12:50:10 PM PDT 24
Finished Mar 26 12:50:11 PM PDT 24
Peak memory 199384 kb
Host smart-9a271f66-0cac-46a0-9ff9-249e11a0831e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307329934 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.3307329934
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.1811974251
Short name T587
Test name
Test status
Simulation time 45433095821 ps
CPU time 572.06 seconds
Started Mar 26 12:50:11 PM PDT 24
Finished Mar 26 12:59:43 PM PDT 24
Peak memory 200252 kb
Host smart-1c2b4032-997d-426c-9c06-7e2eaf953fd4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811974251 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.1811974251
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.916855952
Short name T173
Test name
Test status
Simulation time 3145982206 ps
CPU time 13.17 seconds
Started Mar 26 12:50:11 PM PDT 24
Finished Mar 26 12:50:25 PM PDT 24
Peak memory 200080 kb
Host smart-290484fd-4af2-4932-95e6-a0cdc8872e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916855952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.916855952
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3034765147
Short name T161
Test name
Test status
Simulation time 16646711 ps
CPU time 0.56 seconds
Started Mar 26 12:50:23 PM PDT 24
Finished Mar 26 12:50:24 PM PDT 24
Peak memory 194488 kb
Host smart-8d4804d6-ce46-42a3-bf5a-b6c3e9f0ca8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034765147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3034765147
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3608452301
Short name T288
Test name
Test status
Simulation time 2132135438 ps
CPU time 39.75 seconds
Started Mar 26 12:50:14 PM PDT 24
Finished Mar 26 12:50:54 PM PDT 24
Peak memory 229204 kb
Host smart-f0ed48fd-74d3-45fb-9126-75fd04d87afe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3608452301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3608452301
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3886496387
Short name T438
Test name
Test status
Simulation time 2649741849 ps
CPU time 37.25 seconds
Started Mar 26 12:50:12 PM PDT 24
Finished Mar 26 12:50:50 PM PDT 24
Peak memory 199980 kb
Host smart-25c35319-d28c-4173-b47f-9152a89d0628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886496387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3886496387
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3148059705
Short name T262
Test name
Test status
Simulation time 71959775 ps
CPU time 0.76 seconds
Started Mar 26 12:50:11 PM PDT 24
Finished Mar 26 12:50:12 PM PDT 24
Peak memory 197256 kb
Host smart-17026f88-2770-413d-8feb-cd81213248fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3148059705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3148059705
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.1156769235
Short name T377
Test name
Test status
Simulation time 1255199196 ps
CPU time 62.95 seconds
Started Mar 26 12:50:11 PM PDT 24
Finished Mar 26 12:51:14 PM PDT 24
Peak memory 200036 kb
Host smart-cb2dc6c6-0b1d-4d02-871d-89267ee1545f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156769235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1156769235
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1665015949
Short name T556
Test name
Test status
Simulation time 16184508795 ps
CPU time 87.96 seconds
Started Mar 26 12:50:10 PM PDT 24
Finished Mar 26 12:51:38 PM PDT 24
Peak memory 199988 kb
Host smart-c4c939e3-0b6f-4054-9bf9-e1ec9907a733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665015949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1665015949
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1316929762
Short name T280
Test name
Test status
Simulation time 1656303866 ps
CPU time 2.09 seconds
Started Mar 26 12:50:11 PM PDT 24
Finished Mar 26 12:50:13 PM PDT 24
Peak memory 199852 kb
Host smart-a3a610c6-e080-41da-917e-c706be5c430b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316929762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1316929762
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.635571050
Short name T484
Test name
Test status
Simulation time 94436852884 ps
CPU time 2648.62 seconds
Started Mar 26 12:50:21 PM PDT 24
Finished Mar 26 01:34:30 PM PDT 24
Peak memory 199976 kb
Host smart-5267b30b-a1a3-4eef-97bb-b4f601cfe0ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635571050 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.635571050
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.637473716
Short name T226
Test name
Test status
Simulation time 226073108 ps
CPU time 1.34 seconds
Started Mar 26 12:50:12 PM PDT 24
Finished Mar 26 12:50:14 PM PDT 24
Peak memory 199864 kb
Host smart-5b47771f-107f-4af5-8a50-8d091911a49b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637473716 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.hmac_test_hmac_vectors.637473716
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.3567461508
Short name T560
Test name
Test status
Simulation time 28385844751 ps
CPU time 505.99 seconds
Started Mar 26 12:50:11 PM PDT 24
Finished Mar 26 12:58:37 PM PDT 24
Peak memory 199932 kb
Host smart-e611cbc4-3b23-4770-a6ed-39b40c3c090d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567461508 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.3567461508
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1248716172
Short name T212
Test name
Test status
Simulation time 1513522925 ps
CPU time 22.44 seconds
Started Mar 26 12:50:09 PM PDT 24
Finished Mar 26 12:50:33 PM PDT 24
Peak memory 199852 kb
Host smart-b8ecc816-7f4b-4b00-9d21-5b82236b26a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248716172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1248716172
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2084637143
Short name T509
Test name
Test status
Simulation time 15942607 ps
CPU time 0.59 seconds
Started Mar 26 12:50:25 PM PDT 24
Finished Mar 26 12:50:26 PM PDT 24
Peak memory 195496 kb
Host smart-8db63476-f395-4533-a015-34f79195bedb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084637143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2084637143
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.403095303
Short name T404
Test name
Test status
Simulation time 2708195900 ps
CPU time 27.24 seconds
Started Mar 26 12:50:23 PM PDT 24
Finished Mar 26 12:50:50 PM PDT 24
Peak memory 216348 kb
Host smart-358b8f6a-21cb-4352-bc76-c3092cd0916c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=403095303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.403095303
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2681495734
Short name T520
Test name
Test status
Simulation time 4704935364 ps
CPU time 33.56 seconds
Started Mar 26 12:50:21 PM PDT 24
Finished Mar 26 12:50:54 PM PDT 24
Peak memory 200064 kb
Host smart-cd453c87-624b-4f8e-9758-68286c89d5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681495734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2681495734
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.924971348
Short name T360
Test name
Test status
Simulation time 2755596917 ps
CPU time 79.32 seconds
Started Mar 26 12:50:23 PM PDT 24
Finished Mar 26 12:51:42 PM PDT 24
Peak memory 199980 kb
Host smart-3eb0b32f-509a-4374-b817-62806b66f38e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=924971348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.924971348
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.2315607155
Short name T493
Test name
Test status
Simulation time 42313317100 ps
CPU time 186.48 seconds
Started Mar 26 12:50:23 PM PDT 24
Finished Mar 26 12:53:30 PM PDT 24
Peak memory 200096 kb
Host smart-a3bfe37b-dc13-4193-ab9e-ade53796b8f8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315607155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2315607155
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3025121140
Short name T308
Test name
Test status
Simulation time 24136865906 ps
CPU time 18.47 seconds
Started Mar 26 12:50:23 PM PDT 24
Finished Mar 26 12:50:42 PM PDT 24
Peak memory 200008 kb
Host smart-6991be01-ef7e-4149-bafb-9f63341a1b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025121140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3025121140
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3420292575
Short name T282
Test name
Test status
Simulation time 238583933 ps
CPU time 1.35 seconds
Started Mar 26 12:50:23 PM PDT 24
Finished Mar 26 12:50:24 PM PDT 24
Peak memory 199976 kb
Host smart-7e183faf-81d0-4334-86c1-4dece81773b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420292575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3420292575
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1404200086
Short name T224
Test name
Test status
Simulation time 30426291866 ps
CPU time 918.33 seconds
Started Mar 26 12:50:22 PM PDT 24
Finished Mar 26 01:05:40 PM PDT 24
Peak memory 216360 kb
Host smart-99cd2e9a-35c2-4dc9-ad1f-d6486df5e3e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404200086 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1404200086
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.1125172464
Short name T281
Test name
Test status
Simulation time 52762397 ps
CPU time 1.05 seconds
Started Mar 26 12:50:23 PM PDT 24
Finished Mar 26 12:50:24 PM PDT 24
Peak memory 199448 kb
Host smart-e763bf32-f976-4d2d-8952-b47290f585ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125172464 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.1125172464
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.998849110
Short name T369
Test name
Test status
Simulation time 8707973337 ps
CPU time 473.74 seconds
Started Mar 26 12:50:26 PM PDT 24
Finished Mar 26 12:58:20 PM PDT 24
Peak memory 199940 kb
Host smart-787c8065-5187-4979-b23e-e582cafa0422
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998849110 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.998849110
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.1959916028
Short name T575
Test name
Test status
Simulation time 1177630800 ps
CPU time 62.6 seconds
Started Mar 26 12:50:23 PM PDT 24
Finished Mar 26 12:51:26 PM PDT 24
Peak memory 199916 kb
Host smart-b9290ab7-5e2d-448d-97e4-91462656a2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959916028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1959916028
Directory /workspace/9.hmac_wipe_secret/latest
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