Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	12896807	1			T2	70200		T3	69322		T4	34
all_values[1]	12896807	1			T2	70200		T3	69322		T4	34
all_values[2]	12896807	1			T2	70200		T3	69322		T4	34

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

85943

1

T21

21

T6

82

T28

14

auto[1]

38604478

1

T2

210600

T3

207966

T4

102

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36614472

1

T2

202076

T3

199739

T4

98

auto[1]

2075949

1

T2

8524

T3

8227

T4

4

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	35831	1			T6	46		T28	5		T29	66
all_values[0]	auto[0]	auto[1]	476	1			T6	6		T28	2		T29	4
all_values[0]	auto[1]	auto[0]	12817096	1			T2	70006		T3	69128		T4	30
all_values[0]	auto[1]	auto[1]	43404	1			T2	194		T3	194		T4	4
all_values[1]	auto[0]	auto[0]	23683	1			T21	21		T28	7		T13	14
all_values[1]	auto[0]	auto[1]	186	1			T13	3		T15	1		T24	1
all_values[1]	auto[1]	auto[0]	12872459	1			T2	70200		T3	69322		T4	34
all_values[1]	auto[1]	auto[1]	479	1			T13	3		T18	1		T19	1
all_values[2]	auto[0]	auto[0]	20460	1			T6	30		T44	681		T13	3
all_values[2]	auto[0]	auto[1]	5307	1			T13	4		T15	875		T24	4
all_values[2]	auto[1]	auto[0]	10844943	1			T2	61870		T3	61289		T4	34
all_values[2]	auto[1]	auto[1]	2026097	1			T2	8330		T3	8033		T13	47471