Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6193974

1

T2

37183

T3

37173

T4

29

auto[1]

2467304

1

T5

98

T21

27

T6

67

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2448085

1

T5

127

T21

30

T6

47

auto[1]

6213193

1

T2

37183

T3

37173

T4

29

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5447331

1

T2

37183

T3

37173

T5

114

auto[1]

3213947

1

T4

29

T5

108

T21

783

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	5366323	1			T2	34706		T3	22983		T4	24
fifo_depth[1]	438818	1			T2	1450		T3	2424		T4	2
fifo_depth[2]	379359	1			T2	653		T3	2443		T4	2
fifo_depth[3]	315962	1			T2	255		T3	2073		T4	1
fifo_depth[4]	274363	1			T2	87		T3	1590		T5	2
fifo_depth[5]	243738	1			T2	27		T3	1388		T21	3
fifo_depth[6]	231595	1			T2	3		T3	1227		T21	1
fifo_depth[7]	201716	1			T2	2		T3	1013		T28	5
fifo_depth[8]	180561	1			T3	737		T28	3		T29	1
fifo_depth[9]	124159	1			T3	555		T28	4		T44	191
fifo_depth[10]	93506	1			T3	350		T28	2		T44	117
fifo_depth[11]	57749	1			T3	217		T44	64		T13	1697
fifo_depth[12]	55478	1			T3	99		T44	39		T13	2694
fifo_depth[13]	28302	1			T3	44		T28	2		T44	18
fifo_depth[14]	33541	1			T3	19		T44	9		T13	1251
fifo_depth[15]	22670	1			T3	7		T44	2		T13	860
fifo_depth[16]	83364	1			T3	3		T44	2		T13	2929

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3412568

1

T2

2477

T3

14190

T4

5

auto[1]

5248710

1

T2

34706

T3

22983

T4

24

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8543665

1

T2

37183

T3

37173

T4

29

auto[1]

117613

1

T13

978

T18

1229

T19

2614

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

207605

1

T13

1814

T18

541

T25

595

auto[0]

auto[0]

auto[0]

auto[1]

226399

1

T29

24

T13

2180

T18

1871

auto[0]

auto[0]

auto[1]

auto[0]

1105247

1

T2

2477

T3

14190

T21

46

auto[0]

auto[0]

auto[1]

auto[1]

180212

1

T29

17

T13

5066

T18

1216

auto[0]

auto[1]

auto[0]

auto[0]

410184

1

T5

11

T6

2

T28

9

auto[0]

auto[1]

auto[0]

auto[1]

435675

1

T5

10

T21

5

T28

16

auto[0]

auto[1]

auto[1]

auto[0]

435146

1

T4

5

T5

5

T21

108

auto[0]

auto[1]

auto[1]

auto[1]

412100

1

T5

2

T6

7

T28

7

auto[1]

auto[0]

auto[0]

auto[0]

214998

1

T5

20

T21

10

T6

19

auto[1]

auto[0]

auto[0]

auto[1]

203830

1

T5

25

T6

26

T28

16

auto[1]

auto[0]

auto[1]

auto[0]

3088560

1

T2

34706

T3

22983

T5

35

auto[1]

auto[0]

auto[1]

auto[1]

220480

1

T5

34

T21

7

T6

12

auto[1]

auto[1]

auto[0]

auto[0]

364600

1

T5

44

T28

3

T29

37

auto[1]

auto[1]

auto[0]

auto[1]

384794

1

T5

17

T21

15

T28

4

auto[1]

auto[1]

auto[1]

auto[0]

367634

1

T4

24

T5

9

T21

655

auto[1]

auto[1]

auto[1]

auto[1]

403814

1

T5

10

T6

22

T29

980

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

412412

1

T5

20

T21

10

T6

19

auto[0]

auto[0]

auto[0]

auto[1]

415936

1

T5

25

T6

26

T28

16

auto[0]

auto[0]

auto[1]

auto[0]

4180908

1

T2

37183

T3

37173

T5

35

auto[0]

auto[0]

auto[1]

auto[1]

392022

1

T5

34

T21

7

T6

12

auto[0]

auto[1]

auto[0]

auto[0]

756489

1

T5

55

T6

2

T28

12

auto[0]

auto[1]

auto[0]

auto[1]

804258

1

T5

27

T21

20

T28

20

auto[0]

auto[1]

auto[1]

auto[0]

779602

1

T4

29

T5

14

T21

763

auto[0]

auto[1]

auto[1]

auto[1]

802038

1

T5

12

T6

29

T28

7

auto[1]

auto[0]

auto[0]

auto[0]

10191

1

T13

47

T15

1944

T95

229

auto[1]

auto[0]

auto[0]

auto[1]

14293

1

T13

178

T18

188

T19

230

auto[1]

auto[0]

auto[1]

auto[0]

12899

1

T13

92

T18

7

T19

367

auto[1]

auto[0]

auto[1]

auto[1]

8670

1

T13

150

T18

95

T15

23

auto[1]

auto[1]

auto[0]

auto[0]

18295

1

T13

110

T18

53

T19

590

auto[1]

auto[1]

auto[0]

auto[1]

16211

1

T13

55

T18

822

T19

342

auto[1]

auto[1]

auto[1]

auto[0]

23178

1

T13

121

T18

24

T19

986

auto[1]

auto[1]

auto[1]

auto[1]

13876

1

T13

225

T18

40

T19

99

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	225189	1			T5	20		T21	10		T6	19
fifo_depth[0]	auto[0]	auto[0]	auto[1]	218123	1			T5	25		T6	26		T28	16
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3101459	1			T2	34706		T3	22983		T5	35
fifo_depth[0]	auto[0]	auto[1]	auto[1]	229150	1			T5	34		T21	7		T6	12
fifo_depth[0]	auto[1]	auto[0]	auto[0]	382895	1			T5	44		T28	3		T29	37
fifo_depth[0]	auto[1]	auto[0]	auto[1]	401005	1			T5	17		T21	15		T28	4
fifo_depth[0]	auto[1]	auto[1]	auto[0]	390812	1			T4	24		T5	9		T21	655
fifo_depth[0]	auto[1]	auto[1]	auto[1]	417690	1			T5	10		T6	22		T29	980
fifo_depth[1]	auto[0]	auto[0]	auto[0]	17304	1			T13	12		T18	42		T25	69
fifo_depth[1]	auto[0]	auto[0]	auto[1]	16448	1			T29	2		T13	27		T18	22
fifo_depth[1]	auto[0]	auto[1]	auto[0]	220185	1			T2	1450		T3	2424		T21	20
fifo_depth[1]	auto[0]	auto[1]	auto[1]	17321	1			T29	6		T13	2		T14	48
fifo_depth[1]	auto[1]	auto[0]	auto[0]	40010	1			T5	5		T29	4		T44	121
fifo_depth[1]	auto[1]	auto[0]	auto[1]	42510	1			T5	6		T21	1		T13	858
fifo_depth[1]	auto[1]	auto[1]	auto[0]	41588	1			T4	2		T5	3		T21	41
fifo_depth[1]	auto[1]	auto[1]	auto[1]	43452	1			T6	4		T28	2		T29	3
fifo_depth[2]	auto[0]	auto[0]	auto[0]	14171	1			T13	10		T18	32		T25	72
fifo_depth[2]	auto[0]	auto[0]	auto[1]	14087	1			T29	10		T13	34		T18	1
fifo_depth[2]	auto[0]	auto[1]	auto[0]	185654	1			T2	653		T3	2443		T21	11
fifo_depth[2]	auto[0]	auto[1]	auto[1]	14632	1			T29	3		T13	1		T14	63
fifo_depth[2]	auto[1]	auto[0]	auto[0]	36039	1			T5	3		T28	1		T29	2
fifo_depth[2]	auto[1]	auto[0]	auto[1]	38136	1			T5	1		T21	2		T13	842
fifo_depth[2]	auto[1]	auto[1]	auto[0]	37561	1			T4	2		T5	2		T21	38
fifo_depth[2]	auto[1]	auto[1]	auto[1]	39079	1			T5	1		T6	3		T28	2
fifo_depth[3]	auto[0]	auto[0]	auto[0]	11832	1			T13	9		T18	47		T25	76
fifo_depth[3]	auto[0]	auto[0]	auto[1]	11435	1			T29	1		T13	33		T18	22
fifo_depth[3]	auto[0]	auto[1]	auto[0]	146955	1			T2	255		T3	2073		T21	8
fifo_depth[3]	auto[0]	auto[1]	auto[1]	11555	1			T29	1		T13	27		T14	61
fifo_depth[3]	auto[1]	auto[0]	auto[0]	32140	1			T5	2		T6	1		T28	2
fifo_depth[3]	auto[1]	auto[0]	auto[1]	33918	1			T5	2		T21	2		T28	1
fifo_depth[3]	auto[1]	auto[1]	auto[0]	33703	1			T4	1		T21	22		T28	4
fifo_depth[3]	auto[1]	auto[1]	auto[1]	34424	1			T5	1		T44	179		T13	111
fifo_depth[4]	auto[0]	auto[0]	auto[0]	11480	1			T13	40		T18	39		T25	75
fifo_depth[4]	auto[0]	auto[0]	auto[1]	11193	1			T29	9		T13	38		T18	1
fifo_depth[4]	auto[0]	auto[1]	auto[0]	109696	1			T2	87		T3	1590		T21	7
fifo_depth[4]	auto[0]	auto[1]	auto[1]	11420	1			T29	6		T13	52		T18	1
fifo_depth[4]	auto[1]	auto[0]	auto[0]	31381	1			T5	1		T6	1		T28	1
fifo_depth[4]	auto[1]	auto[0]	auto[1]	33096	1			T5	1		T28	3		T13	838
fifo_depth[4]	auto[1]	auto[1]	auto[0]	32349	1			T21	3		T28	4		T44	14
fifo_depth[4]	auto[1]	auto[1]	auto[1]	33748	1			T29	19		T44	176		T13	118
fifo_depth[5]	auto[0]	auto[0]	auto[0]	9868	1			T13	9		T18	38		T25	57
fifo_depth[5]	auto[0]	auto[0]	auto[1]	9848	1			T13	37		T18	23		T25	125
fifo_depth[5]	auto[0]	auto[1]	auto[0]	90204	1			T2	27		T3	1388		T29	1
fifo_depth[5]	auto[0]	auto[1]	auto[1]	9832	1			T13	41		T14	54		T25	50
fifo_depth[5]	auto[1]	auto[0]	auto[0]	29736	1			T28	1		T44	135		T13	432
fifo_depth[5]	auto[1]	auto[0]	auto[1]	31423	1			T28	1		T29	1		T13	792
fifo_depth[5]	auto[1]	auto[1]	auto[0]	30876	1			T21	3		T28	4		T44	10
fifo_depth[5]	auto[1]	auto[1]	auto[1]	31951	1			T44	159		T13	123		T18	3
fifo_depth[6]	auto[0]	auto[0]	auto[0]	10355	1			T13	43		T18	36		T25	65
fifo_depth[6]	auto[0]	auto[0]	auto[1]	9889	1			T29	2		T13	33		T25	134
fifo_depth[6]	auto[0]	auto[1]	auto[0]	79061	1			T2	3		T3	1227		T13	5865
fifo_depth[6]	auto[0]	auto[1]	auto[1]	10018	1			T13	46		T14	49		T25	60
fifo_depth[6]	auto[1]	auto[0]	auto[0]	29524	1			T28	2		T44	126		T13	477
fifo_depth[6]	auto[1]	auto[0]	auto[1]	30897	1			T28	3		T29	2		T13	814
fifo_depth[6]	auto[1]	auto[1]	auto[0]	30594	1			T21	1		T44	10		T13	268
fifo_depth[6]	auto[1]	auto[1]	auto[1]	31257	1			T44	165		T13	127		T18	2
fifo_depth[7]	auto[0]	auto[0]	auto[0]	9024	1			T13	41		T18	44		T25	53
fifo_depth[7]	auto[0]	auto[0]	auto[1]	8866	1			T13	25		T18	21		T25	139
fifo_depth[7]	auto[0]	auto[1]	auto[0]	63393	1			T2	2		T3	1013		T13	4682
fifo_depth[7]	auto[0]	auto[1]	auto[1]	8904	1			T29	1		T13	47		T18	2
fifo_depth[7]	auto[1]	auto[0]	auto[0]	26758	1			T28	1		T44	111		T13	425
fifo_depth[7]	auto[1]	auto[0]	auto[1]	28040	1			T28	3		T13	756		T45	35
fifo_depth[7]	auto[1]	auto[1]	auto[0]	27982	1			T28	1		T44	14		T13	256
fifo_depth[7]	auto[1]	auto[1]	auto[1]	28749	1			T44	137		T13	144		T18	3
fifo_depth[8]	auto[0]	auto[0]	auto[0]	9840	1			T13	72		T18	32		T25	43
fifo_depth[8]	auto[0]	auto[0]	auto[1]	10285	1			T13	146		T18	1		T25	82
fifo_depth[8]	auto[0]	auto[1]	auto[0]	48460	1			T3	737		T13	3552		T46	564
fifo_depth[8]	auto[0]	auto[1]	auto[1]	9212	1			T13	746		T18	1		T14	31
fifo_depth[8]	auto[1]	auto[0]	auto[0]	24972	1			T28	1		T44	90		T13	440
fifo_depth[8]	auto[1]	auto[0]	auto[1]	25193	1			T28	1		T29	1		T13	637
fifo_depth[8]	auto[1]	auto[1]	auto[0]	25949	1			T44	9		T13	590		T45	111
fifo_depth[8]	auto[1]	auto[1]	auto[1]	26650	1			T28	1		T44	124		T13	149
fifo_depth[9]	auto[0]	auto[0]	auto[0]	6012	1			T13	15		T18	37		T25	37
fifo_depth[9]	auto[0]	auto[0]	auto[1]	6180	1			T13	21		T18	22		T25	75
fifo_depth[9]	auto[0]	auto[1]	auto[0]	32787	1			T3	555		T13	2197		T46	397
fifo_depth[9]	auto[0]	auto[1]	auto[1]	5869	1			T13	59		T18	2		T14	19
fifo_depth[9]	auto[1]	auto[0]	auto[0]	17952	1			T44	75		T13	326		T45	10
fifo_depth[9]	auto[1]	auto[0]	auto[1]	18367	1			T28	1		T13	483		T45	31
fifo_depth[9]	auto[1]	auto[1]	auto[0]	18377	1			T28	1		T44	4		T13	204
fifo_depth[9]	auto[1]	auto[1]	auto[1]	18615	1			T28	2		T44	112		T13	109
fifo_depth[10]	auto[0]	auto[0]	auto[0]	5276	1			T13	111		T18	26		T25	25
fifo_depth[10]	auto[0]	auto[0]	auto[1]	5616	1			T13	16		T25	49		T19	2
fifo_depth[10]	auto[0]	auto[1]	auto[0]	22248	1			T3	350		T13	1391		T46	262
fifo_depth[10]	auto[0]	auto[1]	auto[1]	5042	1			T13	76		T18	1		T14	14
fifo_depth[10]	auto[1]	auto[0]	auto[0]	13239	1			T44	47		T13	458		T45	15
fifo_depth[10]	auto[1]	auto[0]	auto[1]	13485	1			T28	1		T13	303		T45	17
fifo_depth[10]	auto[1]	auto[1]	auto[0]	14466	1			T28	1		T44	6		T13	156
fifo_depth[10]	auto[1]	auto[1]	auto[1]	14134	1			T44	64		T13	89		T18	6
fifo_depth[11]	auto[0]	auto[0]	auto[0]	3365	1			T13	16		T18	17		T25	16
fifo_depth[11]	auto[0]	auto[0]	auto[1]	3785	1			T13	11		T18	22		T25	38
fifo_depth[11]	auto[0]	auto[1]	auto[0]	13191	1			T3	217		T13	798		T46	147
fifo_depth[11]	auto[0]	auto[1]	auto[1]	3035	1			T13	57		T14	5		T25	17
fifo_depth[11]	auto[1]	auto[0]	auto[0]	8234	1			T44	24		T13	438		T45	4
fifo_depth[11]	auto[1]	auto[0]	auto[1]	8850	1			T13	190		T45	6		T18	12
fifo_depth[11]	auto[1]	auto[1]	auto[0]	8781	1			T44	4		T13	127		T45	38
fifo_depth[11]	auto[1]	auto[1]	auto[1]	8508	1			T44	36		T13	60		T18	6
fifo_depth[12]	auto[0]	auto[0]	auto[0]	5474	1			T13	142		T18	8		T25	5
fifo_depth[12]	auto[0]	auto[0]	auto[1]	6520	1			T13	126		T25	18		T19	19
fifo_depth[12]	auto[0]	auto[1]	auto[0]	9442	1			T3	99		T13	590		T46	68
fifo_depth[12]	auto[0]	auto[1]	auto[1]	3966	1			T13	686		T18	1		T14	5
fifo_depth[12]	auto[1]	auto[0]	auto[0]	7306	1			T44	11		T13	401		T45	5
fifo_depth[12]	auto[1]	auto[0]	auto[1]	7408	1			T13	298		T45	7		T18	101
fifo_depth[12]	auto[1]	auto[1]	auto[0]	7836	1			T44	4		T13	395		T45	23
fifo_depth[12]	auto[1]	auto[1]	auto[1]	7526	1			T44	24		T13	56		T18	6
fifo_depth[13]	auto[0]	auto[0]	auto[0]	2512	1			T13	35		T18	4		T25	2
fifo_depth[13]	auto[0]	auto[0]	auto[1]	2670	1			T13	8		T18	21		T25	7
fifo_depth[13]	auto[0]	auto[1]	auto[0]	4777	1			T3	44		T13	203		T46	34
fifo_depth[13]	auto[0]	auto[1]	auto[1]	1724	1			T13	60		T18	3		T14	1
fifo_depth[13]	auto[1]	auto[0]	auto[0]	3912	1			T44	9		T13	398		T18	13
fifo_depth[13]	auto[1]	auto[0]	auto[1]	4221	1			T28	2		T13	68		T45	3
fifo_depth[13]	auto[1]	auto[1]	auto[0]	4650	1			T44	1		T13	128		T45	7
fifo_depth[13]	auto[1]	auto[1]	auto[1]	3836	1			T44	8		T13	42		T18	6
fifo_depth[14]	auto[0]	auto[0]	auto[0]	3673	1			T13	95		T15	7		T96	3
fifo_depth[14]	auto[0]	auto[0]	auto[1]	4362	1			T13	11		T18	1		T25	6
fifo_depth[14]	auto[0]	auto[1]	auto[0]	4714	1			T3	19		T13	112		T46	8
fifo_depth[14]	auto[0]	auto[1]	auto[1]	2422	1			T13	81		T18	2		T25	1
fifo_depth[14]	auto[1]	auto[0]	auto[0]	4520	1			T44	5		T13	552		T45	1
fifo_depth[14]	auto[1]	auto[0]	auto[1]	4504	1			T13	236		T45	2		T18	3
fifo_depth[14]	auto[1]	auto[1]	auto[0]	5190	1			T44	2		T13	122		T45	6
fifo_depth[14]	auto[1]	auto[1]	auto[1]	4156	1			T44	2		T13	42		T18	6
fifo_depth[15]	auto[0]	auto[0]	auto[0]	2597	1			T13	13		T18	4		T96	1
fifo_depth[15]	auto[0]	auto[0]	auto[1]	2767	1			T13	6		T18	21		T25	3
fifo_depth[15]	auto[0]	auto[1]	auto[0]	3009	1			T3	7		T13	64		T46	4
fifo_depth[15]	auto[0]	auto[1]	auto[1]	1561	1			T13	61		T14	1		T19	2
fifo_depth[15]	auto[1]	auto[0]	auto[0]	3162	1			T44	2		T13	502		T18	77
fifo_depth[15]	auto[1]	auto[0]	auto[1]	3181	1			T13	28		T45	1		T18	9
fifo_depth[15]	auto[1]	auto[1]	auto[0]	3600	1			T13	149		T45	1		T18	139
fifo_depth[15]	auto[1]	auto[1]	auto[1]	2793	1			T13	37		T18	6		T59	2
fifo_depth[16]	auto[0]	auto[0]	auto[0]	8827	1			T13	77		T18	114		T15	131
fifo_depth[16]	auto[0]	auto[0]	auto[1]	11212	1			T13	106		T18	676		T25	1
fifo_depth[16]	auto[0]	auto[1]	auto[0]	8242	1			T3	3		T13	186		T18	43
fifo_depth[16]	auto[0]	auto[1]	auto[1]	9123	1			T13	1133		T18	12		T19	48
fifo_depth[16]	auto[1]	auto[0]	auto[0]	11684	1			T44	2		T13	454		T18	43
fifo_depth[16]	auto[1]	auto[0]	auto[1]	14051	1			T13	222		T18	104		T59	2
fifo_depth[16]	auto[1]	auto[1]	auto[0]	13548	1			T13	742		T18	550		T59	1
fifo_depth[16]	auto[1]	auto[1]	auto[1]	6677	1			T13	9		T18	201		T59	1