Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	12896807	1			T2	70200		T3	69322		T4	34
all_pins[1]	12896807	1			T2	70200		T3	69322		T4	34
all_pins[2]	12896807	1			T2	70200		T3	69322		T4	34

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	36619214	1			T2	202076		T3	199739		T4	98
values[0x1]	2071207	1			T2	8524		T3	8227		T4	4
transitions[0x0=>0x1]	2071039	1			T2	8524		T3	8227		T4	4
transitions[0x1=>0x0]	2071063	1			T2	8524		T3	8227		T4	4

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	12852195	1			T2	70006		T3	69128		T4	30
all_pins[0]	values[0x1]	44612	1			T2	194		T3	194		T4	4
all_pins[0]	transitions[0x0=>0x1]	44537	1			T2	194		T3	194		T4	4
all_pins[0]	transitions[0x1=>0x0]	2026046	1			T2	8330		T3	8033		T13	47471
all_pins[1]	values[0x0]	12896309	1			T2	70200		T3	69322		T4	34
all_pins[1]	values[0x1]	498	1			T13	4		T18	1		T19	1
all_pins[1]	transitions[0x0=>0x1]	455	1			T13	4		T18	1		T19	1
all_pins[1]	transitions[0x1=>0x0]	44569	1			T2	194		T3	194		T4	4
all_pins[2]	values[0x0]	10870710	1			T2	61870		T3	61289		T4	34
all_pins[2]	values[0x1]	2026097	1			T2	8330		T3	8033		T13	47471
all_pins[2]	transitions[0x0=>0x1]	2026047	1			T2	8330		T3	8033		T13	47471
all_pins[2]	transitions[0x1=>0x0]	448	1			T13	4		T18	1		T19	1