Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 865 1 T13 18 T15 4 T24 7
all_values[1] 865 1 T13 18 T15 4 T24 7
all_values[2] 865 1 T13 18 T15 4 T24 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1300 1 T13 27 T15 10 T24 10
auto[1] 1295 1 T13 27 T15 2 T24 11


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 921 1 T13 22 T15 4 T24 6
auto[1] 1674 1 T13 32 T15 8 T24 15


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1483 1 T13 36 T15 8 T24 10
auto[1] 1112 1 T13 18 T15 4 T24 11


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 169 1 T13 1 T15 1 T24 2
all_values[0] auto[0] auto[0] auto[1] 91 1 T13 4 T15 2 T24 1
all_values[0] auto[0] auto[1] auto[0] 138 1 T13 1 T24 2 T17 5
all_values[0] auto[0] auto[1] auto[1] 88 1 T13 5 T58 1 T9 1
all_values[0] auto[1] auto[0] auto[1] 189 1 T13 4 T15 1 T24 1
all_values[0] auto[1] auto[1] auto[1] 190 1 T13 3 T24 1 T17 5
all_values[1] auto[0] auto[0] auto[0] 141 1 T13 4 T17 3 T58 1
all_values[1] auto[0] auto[0] auto[1] 94 1 T13 2 T15 1 T17 1
all_values[1] auto[0] auto[1] auto[0] 139 1 T13 7 T15 2 T24 2
all_values[1] auto[0] auto[1] auto[1] 114 1 T13 1 T24 2 T17 6
all_values[1] auto[1] auto[0] auto[1] 201 1 T13 3 T15 1 T24 1
all_values[1] auto[1] auto[1] auto[1] 176 1 T13 1 T24 2 T17 5
all_values[2] auto[0] auto[0] auto[0] 167 1 T13 4 T15 1 T58 6
all_values[2] auto[0] auto[0] auto[1] 77 1 T15 1 T24 1 T17 2
all_values[2] auto[0] auto[1] auto[0] 167 1 T13 5 T17 7 T58 1
all_values[2] auto[0] auto[1] auto[1] 98 1 T13 2 T17 5 T58 1
all_values[2] auto[1] auto[0] auto[1] 171 1 T13 5 T15 2 T24 4
all_values[2] auto[1] auto[1] auto[1] 185 1 T13 2 T24 2 T17 8


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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