Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.92 92.34 85.07 100.00 76.32 86.11 99.49 69.08


Total test records in report: 738
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T537 /workspace/coverage/default/32.hmac_burst_wr.2272412558 Mar 28 01:18:40 PM PDT 24 Mar 28 01:19:31 PM PDT 24 7099426025 ps
T538 /workspace/coverage/default/14.hmac_smoke.1780150868 Mar 28 01:17:00 PM PDT 24 Mar 28 01:17:02 PM PDT 24 54088228 ps
T539 /workspace/coverage/default/39.hmac_error.4283795083 Mar 28 01:19:24 PM PDT 24 Mar 28 01:22:55 PM PDT 24 3477519708 ps
T540 /workspace/coverage/default/31.hmac_burst_wr.644748952 Mar 28 01:18:41 PM PDT 24 Mar 28 01:19:23 PM PDT 24 7980185511 ps
T541 /workspace/coverage/default/15.hmac_test_sha_vectors.905574368 Mar 28 01:16:58 PM PDT 24 Mar 28 01:26:11 PM PDT 24 29637391011 ps
T542 /workspace/coverage/default/45.hmac_burst_wr.370353828 Mar 28 01:19:56 PM PDT 24 Mar 28 01:20:42 PM PDT 24 11643612225 ps
T543 /workspace/coverage/default/31.hmac_smoke.1083997810 Mar 28 01:18:39 PM PDT 24 Mar 28 01:18:40 PM PDT 24 26771494 ps
T544 /workspace/coverage/default/3.hmac_back_pressure.3538812215 Mar 28 01:15:34 PM PDT 24 Mar 28 01:15:48 PM PDT 24 1992621796 ps
T545 /workspace/coverage/default/13.hmac_test_hmac_vectors.2543299788 Mar 28 01:16:34 PM PDT 24 Mar 28 01:16:36 PM PDT 24 138078064 ps
T546 /workspace/coverage/default/34.hmac_wipe_secret.3101026940 Mar 28 01:18:42 PM PDT 24 Mar 28 01:19:29 PM PDT 24 4692947794 ps
T547 /workspace/coverage/default/48.hmac_back_pressure.1899629434 Mar 28 01:20:10 PM PDT 24 Mar 28 01:20:17 PM PDT 24 796073227 ps
T548 /workspace/coverage/default/11.hmac_burst_wr.1190847112 Mar 28 01:16:33 PM PDT 24 Mar 28 01:17:00 PM PDT 24 2043575646 ps
T549 /workspace/coverage/default/49.hmac_datapath_stress.1075508967 Mar 28 01:20:10 PM PDT 24 Mar 28 01:20:42 PM PDT 24 2023363555 ps
T550 /workspace/coverage/default/39.hmac_long_msg.347247979 Mar 28 01:19:22 PM PDT 24 Mar 28 01:21:23 PM PDT 24 23414501092 ps
T551 /workspace/coverage/default/41.hmac_datapath_stress.4093879243 Mar 28 01:19:39 PM PDT 24 Mar 28 01:19:57 PM PDT 24 1301099582 ps
T552 /workspace/coverage/default/44.hmac_test_hmac_vectors.3054115330 Mar 28 01:19:41 PM PDT 24 Mar 28 01:19:43 PM PDT 24 255052144 ps
T553 /workspace/coverage/default/34.hmac_error.516230642 Mar 28 01:18:43 PM PDT 24 Mar 28 01:19:24 PM PDT 24 3006545789 ps
T554 /workspace/coverage/default/46.hmac_alert_test.997060286 Mar 28 01:19:58 PM PDT 24 Mar 28 01:19:59 PM PDT 24 12692326 ps
T555 /workspace/coverage/default/48.hmac_test_sha_vectors.96351153 Mar 28 01:20:09 PM PDT 24 Mar 28 01:26:57 PM PDT 24 12526520296 ps
T556 /workspace/coverage/default/16.hmac_wipe_secret.1852916127 Mar 28 01:17:20 PM PDT 24 Mar 28 01:17:24 PM PDT 24 290788964 ps
T53 /workspace/coverage/default/63.hmac_stress_all_with_rand_reset.2433990287 Mar 28 01:20:24 PM PDT 24 Mar 28 01:25:30 PM PDT 24 5423733089 ps
T557 /workspace/coverage/default/6.hmac_alert_test.305963927 Mar 28 01:16:03 PM PDT 24 Mar 28 01:16:05 PM PDT 24 45071881 ps
T558 /workspace/coverage/default/10.hmac_test_hmac_vectors.1510834994 Mar 28 01:16:18 PM PDT 24 Mar 28 01:16:19 PM PDT 24 211390511 ps
T559 /workspace/coverage/default/32.hmac_test_hmac_vectors.2011353725 Mar 28 01:18:44 PM PDT 24 Mar 28 01:18:46 PM PDT 24 542695526 ps
T560 /workspace/coverage/default/30.hmac_back_pressure.2059506861 Mar 28 01:18:24 PM PDT 24 Mar 28 01:19:30 PM PDT 24 1727668115 ps
T561 /workspace/coverage/default/43.hmac_alert_test.249741404 Mar 28 01:19:41 PM PDT 24 Mar 28 01:19:42 PM PDT 24 15033558 ps
T562 /workspace/coverage/default/11.hmac_alert_test.3841507605 Mar 28 01:16:32 PM PDT 24 Mar 28 01:16:33 PM PDT 24 41939371 ps
T563 /workspace/coverage/default/40.hmac_alert_test.205074309 Mar 28 01:19:24 PM PDT 24 Mar 28 01:19:25 PM PDT 24 22310061 ps
T564 /workspace/coverage/default/6.hmac_test_hmac_vectors.4203969449 Mar 28 01:16:02 PM PDT 24 Mar 28 01:16:04 PM PDT 24 43975447 ps
T565 /workspace/coverage/default/3.hmac_long_msg.2300939631 Mar 28 01:15:34 PM PDT 24 Mar 28 01:16:58 PM PDT 24 22140304132 ps
T566 /workspace/coverage/default/18.hmac_wipe_secret.3382334127 Mar 28 01:17:22 PM PDT 24 Mar 28 01:18:29 PM PDT 24 6943125123 ps
T567 /workspace/coverage/default/19.hmac_wipe_secret.1795454621 Mar 28 01:17:22 PM PDT 24 Mar 28 01:17:59 PM PDT 24 30346700630 ps
T568 /workspace/coverage/default/8.hmac_back_pressure.2595260164 Mar 28 01:16:05 PM PDT 24 Mar 28 01:17:03 PM PDT 24 7516248454 ps
T569 /workspace/coverage/default/6.hmac_stress_all.1406768901 Mar 28 01:16:00 PM PDT 24 Mar 28 01:16:25 PM PDT 24 1144006710 ps
T86 /workspace/coverage/default/43.hmac_stress_all.2829328574 Mar 28 01:19:40 PM PDT 24 Mar 28 01:52:00 PM PDT 24 138404914424 ps
T570 /workspace/coverage/default/33.hmac_back_pressure.2386201403 Mar 28 01:18:43 PM PDT 24 Mar 28 01:18:47 PM PDT 24 283972446 ps
T571 /workspace/coverage/default/18.hmac_smoke.894656518 Mar 28 01:17:21 PM PDT 24 Mar 28 01:17:24 PM PDT 24 256330125 ps
T34 /workspace/coverage/default/2.hmac_sec_cm.2939739707 Mar 28 01:15:31 PM PDT 24 Mar 28 01:15:32 PM PDT 24 79398442 ps
T572 /workspace/coverage/default/28.hmac_datapath_stress.1379556292 Mar 28 01:18:22 PM PDT 24 Mar 28 01:18:55 PM PDT 24 514252733 ps
T573 /workspace/coverage/default/25.hmac_back_pressure.2363303324 Mar 28 01:17:52 PM PDT 24 Mar 28 01:17:56 PM PDT 24 446806123 ps
T574 /workspace/coverage/default/39.hmac_test_sha_vectors.1946604382 Mar 28 01:19:24 PM PDT 24 Mar 28 01:27:49 PM PDT 24 32542030881 ps
T575 /workspace/coverage/default/5.hmac_wipe_secret.1280115848 Mar 28 01:15:48 PM PDT 24 Mar 28 01:16:56 PM PDT 24 17582359958 ps
T576 /workspace/coverage/default/24.hmac_error.805597544 Mar 28 01:17:46 PM PDT 24 Mar 28 01:19:06 PM PDT 24 20871929644 ps
T577 /workspace/coverage/default/35.hmac_stress_all.3098011520 Mar 28 01:18:57 PM PDT 24 Mar 28 01:25:05 PM PDT 24 80917599392 ps
T578 /workspace/coverage/default/27.hmac_stress_all.563967821 Mar 28 01:18:23 PM PDT 24 Mar 28 02:02:17 PM PDT 24 808768125902 ps
T579 /workspace/coverage/default/32.hmac_smoke.720987534 Mar 28 01:18:39 PM PDT 24 Mar 28 01:18:45 PM PDT 24 797571463 ps
T580 /workspace/coverage/default/32.hmac_test_sha_vectors.3546872270 Mar 28 01:18:41 PM PDT 24 Mar 28 01:27:36 PM PDT 24 65530767988 ps
T581 /workspace/coverage/default/39.hmac_back_pressure.82604839 Mar 28 01:19:23 PM PDT 24 Mar 28 01:19:36 PM PDT 24 250910706 ps
T582 /workspace/coverage/default/47.hmac_datapath_stress.416849863 Mar 28 01:19:57 PM PDT 24 Mar 28 01:21:28 PM PDT 24 1474115287 ps
T583 /workspace/coverage/default/49.hmac_burst_wr.3420357475 Mar 28 01:20:09 PM PDT 24 Mar 28 01:20:52 PM PDT 24 3312325496 ps
T584 /workspace/coverage/default/20.hmac_back_pressure.1667712143 Mar 28 01:17:33 PM PDT 24 Mar 28 01:17:37 PM PDT 24 356143220 ps
T585 /workspace/coverage/default/41.hmac_stress_all.1180424565 Mar 28 01:19:40 PM PDT 24 Mar 28 01:22:35 PM PDT 24 3447697828 ps
T586 /workspace/coverage/default/10.hmac_burst_wr.1881633413 Mar 28 01:16:17 PM PDT 24 Mar 28 01:16:37 PM PDT 24 1120652936 ps
T587 /workspace/coverage/default/21.hmac_long_msg.1484986558 Mar 28 01:17:39 PM PDT 24 Mar 28 01:17:51 PM PDT 24 1088277365 ps
T588 /workspace/coverage/default/17.hmac_long_msg.1299686121 Mar 28 01:17:20 PM PDT 24 Mar 28 01:18:01 PM PDT 24 5326419972 ps
T589 /workspace/coverage/default/39.hmac_datapath_stress.3203238457 Mar 28 01:19:21 PM PDT 24 Mar 28 01:19:22 PM PDT 24 30084132 ps
T590 /workspace/coverage/default/22.hmac_stress_all.1137898887 Mar 28 01:17:34 PM PDT 24 Mar 28 01:20:06 PM PDT 24 12011558714 ps
T591 /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.1878792592 Mar 28 01:16:22 PM PDT 24 Mar 28 01:32:36 PM PDT 24 193602567124 ps
T592 /workspace/coverage/default/21.hmac_burst_wr.3687458443 Mar 28 01:17:35 PM PDT 24 Mar 28 01:17:37 PM PDT 24 139521672 ps
T593 /workspace/coverage/default/23.hmac_test_sha_vectors.3550532739 Mar 28 01:17:47 PM PDT 24 Mar 28 01:27:22 PM PDT 24 84835302098 ps
T594 /workspace/coverage/default/6.hmac_burst_wr.695235525 Mar 28 01:15:46 PM PDT 24 Mar 28 01:16:27 PM PDT 24 788764137 ps
T595 /workspace/coverage/default/44.hmac_long_msg.1918609354 Mar 28 01:19:43 PM PDT 24 Mar 28 01:20:04 PM PDT 24 1502371207 ps
T596 /workspace/coverage/default/42.hmac_alert_test.582164159 Mar 28 01:19:42 PM PDT 24 Mar 28 01:19:44 PM PDT 24 44502364 ps
T597 /workspace/coverage/default/13.hmac_smoke.1645828262 Mar 28 01:16:34 PM PDT 24 Mar 28 01:16:42 PM PDT 24 1902519584 ps
T10 /workspace/coverage/default/100.hmac_stress_all_with_rand_reset.1696124885 Mar 28 01:20:45 PM PDT 24 Mar 28 01:32:01 PM PDT 24 105053291827 ps
T598 /workspace/coverage/default/13.hmac_alert_test.3533019426 Mar 28 01:16:59 PM PDT 24 Mar 28 01:17:00 PM PDT 24 13844505 ps
T599 /workspace/coverage/default/8.hmac_stress_all.2367138332 Mar 28 01:16:04 PM PDT 24 Mar 28 01:16:41 PM PDT 24 11793821283 ps
T600 /workspace/coverage/default/34.hmac_long_msg.983774341 Mar 28 01:18:42 PM PDT 24 Mar 28 01:18:58 PM PDT 24 1151671351 ps
T601 /workspace/coverage/default/42.hmac_wipe_secret.2831167028 Mar 28 01:19:42 PM PDT 24 Mar 28 01:20:16 PM PDT 24 2250766820 ps
T602 /workspace/coverage/default/17.hmac_stress_all.2341903713 Mar 28 01:17:20 PM PDT 24 Mar 28 01:22:28 PM PDT 24 57609017460 ps
T603 /workspace/coverage/default/18.hmac_error.1543385907 Mar 28 01:17:22 PM PDT 24 Mar 28 01:18:20 PM PDT 24 18246140783 ps
T604 /workspace/coverage/default/14.hmac_stress_all.1990271896 Mar 28 01:16:59 PM PDT 24 Mar 28 01:17:58 PM PDT 24 12023698059 ps
T11 /workspace/coverage/default/170.hmac_stress_all_with_rand_reset.1844081858 Mar 28 01:21:14 PM PDT 24 Mar 28 01:52:14 PM PDT 24 37579719688 ps
T605 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1725128548 Mar 28 12:44:51 PM PDT 24 Mar 28 12:44:53 PM PDT 24 221750361 ps
T65 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1946661865 Mar 28 12:44:51 PM PDT 24 Mar 28 12:44:53 PM PDT 24 652492286 ps
T606 /workspace/coverage/cover_reg_top/28.hmac_intr_test.251393721 Mar 28 12:45:09 PM PDT 24 Mar 28 12:45:09 PM PDT 24 13621899 ps
T66 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.584978029 Mar 28 12:45:09 PM PDT 24 Mar 28 12:45:11 PM PDT 24 233552975 ps
T62 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2074225421 Mar 28 12:44:53 PM PDT 24 Mar 28 12:44:55 PM PDT 24 173395389 ps
T607 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.719379374 Mar 28 12:44:49 PM PDT 24 Mar 28 12:44:50 PM PDT 24 271859512 ps
T608 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3633269681 Mar 28 12:45:02 PM PDT 24 Mar 28 12:45:02 PM PDT 24 23761617 ps
T609 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3863545845 Mar 28 12:45:10 PM PDT 24 Mar 28 12:45:12 PM PDT 24 51092322 ps
T63 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2837018842 Mar 28 12:44:44 PM PDT 24 Mar 28 12:44:48 PM PDT 24 129739754 ps
T610 /workspace/coverage/cover_reg_top/29.hmac_intr_test.3965876721 Mar 28 12:45:10 PM PDT 24 Mar 28 12:45:11 PM PDT 24 30397718 ps
T611 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2727476368 Mar 28 12:44:48 PM PDT 24 Mar 28 12:44:51 PM PDT 24 429010377 ps
T612 /workspace/coverage/cover_reg_top/36.hmac_intr_test.398201032 Mar 28 12:45:09 PM PDT 24 Mar 28 12:45:10 PM PDT 24 14305201 ps
T64 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3600829433 Mar 28 12:44:49 PM PDT 24 Mar 28 12:44:50 PM PDT 24 523210833 ps
T613 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2762065509 Mar 28 12:45:10 PM PDT 24 Mar 28 12:45:10 PM PDT 24 57122706 ps
T614 /workspace/coverage/cover_reg_top/30.hmac_intr_test.3709518408 Mar 28 12:45:11 PM PDT 24 Mar 28 12:45:11 PM PDT 24 50106471 ps
T615 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2175146550 Mar 28 12:45:36 PM PDT 24 Mar 28 12:48:55 PM PDT 24 81243132311 ps
T106 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.242021596 Mar 28 12:44:44 PM PDT 24 Mar 28 12:44:45 PM PDT 24 61596682 ps
T616 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1428942091 Mar 28 12:45:09 PM PDT 24 Mar 28 12:45:10 PM PDT 24 24805903 ps
T617 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1213731666 Mar 28 12:44:32 PM PDT 24 Mar 28 12:44:34 PM PDT 24 23012955 ps
T618 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1166031524 Mar 28 12:44:50 PM PDT 24 Mar 28 12:44:51 PM PDT 24 13595645 ps
T619 /workspace/coverage/cover_reg_top/27.hmac_intr_test.3574352175 Mar 28 12:45:09 PM PDT 24 Mar 28 12:45:10 PM PDT 24 29953888 ps
T620 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.4167889888 Mar 28 12:44:47 PM PDT 24 Mar 28 12:44:49 PM PDT 24 154543902 ps
T621 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3626009334 Mar 28 12:44:32 PM PDT 24 Mar 28 12:44:33 PM PDT 24 16052244 ps
T622 /workspace/coverage/cover_reg_top/24.hmac_intr_test.804336403 Mar 28 12:45:10 PM PDT 24 Mar 28 12:45:10 PM PDT 24 17364777 ps
T122 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2816451576 Mar 28 12:44:45 PM PDT 24 Mar 28 12:44:49 PM PDT 24 1043095619 ps
T623 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3508354989 Mar 28 12:44:53 PM PDT 24 Mar 28 12:44:54 PM PDT 24 43067651 ps
T624 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2871358951 Mar 28 12:44:48 PM PDT 24 Mar 28 12:44:51 PM PDT 24 53438223 ps
T625 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.978169279 Mar 28 12:44:44 PM PDT 24 Mar 28 12:44:54 PM PDT 24 211633424 ps
T126 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3151383508 Mar 28 12:44:33 PM PDT 24 Mar 28 12:44:37 PM PDT 24 249187702 ps
T626 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2018177314 Mar 28 12:44:49 PM PDT 24 Mar 28 12:44:50 PM PDT 24 82886381 ps
T627 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.227994387 Mar 28 12:44:48 PM PDT 24 Mar 28 12:44:49 PM PDT 24 234762262 ps
T124 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3674604348 Mar 28 12:44:52 PM PDT 24 Mar 28 12:44:55 PM PDT 24 85671086 ps
T628 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3027602834 Mar 28 12:45:07 PM PDT 24 Mar 28 12:45:08 PM PDT 24 187609287 ps
T629 /workspace/coverage/cover_reg_top/33.hmac_intr_test.877589152 Mar 28 12:45:13 PM PDT 24 Mar 28 12:45:14 PM PDT 24 30407637 ps
T630 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3563188443 Mar 28 12:45:01 PM PDT 24 Mar 28 12:45:05 PM PDT 24 151919071 ps
T128 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2951897944 Mar 28 12:44:44 PM PDT 24 Mar 28 12:44:46 PM PDT 24 157022332 ps
T631 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.538489269 Mar 28 12:45:08 PM PDT 24 Mar 28 12:45:09 PM PDT 24 16727266 ps
T632 /workspace/coverage/cover_reg_top/0.hmac_intr_test.921136655 Mar 28 12:44:31 PM PDT 24 Mar 28 12:44:32 PM PDT 24 29597038 ps
T633 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3473421292 Mar 28 12:44:46 PM PDT 24 Mar 28 12:44:49 PM PDT 24 220015621 ps
T634 /workspace/coverage/cover_reg_top/8.hmac_intr_test.1153477392 Mar 28 12:44:44 PM PDT 24 Mar 28 12:44:45 PM PDT 24 14426887 ps
T107 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2744667066 Mar 28 12:44:44 PM PDT 24 Mar 28 12:44:56 PM PDT 24 8134583172 ps
T635 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3396862543 Mar 28 12:45:13 PM PDT 24 Mar 28 12:45:15 PM PDT 24 372950590 ps
T636 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1294571983 Mar 28 12:44:44 PM PDT 24 Mar 28 12:44:47 PM PDT 24 44677656 ps
T637 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1406729126 Mar 28 12:45:07 PM PDT 24 Mar 28 12:45:07 PM PDT 24 12072878 ps
T638 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.743277738 Mar 28 12:44:28 PM PDT 24 Mar 28 12:44:30 PM PDT 24 90116596 ps
T639 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.4128583906 Mar 28 12:45:09 PM PDT 24 Mar 28 12:45:11 PM PDT 24 237550780 ps
T640 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1125627507 Mar 28 12:44:45 PM PDT 24 Mar 28 12:44:46 PM PDT 24 32009685 ps
T641 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1968941884 Mar 28 12:44:45 PM PDT 24 Mar 28 12:44:47 PM PDT 24 391530315 ps
T642 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1765448524 Mar 28 12:44:45 PM PDT 24 Mar 28 12:44:46 PM PDT 24 408426349 ps
T643 /workspace/coverage/cover_reg_top/42.hmac_intr_test.806443335 Mar 28 12:45:09 PM PDT 24 Mar 28 12:45:10 PM PDT 24 28117242 ps
T108 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.225601879 Mar 28 12:44:56 PM PDT 24 Mar 28 12:44:57 PM PDT 24 46417928 ps
T644 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1839210081 Mar 28 12:45:07 PM PDT 24 Mar 28 12:45:10 PM PDT 24 67521940 ps
T129 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.268205522 Mar 28 12:44:47 PM PDT 24 Mar 28 12:44:50 PM PDT 24 165842020 ps
T645 /workspace/coverage/cover_reg_top/34.hmac_intr_test.2316099998 Mar 28 12:45:10 PM PDT 24 Mar 28 12:45:11 PM PDT 24 10939123 ps
T646 /workspace/coverage/cover_reg_top/7.hmac_intr_test.4041626249 Mar 28 12:44:43 PM PDT 24 Mar 28 12:44:44 PM PDT 24 16066172 ps
T647 /workspace/coverage/cover_reg_top/1.hmac_intr_test.2515259234 Mar 28 12:44:45 PM PDT 24 Mar 28 12:44:46 PM PDT 24 38232764 ps
T648 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3155715150 Mar 28 12:45:10 PM PDT 24 Mar 28 12:45:11 PM PDT 24 102328851 ps
T649 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.742509303 Mar 28 12:44:44 PM PDT 24 Mar 28 12:44:45 PM PDT 24 35783287 ps
T109 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3888589567 Mar 28 12:44:31 PM PDT 24 Mar 28 12:44:32 PM PDT 24 28616911 ps
T650 /workspace/coverage/cover_reg_top/6.hmac_intr_test.2581388850 Mar 28 12:44:44 PM PDT 24 Mar 28 12:44:45 PM PDT 24 51151593 ps
T130 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1122462211 Mar 28 12:44:49 PM PDT 24 Mar 28 12:44:51 PM PDT 24 97428668 ps
T651 /workspace/coverage/cover_reg_top/10.hmac_intr_test.428391731 Mar 28 12:44:44 PM PDT 24 Mar 28 12:44:45 PM PDT 24 11726257 ps
T652 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2640514838 Mar 28 12:44:44 PM PDT 24 Mar 28 12:44:46 PM PDT 24 33315504 ps
T110 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2578639344 Mar 28 12:44:52 PM PDT 24 Mar 28 12:44:52 PM PDT 24 92136318 ps
T653 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3857165164 Mar 28 12:45:07 PM PDT 24 Mar 28 12:45:07 PM PDT 24 166341510 ps
T654 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1934028212 Mar 28 12:44:44 PM PDT 24 Mar 28 12:44:50 PM PDT 24 5137254592 ps
T655 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.4102023635 Mar 28 12:44:44 PM PDT 24 Mar 28 12:44:46 PM PDT 24 69119663 ps
T111 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3611963794 Mar 28 12:44:37 PM PDT 24 Mar 28 12:44:38 PM PDT 24 96333794 ps
T656 /workspace/coverage/cover_reg_top/23.hmac_intr_test.1798233043 Mar 28 12:45:07 PM PDT 24 Mar 28 12:45:08 PM PDT 24 13321597 ps
T112 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3780517234 Mar 28 12:44:48 PM PDT 24 Mar 28 12:44:49 PM PDT 24 97185426 ps
T113 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1737979938 Mar 28 12:44:31 PM PDT 24 Mar 28 12:44:32 PM PDT 24 22309494 ps
T657 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.4102617551 Mar 28 12:45:09 PM PDT 24 Mar 28 12:45:12 PM PDT 24 103470823 ps
T658 /workspace/coverage/cover_reg_top/46.hmac_intr_test.1593143044 Mar 28 12:45:09 PM PDT 24 Mar 28 12:45:10 PM PDT 24 12159736 ps
T659 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3719826207 Mar 28 12:45:12 PM PDT 24 Mar 28 12:45:12 PM PDT 24 13990816 ps
T660 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2118665224 Mar 28 12:44:49 PM PDT 24 Mar 28 12:44:49 PM PDT 24 42155521 ps
T661 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1897833596 Mar 28 12:44:52 PM PDT 24 Mar 28 12:44:55 PM PDT 24 115303058 ps
T114 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.125075444 Mar 28 12:44:52 PM PDT 24 Mar 28 12:45:00 PM PDT 24 417492470 ps
T662 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3978688394 Mar 28 12:44:45 PM PDT 24 Mar 28 12:44:47 PM PDT 24 127521413 ps
T118 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3489844977 Mar 28 12:44:52 PM PDT 24 Mar 28 12:44:53 PM PDT 24 182288910 ps
T663 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.672339260 Mar 28 12:44:31 PM PDT 24 Mar 28 12:44:33 PM PDT 24 166869308 ps
T664 /workspace/coverage/cover_reg_top/2.hmac_intr_test.917367244 Mar 28 12:44:30 PM PDT 24 Mar 28 12:44:31 PM PDT 24 55076373 ps
T665 /workspace/coverage/cover_reg_top/44.hmac_intr_test.436346766 Mar 28 12:45:10 PM PDT 24 Mar 28 12:45:11 PM PDT 24 71464502 ps
T666 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3751256485 Mar 28 12:45:10 PM PDT 24 Mar 28 12:45:10 PM PDT 24 38471107 ps
T667 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1102057539 Mar 28 12:44:49 PM PDT 24 Mar 28 12:44:52 PM PDT 24 1017916361 ps
T668 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2071889670 Mar 28 12:45:09 PM PDT 24 Mar 28 12:45:10 PM PDT 24 13517728 ps
T115 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3420315116 Mar 28 12:45:09 PM PDT 24 Mar 28 12:45:11 PM PDT 24 127867968 ps
T669 /workspace/coverage/cover_reg_top/5.hmac_intr_test.344847039 Mar 28 12:44:49 PM PDT 24 Mar 28 12:44:49 PM PDT 24 39822956 ps
T670 /workspace/coverage/cover_reg_top/38.hmac_intr_test.3560652633 Mar 28 12:45:10 PM PDT 24 Mar 28 12:45:11 PM PDT 24 60247331 ps
T671 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2454284183 Mar 28 12:44:58 PM PDT 24 Mar 28 12:45:00 PM PDT 24 264363785 ps
T116 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.4144851342 Mar 28 12:44:44 PM PDT 24 Mar 28 12:44:50 PM PDT 24 611332609 ps
T672 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2994192385 Mar 28 12:44:44 PM PDT 24 Mar 28 12:44:47 PM PDT 24 103683600 ps
T673 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1250175058 Mar 28 12:44:48 PM PDT 24 Mar 28 12:44:51 PM PDT 24 47493904 ps
T674 /workspace/coverage/cover_reg_top/48.hmac_intr_test.3738877717 Mar 28 12:45:09 PM PDT 24 Mar 28 12:45:09 PM PDT 24 44079222 ps
T675 /workspace/coverage/cover_reg_top/4.hmac_intr_test.3553771123 Mar 28 12:44:53 PM PDT 24 Mar 28 12:44:53 PM PDT 24 29192555 ps
T676 /workspace/coverage/cover_reg_top/47.hmac_intr_test.3954300692 Mar 28 12:45:12 PM PDT 24 Mar 28 12:45:14 PM PDT 24 19649692 ps
T125 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2050266435 Mar 28 12:44:39 PM PDT 24 Mar 28 12:44:41 PM PDT 24 163556555 ps
T677 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.377785388 Mar 28 12:45:06 PM PDT 24 Mar 28 12:45:07 PM PDT 24 85633161 ps
T117 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.952657224 Mar 28 12:45:36 PM PDT 24 Mar 28 12:45:38 PM PDT 24 34707242 ps
T678 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1487533962 Mar 28 12:44:44 PM PDT 24 Mar 28 12:44:46 PM PDT 24 172072826 ps
T679 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1507886448 Mar 28 12:44:45 PM PDT 24 Mar 28 12:44:55 PM PDT 24 1091341691 ps
T131 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2663551340 Mar 28 12:44:54 PM PDT 24 Mar 28 12:44:58 PM PDT 24 349634462 ps
T680 /workspace/coverage/cover_reg_top/18.hmac_intr_test.172880270 Mar 28 12:45:10 PM PDT 24 Mar 28 12:45:11 PM PDT 24 17396279 ps
T681 /workspace/coverage/cover_reg_top/17.hmac_intr_test.3537327741 Mar 28 12:45:08 PM PDT 24 Mar 28 12:45:09 PM PDT 24 22751956 ps
T682 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3001156942 Mar 28 12:45:12 PM PDT 24 Mar 28 12:45:13 PM PDT 24 21773397 ps
T683 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2788907855 Mar 28 12:44:52 PM PDT 24 Mar 28 12:44:52 PM PDT 24 35976185 ps
T684 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3812193555 Mar 28 12:44:43 PM PDT 24 Mar 28 12:44:44 PM PDT 24 257859957 ps
T685 /workspace/coverage/cover_reg_top/19.hmac_intr_test.3759718670 Mar 28 12:45:09 PM PDT 24 Mar 28 12:45:10 PM PDT 24 16185353 ps
T686 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2166453614 Mar 28 12:44:37 PM PDT 24 Mar 28 12:44:40 PM PDT 24 160397488 ps
T687 /workspace/coverage/cover_reg_top/16.hmac_intr_test.2446284083 Mar 28 12:44:50 PM PDT 24 Mar 28 12:44:51 PM PDT 24 49358608 ps
T688 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3695550484 Mar 28 12:44:44 PM PDT 24 Mar 28 12:44:46 PM PDT 24 47212257 ps
T689 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2082395990 Mar 28 12:44:46 PM PDT 24 Mar 28 12:44:48 PM PDT 24 123786420 ps
T690 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1530169532 Mar 28 12:44:46 PM PDT 24 Mar 28 12:44:47 PM PDT 24 477468271 ps
T691 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1752696757 Mar 28 12:44:49 PM PDT 24 Mar 28 12:44:51 PM PDT 24 91465115 ps
T692 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2895443107 Mar 28 12:45:09 PM PDT 24 Mar 28 12:45:10 PM PDT 24 21663136 ps
T693 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1622309822 Mar 28 12:44:46 PM PDT 24 Mar 28 12:44:48 PM PDT 24 184169493 ps
T694 /workspace/coverage/cover_reg_top/35.hmac_intr_test.3596843745 Mar 28 12:45:10 PM PDT 24 Mar 28 12:45:11 PM PDT 24 28531114 ps
T119 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2061836475 Mar 28 12:44:43 PM PDT 24 Mar 28 12:44:54 PM PDT 24 4381637150 ps
T695 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.847985103 Mar 28 12:45:11 PM PDT 24 Mar 28 12:45:12 PM PDT 24 36787294 ps
T127 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1706749246 Mar 28 12:44:29 PM PDT 24 Mar 28 12:44:33 PM PDT 24 138893924 ps
T696 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2631617209 Mar 28 12:44:48 PM PDT 24 Mar 28 12:44:50 PM PDT 24 50659583 ps
T697 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1080867724 Mar 28 12:44:48 PM PDT 24 Mar 28 12:44:48 PM PDT 24 54235071 ps
T698 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.226628599 Mar 28 12:44:45 PM PDT 24 Mar 28 12:44:46 PM PDT 24 59366685 ps
T699 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.237360392 Mar 28 12:44:49 PM PDT 24 Mar 28 12:44:51 PM PDT 24 265424485 ps
T700 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1423870638 Mar 28 12:44:48 PM PDT 24 Mar 28 12:44:50 PM PDT 24 29405915 ps
T701 /workspace/coverage/cover_reg_top/3.hmac_intr_test.3300647082 Mar 28 12:44:36 PM PDT 24 Mar 28 12:44:37 PM PDT 24 25371655 ps
T702 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3232310351 Mar 28 12:45:07 PM PDT 24 Mar 28 12:45:08 PM PDT 24 43408754 ps
T703 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.902882572 Mar 28 12:45:07 PM PDT 24 Mar 28 12:45:10 PM PDT 24 412827441 ps
T704 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1219038442 Mar 28 12:44:46 PM PDT 24 Mar 28 12:44:48 PM PDT 24 44946308 ps
T705 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3417657901 Mar 28 12:45:11 PM PDT 24 Mar 28 12:45:15 PM PDT 24 130804556 ps
T120 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3192033005 Mar 28 12:44:33 PM PDT 24 Mar 28 12:44:34 PM PDT 24 159116628 ps
T706 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.4035273458 Mar 28 12:44:46 PM PDT 24 Mar 28 12:44:48 PM PDT 24 98942694 ps
T707 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3362788632 Mar 28 12:44:44 PM PDT 24 Mar 28 12:44:46 PM PDT 24 66287962 ps
T708 /workspace/coverage/cover_reg_top/49.hmac_intr_test.4117313741 Mar 28 12:45:07 PM PDT 24 Mar 28 12:45:08 PM PDT 24 34765047 ps
T709 /workspace/coverage/cover_reg_top/9.hmac_intr_test.3138051839 Mar 28 12:44:45 PM PDT 24 Mar 28 12:44:46 PM PDT 24 22724062 ps
T121 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3526802530 Mar 28 12:45:17 PM PDT 24 Mar 28 12:45:18 PM PDT 24 49881178 ps
T710 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2378254433 Mar 28 12:44:56 PM PDT 24 Mar 28 12:45:01 PM PDT 24 290644162 ps
T711 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3464477484 Mar 28 12:44:47 PM PDT 24 Mar 28 12:44:49 PM PDT 24 1394981308 ps
T712 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1447961277 Mar 28 12:44:44 PM PDT 24 Mar 28 12:44:46 PM PDT 24 119188402 ps
T713 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1143494566 Mar 28 12:44:46 PM PDT 24 Mar 28 12:44:49 PM PDT 24 121379020 ps
T714 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.664872248 Mar 28 12:44:44 PM PDT 24 Mar 28 12:44:46 PM PDT 24 804533919 ps
T715 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2679147910 Mar 28 12:44:46 PM PDT 24 Mar 28 12:44:48 PM PDT 24 546765360 ps
T123 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.174841005 Mar 28 12:44:48 PM PDT 24 Mar 28 12:44:52 PM PDT 24 1653502099 ps
T716 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3523752518 Mar 28 12:44:48 PM PDT 24 Mar 28 12:44:50 PM PDT 24 285905055 ps
T717 /workspace/coverage/cover_reg_top/37.hmac_intr_test.37667269 Mar 28 12:45:13 PM PDT 24 Mar 28 12:45:13 PM PDT 24 27486732 ps
T718 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.4030213373 Mar 28 12:44:48 PM PDT 24 Mar 28 12:44:49 PM PDT 24 47606254 ps
T719 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1150347406 Mar 28 12:44:48 PM PDT 24 Mar 28 12:44:49 PM PDT 24 39193679 ps
T720 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3446376701 Mar 28 12:44:30 PM PDT 24 Mar 28 12:44:45 PM PDT 24 4387113865 ps
T721 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.4087156234 Mar 28 12:44:47 PM PDT 24 Mar 28 12:44:49 PM PDT 24 208251401 ps
T722 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.41969026 Mar 28 12:44:45 PM PDT 24 Mar 28 12:44:48 PM PDT 24 172286818 ps
T723 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.964727735 Mar 28 12:44:48 PM PDT 24 Mar 28 12:44:52 PM PDT 24 820157948 ps
T724 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2736943239 Mar 28 12:44:49 PM PDT 24 Mar 28 12:44:50 PM PDT 24 199609452 ps
T725 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1000249682 Mar 28 12:44:49 PM PDT 24 Mar 28 12:44:54 PM PDT 24 121320906 ps
T726 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1514950858 Mar 28 12:44:29 PM PDT 24 Mar 28 12:44:31 PM PDT 24 167735955 ps
T727 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.165484237 Mar 28 12:44:53 PM PDT 24 Mar 28 12:54:53 PM PDT 24 41301361119 ps
T728 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2769719286 Mar 28 12:45:36 PM PDT 24 Mar 28 12:45:37 PM PDT 24 10196885 ps
T729 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2785666140 Mar 28 12:44:47 PM PDT 24 Mar 28 12:44:48 PM PDT 24 41022772 ps
T730 /workspace/coverage/cover_reg_top/40.hmac_intr_test.4242138319 Mar 28 12:45:11 PM PDT 24 Mar 28 12:45:12 PM PDT 24 53937553 ps
T731 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3406693320 Mar 28 12:44:47 PM PDT 24 Mar 28 12:44:51 PM PDT 24 105044376 ps
T732 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1557320627 Mar 28 12:44:30 PM PDT 24 Mar 28 12:44:31 PM PDT 24 79015811 ps
T733 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3747068943 Mar 28 12:45:12 PM PDT 24 Mar 28 12:45:16 PM PDT 24 555219771 ps
T734 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3310684979 Mar 28 12:44:45 PM PDT 24 Mar 28 12:44:47 PM PDT 24 206145565 ps
T735 /workspace/coverage/cover_reg_top/43.hmac_intr_test.892571177 Mar 28 12:45:11 PM PDT 24 Mar 28 12:45:11 PM PDT 24 17514027 ps
T736 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.683749853 Mar 28 12:45:11 PM PDT 24 Mar 28 12:45:14 PM PDT 24 1948930459 ps
T737 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2190817839 Mar 28 12:44:45 PM PDT 24 Mar 28 12:44:46 PM PDT 24 16563874 ps
T738 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1887716921 Mar 28 12:44:48 PM PDT 24 Mar 28 12:44:52 PM PDT 24 194015694 ps

Test location /workspace/coverage/default/0.hmac_smoke.163415547
Short name T5
Test name
Test status
Simulation time 2349787235 ps
CPU time 5.1 seconds
Started Mar 28 01:15:14 PM PDT 24
Finished Mar 28 01:15:20 PM PDT 24
Peak memory 200212 kb
Host smart-86fd68ce-4be5-4ebc-8df2-848fab23ae20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163415547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.163415547
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2018942419
Short name T13
Test name
Test status
Simulation time 85120075157 ps
CPU time 2444.05 seconds
Started Mar 28 01:18:22 PM PDT 24
Finished Mar 28 01:59:06 PM PDT 24
Peak memory 229808 kb
Host smart-a9798f78-0a7f-4bfe-811c-c722e7e620f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018942419 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2018942419
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/82.hmac_stress_all_with_rand_reset.3362781925
Short name T12
Test name
Test status
Simulation time 75038415167 ps
CPU time 829.51 seconds
Started Mar 28 01:20:28 PM PDT 24
Finished Mar 28 01:34:18 PM PDT 24
Peak memory 249356 kb
Host smart-bc3ec31a-12ab-4a1e-bc55-f9de596137ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3362781925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.hmac_stress_all_with_rand_reset.3362781925
Directory /workspace/82.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2455287410
Short name T32
Test name
Test status
Simulation time 60361067 ps
CPU time 0.93 seconds
Started Mar 28 01:15:15 PM PDT 24
Finished Mar 28 01:15:16 PM PDT 24
Peak memory 218176 kb
Host smart-ae45e681-9c10-4aaf-8356-823c73137051
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455287410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2455287410
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2837018842
Short name T63
Test name
Test status
Simulation time 129739754 ps
CPU time 3.98 seconds
Started Mar 28 12:44:44 PM PDT 24
Finished Mar 28 12:44:48 PM PDT 24
Peak memory 199244 kb
Host smart-f681a666-f783-4de5-871c-c7ae34a605c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837018842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2837018842
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/12.hmac_stress_all.769112927
Short name T17
Test name
Test status
Simulation time 205713814840 ps
CPU time 741.32 seconds
Started Mar 28 01:16:32 PM PDT 24
Finished Mar 28 01:28:54 PM PDT 24
Peak memory 200172 kb
Host smart-511e7bbe-867a-452b-9bb5-dff71ac25b74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769112927 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.769112927
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/100.hmac_stress_all_with_rand_reset.1696124885
Short name T10
Test name
Test status
Simulation time 105053291827 ps
CPU time 676.2 seconds
Started Mar 28 01:20:45 PM PDT 24
Finished Mar 28 01:32:01 PM PDT 24
Peak memory 211100 kb
Host smart-33318c61-e676-4680-9a42-b55f605a512c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1696124885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.hmac_stress_all_with_rand_reset.1696124885
Directory /workspace/100.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_alert_test.806865179
Short name T92
Test name
Test status
Simulation time 14298173 ps
CPU time 0.58 seconds
Started Mar 28 01:15:32 PM PDT 24
Finished Mar 28 01:15:33 PM PDT 24
Peak memory 195632 kb
Host smart-80253b2c-2cf7-41dc-ab14-67d827848e77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806865179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.806865179
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/53.hmac_stress_all_with_rand_reset.1670293467
Short name T52
Test name
Test status
Simulation time 54086920920 ps
CPU time 1051.18 seconds
Started Mar 28 01:20:10 PM PDT 24
Finished Mar 28 01:37:42 PM PDT 24
Peak memory 232948 kb
Host smart-21889533-e3fb-46e7-83e3-73879022b205
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1670293467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.hmac_stress_all_with_rand_reset.1670293467
Directory /workspace/53.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.hmac_error.2720462002
Short name T48
Test name
Test status
Simulation time 20423389348 ps
CPU time 206.97 seconds
Started Mar 28 01:18:21 PM PDT 24
Finished Mar 28 01:21:48 PM PDT 24
Peak memory 200116 kb
Host smart-dae7a500-7304-4632-879b-47373ccfdd31
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720462002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.2720462002
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1571132344
Short name T94
Test name
Test status
Simulation time 2557264093 ps
CPU time 24.99 seconds
Started Mar 28 01:16:59 PM PDT 24
Finished Mar 28 01:17:24 PM PDT 24
Peak memory 200072 kb
Host smart-2fcfec7e-dea4-496e-8bdc-85cfd4c29e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571132344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1571132344
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1706749246
Short name T127
Test name
Test status
Simulation time 138893924 ps
CPU time 3.95 seconds
Started Mar 28 12:44:29 PM PDT 24
Finished Mar 28 12:44:33 PM PDT 24
Peak memory 199248 kb
Host smart-929f2c30-9132-43f3-afa1-e405c02ae9fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706749246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1706749246
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2744667066
Short name T107
Test name
Test status
Simulation time 8134583172 ps
CPU time 11.44 seconds
Started Mar 28 12:44:44 PM PDT 24
Finished Mar 28 12:44:56 PM PDT 24
Peak memory 198492 kb
Host smart-d62cafaf-ab78-4160-b0a0-dbcfeb815734
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744667066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2744667066
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2951897944
Short name T128
Test name
Test status
Simulation time 157022332 ps
CPU time 1.83 seconds
Started Mar 28 12:44:44 PM PDT 24
Finished Mar 28 12:44:46 PM PDT 24
Peak memory 199264 kb
Host smart-e2fa6bd7-9d70-4b44-934b-aa9c22ad939c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951897944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2951897944
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.4144851342
Short name T116
Test name
Test status
Simulation time 611332609 ps
CPU time 6.27 seconds
Started Mar 28 12:44:44 PM PDT 24
Finished Mar 28 12:44:50 PM PDT 24
Peak memory 198508 kb
Host smart-d6fff5ac-8b9d-4af6-92dc-a4a9ef2819b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144851342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.4144851342
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1737979938
Short name T113
Test name
Test status
Simulation time 22309494 ps
CPU time 0.74 seconds
Started Mar 28 12:44:31 PM PDT 24
Finished Mar 28 12:44:32 PM PDT 24
Peak memory 196628 kb
Host smart-e3028db5-4c24-423a-b920-e695257cbebf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737979938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1737979938
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2082395990
Short name T689
Test name
Test status
Simulation time 123786420 ps
CPU time 1.75 seconds
Started Mar 28 12:44:46 PM PDT 24
Finished Mar 28 12:44:48 PM PDT 24
Peak memory 199220 kb
Host smart-9b30f506-abc7-4741-af5d-c57dc466b12a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082395990 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2082395990
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3780517234
Short name T112
Test name
Test status
Simulation time 97185426 ps
CPU time 0.96 seconds
Started Mar 28 12:44:48 PM PDT 24
Finished Mar 28 12:44:49 PM PDT 24
Peak memory 198516 kb
Host smart-0709f8bf-5c52-4150-8e09-8f8b833f2adc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780517234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3780517234
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.921136655
Short name T632
Test name
Test status
Simulation time 29597038 ps
CPU time 0.6 seconds
Started Mar 28 12:44:31 PM PDT 24
Finished Mar 28 12:44:32 PM PDT 24
Peak memory 193856 kb
Host smart-5c5b7d13-40a2-4f0f-8256-17b7cd9f799f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921136655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.921136655
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1514950858
Short name T726
Test name
Test status
Simulation time 167735955 ps
CPU time 1.17 seconds
Started Mar 28 12:44:29 PM PDT 24
Finished Mar 28 12:44:31 PM PDT 24
Peak memory 199072 kb
Host smart-db468fc9-c1bf-4ddc-9746-bce47c5de469
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514950858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.1514950858
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.743277738
Short name T638
Test name
Test status
Simulation time 90116596 ps
CPU time 1.71 seconds
Started Mar 28 12:44:28 PM PDT 24
Finished Mar 28 12:44:30 PM PDT 24
Peak memory 199244 kb
Host smart-d72e44cf-62ee-43a2-a19f-52e3e3f3e840
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743277738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.743277738
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1934028212
Short name T654
Test name
Test status
Simulation time 5137254592 ps
CPU time 6.33 seconds
Started Mar 28 12:44:44 PM PDT 24
Finished Mar 28 12:44:50 PM PDT 24
Peak memory 198880 kb
Host smart-815966d7-9d42-4cfd-98e2-e0c893405b86
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934028212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1934028212
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3446376701
Short name T720
Test name
Test status
Simulation time 4387113865 ps
CPU time 14.49 seconds
Started Mar 28 12:44:30 PM PDT 24
Finished Mar 28 12:44:45 PM PDT 24
Peak memory 199364 kb
Host smart-5da56a8a-b316-4bfb-b8f0-cfcdfadf164a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446376701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3446376701
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3611963794
Short name T111
Test name
Test status
Simulation time 96333794 ps
CPU time 0.85 seconds
Started Mar 28 12:44:37 PM PDT 24
Finished Mar 28 12:44:38 PM PDT 24
Peak memory 198404 kb
Host smart-588dfa84-1928-432d-8490-aeb7135fc13a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611963794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3611963794
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3362788632
Short name T707
Test name
Test status
Simulation time 66287962 ps
CPU time 1.93 seconds
Started Mar 28 12:44:44 PM PDT 24
Finished Mar 28 12:44:46 PM PDT 24
Peak memory 199356 kb
Host smart-6d238d14-4479-444d-8d0b-d8096d856795
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362788632 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.3362788632
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3888589567
Short name T109
Test name
Test status
Simulation time 28616911 ps
CPU time 0.8 seconds
Started Mar 28 12:44:31 PM PDT 24
Finished Mar 28 12:44:32 PM PDT 24
Peak memory 198684 kb
Host smart-4976e51b-56d4-43b8-a5bb-d4e048ef163b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888589567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.3888589567
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2515259234
Short name T647
Test name
Test status
Simulation time 38232764 ps
CPU time 0.69 seconds
Started Mar 28 12:44:45 PM PDT 24
Finished Mar 28 12:44:46 PM PDT 24
Peak memory 193880 kb
Host smart-bf4a3b71-10ce-42a3-ac19-9eea34c9b4f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515259234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2515259234
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2736943239
Short name T724
Test name
Test status
Simulation time 199609452 ps
CPU time 1.09 seconds
Started Mar 28 12:44:49 PM PDT 24
Finished Mar 28 12:44:50 PM PDT 24
Peak memory 198588 kb
Host smart-480627c0-cf35-48e4-931c-c84a6b8d4874
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736943239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2736943239
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2166453614
Short name T686
Test name
Test status
Simulation time 160397488 ps
CPU time 3.56 seconds
Started Mar 28 12:44:37 PM PDT 24
Finished Mar 28 12:44:40 PM PDT 24
Peak memory 199384 kb
Host smart-02437a07-0e4b-48cb-b60a-67f355ee2d71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166453614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2166453614
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.237360392
Short name T699
Test name
Test status
Simulation time 265424485 ps
CPU time 1.88 seconds
Started Mar 28 12:44:49 PM PDT 24
Finished Mar 28 12:44:51 PM PDT 24
Peak memory 199216 kb
Host smart-ab1daaf3-00ce-4f79-9986-f94eb71ff01a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237360392 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.237360392
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.226628599
Short name T698
Test name
Test status
Simulation time 59366685 ps
CPU time 0.8 seconds
Started Mar 28 12:44:45 PM PDT 24
Finished Mar 28 12:44:46 PM PDT 24
Peak memory 198180 kb
Host smart-f4de775f-2564-47da-b21a-7a0b009ba413
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226628599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.226628599
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.428391731
Short name T651
Test name
Test status
Simulation time 11726257 ps
CPU time 0.58 seconds
Started Mar 28 12:44:44 PM PDT 24
Finished Mar 28 12:44:45 PM PDT 24
Peak memory 193912 kb
Host smart-e5afe98e-3122-4a3a-9f9e-d854c430340f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428391731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.428391731
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.4167889888
Short name T620
Test name
Test status
Simulation time 154543902 ps
CPU time 1.12 seconds
Started Mar 28 12:44:47 PM PDT 24
Finished Mar 28 12:44:49 PM PDT 24
Peak memory 199128 kb
Host smart-98439d73-65f2-4c5f-b999-81effe1b7e4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167889888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.4167889888
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2727476368
Short name T611
Test name
Test status
Simulation time 429010377 ps
CPU time 2.68 seconds
Started Mar 28 12:44:48 PM PDT 24
Finished Mar 28 12:44:51 PM PDT 24
Peak memory 199192 kb
Host smart-9982b5d0-d1ac-4bfd-b184-c9841a7a9eda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727476368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2727476368
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.268205522
Short name T129
Test name
Test status
Simulation time 165842020 ps
CPU time 2.81 seconds
Started Mar 28 12:44:47 PM PDT 24
Finished Mar 28 12:44:50 PM PDT 24
Peak memory 199160 kb
Host smart-d09c2565-1298-4dab-b0ba-1f142606112f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268205522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.268205522
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2785666140
Short name T729
Test name
Test status
Simulation time 41022772 ps
CPU time 1.14 seconds
Started Mar 28 12:44:47 PM PDT 24
Finished Mar 28 12:44:48 PM PDT 24
Peak memory 199140 kb
Host smart-0b6b3c43-0e9c-473d-b38f-57c51a5c2af4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785666140 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.2785666140
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3626009334
Short name T621
Test name
Test status
Simulation time 16052244 ps
CPU time 0.79 seconds
Started Mar 28 12:44:32 PM PDT 24
Finished Mar 28 12:44:33 PM PDT 24
Peak memory 198332 kb
Host smart-e2018485-6ba8-4c6c-be81-e31401f52870
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626009334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3626009334
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1080867724
Short name T697
Test name
Test status
Simulation time 54235071 ps
CPU time 0.61 seconds
Started Mar 28 12:44:48 PM PDT 24
Finished Mar 28 12:44:48 PM PDT 24
Peak memory 193824 kb
Host smart-1de5a824-2aff-4b27-9b30-d13686cdc866
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080867724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1080867724
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3523752518
Short name T716
Test name
Test status
Simulation time 285905055 ps
CPU time 1.66 seconds
Started Mar 28 12:44:48 PM PDT 24
Finished Mar 28 12:44:50 PM PDT 24
Peak memory 198588 kb
Host smart-9d00cf16-92ce-4fe0-ba6a-1d265a7050c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523752518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3523752518
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.964727735
Short name T723
Test name
Test status
Simulation time 820157948 ps
CPU time 3.66 seconds
Started Mar 28 12:44:48 PM PDT 24
Finished Mar 28 12:44:52 PM PDT 24
Peak memory 199236 kb
Host smart-d4c05eb1-4ab9-42bd-8e66-7a4330adad94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964727735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.964727735
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3151383508
Short name T126
Test name
Test status
Simulation time 249187702 ps
CPU time 3.97 seconds
Started Mar 28 12:44:33 PM PDT 24
Finished Mar 28 12:44:37 PM PDT 24
Peak memory 199260 kb
Host smart-c23b0bbb-ee94-4aa5-aec1-47df2ed4bc5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151383508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3151383508
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1752696757
Short name T691
Test name
Test status
Simulation time 91465115 ps
CPU time 2.53 seconds
Started Mar 28 12:44:49 PM PDT 24
Finished Mar 28 12:44:51 PM PDT 24
Peak memory 199328 kb
Host smart-1247382d-84d0-4fd5-8c51-06481d5e2c6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752696757 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1752696757
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2118665224
Short name T660
Test name
Test status
Simulation time 42155521 ps
CPU time 0.69 seconds
Started Mar 28 12:44:49 PM PDT 24
Finished Mar 28 12:44:49 PM PDT 24
Peak memory 196676 kb
Host smart-2a46305b-53be-4c8f-8672-41b894d38389
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118665224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2118665224
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1166031524
Short name T618
Test name
Test status
Simulation time 13595645 ps
CPU time 0.6 seconds
Started Mar 28 12:44:50 PM PDT 24
Finished Mar 28 12:44:51 PM PDT 24
Peak memory 193832 kb
Host smart-5c0b6955-fcd2-4505-ae6a-a049afc9156e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166031524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1166031524
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.4087156234
Short name T721
Test name
Test status
Simulation time 208251401 ps
CPU time 2.12 seconds
Started Mar 28 12:44:47 PM PDT 24
Finished Mar 28 12:44:49 PM PDT 24
Peak memory 199156 kb
Host smart-34408b98-9711-46ba-b18d-43617a4aeff9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087156234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.4087156234
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.227994387
Short name T627
Test name
Test status
Simulation time 234762262 ps
CPU time 1.41 seconds
Started Mar 28 12:44:48 PM PDT 24
Finished Mar 28 12:44:49 PM PDT 24
Peak memory 199288 kb
Host smart-b8dda533-9f06-4248-bd2a-79e815b5774f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227994387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.227994387
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.174841005
Short name T123
Test name
Test status
Simulation time 1653502099 ps
CPU time 3.11 seconds
Started Mar 28 12:44:48 PM PDT 24
Finished Mar 28 12:44:52 PM PDT 24
Peak memory 199160 kb
Host smart-469ed7b5-19b1-4ffb-8542-39af7bc07d65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174841005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.174841005
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2175146550
Short name T615
Test name
Test status
Simulation time 81243132311 ps
CPU time 198.04 seconds
Started Mar 28 12:45:36 PM PDT 24
Finished Mar 28 12:48:55 PM PDT 24
Peak memory 213280 kb
Host smart-b54f00e4-5205-42b6-9e8c-0c0db0cb5c2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175146550 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2175146550
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.952657224
Short name T117
Test name
Test status
Simulation time 34707242 ps
CPU time 0.94 seconds
Started Mar 28 12:45:36 PM PDT 24
Finished Mar 28 12:45:38 PM PDT 24
Peak memory 197008 kb
Host smart-518dd268-090a-4390-bfaf-8287b64f8848
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952657224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.952657224
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2769719286
Short name T728
Test name
Test status
Simulation time 10196885 ps
CPU time 0.59 seconds
Started Mar 28 12:45:36 PM PDT 24
Finished Mar 28 12:45:37 PM PDT 24
Peak memory 192424 kb
Host smart-805c8b6d-a2f1-486a-b687-74f16ca36a87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769719286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2769719286
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3464477484
Short name T711
Test name
Test status
Simulation time 1394981308 ps
CPU time 2.29 seconds
Started Mar 28 12:44:47 PM PDT 24
Finished Mar 28 12:44:49 PM PDT 24
Peak memory 199184 kb
Host smart-85f600da-fac0-46d8-b3e5-2e3f988d838a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464477484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3464477484
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2871358951
Short name T624
Test name
Test status
Simulation time 53438223 ps
CPU time 2.96 seconds
Started Mar 28 12:44:48 PM PDT 24
Finished Mar 28 12:44:51 PM PDT 24
Peak memory 199220 kb
Host smart-53af0a75-77d5-4853-9268-20203957956c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871358951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2871358951
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3600829433
Short name T64
Test name
Test status
Simulation time 523210833 ps
CPU time 1.75 seconds
Started Mar 28 12:44:49 PM PDT 24
Finished Mar 28 12:44:50 PM PDT 24
Peak memory 199216 kb
Host smart-b8830883-a7ad-4e00-a262-66ee7dd781d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600829433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3600829433
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2454284183
Short name T671
Test name
Test status
Simulation time 264363785 ps
CPU time 1.98 seconds
Started Mar 28 12:44:58 PM PDT 24
Finished Mar 28 12:45:00 PM PDT 24
Peak memory 199304 kb
Host smart-e4cc49d9-b9c3-4f9f-895e-3e2d770d31d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454284183 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2454284183
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3489844977
Short name T118
Test name
Test status
Simulation time 182288910 ps
CPU time 0.83 seconds
Started Mar 28 12:44:52 PM PDT 24
Finished Mar 28 12:44:53 PM PDT 24
Peak memory 199076 kb
Host smart-a82fc278-2c70-46d8-a954-964621b94bc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489844977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3489844977
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1150347406
Short name T719
Test name
Test status
Simulation time 39193679 ps
CPU time 0.54 seconds
Started Mar 28 12:44:48 PM PDT 24
Finished Mar 28 12:44:49 PM PDT 24
Peak memory 193896 kb
Host smart-b30767ad-1fb2-44a5-857c-b846f4a6072a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150347406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1150347406
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1946661865
Short name T65
Test name
Test status
Simulation time 652492286 ps
CPU time 1.91 seconds
Started Mar 28 12:44:51 PM PDT 24
Finished Mar 28 12:44:53 PM PDT 24
Peak memory 199176 kb
Host smart-408ab741-b18f-42e0-bb64-15a29ddbe515
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946661865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1946661865
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.719379374
Short name T607
Test name
Test status
Simulation time 271859512 ps
CPU time 1.77 seconds
Started Mar 28 12:44:49 PM PDT 24
Finished Mar 28 12:44:50 PM PDT 24
Peak memory 199220 kb
Host smart-29da6f90-f7a1-4df4-a23f-48fe8b2cd81a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719379374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.719379374
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2074225421
Short name T62
Test name
Test status
Simulation time 173395389 ps
CPU time 1.84 seconds
Started Mar 28 12:44:53 PM PDT 24
Finished Mar 28 12:44:55 PM PDT 24
Peak memory 199308 kb
Host smart-32a65dfc-7422-414f-a06a-15a156b1215e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074225421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2074225421
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.165484237
Short name T727
Test name
Test status
Simulation time 41301361119 ps
CPU time 600.2 seconds
Started Mar 28 12:44:53 PM PDT 24
Finished Mar 28 12:54:53 PM PDT 24
Peak memory 215060 kb
Host smart-f4985531-932a-493b-8327-bba56b2b8339
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165484237 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.165484237
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3633269681
Short name T608
Test name
Test status
Simulation time 23761617 ps
CPU time 0.66 seconds
Started Mar 28 12:45:02 PM PDT 24
Finished Mar 28 12:45:02 PM PDT 24
Peak memory 196792 kb
Host smart-65989a70-0c95-4f20-b268-6630764735a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633269681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3633269681
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2788907855
Short name T683
Test name
Test status
Simulation time 35976185 ps
CPU time 0.6 seconds
Started Mar 28 12:44:52 PM PDT 24
Finished Mar 28 12:44:52 PM PDT 24
Peak memory 194128 kb
Host smart-41e4f469-4b2b-4704-a81d-fdd2df47145e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788907855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2788907855
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1897833596
Short name T661
Test name
Test status
Simulation time 115303058 ps
CPU time 2.35 seconds
Started Mar 28 12:44:52 PM PDT 24
Finished Mar 28 12:44:55 PM PDT 24
Peak memory 199328 kb
Host smart-62c1af8c-e7b9-4105-b6b2-2dd152e7909e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897833596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.1897833596
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3563188443
Short name T630
Test name
Test status
Simulation time 151919071 ps
CPU time 4.01 seconds
Started Mar 28 12:45:01 PM PDT 24
Finished Mar 28 12:45:05 PM PDT 24
Peak memory 199176 kb
Host smart-347844e1-b887-477c-82e7-f8375ba8f00d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563188443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3563188443
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2378254433
Short name T710
Test name
Test status
Simulation time 290644162 ps
CPU time 4.44 seconds
Started Mar 28 12:44:56 PM PDT 24
Finished Mar 28 12:45:01 PM PDT 24
Peak memory 199280 kb
Host smart-2b9c67fc-9cdd-45c7-9a36-d4d978eac062
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378254433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2378254433
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.584978029
Short name T66
Test name
Test status
Simulation time 233552975 ps
CPU time 1.83 seconds
Started Mar 28 12:45:09 PM PDT 24
Finished Mar 28 12:45:11 PM PDT 24
Peak memory 199380 kb
Host smart-5bcc7a97-d375-4a6f-8aa7-7fc0b5940746
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584978029 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.584978029
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.225601879
Short name T108
Test name
Test status
Simulation time 46417928 ps
CPU time 0.7 seconds
Started Mar 28 12:44:56 PM PDT 24
Finished Mar 28 12:44:57 PM PDT 24
Peak memory 196764 kb
Host smart-351b723a-a733-4b3b-9ffa-79acd1639495
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225601879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.225601879
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.2446284083
Short name T687
Test name
Test status
Simulation time 49358608 ps
CPU time 0.61 seconds
Started Mar 28 12:44:50 PM PDT 24
Finished Mar 28 12:44:51 PM PDT 24
Peak memory 194016 kb
Host smart-6f26c5b1-072a-42a9-acb0-6d9e75694937
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446284083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2446284083
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3232310351
Short name T702
Test name
Test status
Simulation time 43408754 ps
CPU time 1.15 seconds
Started Mar 28 12:45:07 PM PDT 24
Finished Mar 28 12:45:08 PM PDT 24
Peak memory 197292 kb
Host smart-c6f75c1b-7624-4633-b97b-966b465681f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232310351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3232310351
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1725128548
Short name T605
Test name
Test status
Simulation time 221750361 ps
CPU time 1.4 seconds
Started Mar 28 12:44:51 PM PDT 24
Finished Mar 28 12:44:53 PM PDT 24
Peak memory 199380 kb
Host smart-22b031ad-0307-4f03-bbcf-d6985b64fe9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725128548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1725128548
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2663551340
Short name T131
Test name
Test status
Simulation time 349634462 ps
CPU time 4.24 seconds
Started Mar 28 12:44:54 PM PDT 24
Finished Mar 28 12:44:58 PM PDT 24
Peak memory 199280 kb
Host smart-f49d9c0f-76cc-495b-997f-a90c890f15a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663551340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2663551340
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.4102617551
Short name T657
Test name
Test status
Simulation time 103470823 ps
CPU time 2.1 seconds
Started Mar 28 12:45:09 PM PDT 24
Finished Mar 28 12:45:12 PM PDT 24
Peak memory 199248 kb
Host smart-96917425-f70a-4623-9959-6d654f29bf0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102617551 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.4102617551
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3526802530
Short name T121
Test name
Test status
Simulation time 49881178 ps
CPU time 0.95 seconds
Started Mar 28 12:45:17 PM PDT 24
Finished Mar 28 12:45:18 PM PDT 24
Peak memory 199164 kb
Host smart-89667399-e8dd-4b27-a530-89dc19edc9ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526802530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3526802530
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.3537327741
Short name T681
Test name
Test status
Simulation time 22751956 ps
CPU time 0.59 seconds
Started Mar 28 12:45:08 PM PDT 24
Finished Mar 28 12:45:09 PM PDT 24
Peak memory 193924 kb
Host smart-8eeafb1e-4e95-4185-8de1-3330181cc2ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537327741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3537327741
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3155715150
Short name T648
Test name
Test status
Simulation time 102328851 ps
CPU time 1.5 seconds
Started Mar 28 12:45:10 PM PDT 24
Finished Mar 28 12:45:11 PM PDT 24
Peak memory 198760 kb
Host smart-710d573d-2411-4fb8-bcbb-59d1d246d148
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155715150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3155715150
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.377785388
Short name T677
Test name
Test status
Simulation time 85633161 ps
CPU time 1.32 seconds
Started Mar 28 12:45:06 PM PDT 24
Finished Mar 28 12:45:07 PM PDT 24
Peak memory 199344 kb
Host smart-5e8bc866-2055-46e0-b5d2-ae18dcf8034a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377785388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.377785388
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3747068943
Short name T733
Test name
Test status
Simulation time 555219771 ps
CPU time 4.15 seconds
Started Mar 28 12:45:12 PM PDT 24
Finished Mar 28 12:45:16 PM PDT 24
Peak memory 199308 kb
Host smart-64670a8e-680c-4be4-b6cc-b6a77d5cd8fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747068943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3747068943
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1839210081
Short name T644
Test name
Test status
Simulation time 67521940 ps
CPU time 2.25 seconds
Started Mar 28 12:45:07 PM PDT 24
Finished Mar 28 12:45:10 PM PDT 24
Peak memory 199360 kb
Host smart-27bbb550-d849-45f1-977c-b10dbcdc6c33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839210081 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1839210081
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.538489269
Short name T631
Test name
Test status
Simulation time 16727266 ps
CPU time 0.71 seconds
Started Mar 28 12:45:08 PM PDT 24
Finished Mar 28 12:45:09 PM PDT 24
Peak memory 196996 kb
Host smart-49e54112-e436-455a-b347-aff7302d4c32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538489269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.538489269
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.172880270
Short name T680
Test name
Test status
Simulation time 17396279 ps
CPU time 0.65 seconds
Started Mar 28 12:45:10 PM PDT 24
Finished Mar 28 12:45:11 PM PDT 24
Peak memory 193904 kb
Host smart-2535de7d-afa5-4419-8cd5-73015b775af0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172880270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.172880270
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3396862543
Short name T635
Test name
Test status
Simulation time 372950590 ps
CPU time 1.75 seconds
Started Mar 28 12:45:13 PM PDT 24
Finished Mar 28 12:45:15 PM PDT 24
Peak memory 198708 kb
Host smart-fbb2cbc4-e0c9-49a1-a11d-a78e1984a04f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396862543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3396862543
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3863545845
Short name T609
Test name
Test status
Simulation time 51092322 ps
CPU time 1.66 seconds
Started Mar 28 12:45:10 PM PDT 24
Finished Mar 28 12:45:12 PM PDT 24
Peak memory 199356 kb
Host smart-050ba160-32c2-45b7-ac88-b9ea1cb08257
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863545845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3863545845
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.683749853
Short name T736
Test name
Test status
Simulation time 1948930459 ps
CPU time 3.16 seconds
Started Mar 28 12:45:11 PM PDT 24
Finished Mar 28 12:45:14 PM PDT 24
Peak memory 199256 kb
Host smart-9f3add8e-1034-4f8b-9a73-74509c29e2b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683749853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.683749853
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.4128583906
Short name T639
Test name
Test status
Simulation time 237550780 ps
CPU time 1.73 seconds
Started Mar 28 12:45:09 PM PDT 24
Finished Mar 28 12:45:11 PM PDT 24
Peak memory 199376 kb
Host smart-e133e2b8-78ff-47de-9331-36053e32a49a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128583906 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.4128583906
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3420315116
Short name T115
Test name
Test status
Simulation time 127867968 ps
CPU time 0.95 seconds
Started Mar 28 12:45:09 PM PDT 24
Finished Mar 28 12:45:11 PM PDT 24
Peak memory 198504 kb
Host smart-2cb1ac8e-f37e-42a7-9b13-e6ce1f6f82a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420315116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3420315116
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.3759718670
Short name T685
Test name
Test status
Simulation time 16185353 ps
CPU time 0.61 seconds
Started Mar 28 12:45:09 PM PDT 24
Finished Mar 28 12:45:10 PM PDT 24
Peak memory 194200 kb
Host smart-24560957-c5bd-4540-acf9-25776f4fa34c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759718670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3759718670
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.847985103
Short name T695
Test name
Test status
Simulation time 36787294 ps
CPU time 1.08 seconds
Started Mar 28 12:45:11 PM PDT 24
Finished Mar 28 12:45:12 PM PDT 24
Peak memory 199268 kb
Host smart-c7caa41f-3b95-4813-9da0-54e53b29cb4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847985103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.847985103
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.902882572
Short name T703
Test name
Test status
Simulation time 412827441 ps
CPU time 2.47 seconds
Started Mar 28 12:45:07 PM PDT 24
Finished Mar 28 12:45:10 PM PDT 24
Peak memory 199152 kb
Host smart-c426ee9a-2576-40eb-a484-03534a0b57b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902882572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.902882572
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3417657901
Short name T705
Test name
Test status
Simulation time 130804556 ps
CPU time 4.17 seconds
Started Mar 28 12:45:11 PM PDT 24
Finished Mar 28 12:45:15 PM PDT 24
Peak memory 199228 kb
Host smart-feb68eb3-78f1-4e5e-b57d-ab6697eeffe5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417657901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3417657901
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1000249682
Short name T725
Test name
Test status
Simulation time 121320906 ps
CPU time 5.59 seconds
Started Mar 28 12:44:49 PM PDT 24
Finished Mar 28 12:44:54 PM PDT 24
Peak memory 198032 kb
Host smart-f467e807-9ae2-4b59-9d21-4bfbfa2bf5d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000249682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1000249682
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.978169279
Short name T625
Test name
Test status
Simulation time 211633424 ps
CPU time 9.7 seconds
Started Mar 28 12:44:44 PM PDT 24
Finished Mar 28 12:44:54 PM PDT 24
Peak memory 198040 kb
Host smart-837a6f57-0205-454b-acc0-4f5119d458e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978169279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.978169279
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2190817839
Short name T737
Test name
Test status
Simulation time 16563874 ps
CPU time 0.87 seconds
Started Mar 28 12:44:45 PM PDT 24
Finished Mar 28 12:44:46 PM PDT 24
Peak memory 198340 kb
Host smart-35088133-1eda-434b-af0d-f89e1329c2fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190817839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2190817839
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1765448524
Short name T642
Test name
Test status
Simulation time 408426349 ps
CPU time 1.32 seconds
Started Mar 28 12:44:45 PM PDT 24
Finished Mar 28 12:44:46 PM PDT 24
Peak memory 199256 kb
Host smart-855514b1-87de-4810-aa45-e098ef4bae06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765448524 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1765448524
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2578639344
Short name T110
Test name
Test status
Simulation time 92136318 ps
CPU time 0.8 seconds
Started Mar 28 12:44:52 PM PDT 24
Finished Mar 28 12:44:52 PM PDT 24
Peak memory 197796 kb
Host smart-0c89f4b2-8925-4880-9fa8-a430109f48ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578639344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2578639344
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.917367244
Short name T664
Test name
Test status
Simulation time 55076373 ps
CPU time 0.66 seconds
Started Mar 28 12:44:30 PM PDT 24
Finished Mar 28 12:44:31 PM PDT 24
Peak memory 193956 kb
Host smart-0aa97ac5-dc61-4839-9d3b-74cd5eb716bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917367244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.917367244
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1219038442
Short name T704
Test name
Test status
Simulation time 44946308 ps
CPU time 1.21 seconds
Started Mar 28 12:44:46 PM PDT 24
Finished Mar 28 12:44:48 PM PDT 24
Peak memory 197336 kb
Host smart-65bd5461-8fe5-41ee-a218-18c7a15c8b57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219038442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1219038442
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1294571983
Short name T636
Test name
Test status
Simulation time 44677656 ps
CPU time 2.51 seconds
Started Mar 28 12:44:44 PM PDT 24
Finished Mar 28 12:44:47 PM PDT 24
Peak memory 199296 kb
Host smart-0a566b7f-8f72-40b0-8d89-1c605b73bf49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294571983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1294571983
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3674604348
Short name T124
Test name
Test status
Simulation time 85671086 ps
CPU time 2.91 seconds
Started Mar 28 12:44:52 PM PDT 24
Finished Mar 28 12:44:55 PM PDT 24
Peak memory 199084 kb
Host smart-7d7e516f-4ee8-4778-8d47-25bb9ed6e596
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674604348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3674604348
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1428942091
Short name T616
Test name
Test status
Simulation time 24805903 ps
CPU time 0.62 seconds
Started Mar 28 12:45:09 PM PDT 24
Finished Mar 28 12:45:10 PM PDT 24
Peak memory 193908 kb
Host smart-2673b231-f074-48ac-8038-702da5496cf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428942091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1428942091
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3751256485
Short name T666
Test name
Test status
Simulation time 38471107 ps
CPU time 0.6 seconds
Started Mar 28 12:45:10 PM PDT 24
Finished Mar 28 12:45:10 PM PDT 24
Peak memory 193968 kb
Host smart-e0e5d112-e4a1-4a4d-b277-9e5ec8b660de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751256485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3751256485
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3027602834
Short name T628
Test name
Test status
Simulation time 187609287 ps
CPU time 0.58 seconds
Started Mar 28 12:45:07 PM PDT 24
Finished Mar 28 12:45:08 PM PDT 24
Peak memory 193920 kb
Host smart-b2830a3c-e1a8-4430-8db1-527dbdef7542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027602834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3027602834
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1798233043
Short name T656
Test name
Test status
Simulation time 13321597 ps
CPU time 0.6 seconds
Started Mar 28 12:45:07 PM PDT 24
Finished Mar 28 12:45:08 PM PDT 24
Peak memory 193984 kb
Host smart-0c0ea714-fa13-4ce9-a948-0ab6b8909b18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798233043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1798233043
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.804336403
Short name T622
Test name
Test status
Simulation time 17364777 ps
CPU time 0.61 seconds
Started Mar 28 12:45:10 PM PDT 24
Finished Mar 28 12:45:10 PM PDT 24
Peak memory 194184 kb
Host smart-e188a665-3545-4fc4-a380-45580ef70dc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804336403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.804336403
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2071889670
Short name T668
Test name
Test status
Simulation time 13517728 ps
CPU time 0.58 seconds
Started Mar 28 12:45:09 PM PDT 24
Finished Mar 28 12:45:10 PM PDT 24
Peak memory 193860 kb
Host smart-e8ae2126-f421-4b3b-a019-2f3ac46470c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071889670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2071889670
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1406729126
Short name T637
Test name
Test status
Simulation time 12072878 ps
CPU time 0.59 seconds
Started Mar 28 12:45:07 PM PDT 24
Finished Mar 28 12:45:07 PM PDT 24
Peak memory 194192 kb
Host smart-f924dc5c-876f-43d0-b1ba-0a939eb18730
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406729126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1406729126
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3574352175
Short name T619
Test name
Test status
Simulation time 29953888 ps
CPU time 0.58 seconds
Started Mar 28 12:45:09 PM PDT 24
Finished Mar 28 12:45:10 PM PDT 24
Peak memory 194136 kb
Host smart-d0a142a5-3773-4fc3-9e57-17d2aa6398a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574352175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3574352175
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.251393721
Short name T606
Test name
Test status
Simulation time 13621899 ps
CPU time 0.57 seconds
Started Mar 28 12:45:09 PM PDT 24
Finished Mar 28 12:45:09 PM PDT 24
Peak memory 194076 kb
Host smart-b67f6553-d2b1-4f26-9362-d671367ad402
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251393721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.251393721
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3965876721
Short name T610
Test name
Test status
Simulation time 30397718 ps
CPU time 0.58 seconds
Started Mar 28 12:45:10 PM PDT 24
Finished Mar 28 12:45:11 PM PDT 24
Peak memory 193968 kb
Host smart-13ca9ee8-15d1-4483-8a87-4d7f440a276b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965876721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3965876721
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1102057539
Short name T667
Test name
Test status
Simulation time 1017916361 ps
CPU time 3.21 seconds
Started Mar 28 12:44:49 PM PDT 24
Finished Mar 28 12:44:52 PM PDT 24
Peak memory 197516 kb
Host smart-8e3a93f3-c19b-4f4a-9dad-1425d5bffb75
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102057539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1102057539
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2061836475
Short name T119
Test name
Test status
Simulation time 4381637150 ps
CPU time 11.22 seconds
Started Mar 28 12:44:43 PM PDT 24
Finished Mar 28 12:44:54 PM PDT 24
Peak memory 198344 kb
Host smart-12887d1a-1f2d-4706-beaa-9a23677eb4c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061836475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2061836475
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3192033005
Short name T120
Test name
Test status
Simulation time 159116628 ps
CPU time 1.03 seconds
Started Mar 28 12:44:33 PM PDT 24
Finished Mar 28 12:44:34 PM PDT 24
Peak memory 198420 kb
Host smart-fddba5fc-cf32-4bbc-bd6d-72d8b0bc02a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192033005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3192033005
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.672339260
Short name T663
Test name
Test status
Simulation time 166869308 ps
CPU time 1.39 seconds
Started Mar 28 12:44:31 PM PDT 24
Finished Mar 28 12:44:33 PM PDT 24
Peak memory 199376 kb
Host smart-82fe5670-02d7-43ca-8c69-f9b8274d8d02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672339260 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.672339260
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.742509303
Short name T649
Test name
Test status
Simulation time 35783287 ps
CPU time 0.73 seconds
Started Mar 28 12:44:44 PM PDT 24
Finished Mar 28 12:44:45 PM PDT 24
Peak memory 196676 kb
Host smart-3575ca52-1f9e-4d92-be3b-a4a6fa00b001
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742509303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.742509303
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3300647082
Short name T701
Test name
Test status
Simulation time 25371655 ps
CPU time 0.64 seconds
Started Mar 28 12:44:36 PM PDT 24
Finished Mar 28 12:44:37 PM PDT 24
Peak memory 194132 kb
Host smart-8ab7ffc1-13da-4aea-bc7c-7035ab376236
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300647082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3300647082
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1213731666
Short name T617
Test name
Test status
Simulation time 23012955 ps
CPU time 1.11 seconds
Started Mar 28 12:44:32 PM PDT 24
Finished Mar 28 12:44:34 PM PDT 24
Peak memory 198908 kb
Host smart-1634cfe5-6250-48f8-be10-d61857dc7314
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213731666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.1213731666
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2994192385
Short name T672
Test name
Test status
Simulation time 103683600 ps
CPU time 2.63 seconds
Started Mar 28 12:44:44 PM PDT 24
Finished Mar 28 12:44:47 PM PDT 24
Peak memory 199296 kb
Host smart-9f12d958-29d5-43ed-8e1e-475c9a5d9a73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994192385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2994192385
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2050266435
Short name T125
Test name
Test status
Simulation time 163556555 ps
CPU time 1.65 seconds
Started Mar 28 12:44:39 PM PDT 24
Finished Mar 28 12:44:41 PM PDT 24
Peak memory 199224 kb
Host smart-7d7e955c-c580-40ed-b6a8-1f0f6e2ec303
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050266435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2050266435
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.3709518408
Short name T614
Test name
Test status
Simulation time 50106471 ps
CPU time 0.6 seconds
Started Mar 28 12:45:11 PM PDT 24
Finished Mar 28 12:45:11 PM PDT 24
Peak memory 193904 kb
Host smart-577a23a5-dee5-40ac-aeac-8008df2a7d53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709518408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.3709518408
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3001156942
Short name T682
Test name
Test status
Simulation time 21773397 ps
CPU time 0.63 seconds
Started Mar 28 12:45:12 PM PDT 24
Finished Mar 28 12:45:13 PM PDT 24
Peak memory 193676 kb
Host smart-5e78351f-a958-480b-9411-1373b07b65e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001156942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3001156942
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3857165164
Short name T653
Test name
Test status
Simulation time 166341510 ps
CPU time 0.54 seconds
Started Mar 28 12:45:07 PM PDT 24
Finished Mar 28 12:45:07 PM PDT 24
Peak memory 193908 kb
Host smart-1b6d4fcc-4678-4049-81b6-f4beaf711083
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857165164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3857165164
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.877589152
Short name T629
Test name
Test status
Simulation time 30407637 ps
CPU time 0.64 seconds
Started Mar 28 12:45:13 PM PDT 24
Finished Mar 28 12:45:14 PM PDT 24
Peak memory 193924 kb
Host smart-8c1703cb-c835-4249-92ca-30e257da7e87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877589152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.877589152
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.2316099998
Short name T645
Test name
Test status
Simulation time 10939123 ps
CPU time 0.59 seconds
Started Mar 28 12:45:10 PM PDT 24
Finished Mar 28 12:45:11 PM PDT 24
Peak memory 193824 kb
Host smart-31b6404d-eccc-441a-8026-f9f9cf86ea0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316099998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2316099998
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.3596843745
Short name T694
Test name
Test status
Simulation time 28531114 ps
CPU time 0.63 seconds
Started Mar 28 12:45:10 PM PDT 24
Finished Mar 28 12:45:11 PM PDT 24
Peak memory 193960 kb
Host smart-6cb229dd-b452-44bf-a990-cdba59a6f191
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596843745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3596843745
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.398201032
Short name T612
Test name
Test status
Simulation time 14305201 ps
CPU time 0.56 seconds
Started Mar 28 12:45:09 PM PDT 24
Finished Mar 28 12:45:10 PM PDT 24
Peak memory 193852 kb
Host smart-f1f52410-5629-4de8-a358-1e86fcf47ee8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398201032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.398201032
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.37667269
Short name T717
Test name
Test status
Simulation time 27486732 ps
CPU time 0.6 seconds
Started Mar 28 12:45:13 PM PDT 24
Finished Mar 28 12:45:13 PM PDT 24
Peak memory 193904 kb
Host smart-d5ce1095-64ca-4389-bf44-5fb45d890e0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37667269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.37667269
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.3560652633
Short name T670
Test name
Test status
Simulation time 60247331 ps
CPU time 0.6 seconds
Started Mar 28 12:45:10 PM PDT 24
Finished Mar 28 12:45:11 PM PDT 24
Peak memory 194192 kb
Host smart-ee66ae27-f06c-415c-8be7-075ab6df90d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560652633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3560652633
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3719826207
Short name T659
Test name
Test status
Simulation time 13990816 ps
CPU time 0.57 seconds
Started Mar 28 12:45:12 PM PDT 24
Finished Mar 28 12:45:12 PM PDT 24
Peak memory 193904 kb
Host smart-0ca1d728-6916-4fe2-9ce4-2d155d409ffe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719826207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3719826207
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.125075444
Short name T114
Test name
Test status
Simulation time 417492470 ps
CPU time 7.62 seconds
Started Mar 28 12:44:52 PM PDT 24
Finished Mar 28 12:45:00 PM PDT 24
Peak memory 199164 kb
Host smart-3e369ae6-7ca4-461f-bb16-fd7b4bb5a93a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125075444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.125075444
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1507886448
Short name T679
Test name
Test status
Simulation time 1091341691 ps
CPU time 9.95 seconds
Started Mar 28 12:44:45 PM PDT 24
Finished Mar 28 12:44:55 PM PDT 24
Peak memory 197820 kb
Host smart-35998de1-ddf0-4933-91f3-22dd0a2a99ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507886448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1507886448
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.4030213373
Short name T718
Test name
Test status
Simulation time 47606254 ps
CPU time 0.72 seconds
Started Mar 28 12:44:48 PM PDT 24
Finished Mar 28 12:44:49 PM PDT 24
Peak memory 196844 kb
Host smart-0dc7da47-3004-44b8-82b8-29fcf01d5f59
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030213373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.4030213373
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1423870638
Short name T700
Test name
Test status
Simulation time 29405915 ps
CPU time 1.84 seconds
Started Mar 28 12:44:48 PM PDT 24
Finished Mar 28 12:44:50 PM PDT 24
Peak memory 199160 kb
Host smart-5843b789-8fb8-4f86-a207-0185c03990e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423870638 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1423870638
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1557320627
Short name T732
Test name
Test status
Simulation time 79015811 ps
CPU time 0.8 seconds
Started Mar 28 12:44:30 PM PDT 24
Finished Mar 28 12:44:31 PM PDT 24
Peak memory 198296 kb
Host smart-8b28bb8c-29ba-4c23-a6ca-556e10c40a68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557320627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1557320627
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3553771123
Short name T675
Test name
Test status
Simulation time 29192555 ps
CPU time 0.59 seconds
Started Mar 28 12:44:53 PM PDT 24
Finished Mar 28 12:44:53 PM PDT 24
Peak memory 193896 kb
Host smart-5e27fabf-0e8c-4f4a-93fa-108870c59322
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553771123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3553771123
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2631617209
Short name T696
Test name
Test status
Simulation time 50659583 ps
CPU time 1.24 seconds
Started Mar 28 12:44:48 PM PDT 24
Finished Mar 28 12:44:50 PM PDT 24
Peak memory 198960 kb
Host smart-83c2b383-efc9-4a66-aa24-c577ec3a3bc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631617209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.2631617209
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.4102023635
Short name T655
Test name
Test status
Simulation time 69119663 ps
CPU time 2.15 seconds
Started Mar 28 12:44:44 PM PDT 24
Finished Mar 28 12:44:46 PM PDT 24
Peak memory 199336 kb
Host smart-d43c6b37-3b31-48a6-8e11-6b2c651d810b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102023635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.4102023635
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3978688394
Short name T662
Test name
Test status
Simulation time 127521413 ps
CPU time 1.67 seconds
Started Mar 28 12:44:45 PM PDT 24
Finished Mar 28 12:44:47 PM PDT 24
Peak memory 199224 kb
Host smart-1f3d12b8-b012-4ff0-a6de-24300d91efa3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978688394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3978688394
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.4242138319
Short name T730
Test name
Test status
Simulation time 53937553 ps
CPU time 0.66 seconds
Started Mar 28 12:45:11 PM PDT 24
Finished Mar 28 12:45:12 PM PDT 24
Peak memory 194100 kb
Host smart-773687ff-6d35-4927-a03b-b4cc9b25706e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242138319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.4242138319
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2895443107
Short name T692
Test name
Test status
Simulation time 21663136 ps
CPU time 0.59 seconds
Started Mar 28 12:45:09 PM PDT 24
Finished Mar 28 12:45:10 PM PDT 24
Peak memory 193952 kb
Host smart-84f610d0-f122-4f63-b030-29bb7a78e154
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895443107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2895443107
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.806443335
Short name T643
Test name
Test status
Simulation time 28117242 ps
CPU time 0.62 seconds
Started Mar 28 12:45:09 PM PDT 24
Finished Mar 28 12:45:10 PM PDT 24
Peak memory 193944 kb
Host smart-c0b4dabf-d735-4b49-9e4a-b611dcd3ea06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806443335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.806443335
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.892571177
Short name T735
Test name
Test status
Simulation time 17514027 ps
CPU time 0.67 seconds
Started Mar 28 12:45:11 PM PDT 24
Finished Mar 28 12:45:11 PM PDT 24
Peak memory 193972 kb
Host smart-a862d88c-6479-4e71-b0e7-c98d9847f213
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892571177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.892571177
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.436346766
Short name T665
Test name
Test status
Simulation time 71464502 ps
CPU time 0.62 seconds
Started Mar 28 12:45:10 PM PDT 24
Finished Mar 28 12:45:11 PM PDT 24
Peak memory 193960 kb
Host smart-c9a74c41-d28d-4598-98bf-bb232f4b443e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436346766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.436346766
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2762065509
Short name T613
Test name
Test status
Simulation time 57122706 ps
CPU time 0.6 seconds
Started Mar 28 12:45:10 PM PDT 24
Finished Mar 28 12:45:10 PM PDT 24
Peak memory 193972 kb
Host smart-9c61c706-d76a-4597-816f-ba2d9a838817
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762065509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2762065509
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1593143044
Short name T658
Test name
Test status
Simulation time 12159736 ps
CPU time 0.59 seconds
Started Mar 28 12:45:09 PM PDT 24
Finished Mar 28 12:45:10 PM PDT 24
Peak memory 193904 kb
Host smart-d0b27846-3de6-49b2-bd83-b86c25772939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593143044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1593143044
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3954300692
Short name T676
Test name
Test status
Simulation time 19649692 ps
CPU time 0.7 seconds
Started Mar 28 12:45:12 PM PDT 24
Finished Mar 28 12:45:14 PM PDT 24
Peak memory 193976 kb
Host smart-48b855d8-c01d-4dc6-8b9f-e5af80df8f15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954300692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3954300692
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.3738877717
Short name T674
Test name
Test status
Simulation time 44079222 ps
CPU time 0.61 seconds
Started Mar 28 12:45:09 PM PDT 24
Finished Mar 28 12:45:09 PM PDT 24
Peak memory 193972 kb
Host smart-7efc7631-c854-4c9b-8b18-5e2c0855519c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738877717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3738877717
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.4117313741
Short name T708
Test name
Test status
Simulation time 34765047 ps
CPU time 0.54 seconds
Started Mar 28 12:45:07 PM PDT 24
Finished Mar 28 12:45:08 PM PDT 24
Peak memory 193952 kb
Host smart-95588444-fba8-4783-b5f2-063488ec7ca1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117313741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.4117313741
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1487533962
Short name T678
Test name
Test status
Simulation time 172072826 ps
CPU time 1.83 seconds
Started Mar 28 12:44:44 PM PDT 24
Finished Mar 28 12:44:46 PM PDT 24
Peak memory 199356 kb
Host smart-6af6bbb0-d57f-4875-9287-0e75ca7b1e69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487533962 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.1487533962
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3310684979
Short name T734
Test name
Test status
Simulation time 206145565 ps
CPU time 0.96 seconds
Started Mar 28 12:44:45 PM PDT 24
Finished Mar 28 12:44:47 PM PDT 24
Peak memory 198668 kb
Host smart-5e1c1809-6fef-4792-bfcf-45411842a002
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310684979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3310684979
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.344847039
Short name T669
Test name
Test status
Simulation time 39822956 ps
CPU time 0.64 seconds
Started Mar 28 12:44:49 PM PDT 24
Finished Mar 28 12:44:49 PM PDT 24
Peak memory 193764 kb
Host smart-435f8e45-09c3-43cf-a1f6-72636db30df4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344847039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.344847039
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3473421292
Short name T633
Test name
Test status
Simulation time 220015621 ps
CPU time 2.67 seconds
Started Mar 28 12:44:46 PM PDT 24
Finished Mar 28 12:44:49 PM PDT 24
Peak memory 199168 kb
Host smart-0f6651dd-19f8-4938-814e-6490ff56031f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473421292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3473421292
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2018177314
Short name T626
Test name
Test status
Simulation time 82886381 ps
CPU time 1.22 seconds
Started Mar 28 12:44:49 PM PDT 24
Finished Mar 28 12:44:50 PM PDT 24
Peak memory 199132 kb
Host smart-cbc28f6a-9a21-415b-9c3c-1af0b71ec895
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018177314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.2018177314
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1143494566
Short name T713
Test name
Test status
Simulation time 121379020 ps
CPU time 2.91 seconds
Started Mar 28 12:44:46 PM PDT 24
Finished Mar 28 12:44:49 PM PDT 24
Peak memory 199192 kb
Host smart-bdae4e28-4ae3-4b56-b8b8-f01c97bdc080
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143494566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1143494566
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1250175058
Short name T673
Test name
Test status
Simulation time 47493904 ps
CPU time 2.94 seconds
Started Mar 28 12:44:48 PM PDT 24
Finished Mar 28 12:44:51 PM PDT 24
Peak memory 199228 kb
Host smart-e455fadc-aefa-4471-ae1f-a1cb227a0b24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250175058 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1250175058
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.242021596
Short name T106
Test name
Test status
Simulation time 61596682 ps
CPU time 0.68 seconds
Started Mar 28 12:44:44 PM PDT 24
Finished Mar 28 12:44:45 PM PDT 24
Peak memory 196564 kb
Host smart-7d80ffcf-4d51-4ce6-93eb-1015e67a4591
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242021596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.242021596
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2581388850
Short name T650
Test name
Test status
Simulation time 51151593 ps
CPU time 0.62 seconds
Started Mar 28 12:44:44 PM PDT 24
Finished Mar 28 12:44:45 PM PDT 24
Peak memory 193864 kb
Host smart-1575c2f0-89a8-4118-8484-46d3347a5e8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581388850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2581388850
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2679147910
Short name T715
Test name
Test status
Simulation time 546765360 ps
CPU time 1.24 seconds
Started Mar 28 12:44:46 PM PDT 24
Finished Mar 28 12:44:48 PM PDT 24
Peak memory 197280 kb
Host smart-b58b2442-04e0-4854-8204-0e88d641bf3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679147910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2679147910
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1968941884
Short name T641
Test name
Test status
Simulation time 391530315 ps
CPU time 1.98 seconds
Started Mar 28 12:44:45 PM PDT 24
Finished Mar 28 12:44:47 PM PDT 24
Peak memory 199332 kb
Host smart-96cd02e0-90fd-4b15-9360-33c478b5b4db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968941884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1968941884
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1622309822
Short name T693
Test name
Test status
Simulation time 184169493 ps
CPU time 1.75 seconds
Started Mar 28 12:44:46 PM PDT 24
Finished Mar 28 12:44:48 PM PDT 24
Peak memory 199160 kb
Host smart-8a40de4d-2665-48cd-8fb1-95bb6841b1fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622309822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1622309822
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1530169532
Short name T690
Test name
Test status
Simulation time 477468271 ps
CPU time 1.69 seconds
Started Mar 28 12:44:46 PM PDT 24
Finished Mar 28 12:44:47 PM PDT 24
Peak memory 199300 kb
Host smart-eb8c15b4-3ec2-46be-827f-7c1e43ad990f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530169532 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1530169532
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3812193555
Short name T684
Test name
Test status
Simulation time 257859957 ps
CPU time 0.89 seconds
Started Mar 28 12:44:43 PM PDT 24
Finished Mar 28 12:44:44 PM PDT 24
Peak memory 198644 kb
Host smart-0ea02e20-c6f6-41ee-a1cb-32506bedf2ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812193555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3812193555
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.4041626249
Short name T646
Test name
Test status
Simulation time 16066172 ps
CPU time 0.55 seconds
Started Mar 28 12:44:43 PM PDT 24
Finished Mar 28 12:44:44 PM PDT 24
Peak memory 193868 kb
Host smart-26c4bdbd-2118-47aa-bf6e-60c203a2c241
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041626249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.4041626249
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1447961277
Short name T712
Test name
Test status
Simulation time 119188402 ps
CPU time 1.56 seconds
Started Mar 28 12:44:44 PM PDT 24
Finished Mar 28 12:44:46 PM PDT 24
Peak memory 199148 kb
Host smart-66272679-d4e8-46c5-a4bc-dce269d571f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447961277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.1447961277
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2640514838
Short name T652
Test name
Test status
Simulation time 33315504 ps
CPU time 1.79 seconds
Started Mar 28 12:44:44 PM PDT 24
Finished Mar 28 12:44:46 PM PDT 24
Peak memory 199300 kb
Host smart-a416d628-185f-4a83-8313-12245a2f5089
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640514838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2640514838
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2816451576
Short name T122
Test name
Test status
Simulation time 1043095619 ps
CPU time 4.28 seconds
Started Mar 28 12:44:45 PM PDT 24
Finished Mar 28 12:44:49 PM PDT 24
Peak memory 199280 kb
Host smart-7afa6793-fe3b-4fca-a3e6-40e06082d09e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816451576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2816451576
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.41969026
Short name T722
Test name
Test status
Simulation time 172286818 ps
CPU time 2.93 seconds
Started Mar 28 12:44:45 PM PDT 24
Finished Mar 28 12:44:48 PM PDT 24
Peak memory 207608 kb
Host smart-577839f8-c0e8-4bcb-b139-8808cd2a6c04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41969026 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.41969026
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3508354989
Short name T623
Test name
Test status
Simulation time 43067651 ps
CPU time 0.82 seconds
Started Mar 28 12:44:53 PM PDT 24
Finished Mar 28 12:44:54 PM PDT 24
Peak memory 199068 kb
Host smart-e081e23f-77bf-4aae-8e55-1d45225380db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508354989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3508354989
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.1153477392
Short name T634
Test name
Test status
Simulation time 14426887 ps
CPU time 0.57 seconds
Started Mar 28 12:44:44 PM PDT 24
Finished Mar 28 12:44:45 PM PDT 24
Peak memory 194132 kb
Host smart-dabe63c5-8b51-4511-a1fd-737759f4f302
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153477392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.1153477392
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3695550484
Short name T688
Test name
Test status
Simulation time 47212257 ps
CPU time 2.18 seconds
Started Mar 28 12:44:44 PM PDT 24
Finished Mar 28 12:44:46 PM PDT 24
Peak memory 199232 kb
Host smart-5f411665-6d84-4a5f-a63c-078c609f1504
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695550484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3695550484
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.4035273458
Short name T706
Test name
Test status
Simulation time 98942694 ps
CPU time 2.09 seconds
Started Mar 28 12:44:46 PM PDT 24
Finished Mar 28 12:44:48 PM PDT 24
Peak memory 199284 kb
Host smart-4e64d71e-1f69-438f-a96d-5cc50ebbc4c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035273458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.4035273458
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1122462211
Short name T130
Test name
Test status
Simulation time 97428668 ps
CPU time 2.77 seconds
Started Mar 28 12:44:49 PM PDT 24
Finished Mar 28 12:44:51 PM PDT 24
Peak memory 199208 kb
Host smart-7797a94b-8b21-4721-be9b-54b38815fd22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122462211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1122462211
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3406693320
Short name T731
Test name
Test status
Simulation time 105044376 ps
CPU time 3.49 seconds
Started Mar 28 12:44:47 PM PDT 24
Finished Mar 28 12:44:51 PM PDT 24
Peak memory 199304 kb
Host smart-c538becc-78d5-4708-b862-1f17d383aeb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406693320 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3406693320
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1125627507
Short name T640
Test name
Test status
Simulation time 32009685 ps
CPU time 0.7 seconds
Started Mar 28 12:44:45 PM PDT 24
Finished Mar 28 12:44:46 PM PDT 24
Peak memory 196748 kb
Host smart-1b7103e5-f1e3-4276-a362-1c893289ec6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125627507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1125627507
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.3138051839
Short name T709
Test name
Test status
Simulation time 22724062 ps
CPU time 0.57 seconds
Started Mar 28 12:44:45 PM PDT 24
Finished Mar 28 12:44:46 PM PDT 24
Peak memory 194092 kb
Host smart-c2af0d91-08ef-4753-9212-24f0c4bc8b48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138051839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3138051839
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.664872248
Short name T714
Test name
Test status
Simulation time 804533919 ps
CPU time 2.44 seconds
Started Mar 28 12:44:44 PM PDT 24
Finished Mar 28 12:44:46 PM PDT 24
Peak memory 199280 kb
Host smart-8bf5f4fa-e416-4231-965f-31a5bfd3bda1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664872248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.664872248
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1887716921
Short name T738
Test name
Test status
Simulation time 194015694 ps
CPU time 3.52 seconds
Started Mar 28 12:44:48 PM PDT 24
Finished Mar 28 12:44:52 PM PDT 24
Peak memory 199212 kb
Host smart-f8eefd28-50c9-4d88-9071-4442dc383eb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887716921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1887716921
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1113875842
Short name T102
Test name
Test status
Simulation time 13946555 ps
CPU time 0.59 seconds
Started Mar 28 01:15:21 PM PDT 24
Finished Mar 28 01:15:21 PM PDT 24
Peak memory 194540 kb
Host smart-843fded8-c216-4402-8e16-2e487f97d4a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113875842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1113875842
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.1225833382
Short name T512
Test name
Test status
Simulation time 251544409 ps
CPU time 10.05 seconds
Started Mar 28 01:15:13 PM PDT 24
Finished Mar 28 01:15:23 PM PDT 24
Peak memory 227684 kb
Host smart-6d04188b-ce94-4198-b532-5b22f70ed759
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1225833382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.1225833382
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3130934809
Short name T212
Test name
Test status
Simulation time 336577477 ps
CPU time 17.69 seconds
Started Mar 28 01:15:13 PM PDT 24
Finished Mar 28 01:15:30 PM PDT 24
Peak memory 200048 kb
Host smart-2150d8ec-296a-46f7-b533-801927b19732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130934809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3130934809
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1472072317
Short name T98
Test name
Test status
Simulation time 2205347935 ps
CPU time 130.07 seconds
Started Mar 28 01:15:15 PM PDT 24
Finished Mar 28 01:17:25 PM PDT 24
Peak memory 200076 kb
Host smart-9afca04d-6276-41d2-8800-199986506681
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1472072317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1472072317
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2128871401
Short name T435
Test name
Test status
Simulation time 1035991399 ps
CPU time 19.53 seconds
Started Mar 28 01:15:14 PM PDT 24
Finished Mar 28 01:15:33 PM PDT 24
Peak memory 200092 kb
Host smart-f416f773-1989-4a0b-b1df-0e63b5eeebba
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128871401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2128871401
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1831740381
Short name T477
Test name
Test status
Simulation time 6369732352 ps
CPU time 52.1 seconds
Started Mar 28 01:15:15 PM PDT 24
Finished Mar 28 01:16:07 PM PDT 24
Peak memory 200128 kb
Host smart-a9cd10ac-c87e-41fa-9918-ea6c79efee74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831740381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1831740381
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3654115912
Short name T469
Test name
Test status
Simulation time 6511891782 ps
CPU time 301.38 seconds
Started Mar 28 01:15:16 PM PDT 24
Finished Mar 28 01:20:18 PM PDT 24
Peak memory 233728 kb
Host smart-9b4f381c-3f7e-4224-9e3e-bf285e76cf12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654115912 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3654115912
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.1474788759
Short name T410
Test name
Test status
Simulation time 408011431 ps
CPU time 1.09 seconds
Started Mar 28 01:15:14 PM PDT 24
Finished Mar 28 01:15:15 PM PDT 24
Peak memory 199240 kb
Host smart-150ed3df-e6c8-48b2-a78f-b428a3d4e550
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474788759 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.1474788759
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.1692293403
Short name T421
Test name
Test status
Simulation time 29489074185 ps
CPU time 564.18 seconds
Started Mar 28 01:15:14 PM PDT 24
Finished Mar 28 01:24:39 PM PDT 24
Peak memory 200040 kb
Host smart-271597f4-4063-401a-9aa2-0b99997fba74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692293403 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.1692293403
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1685466752
Short name T475
Test name
Test status
Simulation time 8303405535 ps
CPU time 81 seconds
Started Mar 28 01:15:15 PM PDT 24
Finished Mar 28 01:16:36 PM PDT 24
Peak memory 200152 kb
Host smart-4197520b-f037-480d-8081-3dd3c073927b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685466752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1685466752
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.4026090145
Short name T331
Test name
Test status
Simulation time 5038891529 ps
CPU time 48.15 seconds
Started Mar 28 01:15:14 PM PDT 24
Finished Mar 28 01:16:02 PM PDT 24
Peak memory 212020 kb
Host smart-8dfb2fe9-f16c-4299-98d1-0d74ce62ecd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4026090145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.4026090145
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2906697931
Short name T306
Test name
Test status
Simulation time 5761876358 ps
CPU time 28.78 seconds
Started Mar 28 01:15:14 PM PDT 24
Finished Mar 28 01:15:43 PM PDT 24
Peak memory 200072 kb
Host smart-6bd54266-399e-4a63-bbbf-393fe62d98ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906697931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2906697931
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2883827351
Short name T219
Test name
Test status
Simulation time 3017365375 ps
CPU time 107.22 seconds
Started Mar 28 01:15:15 PM PDT 24
Finished Mar 28 01:17:02 PM PDT 24
Peak memory 200132 kb
Host smart-319dbfd5-af94-403c-b4c3-150f0c4bea1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2883827351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2883827351
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3819610045
Short name T314
Test name
Test status
Simulation time 58956604648 ps
CPU time 145.23 seconds
Started Mar 28 01:15:20 PM PDT 24
Finished Mar 28 01:17:45 PM PDT 24
Peak memory 200032 kb
Host smart-4a4440c4-5f5a-45c2-92ae-294c129f7e6d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819610045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3819610045
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2997249452
Short name T93
Test name
Test status
Simulation time 16998530163 ps
CPU time 60.11 seconds
Started Mar 28 01:15:20 PM PDT 24
Finished Mar 28 01:16:20 PM PDT 24
Peak memory 200008 kb
Host smart-43a52914-6d8c-483a-baed-19bd72153462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997249452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2997249452
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.2735180320
Short name T31
Test name
Test status
Simulation time 130945459 ps
CPU time 0.78 seconds
Started Mar 28 01:15:30 PM PDT 24
Finished Mar 28 01:15:31 PM PDT 24
Peak memory 218240 kb
Host smart-108beb6e-80dc-4269-9ddd-f50764051c89
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735180320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2735180320
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.2145598224
Short name T248
Test name
Test status
Simulation time 1237794067 ps
CPU time 4.99 seconds
Started Mar 28 01:15:18 PM PDT 24
Finished Mar 28 01:15:23 PM PDT 24
Peak memory 200080 kb
Host smart-18c80a53-1bda-4089-8756-8038db1d62e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145598224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2145598224
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.2295748356
Short name T81
Test name
Test status
Simulation time 1147054832 ps
CPU time 19.89 seconds
Started Mar 28 01:15:31 PM PDT 24
Finished Mar 28 01:15:51 PM PDT 24
Peak memory 200016 kb
Host smart-d49cb2bd-879c-4794-a131-edc3812ecd93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295748356 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2295748356
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.656073518
Short name T513
Test name
Test status
Simulation time 63663728 ps
CPU time 1.33 seconds
Started Mar 28 01:15:19 PM PDT 24
Finished Mar 28 01:15:20 PM PDT 24
Peak memory 199940 kb
Host smart-a306c337-a7f8-4624-b14b-1eadfc786879
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656073518 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_hmac_vectors.656073518
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.2118947128
Short name T247
Test name
Test status
Simulation time 15194696353 ps
CPU time 430.34 seconds
Started Mar 28 01:15:14 PM PDT 24
Finished Mar 28 01:22:24 PM PDT 24
Peak memory 200100 kb
Host smart-1236e404-5e16-4ddb-a077-69132359607e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118947128 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.2118947128
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.2411529003
Short name T189
Test name
Test status
Simulation time 1338612208 ps
CPU time 28.19 seconds
Started Mar 28 01:15:19 PM PDT 24
Finished Mar 28 01:15:48 PM PDT 24
Peak memory 199964 kb
Host smart-d8af4e28-6361-4985-9285-002d1df706c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411529003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2411529003
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.292854961
Short name T181
Test name
Test status
Simulation time 14073813 ps
CPU time 0.6 seconds
Started Mar 28 01:16:17 PM PDT 24
Finished Mar 28 01:16:18 PM PDT 24
Peak memory 195604 kb
Host smart-a9509f14-936e-42c7-a45b-9a6ef5723f30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292854961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.292854961
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1245702693
Short name T536
Test name
Test status
Simulation time 6207460768 ps
CPU time 66.01 seconds
Started Mar 28 01:16:16 PM PDT 24
Finished Mar 28 01:17:22 PM PDT 24
Peak memory 232572 kb
Host smart-f4f011f6-c865-4f50-a91d-61b9bc432203
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1245702693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1245702693
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.1881633413
Short name T586
Test name
Test status
Simulation time 1120652936 ps
CPU time 19.23 seconds
Started Mar 28 01:16:17 PM PDT 24
Finished Mar 28 01:16:37 PM PDT 24
Peak memory 200120 kb
Host smart-70d0770b-1a23-4080-b9e7-515c2ba71058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881633413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1881633413
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.813498446
Short name T154
Test name
Test status
Simulation time 9576950105 ps
CPU time 151.51 seconds
Started Mar 28 01:16:18 PM PDT 24
Finished Mar 28 01:18:49 PM PDT 24
Peak memory 200136 kb
Host smart-37cadad6-65d5-4493-bc7d-e3fd37f365d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=813498446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.813498446
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.344767488
Short name T455
Test name
Test status
Simulation time 35679452867 ps
CPU time 99.12 seconds
Started Mar 28 01:16:17 PM PDT 24
Finished Mar 28 01:17:56 PM PDT 24
Peak memory 200032 kb
Host smart-2962f40a-d242-41f3-b6cd-eb81792c051e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344767488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.344767488
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.1281366605
Short name T494
Test name
Test status
Simulation time 4839989001 ps
CPU time 70.04 seconds
Started Mar 28 01:16:17 PM PDT 24
Finished Mar 28 01:17:28 PM PDT 24
Peak memory 200096 kb
Host smart-7ca10a34-7d1f-4a1d-8fe1-d45eb071a2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281366605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1281366605
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.821677192
Short name T293
Test name
Test status
Simulation time 1517234897 ps
CPU time 5.77 seconds
Started Mar 28 01:16:17 PM PDT 24
Finished Mar 28 01:16:24 PM PDT 24
Peak memory 200052 kb
Host smart-5f4fdbc7-8b2f-4942-b121-3c060b5aca80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821677192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.821677192
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1345935281
Short name T437
Test name
Test status
Simulation time 89567976524 ps
CPU time 1495.84 seconds
Started Mar 28 01:16:18 PM PDT 24
Finished Mar 28 01:41:14 PM PDT 24
Peak memory 236244 kb
Host smart-dd7ffa60-ce11-475a-b16f-2a1972a83ec6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345935281 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1345935281
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.1510834994
Short name T558
Test name
Test status
Simulation time 211390511 ps
CPU time 1.27 seconds
Started Mar 28 01:16:18 PM PDT 24
Finished Mar 28 01:16:19 PM PDT 24
Peak memory 200108 kb
Host smart-9e92478a-86a5-4486-9451-297a48be757d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510834994 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.1510834994
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.676039437
Short name T250
Test name
Test status
Simulation time 108256513714 ps
CPU time 521.7 seconds
Started Mar 28 01:16:23 PM PDT 24
Finished Mar 28 01:25:05 PM PDT 24
Peak memory 199980 kb
Host smart-45e9bac9-a280-4a16-aba4-d784b0011012
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676039437 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.676039437
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.1162118375
Short name T180
Test name
Test status
Simulation time 1494270386 ps
CPU time 7.88 seconds
Started Mar 28 01:16:23 PM PDT 24
Finished Mar 28 01:16:31 PM PDT 24
Peak memory 199968 kb
Host smart-ee63bbf1-3ff5-495d-8c19-ac2e13dcbc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162118375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1162118375
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/102.hmac_stress_all_with_rand_reset.3117548329
Short name T67
Test name
Test status
Simulation time 222728807804 ps
CPU time 2988.44 seconds
Started Mar 28 01:20:40 PM PDT 24
Finished Mar 28 02:10:29 PM PDT 24
Peak memory 254748 kb
Host smart-e2a23585-a391-48a6-a032-60bf210ab85b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3117548329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.hmac_stress_all_with_rand_reset.3117548329
Directory /workspace/102.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3841507605
Short name T562
Test name
Test status
Simulation time 41939371 ps
CPU time 0.57 seconds
Started Mar 28 01:16:32 PM PDT 24
Finished Mar 28 01:16:33 PM PDT 24
Peak memory 195564 kb
Host smart-ce54dd22-a3bd-4738-94df-6e8bfc04a85f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841507605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3841507605
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2812998115
Short name T464
Test name
Test status
Simulation time 855517375 ps
CPU time 34.11 seconds
Started Mar 28 01:16:16 PM PDT 24
Finished Mar 28 01:16:50 PM PDT 24
Peak memory 224464 kb
Host smart-7aa09807-f506-4309-b211-6eab90eb77fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2812998115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2812998115
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.1190847112
Short name T548
Test name
Test status
Simulation time 2043575646 ps
CPU time 25.63 seconds
Started Mar 28 01:16:33 PM PDT 24
Finished Mar 28 01:17:00 PM PDT 24
Peak memory 200056 kb
Host smart-48f65748-737c-45c0-b1eb-bd76d4085893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190847112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1190847112
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1992023011
Short name T352
Test name
Test status
Simulation time 3992129709 ps
CPU time 111.75 seconds
Started Mar 28 01:16:35 PM PDT 24
Finished Mar 28 01:18:27 PM PDT 24
Peak memory 200116 kb
Host smart-2cb9770e-14a8-45cd-b5e9-cd1e19b0a721
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1992023011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1992023011
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2433986392
Short name T336
Test name
Test status
Simulation time 6948316391 ps
CPU time 93.52 seconds
Started Mar 28 01:16:39 PM PDT 24
Finished Mar 28 01:18:13 PM PDT 24
Peak memory 200156 kb
Host smart-8e419a0f-6371-46df-83f1-d9a5e99c4a73
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433986392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2433986392
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.173004641
Short name T37
Test name
Test status
Simulation time 9363842518 ps
CPU time 127.9 seconds
Started Mar 28 01:16:17 PM PDT 24
Finished Mar 28 01:18:25 PM PDT 24
Peak memory 200144 kb
Host smart-39676065-1abe-4bc7-8a1e-b2d2df14ec56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173004641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.173004641
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1482978863
Short name T508
Test name
Test status
Simulation time 4933560333 ps
CPU time 5.04 seconds
Started Mar 28 01:16:18 PM PDT 24
Finished Mar 28 01:16:23 PM PDT 24
Peak memory 200100 kb
Host smart-939c77a4-3bfe-40a1-83b4-ac05124b614f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482978863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1482978863
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.1696104063
Short name T218
Test name
Test status
Simulation time 645270002343 ps
CPU time 2193.22 seconds
Started Mar 28 01:16:32 PM PDT 24
Finished Mar 28 01:53:07 PM PDT 24
Peak memory 200116 kb
Host smart-9f05b7b9-1135-4fbe-aefc-c5bf7c864836
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696104063 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1696104063
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.1276556191
Short name T476
Test name
Test status
Simulation time 99756734 ps
CPU time 1.37 seconds
Started Mar 28 01:16:36 PM PDT 24
Finished Mar 28 01:16:38 PM PDT 24
Peak memory 200004 kb
Host smart-06b0db7f-d136-4360-93bf-22ba6eb47982
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276556191 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.1276556191
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.2634578176
Short name T484
Test name
Test status
Simulation time 7664482499 ps
CPU time 480.05 seconds
Started Mar 28 01:16:40 PM PDT 24
Finished Mar 28 01:24:40 PM PDT 24
Peak memory 199500 kb
Host smart-0c5235f0-3d59-4e80-9bee-b61747e30143
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634578176 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.2634578176
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.473686348
Short name T526
Test name
Test status
Simulation time 10153869900 ps
CPU time 35.22 seconds
Started Mar 28 01:16:35 PM PDT 24
Finished Mar 28 01:17:10 PM PDT 24
Peak memory 200144 kb
Host smart-86ef2ccb-4783-41ba-b3a2-3d33dc134805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473686348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.473686348
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/110.hmac_stress_all_with_rand_reset.1543694807
Short name T47
Test name
Test status
Simulation time 58293207630 ps
CPU time 649.68 seconds
Started Mar 28 01:20:43 PM PDT 24
Finished Mar 28 01:31:33 PM PDT 24
Peak memory 245096 kb
Host smart-83185d42-df31-4983-9836-4fa53d5469ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1543694807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.hmac_stress_all_with_rand_reset.1543694807
Directory /workspace/110.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2822794383
Short name T534
Test name
Test status
Simulation time 163729063 ps
CPU time 0.61 seconds
Started Mar 28 01:16:34 PM PDT 24
Finished Mar 28 01:16:36 PM PDT 24
Peak memory 195628 kb
Host smart-e84dbcbe-6211-44b4-9e13-342b943fe2b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822794383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2822794383
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.291276937
Short name T458
Test name
Test status
Simulation time 4374915141 ps
CPU time 37.36 seconds
Started Mar 28 01:16:39 PM PDT 24
Finished Mar 28 01:17:17 PM PDT 24
Peak memory 208328 kb
Host smart-393defb5-5da1-40bf-9347-212dad5946fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=291276937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.291276937
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2905336945
Short name T87
Test name
Test status
Simulation time 267219491 ps
CPU time 2.79 seconds
Started Mar 28 01:16:40 PM PDT 24
Finished Mar 28 01:16:43 PM PDT 24
Peak memory 199648 kb
Host smart-081a1763-a363-4e9d-947b-2e489caef6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905336945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2905336945
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.1106087118
Short name T334
Test name
Test status
Simulation time 1745385637 ps
CPU time 94.85 seconds
Started Mar 28 01:16:33 PM PDT 24
Finished Mar 28 01:18:08 PM PDT 24
Peak memory 200008 kb
Host smart-201a4265-6b10-48ef-866d-3342f53479d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1106087118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1106087118
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1611252513
Short name T14
Test name
Test status
Simulation time 12189077643 ps
CPU time 154.62 seconds
Started Mar 28 01:16:34 PM PDT 24
Finished Mar 28 01:19:10 PM PDT 24
Peak memory 200116 kb
Host smart-b91b8835-b7fc-44fe-8799-a56f56997574
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611252513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1611252513
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1275754736
Short name T21
Test name
Test status
Simulation time 2112773932 ps
CPU time 9.56 seconds
Started Mar 28 01:16:34 PM PDT 24
Finished Mar 28 01:16:45 PM PDT 24
Peak memory 200068 kb
Host smart-05141ea5-41b4-488d-8f2e-4b9577ea02c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275754736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1275754736
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.442349970
Short name T402
Test name
Test status
Simulation time 157314149 ps
CPU time 1.15 seconds
Started Mar 28 01:16:36 PM PDT 24
Finished Mar 28 01:16:38 PM PDT 24
Peak memory 199976 kb
Host smart-54a4d582-647c-44a9-8853-a8733896976b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442349970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.442349970
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.1904177782
Short name T275
Test name
Test status
Simulation time 45355720 ps
CPU time 1.12 seconds
Started Mar 28 01:16:32 PM PDT 24
Finished Mar 28 01:16:33 PM PDT 24
Peak memory 199240 kb
Host smart-d8ce870a-57b6-4168-852e-7c6a4c09adad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904177782 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.1904177782
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.2640843323
Short name T241
Test name
Test status
Simulation time 34757672010 ps
CPU time 433.61 seconds
Started Mar 28 01:16:33 PM PDT 24
Finished Mar 28 01:23:47 PM PDT 24
Peak memory 199976 kb
Host smart-828efcbf-78d6-49bd-995b-fe65f4749877
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640843323 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.2640843323
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.605589816
Short name T25
Test name
Test status
Simulation time 3913867034 ps
CPU time 84.27 seconds
Started Mar 28 01:16:32 PM PDT 24
Finished Mar 28 01:17:58 PM PDT 24
Peak memory 200056 kb
Host smart-1a94e204-d65c-43e8-b37b-5e5f45a75cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605589816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.605589816
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/128.hmac_stress_all_with_rand_reset.2413929123
Short name T7
Test name
Test status
Simulation time 3100859581 ps
CPU time 200.69 seconds
Started Mar 28 01:20:57 PM PDT 24
Finished Mar 28 01:24:18 PM PDT 24
Peak memory 215800 kb
Host smart-e6816116-e036-4195-9086-9eda0a09eeca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2413929123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.hmac_stress_all_with_rand_reset.2413929123
Directory /workspace/128.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3533019426
Short name T598
Test name
Test status
Simulation time 13844505 ps
CPU time 0.58 seconds
Started Mar 28 01:16:59 PM PDT 24
Finished Mar 28 01:17:00 PM PDT 24
Peak memory 195324 kb
Host smart-2f88facf-29a2-4bf4-88b4-35572e1a7b73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533019426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3533019426
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1426007474
Short name T503
Test name
Test status
Simulation time 348653485 ps
CPU time 13.11 seconds
Started Mar 28 01:16:36 PM PDT 24
Finished Mar 28 01:16:49 PM PDT 24
Peak memory 208204 kb
Host smart-158e9e1e-d24f-41a8-8dac-a3ad709545dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1426007474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1426007474
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.420712276
Short name T290
Test name
Test status
Simulation time 3076098656 ps
CPU time 60.61 seconds
Started Mar 28 01:16:34 PM PDT 24
Finished Mar 28 01:17:36 PM PDT 24
Peak memory 200128 kb
Host smart-616a42cd-b202-440c-a671-b4144240baef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420712276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.420712276
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.3685870249
Short name T349
Test name
Test status
Simulation time 1426383201 ps
CPU time 86.65 seconds
Started Mar 28 01:16:33 PM PDT 24
Finished Mar 28 01:18:00 PM PDT 24
Peak memory 200096 kb
Host smart-029f5bc1-42b3-4895-a796-01e184b029ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3685870249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.3685870249
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.1994817983
Short name T490
Test name
Test status
Simulation time 3131596984 ps
CPU time 86.12 seconds
Started Mar 28 01:16:33 PM PDT 24
Finished Mar 28 01:18:00 PM PDT 24
Peak memory 200152 kb
Host smart-f86bcecb-781d-4fa7-83d4-32777046428c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994817983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1994817983
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.3796400500
Short name T230
Test name
Test status
Simulation time 2982254625 ps
CPU time 60.76 seconds
Started Mar 28 01:16:34 PM PDT 24
Finished Mar 28 01:17:36 PM PDT 24
Peak memory 200144 kb
Host smart-a068ee0a-088f-4a9e-aa74-a31940e67a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796400500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.3796400500
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1645828262
Short name T597
Test name
Test status
Simulation time 1902519584 ps
CPU time 6.56 seconds
Started Mar 28 01:16:34 PM PDT 24
Finished Mar 28 01:16:42 PM PDT 24
Peak memory 200092 kb
Host smart-f7b04328-739e-4cde-bff9-c1a78bb98047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645828262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1645828262
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.3478690119
Short name T202
Test name
Test status
Simulation time 19161261572 ps
CPU time 86.84 seconds
Started Mar 28 01:16:34 PM PDT 24
Finished Mar 28 01:18:02 PM PDT 24
Peak memory 208328 kb
Host smart-33f1fceb-5958-4e58-a34f-6d1f41be3424
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478690119 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3478690119
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.2543299788
Short name T545
Test name
Test status
Simulation time 138078064 ps
CPU time 1.08 seconds
Started Mar 28 01:16:34 PM PDT 24
Finished Mar 28 01:16:36 PM PDT 24
Peak memory 199668 kb
Host smart-0abc8325-46ef-4af7-b2a0-0725ac93976b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543299788 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.2543299788
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.2413773118
Short name T232
Test name
Test status
Simulation time 26359327962 ps
CPU time 496.52 seconds
Started Mar 28 01:16:36 PM PDT 24
Finished Mar 28 01:24:53 PM PDT 24
Peak memory 200036 kb
Host smart-46d0befb-2344-445f-9358-45537b468ee2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413773118 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.2413773118
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2886544170
Short name T388
Test name
Test status
Simulation time 14056613238 ps
CPU time 73.82 seconds
Started Mar 28 01:16:34 PM PDT 24
Finished Mar 28 01:17:49 PM PDT 24
Peak memory 200116 kb
Host smart-ad794809-3e0a-4b76-8cbf-74cb87a181db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886544170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2886544170
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/138.hmac_stress_all_with_rand_reset.1483541616
Short name T9
Test name
Test status
Simulation time 266138817112 ps
CPU time 1922.59 seconds
Started Mar 28 01:20:59 PM PDT 24
Finished Mar 28 01:53:01 PM PDT 24
Peak memory 233004 kb
Host smart-bb882c56-544f-4e18-aabf-9100881c4ec1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1483541616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.hmac_stress_all_with_rand_reset.1483541616
Directory /workspace/138.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2476393745
Short name T237
Test name
Test status
Simulation time 13233492 ps
CPU time 0.58 seconds
Started Mar 28 01:16:59 PM PDT 24
Finished Mar 28 01:16:59 PM PDT 24
Peak memory 194512 kb
Host smart-51b165c2-fa5c-44bd-9caf-b044cae64a51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476393745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2476393745
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2994257721
Short name T272
Test name
Test status
Simulation time 354411460 ps
CPU time 4.73 seconds
Started Mar 28 01:16:57 PM PDT 24
Finished Mar 28 01:17:02 PM PDT 24
Peak memory 200076 kb
Host smart-9f2ef56a-817f-4ee4-a7ec-7c24200a9275
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2994257721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2994257721
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.1471775269
Short name T203
Test name
Test status
Simulation time 773259582 ps
CPU time 36.96 seconds
Started Mar 28 01:16:58 PM PDT 24
Finished Mar 28 01:17:35 PM PDT 24
Peak memory 200076 kb
Host smart-1d5c387d-17e2-4189-bd8f-9a3ba8f6b0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471775269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.1471775269
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.2822689714
Short name T103
Test name
Test status
Simulation time 152539123 ps
CPU time 9.83 seconds
Started Mar 28 01:16:57 PM PDT 24
Finished Mar 28 01:17:07 PM PDT 24
Peak memory 200072 kb
Host smart-86441f4c-2988-4fe4-ab84-78a23f795e25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2822689714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2822689714
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.597533900
Short name T462
Test name
Test status
Simulation time 22309999485 ps
CPU time 88.6 seconds
Started Mar 28 01:16:59 PM PDT 24
Finished Mar 28 01:18:27 PM PDT 24
Peak memory 200112 kb
Host smart-ef222aad-563d-46b6-9b29-a47a9863cfef
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597533900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.597533900
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.3643081400
Short name T200
Test name
Test status
Simulation time 4266651088 ps
CPU time 47.94 seconds
Started Mar 28 01:16:59 PM PDT 24
Finished Mar 28 01:17:47 PM PDT 24
Peak memory 200196 kb
Host smart-bca00b8b-a96a-4f90-bec8-42be9995a5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643081400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3643081400
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1780150868
Short name T538
Test name
Test status
Simulation time 54088228 ps
CPU time 1.19 seconds
Started Mar 28 01:17:00 PM PDT 24
Finished Mar 28 01:17:02 PM PDT 24
Peak memory 199060 kb
Host smart-181bbe27-9fdb-4421-8f8d-a711160f3f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780150868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1780150868
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.1990271896
Short name T604
Test name
Test status
Simulation time 12023698059 ps
CPU time 59.25 seconds
Started Mar 28 01:16:59 PM PDT 24
Finished Mar 28 01:17:58 PM PDT 24
Peak memory 232784 kb
Host smart-52563a55-c84e-4dc8-95b5-2ba8e3265236
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990271896 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.1990271896
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.3462885573
Short name T253
Test name
Test status
Simulation time 155072676 ps
CPU time 1.26 seconds
Started Mar 28 01:16:57 PM PDT 24
Finished Mar 28 01:16:59 PM PDT 24
Peak memory 199688 kb
Host smart-542f21ac-10af-4de9-89a6-38afa3ca234f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462885573 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.3462885573
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.1004168382
Short name T3
Test name
Test status
Simulation time 7342051822 ps
CPU time 402.28 seconds
Started Mar 28 01:16:58 PM PDT 24
Finished Mar 28 01:23:40 PM PDT 24
Peak memory 200056 kb
Host smart-80ce1b0d-b0ec-46fb-a377-b5461e62f8ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004168382 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.1004168382
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3910466548
Short name T482
Test name
Test status
Simulation time 2496450627 ps
CPU time 52.53 seconds
Started Mar 28 01:16:59 PM PDT 24
Finished Mar 28 01:17:51 PM PDT 24
Peak memory 200108 kb
Host smart-9d8bffdd-4357-48e5-bf21-26287b83011f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910466548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3910466548
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.127744685
Short name T226
Test name
Test status
Simulation time 13049374 ps
CPU time 0.59 seconds
Started Mar 28 01:17:00 PM PDT 24
Finished Mar 28 01:17:01 PM PDT 24
Peak memory 195616 kb
Host smart-06a50d40-131f-4c06-a014-f155c498f650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127744685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.127744685
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.2612121800
Short name T404
Test name
Test status
Simulation time 4437055701 ps
CPU time 50.68 seconds
Started Mar 28 01:16:59 PM PDT 24
Finished Mar 28 01:17:50 PM PDT 24
Peak memory 232820 kb
Host smart-79d35f7a-798e-42ba-8712-ed8fd5b322cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2612121800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2612121800
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1305723932
Short name T95
Test name
Test status
Simulation time 779384740 ps
CPU time 42.36 seconds
Started Mar 28 01:16:59 PM PDT 24
Finished Mar 28 01:17:41 PM PDT 24
Peak memory 200072 kb
Host smart-f8abcd89-96e8-44d9-95a9-8a87afe368a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305723932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1305723932
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1976095962
Short name T368
Test name
Test status
Simulation time 1003551769 ps
CPU time 56.67 seconds
Started Mar 28 01:16:58 PM PDT 24
Finished Mar 28 01:17:55 PM PDT 24
Peak memory 200060 kb
Host smart-3e57a199-2a10-4b96-bc6f-434c77137a2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1976095962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1976095962
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.67821787
Short name T489
Test name
Test status
Simulation time 142186495 ps
CPU time 8.8 seconds
Started Mar 28 01:16:58 PM PDT 24
Finished Mar 28 01:17:07 PM PDT 24
Peak memory 199980 kb
Host smart-ff18a3e7-8e0f-40ec-9f3e-f5ca17a27817
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67821787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.67821787
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_smoke.3562197444
Short name T139
Test name
Test status
Simulation time 975384863 ps
CPU time 3.03 seconds
Started Mar 28 01:17:00 PM PDT 24
Finished Mar 28 01:17:03 PM PDT 24
Peak memory 200064 kb
Host smart-97600022-b243-4dcd-aad2-2e5d1ba11eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562197444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3562197444
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.534157497
Short name T330
Test name
Test status
Simulation time 79344433009 ps
CPU time 407.61 seconds
Started Mar 28 01:17:00 PM PDT 24
Finished Mar 28 01:23:48 PM PDT 24
Peak memory 208328 kb
Host smart-5c8503ac-5d57-4faa-8961-9eed2d172985
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534157497 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.534157497
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.3643246454
Short name T243
Test name
Test status
Simulation time 99520807 ps
CPU time 1 seconds
Started Mar 28 01:17:00 PM PDT 24
Finished Mar 28 01:17:01 PM PDT 24
Peak memory 199384 kb
Host smart-e8ac739a-95c9-48ca-b554-db2647a36180
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643246454 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.3643246454
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.905574368
Short name T541
Test name
Test status
Simulation time 29637391011 ps
CPU time 552.69 seconds
Started Mar 28 01:16:58 PM PDT 24
Finished Mar 28 01:26:11 PM PDT 24
Peak memory 200056 kb
Host smart-d6ac1ad1-631c-4f13-80d4-5d4c8f0d736f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905574368 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.905574368
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1834156285
Short name T342
Test name
Test status
Simulation time 381137184 ps
CPU time 5.86 seconds
Started Mar 28 01:16:59 PM PDT 24
Finished Mar 28 01:17:05 PM PDT 24
Peak memory 200032 kb
Host smart-d2a4346e-7472-495e-9e2c-6c330fd3f868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834156285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1834156285
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/158.hmac_stress_all_with_rand_reset.3602072902
Short name T71
Test name
Test status
Simulation time 24082558719 ps
CPU time 586.34 seconds
Started Mar 28 01:21:05 PM PDT 24
Finished Mar 28 01:30:51 PM PDT 24
Peak memory 248184 kb
Host smart-a1a422a4-761b-43e2-960b-bdb018d1524a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3602072902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.hmac_stress_all_with_rand_reset.3602072902
Directory /workspace/158.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_alert_test.1642265577
Short name T333
Test name
Test status
Simulation time 52754682 ps
CPU time 0.57 seconds
Started Mar 28 01:17:19 PM PDT 24
Finished Mar 28 01:17:20 PM PDT 24
Peak memory 194556 kb
Host smart-b868dc89-33bf-4d36-9630-5e8d877c40db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642265577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.1642265577
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1121573963
Short name T439
Test name
Test status
Simulation time 368519645 ps
CPU time 16.81 seconds
Started Mar 28 01:17:00 PM PDT 24
Finished Mar 28 01:17:17 PM PDT 24
Peak memory 225576 kb
Host smart-1ae91512-a887-4c2b-a882-52e361b97005
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1121573963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1121573963
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.566390456
Short name T487
Test name
Test status
Simulation time 320050351 ps
CPU time 5.64 seconds
Started Mar 28 01:17:24 PM PDT 24
Finished Mar 28 01:17:29 PM PDT 24
Peak memory 199924 kb
Host smart-ef5237d1-930c-4823-8c38-8c07da5ee3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566390456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.566390456
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3061370188
Short name T297
Test name
Test status
Simulation time 2621389273 ps
CPU time 41.7 seconds
Started Mar 28 01:17:01 PM PDT 24
Finished Mar 28 01:17:43 PM PDT 24
Peak memory 200104 kb
Host smart-63bc69c1-0c59-4eaa-afa7-c29115c9bc0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3061370188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3061370188
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.1002779457
Short name T506
Test name
Test status
Simulation time 1760251723 ps
CPU time 68.22 seconds
Started Mar 28 01:17:20 PM PDT 24
Finished Mar 28 01:18:28 PM PDT 24
Peak memory 200028 kb
Host smart-a4011a28-5696-43aa-b1c6-aa34b92b119e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002779457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1002779457
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.981146941
Short name T303
Test name
Test status
Simulation time 1722271671 ps
CPU time 35.27 seconds
Started Mar 28 01:17:01 PM PDT 24
Finished Mar 28 01:17:37 PM PDT 24
Peak memory 200084 kb
Host smart-c3083c2e-1ce9-4cef-99a3-a4e84e566b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981146941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.981146941
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.508381077
Short name T468
Test name
Test status
Simulation time 23093342 ps
CPU time 0.72 seconds
Started Mar 28 01:17:03 PM PDT 24
Finished Mar 28 01:17:04 PM PDT 24
Peak memory 197180 kb
Host smart-906d6274-58ce-43b6-bc6e-2744e82cff37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508381077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.508381077
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3167644362
Short name T370
Test name
Test status
Simulation time 16757861874 ps
CPU time 893.81 seconds
Started Mar 28 01:17:19 PM PDT 24
Finished Mar 28 01:32:13 PM PDT 24
Peak memory 224752 kb
Host smart-30f3c33b-dc54-4b31-a393-c566d10a8f86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167644362 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3167644362
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.491130845
Short name T343
Test name
Test status
Simulation time 71859201 ps
CPU time 1.22 seconds
Started Mar 28 01:17:19 PM PDT 24
Finished Mar 28 01:17:20 PM PDT 24
Peak memory 200052 kb
Host smart-f10379be-08df-4686-9d48-6f2e8d653226
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491130845 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.hmac_test_hmac_vectors.491130845
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.2701377308
Short name T162
Test name
Test status
Simulation time 13747146067 ps
CPU time 412.83 seconds
Started Mar 28 01:17:37 PM PDT 24
Finished Mar 28 01:24:30 PM PDT 24
Peak memory 200152 kb
Host smart-dc6262a3-d458-469d-84fa-c999fd1593d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701377308 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.2701377308
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1852916127
Short name T556
Test name
Test status
Simulation time 290788964 ps
CPU time 4.06 seconds
Started Mar 28 01:17:20 PM PDT 24
Finished Mar 28 01:17:24 PM PDT 24
Peak memory 200076 kb
Host smart-0a472ec6-26b9-4460-a749-80fbc953d04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852916127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1852916127
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.4226566266
Short name T61
Test name
Test status
Simulation time 34431079 ps
CPU time 0.59 seconds
Started Mar 28 01:17:22 PM PDT 24
Finished Mar 28 01:17:22 PM PDT 24
Peak memory 195600 kb
Host smart-f3f6bb46-b651-4989-a2eb-9548364548ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226566266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.4226566266
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.1560663945
Short name T55
Test name
Test status
Simulation time 1542073874 ps
CPU time 18.39 seconds
Started Mar 28 01:17:18 PM PDT 24
Finished Mar 28 01:17:37 PM PDT 24
Peak memory 236628 kb
Host smart-a88db207-2117-48b6-b4fc-f771ef119559
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1560663945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1560663945
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.194443250
Short name T320
Test name
Test status
Simulation time 8088617525 ps
CPU time 34.08 seconds
Started Mar 28 01:17:22 PM PDT 24
Finished Mar 28 01:17:56 PM PDT 24
Peak memory 200160 kb
Host smart-343ff274-d3cc-4246-8569-c0785dbe067c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194443250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.194443250
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3758606893
Short name T405
Test name
Test status
Simulation time 104121751 ps
CPU time 5.8 seconds
Started Mar 28 01:17:19 PM PDT 24
Finished Mar 28 01:17:25 PM PDT 24
Peak memory 199976 kb
Host smart-dc33821e-c42a-4016-8068-ba2307b016a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3758606893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3758606893
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.774315349
Short name T54
Test name
Test status
Simulation time 347330228 ps
CPU time 21.01 seconds
Started Mar 28 01:17:19 PM PDT 24
Finished Mar 28 01:17:40 PM PDT 24
Peak memory 200056 kb
Host smart-a6b11585-49ba-410e-b7eb-3411e1737df1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774315349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.774315349
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.1299686121
Short name T588
Test name
Test status
Simulation time 5326419972 ps
CPU time 41.12 seconds
Started Mar 28 01:17:20 PM PDT 24
Finished Mar 28 01:18:01 PM PDT 24
Peak memory 200136 kb
Host smart-855d41bd-88ed-4e53-94ca-b2ceb981d612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299686121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1299686121
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.1092790162
Short name T91
Test name
Test status
Simulation time 1857481496 ps
CPU time 5.75 seconds
Started Mar 28 01:17:19 PM PDT 24
Finished Mar 28 01:17:25 PM PDT 24
Peak memory 200072 kb
Host smart-79c0d184-0ee2-4cef-bf2e-b174ecc46b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092790162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.1092790162
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2341903713
Short name T602
Test name
Test status
Simulation time 57609017460 ps
CPU time 307.44 seconds
Started Mar 28 01:17:20 PM PDT 24
Finished Mar 28 01:22:28 PM PDT 24
Peak memory 209252 kb
Host smart-7ca05bb7-84ce-482e-a782-09d1cab10d2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341903713 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2341903713
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.3524287768
Short name T259
Test name
Test status
Simulation time 348130908 ps
CPU time 1.36 seconds
Started Mar 28 01:17:20 PM PDT 24
Finished Mar 28 01:17:22 PM PDT 24
Peak memory 199944 kb
Host smart-9fd22840-1eb4-408f-b154-cf95f4a58c67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524287768 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.3524287768
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.1457163071
Short name T317
Test name
Test status
Simulation time 7834028447 ps
CPU time 422.41 seconds
Started Mar 28 01:17:21 PM PDT 24
Finished Mar 28 01:24:23 PM PDT 24
Peak memory 200084 kb
Host smart-47dd405d-b438-4597-a68b-3f23aff483e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457163071 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.1457163071
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.2120184711
Short name T39
Test name
Test status
Simulation time 421028173 ps
CPU time 6.62 seconds
Started Mar 28 01:17:20 PM PDT 24
Finished Mar 28 01:17:26 PM PDT 24
Peak memory 200076 kb
Host smart-35b8de27-09d1-4728-92bf-2d5815f53e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120184711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.2120184711
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/170.hmac_stress_all_with_rand_reset.1844081858
Short name T11
Test name
Test status
Simulation time 37579719688 ps
CPU time 1859.64 seconds
Started Mar 28 01:21:14 PM PDT 24
Finished Mar 28 01:52:14 PM PDT 24
Peak memory 226648 kb
Host smart-d9efbd0a-d45d-44ac-83bc-93fc79fc3776
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1844081858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.hmac_stress_all_with_rand_reset.1844081858
Directory /workspace/170.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/171.hmac_stress_all_with_rand_reset.117913463
Short name T415
Test name
Test status
Simulation time 70825439866 ps
CPU time 1330.91 seconds
Started Mar 28 01:21:14 PM PDT 24
Finished Mar 28 01:43:25 PM PDT 24
Peak memory 248788 kb
Host smart-63e29cfe-e5a1-4578-b26b-6c45c4082c53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=117913463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.hmac_stress_all_with_rand_reset.117913463
Directory /workspace/171.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2874188171
Short name T255
Test name
Test status
Simulation time 103768543 ps
CPU time 0.58 seconds
Started Mar 28 01:17:23 PM PDT 24
Finished Mar 28 01:17:24 PM PDT 24
Peak memory 194448 kb
Host smart-06836e58-3641-448e-b9bc-f75c20f5994d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874188171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2874188171
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2095813178
Short name T279
Test name
Test status
Simulation time 689255622 ps
CPU time 2.29 seconds
Started Mar 28 01:17:22 PM PDT 24
Finished Mar 28 01:17:24 PM PDT 24
Peak memory 215968 kb
Host smart-45970f95-6a2c-4eac-ab7f-a5d5f0619a2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2095813178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2095813178
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.2440339329
Short name T208
Test name
Test status
Simulation time 3013508808 ps
CPU time 31.27 seconds
Started Mar 28 01:17:22 PM PDT 24
Finished Mar 28 01:17:53 PM PDT 24
Peak memory 200136 kb
Host smart-6abc7dfc-d2ce-4676-ab6f-40682e671235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440339329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.2440339329
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2779371677
Short name T45
Test name
Test status
Simulation time 361863367 ps
CPU time 20.65 seconds
Started Mar 28 01:17:21 PM PDT 24
Finished Mar 28 01:17:42 PM PDT 24
Peak memory 200080 kb
Host smart-58e988d9-92c4-4636-b0ea-3a8a17f1aa9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2779371677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2779371677
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.1543385907
Short name T603
Test name
Test status
Simulation time 18246140783 ps
CPU time 57.79 seconds
Started Mar 28 01:17:22 PM PDT 24
Finished Mar 28 01:18:20 PM PDT 24
Peak memory 200040 kb
Host smart-87073bf9-0a35-4513-a865-12ad115b680a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543385907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1543385907
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.4186663349
Short name T105
Test name
Test status
Simulation time 1417070457 ps
CPU time 57.83 seconds
Started Mar 28 01:17:20 PM PDT 24
Finished Mar 28 01:18:18 PM PDT 24
Peak memory 200052 kb
Host smart-01b6d4ca-077b-4230-b4fa-bbb72ebab306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186663349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.4186663349
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.894656518
Short name T571
Test name
Test status
Simulation time 256330125 ps
CPU time 2.32 seconds
Started Mar 28 01:17:21 PM PDT 24
Finished Mar 28 01:17:24 PM PDT 24
Peak memory 200032 kb
Host smart-3e9b2aba-93ed-44d2-8b40-dae04881ff03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894656518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.894656518
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.646751899
Short name T50
Test name
Test status
Simulation time 17979144213 ps
CPU time 960.89 seconds
Started Mar 28 01:17:22 PM PDT 24
Finished Mar 28 01:33:24 PM PDT 24
Peak memory 210396 kb
Host smart-56ea4d6d-4fdb-4f9a-9395-6046f9ddbfc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646751899 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.646751899
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.927262818
Short name T529
Test name
Test status
Simulation time 86530094 ps
CPU time 1.09 seconds
Started Mar 28 01:17:22 PM PDT 24
Finished Mar 28 01:17:24 PM PDT 24
Peak memory 198272 kb
Host smart-9f9df362-bcc5-43be-a101-8b3baafcd7c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927262818 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_hmac_vectors.927262818
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.2217184735
Short name T424
Test name
Test status
Simulation time 149514830958 ps
CPU time 506.06 seconds
Started Mar 28 01:17:22 PM PDT 24
Finished Mar 28 01:25:48 PM PDT 24
Peak memory 199996 kb
Host smart-e550ed95-1973-407a-aed9-458f3528cee3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217184735 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.2217184735
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.3382334127
Short name T566
Test name
Test status
Simulation time 6943125123 ps
CPU time 66.41 seconds
Started Mar 28 01:17:22 PM PDT 24
Finished Mar 28 01:18:29 PM PDT 24
Peak memory 200092 kb
Host smart-cafaf8ce-d5c0-4140-8aa2-a4d537765ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382334127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3382334127
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.3088207716
Short name T269
Test name
Test status
Simulation time 12542765 ps
CPU time 0.57 seconds
Started Mar 28 01:17:34 PM PDT 24
Finished Mar 28 01:17:35 PM PDT 24
Peak memory 195500 kb
Host smart-426855ae-d442-4545-ad23-b12eb5aa5f63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088207716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3088207716
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.783015541
Short name T322
Test name
Test status
Simulation time 1490282482 ps
CPU time 25.96 seconds
Started Mar 28 01:17:22 PM PDT 24
Finished Mar 28 01:17:48 PM PDT 24
Peak memory 200048 kb
Host smart-df1d22ef-6184-41bb-a31e-b8499895edb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=783015541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.783015541
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1476592192
Short name T199
Test name
Test status
Simulation time 2432655365 ps
CPU time 53.07 seconds
Started Mar 28 01:17:23 PM PDT 24
Finished Mar 28 01:18:17 PM PDT 24
Peak memory 200136 kb
Host smart-957641c0-4ee8-4814-aee9-1312f0af009f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476592192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1476592192
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.60768978
Short name T358
Test name
Test status
Simulation time 998124971 ps
CPU time 65.91 seconds
Started Mar 28 01:17:20 PM PDT 24
Finished Mar 28 01:18:26 PM PDT 24
Peak memory 200056 kb
Host smart-4208b0cd-9e61-43a3-8daa-cf73f20a0745
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=60768978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.60768978
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.4026763485
Short name T101
Test name
Test status
Simulation time 11144696081 ps
CPU time 76.43 seconds
Started Mar 28 01:17:21 PM PDT 24
Finished Mar 28 01:18:37 PM PDT 24
Peak memory 200148 kb
Host smart-46b1d29c-65cb-4b01-9dde-4e5d70070681
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026763485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.4026763485
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.2816958226
Short name T493
Test name
Test status
Simulation time 2459483227 ps
CPU time 9.63 seconds
Started Mar 28 01:17:21 PM PDT 24
Finished Mar 28 01:17:31 PM PDT 24
Peak memory 200036 kb
Host smart-4c8dd511-90aa-444e-bd2c-f75b613c80d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816958226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2816958226
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.2269641756
Short name T492
Test name
Test status
Simulation time 777370074 ps
CPU time 6.68 seconds
Started Mar 28 01:17:22 PM PDT 24
Finished Mar 28 01:17:29 PM PDT 24
Peak memory 200020 kb
Host smart-f8dc339a-4520-4bf3-84cf-ae3f446afaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269641756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2269641756
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1484691941
Short name T15
Test name
Test status
Simulation time 30155692089 ps
CPU time 1396.66 seconds
Started Mar 28 01:17:27 PM PDT 24
Finished Mar 28 01:40:43 PM PDT 24
Peak memory 248764 kb
Host smart-d7800960-41a8-4a33-bab9-e426ed694ff7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484691941 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1484691941
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.1454846737
Short name T495
Test name
Test status
Simulation time 268000502 ps
CPU time 1.07 seconds
Started Mar 28 01:17:22 PM PDT 24
Finished Mar 28 01:17:24 PM PDT 24
Peak memory 199512 kb
Host smart-694d3b45-b10f-410e-b05e-61ebf6e6f21d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454846737 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.1454846737
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.421483633
Short name T450
Test name
Test status
Simulation time 27259298484 ps
CPU time 486.69 seconds
Started Mar 28 01:17:22 PM PDT 24
Finished Mar 28 01:25:29 PM PDT 24
Peak memory 200124 kb
Host smart-55790a16-874c-4382-91de-6e91bd328699
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421483633 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.421483633
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1795454621
Short name T567
Test name
Test status
Simulation time 30346700630 ps
CPU time 36.56 seconds
Started Mar 28 01:17:22 PM PDT 24
Finished Mar 28 01:17:59 PM PDT 24
Peak memory 200156 kb
Host smart-21202802-b07e-4e54-af1a-d00cff61224d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795454621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1795454621
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/191.hmac_stress_all_with_rand_reset.2286692756
Short name T70
Test name
Test status
Simulation time 79027062165 ps
CPU time 1866.16 seconds
Started Mar 28 01:21:30 PM PDT 24
Finished Mar 28 01:52:36 PM PDT 24
Peak memory 238420 kb
Host smart-2732c6ec-a6c2-4049-baa9-f35eaa188b40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2286692756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.hmac_stress_all_with_rand_reset.2286692756
Directory /workspace/191.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1928569766
Short name T249
Test name
Test status
Simulation time 67508709 ps
CPU time 0.55 seconds
Started Mar 28 01:15:32 PM PDT 24
Finished Mar 28 01:15:33 PM PDT 24
Peak memory 195508 kb
Host smart-921b50a6-b246-45c5-9c12-e35e4debae7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928569766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1928569766
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.2898624307
Short name T451
Test name
Test status
Simulation time 1200980624 ps
CPU time 43.92 seconds
Started Mar 28 01:15:32 PM PDT 24
Finished Mar 28 01:16:16 PM PDT 24
Peak memory 208248 kb
Host smart-e14a7e9e-91d5-4cd5-911a-ed5394ec3c44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2898624307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.2898624307
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1682244240
Short name T201
Test name
Test status
Simulation time 11084003540 ps
CPU time 44.47 seconds
Started Mar 28 01:15:30 PM PDT 24
Finished Mar 28 01:16:15 PM PDT 24
Peak memory 200144 kb
Host smart-be344534-6f03-42dc-a3cc-ac1862744ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682244240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1682244240
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.377410767
Short name T433
Test name
Test status
Simulation time 2589609567 ps
CPU time 160.82 seconds
Started Mar 28 01:15:34 PM PDT 24
Finished Mar 28 01:18:15 PM PDT 24
Peak memory 200156 kb
Host smart-f281b772-575b-4f86-a21f-60aa08a25352
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=377410767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.377410767
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3233914946
Short name T164
Test name
Test status
Simulation time 52700866782 ps
CPU time 181.25 seconds
Started Mar 28 01:15:31 PM PDT 24
Finished Mar 28 01:18:32 PM PDT 24
Peak memory 200112 kb
Host smart-5ce89123-6351-4d79-9606-ffbe4e2e9f46
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233914946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3233914946
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.4208652972
Short name T245
Test name
Test status
Simulation time 8490803189 ps
CPU time 141.63 seconds
Started Mar 28 01:15:51 PM PDT 24
Finished Mar 28 01:18:13 PM PDT 24
Peak memory 200104 kb
Host smart-a1f95325-8e04-48bf-a0a6-90dece2f31d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208652972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.4208652972
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2939739707
Short name T34
Test name
Test status
Simulation time 79398442 ps
CPU time 0.82 seconds
Started Mar 28 01:15:31 PM PDT 24
Finished Mar 28 01:15:32 PM PDT 24
Peak memory 218116 kb
Host smart-ea739104-ba04-4bdd-a3e0-2104d00afa39
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939739707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2939739707
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.914726813
Short name T367
Test name
Test status
Simulation time 140489177 ps
CPU time 4.59 seconds
Started Mar 28 01:15:30 PM PDT 24
Finished Mar 28 01:15:34 PM PDT 24
Peak memory 200076 kb
Host smart-090a21de-ac9f-4141-b43c-8aa29a8eb73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914726813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.914726813
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3291855090
Short name T337
Test name
Test status
Simulation time 10846864880 ps
CPU time 582.81 seconds
Started Mar 28 01:15:35 PM PDT 24
Finished Mar 28 01:25:18 PM PDT 24
Peak memory 200116 kb
Host smart-4aa592ac-1b19-4e61-8c83-edc2dd038a06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291855090 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3291855090
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.3390967582
Short name T518
Test name
Test status
Simulation time 92955940 ps
CPU time 0.97 seconds
Started Mar 28 01:15:32 PM PDT 24
Finished Mar 28 01:15:33 PM PDT 24
Peak memory 199552 kb
Host smart-95e5dc9f-9481-41b3-81e0-59875fa4016e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390967582 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.3390967582
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.135687845
Short name T305
Test name
Test status
Simulation time 14786339101 ps
CPU time 452.6 seconds
Started Mar 28 01:15:31 PM PDT 24
Finished Mar 28 01:23:04 PM PDT 24
Peak memory 200136 kb
Host smart-924ef2c1-0682-4e82-b7f5-1cc2b0b9e379
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135687845 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.135687845
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.1446649329
Short name T419
Test name
Test status
Simulation time 263258285 ps
CPU time 7.76 seconds
Started Mar 28 01:15:31 PM PDT 24
Finished Mar 28 01:15:39 PM PDT 24
Peak memory 200040 kb
Host smart-6601ecd6-9602-4fde-acde-b401baf6bd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446649329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1446649329
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1279880892
Short name T159
Test name
Test status
Simulation time 16758058 ps
CPU time 0.62 seconds
Started Mar 28 01:17:34 PM PDT 24
Finished Mar 28 01:17:35 PM PDT 24
Peak memory 195628 kb
Host smart-1ecfd29a-d264-4430-ba01-a1c90650232f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279880892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1279880892
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1667712143
Short name T584
Test name
Test status
Simulation time 356143220 ps
CPU time 3.7 seconds
Started Mar 28 01:17:33 PM PDT 24
Finished Mar 28 01:17:37 PM PDT 24
Peak memory 207752 kb
Host smart-f18b998b-af62-404d-8d4e-498ff9c54f03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1667712143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1667712143
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.309960878
Short name T422
Test name
Test status
Simulation time 714667835 ps
CPU time 15.09 seconds
Started Mar 28 01:17:30 PM PDT 24
Finished Mar 28 01:17:46 PM PDT 24
Peak memory 200076 kb
Host smart-78b357f9-895e-46e9-ab89-91e9163b84dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309960878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.309960878
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.401866655
Short name T217
Test name
Test status
Simulation time 215852014 ps
CPU time 12.59 seconds
Started Mar 28 01:17:35 PM PDT 24
Finished Mar 28 01:17:47 PM PDT 24
Peak memory 199940 kb
Host smart-f37ea93c-b067-47c6-b0e8-32dcb53aab17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=401866655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.401866655
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.2733594456
Short name T418
Test name
Test status
Simulation time 8830506963 ps
CPU time 158.79 seconds
Started Mar 28 01:17:33 PM PDT 24
Finished Mar 28 01:20:12 PM PDT 24
Peak memory 200168 kb
Host smart-f55a8573-cf5b-4bf7-abaa-b55abbe11a89
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733594456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2733594456
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.3114462528
Short name T345
Test name
Test status
Simulation time 7349880112 ps
CPU time 114.1 seconds
Started Mar 28 01:17:34 PM PDT 24
Finished Mar 28 01:19:28 PM PDT 24
Peak memory 200136 kb
Host smart-680b8ab5-caaf-4efc-a199-1f755daca9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114462528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.3114462528
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.2723384318
Short name T28
Test name
Test status
Simulation time 506800141 ps
CPU time 4.09 seconds
Started Mar 28 01:17:39 PM PDT 24
Finished Mar 28 01:17:43 PM PDT 24
Peak memory 199916 kb
Host smart-060ab58f-a06f-4eaa-bf39-5746597a1995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723384318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2723384318
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.633821229
Short name T449
Test name
Test status
Simulation time 19278182080 ps
CPU time 1032.41 seconds
Started Mar 28 01:17:34 PM PDT 24
Finished Mar 28 01:34:46 PM PDT 24
Peak memory 230156 kb
Host smart-731a9f23-35cd-42bf-80b1-deb9ce3a8173
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633821229 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.633821229
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.4214461843
Short name T215
Test name
Test status
Simulation time 174353229 ps
CPU time 1.2 seconds
Started Mar 28 01:17:35 PM PDT 24
Finished Mar 28 01:17:36 PM PDT 24
Peak memory 199916 kb
Host smart-0f24e43d-333a-486d-990d-8270f8ee10f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214461843 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.4214461843
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.2638323384
Short name T133
Test name
Test status
Simulation time 54538668818 ps
CPU time 459.35 seconds
Started Mar 28 01:17:32 PM PDT 24
Finished Mar 28 01:25:13 PM PDT 24
Peak memory 200036 kb
Host smart-e3071027-9207-4f8d-b6f2-bf933c629120
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638323384 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.2638323384
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.2019422909
Short name T138
Test name
Test status
Simulation time 3959261874 ps
CPU time 89.03 seconds
Started Mar 28 01:17:31 PM PDT 24
Finished Mar 28 01:19:00 PM PDT 24
Peak memory 200144 kb
Host smart-c5acd7b9-f609-42ed-96d7-671acf6e4de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019422909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2019422909
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1346888214
Short name T282
Test name
Test status
Simulation time 18562053 ps
CPU time 0.58 seconds
Started Mar 28 01:17:30 PM PDT 24
Finished Mar 28 01:17:31 PM PDT 24
Peak memory 195572 kb
Host smart-6748b5e5-04db-40cd-b51c-3dd4541a6d13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346888214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1346888214
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1794186682
Short name T329
Test name
Test status
Simulation time 112682038 ps
CPU time 3.73 seconds
Started Mar 28 01:17:34 PM PDT 24
Finished Mar 28 01:17:38 PM PDT 24
Peak memory 200068 kb
Host smart-18788cd6-50cb-445d-b62a-d8e288aa2ea6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1794186682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1794186682
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3687458443
Short name T592
Test name
Test status
Simulation time 139521672 ps
CPU time 2.39 seconds
Started Mar 28 01:17:35 PM PDT 24
Finished Mar 28 01:17:37 PM PDT 24
Peak memory 199944 kb
Host smart-e6dd7a0c-f772-4a40-a8f2-53d2f7fed7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687458443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3687458443
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.192881418
Short name T301
Test name
Test status
Simulation time 11394193877 ps
CPU time 128.16 seconds
Started Mar 28 01:17:34 PM PDT 24
Finished Mar 28 01:19:42 PM PDT 24
Peak memory 200164 kb
Host smart-bb907935-4932-4680-8ea1-ba064ea8aa3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=192881418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.192881418
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.940609334
Short name T350
Test name
Test status
Simulation time 2311479411 ps
CPU time 135.27 seconds
Started Mar 28 01:17:40 PM PDT 24
Finished Mar 28 01:19:55 PM PDT 24
Peak memory 200112 kb
Host smart-8267c796-eec3-4787-9f51-c323ba82f77c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940609334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.940609334
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1484986558
Short name T587
Test name
Test status
Simulation time 1088277365 ps
CPU time 11.42 seconds
Started Mar 28 01:17:39 PM PDT 24
Finished Mar 28 01:17:51 PM PDT 24
Peak memory 199884 kb
Host smart-442c2c30-7079-4583-8e6d-4358fd69e274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484986558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1484986558
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2643823015
Short name T210
Test name
Test status
Simulation time 201970888 ps
CPU time 3.32 seconds
Started Mar 28 01:17:35 PM PDT 24
Finished Mar 28 01:17:38 PM PDT 24
Peak memory 200136 kb
Host smart-4235a500-ee9a-43bd-ad06-5a45efaba5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643823015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2643823015
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2417241719
Short name T235
Test name
Test status
Simulation time 35706787668 ps
CPU time 268.49 seconds
Started Mar 28 01:17:30 PM PDT 24
Finished Mar 28 01:21:59 PM PDT 24
Peak memory 226744 kb
Host smart-5ab45c81-a72f-4321-86b2-711953918131
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417241719 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2417241719
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.3365487294
Short name T348
Test name
Test status
Simulation time 60267363 ps
CPU time 1.15 seconds
Started Mar 28 01:17:33 PM PDT 24
Finished Mar 28 01:17:34 PM PDT 24
Peak memory 199904 kb
Host smart-7eb94b81-567b-448f-8002-ebce24bf10de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365487294 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.3365487294
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.3292129284
Short name T276
Test name
Test status
Simulation time 15101157703 ps
CPU time 422.71 seconds
Started Mar 28 01:17:40 PM PDT 24
Finished Mar 28 01:24:43 PM PDT 24
Peak memory 200060 kb
Host smart-5a87bfb6-1a8c-4098-ac8f-d36d23900118
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292129284 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.3292129284
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2150042588
Short name T412
Test name
Test status
Simulation time 8878162276 ps
CPU time 64.54 seconds
Started Mar 28 01:17:34 PM PDT 24
Finished Mar 28 01:18:39 PM PDT 24
Peak memory 200212 kb
Host smart-e86f8114-d547-48bc-80ce-f23f3391b197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150042588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2150042588
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.2944436714
Short name T481
Test name
Test status
Simulation time 40707648 ps
CPU time 0.58 seconds
Started Mar 28 01:17:31 PM PDT 24
Finished Mar 28 01:17:32 PM PDT 24
Peak memory 195716 kb
Host smart-cd1723ef-801e-4ad2-982d-dcfcae7aba63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944436714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2944436714
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.78326066
Short name T191
Test name
Test status
Simulation time 3006176877 ps
CPU time 25.6 seconds
Started Mar 28 01:17:33 PM PDT 24
Finished Mar 28 01:17:59 PM PDT 24
Peak memory 208440 kb
Host smart-4e588607-bc11-4548-9cf5-1e4864d151a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=78326066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.78326066
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.3053055516
Short name T166
Test name
Test status
Simulation time 280683494 ps
CPU time 14.19 seconds
Started Mar 28 01:17:39 PM PDT 24
Finished Mar 28 01:17:54 PM PDT 24
Peak memory 199892 kb
Host smart-28c7ee0b-4169-4c5b-955f-77824f710c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053055516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.3053055516
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3079221158
Short name T362
Test name
Test status
Simulation time 2994160147 ps
CPU time 44.5 seconds
Started Mar 28 01:17:39 PM PDT 24
Finished Mar 28 01:18:24 PM PDT 24
Peak memory 199976 kb
Host smart-be003758-7dae-4506-acab-a7e0cee7ebbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3079221158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3079221158
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.4210817815
Short name T360
Test name
Test status
Simulation time 395864207 ps
CPU time 22.29 seconds
Started Mar 28 01:17:33 PM PDT 24
Finished Mar 28 01:17:56 PM PDT 24
Peak memory 199564 kb
Host smart-ef42c081-fb62-4f93-83ce-df9584298b13
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210817815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.4210817815
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3703078752
Short name T488
Test name
Test status
Simulation time 10273182802 ps
CPU time 150.15 seconds
Started Mar 28 01:17:40 PM PDT 24
Finished Mar 28 01:20:10 PM PDT 24
Peak memory 200116 kb
Host smart-d091b8b9-68a6-443d-ae17-222d6703e6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703078752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3703078752
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.898978538
Short name T460
Test name
Test status
Simulation time 570750271 ps
CPU time 4.22 seconds
Started Mar 28 01:17:33 PM PDT 24
Finished Mar 28 01:17:37 PM PDT 24
Peak memory 200064 kb
Host smart-c81af939-a8c1-467c-88bb-753ab5b32f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898978538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.898978538
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.1137898887
Short name T590
Test name
Test status
Simulation time 12011558714 ps
CPU time 151.8 seconds
Started Mar 28 01:17:34 PM PDT 24
Finished Mar 28 01:20:06 PM PDT 24
Peak memory 200176 kb
Host smart-bc316577-06e9-45c7-8a94-271a5635a1a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137898887 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1137898887
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.1218957026
Short name T524
Test name
Test status
Simulation time 50054376 ps
CPU time 1.29 seconds
Started Mar 28 01:17:31 PM PDT 24
Finished Mar 28 01:17:33 PM PDT 24
Peak memory 199952 kb
Host smart-39837d7a-bfde-4678-9309-7aca466d1961
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218957026 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.1218957026
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.1458058823
Short name T148
Test name
Test status
Simulation time 146654181234 ps
CPU time 486.28 seconds
Started Mar 28 01:17:40 PM PDT 24
Finished Mar 28 01:25:46 PM PDT 24
Peak memory 200028 kb
Host smart-06442ec4-ffe3-42f6-9a89-7cd0e0a7985a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458058823 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.1458058823
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2525165650
Short name T172
Test name
Test status
Simulation time 4865442145 ps
CPU time 71.32 seconds
Started Mar 28 01:17:32 PM PDT 24
Finished Mar 28 01:18:44 PM PDT 24
Peak memory 200172 kb
Host smart-262f4f61-3c18-471d-a92f-88f8b640cdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525165650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2525165650
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2087572623
Short name T511
Test name
Test status
Simulation time 21835511 ps
CPU time 0.61 seconds
Started Mar 28 01:17:45 PM PDT 24
Finished Mar 28 01:17:46 PM PDT 24
Peak memory 195700 kb
Host smart-288f4a52-acd7-4b55-9982-800bbc2bd51b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087572623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2087572623
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1063728552
Short name T268
Test name
Test status
Simulation time 176387653 ps
CPU time 3.7 seconds
Started Mar 28 01:17:39 PM PDT 24
Finished Mar 28 01:17:43 PM PDT 24
Peak memory 199912 kb
Host smart-0c011eed-163c-461f-b24d-118d43e14f81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1063728552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1063728552
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.2089037827
Short name T165
Test name
Test status
Simulation time 769698305 ps
CPU time 37.1 seconds
Started Mar 28 01:17:33 PM PDT 24
Finished Mar 28 01:18:10 PM PDT 24
Peak memory 200064 kb
Host smart-c5278e4f-a0f0-46a0-a73a-af7a7ec62d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089037827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2089037827
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1485156104
Short name T228
Test name
Test status
Simulation time 3998156868 ps
CPU time 63.6 seconds
Started Mar 28 01:17:33 PM PDT 24
Finished Mar 28 01:18:37 PM PDT 24
Peak memory 200136 kb
Host smart-8825acca-23b0-47b1-ba5f-176f7159ad82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1485156104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1485156104
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2974593967
Short name T408
Test name
Test status
Simulation time 5830460062 ps
CPU time 82.4 seconds
Started Mar 28 01:17:49 PM PDT 24
Finished Mar 28 01:19:11 PM PDT 24
Peak memory 200148 kb
Host smart-76eabbf5-87e3-4bda-bd20-4d6831d3f4e1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974593967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2974593967
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2998367668
Short name T231
Test name
Test status
Simulation time 1389463544 ps
CPU time 14.72 seconds
Started Mar 28 01:17:34 PM PDT 24
Finished Mar 28 01:17:49 PM PDT 24
Peak memory 200076 kb
Host smart-606131c3-5aaa-402a-90ef-1b2d5dae7553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998367668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2998367668
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.755952851
Short name T77
Test name
Test status
Simulation time 259225028 ps
CPU time 2.32 seconds
Started Mar 28 01:17:39 PM PDT 24
Finished Mar 28 01:17:42 PM PDT 24
Peak memory 200052 kb
Host smart-f6f6232c-52bd-4f06-81ba-0cbd27e38c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755952851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.755952851
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3734824596
Short name T432
Test name
Test status
Simulation time 26550661934 ps
CPU time 949.37 seconds
Started Mar 28 01:17:48 PM PDT 24
Finished Mar 28 01:33:37 PM PDT 24
Peak memory 216368 kb
Host smart-f3b5799c-477c-4068-adb0-a6b5e09369a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734824596 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3734824596
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.2977410182
Short name T447
Test name
Test status
Simulation time 242459702 ps
CPU time 1.31 seconds
Started Mar 28 01:17:45 PM PDT 24
Finished Mar 28 01:17:47 PM PDT 24
Peak memory 199868 kb
Host smart-a7676231-5090-44e3-a99c-6a9947edc447
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977410182 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.2977410182
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.3550532739
Short name T593
Test name
Test status
Simulation time 84835302098 ps
CPU time 574.88 seconds
Started Mar 28 01:17:47 PM PDT 24
Finished Mar 28 01:27:22 PM PDT 24
Peak memory 200040 kb
Host smart-11cfc04e-15fd-4119-ac0a-6779452128fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550532739 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.3550532739
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3896484722
Short name T205
Test name
Test status
Simulation time 2614010860 ps
CPU time 45.24 seconds
Started Mar 28 01:17:50 PM PDT 24
Finished Mar 28 01:18:36 PM PDT 24
Peak memory 200056 kb
Host smart-0855540a-0245-4359-9381-7504627e84ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896484722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3896484722
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.4241183314
Short name T23
Test name
Test status
Simulation time 29778995 ps
CPU time 0.56 seconds
Started Mar 28 01:17:46 PM PDT 24
Finished Mar 28 01:17:47 PM PDT 24
Peak memory 195508 kb
Host smart-dc8d257b-d98a-4d04-92dd-54f6e35241c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241183314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.4241183314
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1358704966
Short name T359
Test name
Test status
Simulation time 2960474493 ps
CPU time 19.15 seconds
Started Mar 28 01:17:46 PM PDT 24
Finished Mar 28 01:18:05 PM PDT 24
Peak memory 208328 kb
Host smart-a6fb7247-13bb-417f-9bbb-2da7b36d0a4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1358704966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1358704966
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2687111305
Short name T96
Test name
Test status
Simulation time 1374155582 ps
CPU time 55.3 seconds
Started Mar 28 01:17:47 PM PDT 24
Finished Mar 28 01:18:42 PM PDT 24
Peak memory 199996 kb
Host smart-fdf8b1cb-21e3-4222-b792-f8e1bd411f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687111305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2687111305
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1415015601
Short name T265
Test name
Test status
Simulation time 870349574 ps
CPU time 48.29 seconds
Started Mar 28 01:17:47 PM PDT 24
Finished Mar 28 01:18:35 PM PDT 24
Peak memory 199996 kb
Host smart-779932e8-e2ae-4596-b512-748b51783bda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1415015601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1415015601
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.805597544
Short name T576
Test name
Test status
Simulation time 20871929644 ps
CPU time 79.8 seconds
Started Mar 28 01:17:46 PM PDT 24
Finished Mar 28 01:19:06 PM PDT 24
Peak memory 200100 kb
Host smart-6dc6a60a-50e2-40ca-88b2-fa081865bb76
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805597544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.805597544
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.512754797
Short name T379
Test name
Test status
Simulation time 7921839893 ps
CPU time 59.63 seconds
Started Mar 28 01:17:47 PM PDT 24
Finished Mar 28 01:18:47 PM PDT 24
Peak memory 200164 kb
Host smart-5cc70846-760d-4d74-9a7b-d50d14b48e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512754797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.512754797
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.3506430322
Short name T442
Test name
Test status
Simulation time 308965923 ps
CPU time 1.37 seconds
Started Mar 28 01:17:48 PM PDT 24
Finished Mar 28 01:17:49 PM PDT 24
Peak memory 200076 kb
Host smart-f8fef110-416a-479a-9ba0-b4929e44c1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506430322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3506430322
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.4013976832
Short name T254
Test name
Test status
Simulation time 88006499049 ps
CPU time 165.46 seconds
Started Mar 28 01:17:46 PM PDT 24
Finished Mar 28 01:20:32 PM PDT 24
Peak memory 242536 kb
Host smart-0fdd1d0e-4def-4f56-a2a7-308bf8589bf3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013976832 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.4013976832
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.3434976040
Short name T430
Test name
Test status
Simulation time 55099822 ps
CPU time 1.05 seconds
Started Mar 28 01:17:47 PM PDT 24
Finished Mar 28 01:17:48 PM PDT 24
Peak memory 199348 kb
Host smart-73573172-b94f-49c6-a1d4-5bd3eba688c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434976040 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.3434976040
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.3229105166
Short name T72
Test name
Test status
Simulation time 294017525533 ps
CPU time 486.59 seconds
Started Mar 28 01:17:53 PM PDT 24
Finished Mar 28 01:26:00 PM PDT 24
Peak memory 200064 kb
Host smart-c980135d-9427-433d-8d35-b9013221bd67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229105166 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.3229105166
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3519626824
Short name T171
Test name
Test status
Simulation time 11349684983 ps
CPU time 101.89 seconds
Started Mar 28 01:17:47 PM PDT 24
Finished Mar 28 01:19:29 PM PDT 24
Peak memory 200152 kb
Host smart-5453c11f-b5f9-4380-98d6-cba7a5156a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519626824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3519626824
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.1409209596
Short name T143
Test name
Test status
Simulation time 16638267 ps
CPU time 0.63 seconds
Started Mar 28 01:18:05 PM PDT 24
Finished Mar 28 01:18:06 PM PDT 24
Peak memory 195584 kb
Host smart-858afedd-b5d4-4054-93f6-0c636aff464a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409209596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1409209596
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.2363303324
Short name T573
Test name
Test status
Simulation time 446806123 ps
CPU time 3.98 seconds
Started Mar 28 01:17:52 PM PDT 24
Finished Mar 28 01:17:56 PM PDT 24
Peak memory 208116 kb
Host smart-6c833bad-5dfc-47b9-aa7f-3755d0812965
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2363303324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2363303324
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3297717116
Short name T209
Test name
Test status
Simulation time 2264346305 ps
CPU time 9 seconds
Started Mar 28 01:17:45 PM PDT 24
Finished Mar 28 01:17:54 PM PDT 24
Peak memory 200068 kb
Host smart-e742afe5-f125-4d3a-97a1-d84ccc6fcdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297717116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3297717116
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.2781225677
Short name T382
Test name
Test status
Simulation time 130593125 ps
CPU time 8.76 seconds
Started Mar 28 01:17:47 PM PDT 24
Finished Mar 28 01:17:56 PM PDT 24
Peak memory 200028 kb
Host smart-184cb12b-46c4-4ba5-8be1-08080fb917c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2781225677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2781225677
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2436664150
Short name T27
Test name
Test status
Simulation time 11318169898 ps
CPU time 228.98 seconds
Started Mar 28 01:17:46 PM PDT 24
Finished Mar 28 01:21:35 PM PDT 24
Peak memory 200148 kb
Host smart-276a2dda-0003-4814-8470-1f8a91ff6c51
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436664150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2436664150
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1217313290
Short name T280
Test name
Test status
Simulation time 478523146 ps
CPU time 5.56 seconds
Started Mar 28 01:17:46 PM PDT 24
Finished Mar 28 01:17:51 PM PDT 24
Peak memory 200012 kb
Host smart-dcb6352d-da70-4ffa-8caa-da4ad563808f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217313290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1217313290
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3158764033
Short name T300
Test name
Test status
Simulation time 154359373 ps
CPU time 4.94 seconds
Started Mar 28 01:17:47 PM PDT 24
Finished Mar 28 01:17:52 PM PDT 24
Peak memory 200016 kb
Host smart-2ffdc80d-5d67-4785-8621-dcf71c1a201b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158764033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3158764033
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2768243612
Short name T193
Test name
Test status
Simulation time 25998317797 ps
CPU time 1251.65 seconds
Started Mar 28 01:18:04 PM PDT 24
Finished Mar 28 01:38:56 PM PDT 24
Peak memory 200184 kb
Host smart-66bb63f2-49fc-4f02-8708-99b67ffad9d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768243612 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2768243612
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.3269057110
Short name T291
Test name
Test status
Simulation time 136692280 ps
CPU time 1.05 seconds
Started Mar 28 01:18:03 PM PDT 24
Finished Mar 28 01:18:06 PM PDT 24
Peak memory 199420 kb
Host smart-f5798005-5e2f-476b-b676-5a3a8847a59e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269057110 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.3269057110
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.2717518376
Short name T292
Test name
Test status
Simulation time 30512366066 ps
CPU time 428.46 seconds
Started Mar 28 01:17:47 PM PDT 24
Finished Mar 28 01:24:55 PM PDT 24
Peak memory 200092 kb
Host smart-24b7860f-387c-49fc-a34f-baba180acd93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717518376 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.2717518376
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.56774822
Short name T431
Test name
Test status
Simulation time 780894524 ps
CPU time 16.49 seconds
Started Mar 28 01:17:52 PM PDT 24
Finished Mar 28 01:18:09 PM PDT 24
Peak memory 199908 kb
Host smart-4a5c48b7-2cde-4791-8e1b-b9e22ce516fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56774822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.56774822
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1297147253
Short name T392
Test name
Test status
Simulation time 42613364 ps
CPU time 0.6 seconds
Started Mar 28 01:18:05 PM PDT 24
Finished Mar 28 01:18:06 PM PDT 24
Peak memory 195656 kb
Host smart-d4297b61-6a68-4a37-8656-cb3bba69c9cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297147253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1297147253
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.611221431
Short name T446
Test name
Test status
Simulation time 687855219 ps
CPU time 25.22 seconds
Started Mar 28 01:18:04 PM PDT 24
Finished Mar 28 01:18:30 PM PDT 24
Peak memory 216392 kb
Host smart-6924bead-3916-4d8b-ba21-fbb03e3669e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=611221431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.611221431
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.211381107
Short name T307
Test name
Test status
Simulation time 13547207533 ps
CPU time 39.81 seconds
Started Mar 28 01:18:02 PM PDT 24
Finished Mar 28 01:18:44 PM PDT 24
Peak memory 200156 kb
Host smart-6b6e9729-2e45-402f-be28-7926526391b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211381107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.211381107
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1522647960
Short name T223
Test name
Test status
Simulation time 6181189392 ps
CPU time 100.57 seconds
Started Mar 28 01:18:05 PM PDT 24
Finished Mar 28 01:19:46 PM PDT 24
Peak memory 200100 kb
Host smart-4d024cfc-793a-4ff2-ad6d-53ae68fe1fb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1522647960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1522647960
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3597326608
Short name T251
Test name
Test status
Simulation time 24523282804 ps
CPU time 235.15 seconds
Started Mar 28 01:18:03 PM PDT 24
Finished Mar 28 01:22:00 PM PDT 24
Peak memory 200148 kb
Host smart-21197590-2b26-4a59-9a6e-ac28702ac91e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597326608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3597326608
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1030200995
Short name T309
Test name
Test status
Simulation time 10826746189 ps
CPU time 52.98 seconds
Started Mar 28 01:18:05 PM PDT 24
Finished Mar 28 01:18:58 PM PDT 24
Peak memory 200096 kb
Host smart-4576088d-8690-4f3c-b84a-ddca314fe2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030200995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1030200995
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.4228392409
Short name T515
Test name
Test status
Simulation time 352128455 ps
CPU time 1.94 seconds
Started Mar 28 01:18:04 PM PDT 24
Finished Mar 28 01:18:07 PM PDT 24
Peak memory 200080 kb
Host smart-7fe8e645-3dee-4ff8-8159-f2eda016b4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228392409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.4228392409
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.507138520
Short name T325
Test name
Test status
Simulation time 7304512964 ps
CPU time 433.21 seconds
Started Mar 28 01:18:04 PM PDT 24
Finished Mar 28 01:25:18 PM PDT 24
Peak memory 200056 kb
Host smart-9ef788f4-0adf-46a4-ab30-8f22875abab3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507138520 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.507138520
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.327291218
Short name T260
Test name
Test status
Simulation time 65531067 ps
CPU time 1.26 seconds
Started Mar 28 01:18:04 PM PDT 24
Finished Mar 28 01:18:06 PM PDT 24
Peak memory 200048 kb
Host smart-7048b446-46bd-413c-934d-09ebcaf3c0ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327291218 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_hmac_vectors.327291218
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.873871654
Short name T318
Test name
Test status
Simulation time 148455171089 ps
CPU time 422.09 seconds
Started Mar 28 01:18:06 PM PDT 24
Finished Mar 28 01:25:09 PM PDT 24
Peak memory 200132 kb
Host smart-95c0366d-486a-4b68-824d-e8425b61fe15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873871654 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.873871654
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.4123189559
Short name T391
Test name
Test status
Simulation time 11551293423 ps
CPU time 44.68 seconds
Started Mar 28 01:18:05 PM PDT 24
Finished Mar 28 01:18:50 PM PDT 24
Peak memory 200092 kb
Host smart-dec779d2-9ad9-4765-971e-29ccc16e7ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123189559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.4123189559
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1909344293
Short name T510
Test name
Test status
Simulation time 13818701 ps
CPU time 0.6 seconds
Started Mar 28 01:18:18 PM PDT 24
Finished Mar 28 01:18:19 PM PDT 24
Peak memory 195600 kb
Host smart-41550ee0-4fae-49b9-aaca-3fc59fed4aee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909344293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1909344293
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1019522950
Short name T444
Test name
Test status
Simulation time 1874788704 ps
CPU time 40.55 seconds
Started Mar 28 01:18:05 PM PDT 24
Finished Mar 28 01:18:46 PM PDT 24
Peak memory 211076 kb
Host smart-458c3e9d-fef8-42a6-8e0e-be522bbb23c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1019522950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1019522950
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.886754768
Short name T498
Test name
Test status
Simulation time 1127545346 ps
CPU time 28.31 seconds
Started Mar 28 01:18:04 PM PDT 24
Finished Mar 28 01:18:33 PM PDT 24
Peak memory 200080 kb
Host smart-0a431af3-acd9-41bf-962f-21f97036b4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886754768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.886754768
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1753263785
Short name T221
Test name
Test status
Simulation time 892911034 ps
CPU time 14.05 seconds
Started Mar 28 01:18:04 PM PDT 24
Finished Mar 28 01:18:19 PM PDT 24
Peak memory 200036 kb
Host smart-7e8bc8ef-3ec5-4ff7-9c4e-dff14f64f99c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1753263785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1753263785
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2635312303
Short name T407
Test name
Test status
Simulation time 15777229010 ps
CPU time 131.88 seconds
Started Mar 28 01:18:06 PM PDT 24
Finished Mar 28 01:20:18 PM PDT 24
Peak memory 200100 kb
Host smart-6d75a203-253c-4d31-aa04-b3a6b5886aec
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635312303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2635312303
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.721098233
Short name T89
Test name
Test status
Simulation time 4820159080 ps
CPU time 100.11 seconds
Started Mar 28 01:18:06 PM PDT 24
Finished Mar 28 01:19:48 PM PDT 24
Peak memory 200144 kb
Host smart-116487cf-afef-40f6-b67a-c8c22c49efd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721098233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.721098233
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2345746202
Short name T454
Test name
Test status
Simulation time 356293489 ps
CPU time 6 seconds
Started Mar 28 01:18:05 PM PDT 24
Finished Mar 28 01:18:11 PM PDT 24
Peak memory 200048 kb
Host smart-87976905-2d67-4cf9-aa34-a16050c373e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345746202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2345746202
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.563967821
Short name T578
Test name
Test status
Simulation time 808768125902 ps
CPU time 2633.78 seconds
Started Mar 28 01:18:23 PM PDT 24
Finished Mar 28 02:02:17 PM PDT 24
Peak memory 230420 kb
Host smart-30c51787-3f70-4930-8ac7-e08341897145
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563967821 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.563967821
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.2730229845
Short name T179
Test name
Test status
Simulation time 158779093 ps
CPU time 1.04 seconds
Started Mar 28 01:18:04 PM PDT 24
Finished Mar 28 01:18:06 PM PDT 24
Peak memory 199432 kb
Host smart-d972e8e5-ad1c-456d-8d74-3d2fd1ac3389
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730229845 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.2730229845
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.2338284485
Short name T393
Test name
Test status
Simulation time 32405681001 ps
CPU time 453.04 seconds
Started Mar 28 01:18:06 PM PDT 24
Finished Mar 28 01:25:39 PM PDT 24
Peak memory 200048 kb
Host smart-b5e56a21-4beb-4f53-8b25-457bbfbb036f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338284485 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.2338284485
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.2972438357
Short name T321
Test name
Test status
Simulation time 4582420871 ps
CPU time 91.86 seconds
Started Mar 28 01:18:04 PM PDT 24
Finished Mar 28 01:19:37 PM PDT 24
Peak memory 200032 kb
Host smart-83e495a1-a39f-495d-b757-6f9c3489eb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972438357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2972438357
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.3099145052
Short name T472
Test name
Test status
Simulation time 15631697 ps
CPU time 0.6 seconds
Started Mar 28 01:18:22 PM PDT 24
Finished Mar 28 01:18:23 PM PDT 24
Peak memory 195576 kb
Host smart-43c25cda-bb77-4f8f-9f9a-b84db9c94de6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099145052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.3099145052
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.616314583
Short name T151
Test name
Test status
Simulation time 427310198 ps
CPU time 14.88 seconds
Started Mar 28 01:18:22 PM PDT 24
Finished Mar 28 01:18:37 PM PDT 24
Peak memory 200036 kb
Host smart-4a228e19-3700-464a-811a-d4fcbf87214a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=616314583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.616314583
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.2606025086
Short name T467
Test name
Test status
Simulation time 1790238803 ps
CPU time 14.57 seconds
Started Mar 28 01:18:21 PM PDT 24
Finished Mar 28 01:18:36 PM PDT 24
Peak memory 200024 kb
Host smart-839982b7-fe0c-4ea6-a3e7-1b4bf1443516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606025086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2606025086
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.1379556292
Short name T572
Test name
Test status
Simulation time 514252733 ps
CPU time 32.81 seconds
Started Mar 28 01:18:22 PM PDT 24
Finished Mar 28 01:18:55 PM PDT 24
Peak memory 200072 kb
Host smart-e42a3856-6621-42cc-9e30-1278134271f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1379556292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1379556292
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_long_msg.3101731406
Short name T136
Test name
Test status
Simulation time 5570205960 ps
CPU time 55.45 seconds
Started Mar 28 01:18:21 PM PDT 24
Finished Mar 28 01:19:17 PM PDT 24
Peak memory 200132 kb
Host smart-a9e90578-49f5-4d25-95d2-d54e31be6cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101731406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3101731406
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.2772206426
Short name T443
Test name
Test status
Simulation time 305736073 ps
CPU time 1.46 seconds
Started Mar 28 01:18:23 PM PDT 24
Finished Mar 28 01:18:25 PM PDT 24
Peak memory 200072 kb
Host smart-39f9d87c-43cc-488a-85ff-30bbba2c1123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772206426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2772206426
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.3280813662
Short name T453
Test name
Test status
Simulation time 78588083 ps
CPU time 1.35 seconds
Started Mar 28 01:18:24 PM PDT 24
Finished Mar 28 01:18:25 PM PDT 24
Peak memory 200068 kb
Host smart-8414c771-d2a5-4cf6-a5ad-bb21e83eb112
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280813662 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.3280813662
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.3655046059
Short name T298
Test name
Test status
Simulation time 8182823617 ps
CPU time 463.53 seconds
Started Mar 28 01:18:20 PM PDT 24
Finished Mar 28 01:26:04 PM PDT 24
Peak memory 200080 kb
Host smart-a319fc4f-a553-4ce5-8f8b-2e826f193031
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655046059 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.3655046059
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.4259980572
Short name T339
Test name
Test status
Simulation time 1551353836 ps
CPU time 77.92 seconds
Started Mar 28 01:18:21 PM PDT 24
Finished Mar 28 01:19:39 PM PDT 24
Peak memory 200100 kb
Host smart-1141a24a-3ef9-45a5-b039-2a6661f371fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259980572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.4259980572
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.670356559
Short name T400
Test name
Test status
Simulation time 21658655 ps
CPU time 0.6 seconds
Started Mar 28 01:18:22 PM PDT 24
Finished Mar 28 01:18:23 PM PDT 24
Peak memory 195312 kb
Host smart-6d5bc55a-b0da-416a-ae79-5c36f3b91d0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670356559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.670356559
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2070373447
Short name T233
Test name
Test status
Simulation time 264690779 ps
CPU time 11.82 seconds
Started Mar 28 01:18:21 PM PDT 24
Finished Mar 28 01:18:33 PM PDT 24
Peak memory 216460 kb
Host smart-77db267c-da5a-4375-b7a4-f9ed323e9050
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2070373447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2070373447
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2547715668
Short name T134
Test name
Test status
Simulation time 313744711 ps
CPU time 15.96 seconds
Started Mar 28 01:18:21 PM PDT 24
Finished Mar 28 01:18:37 PM PDT 24
Peak memory 200148 kb
Host smart-35ccd7f5-d739-4cc6-9ca2-4c6f31683263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547715668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2547715668
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.488965253
Short name T190
Test name
Test status
Simulation time 8706068960 ps
CPU time 105.43 seconds
Started Mar 28 01:18:21 PM PDT 24
Finished Mar 28 01:20:06 PM PDT 24
Peak memory 200144 kb
Host smart-db4fcb22-6e33-45ab-ba3c-c65acccabab4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=488965253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.488965253
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.3440999866
Short name T377
Test name
Test status
Simulation time 21508996232 ps
CPU time 146.33 seconds
Started Mar 28 01:18:23 PM PDT 24
Finished Mar 28 01:20:49 PM PDT 24
Peak memory 200148 kb
Host smart-28d9edbe-9406-4730-ad54-ceafbcf2bd49
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440999866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.3440999866
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.3030287261
Short name T234
Test name
Test status
Simulation time 17434512636 ps
CPU time 115.2 seconds
Started Mar 28 01:18:21 PM PDT 24
Finished Mar 28 01:20:17 PM PDT 24
Peak memory 199976 kb
Host smart-9d21c991-f9e2-4d14-86d0-8b3edac41ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030287261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3030287261
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.1842620791
Short name T466
Test name
Test status
Simulation time 150184550 ps
CPU time 4.45 seconds
Started Mar 28 01:18:21 PM PDT 24
Finished Mar 28 01:18:26 PM PDT 24
Peak memory 199932 kb
Host smart-72613410-198a-4c62-a7cd-f306940f0793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842620791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1842620791
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2709040915
Short name T24
Test name
Test status
Simulation time 22447131617 ps
CPU time 736.47 seconds
Started Mar 28 01:18:20 PM PDT 24
Finished Mar 28 01:30:37 PM PDT 24
Peak memory 229716 kb
Host smart-d51fecd4-af69-4946-860c-93805b9cb78e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709040915 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2709040915
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.729029087
Short name T398
Test name
Test status
Simulation time 112920579 ps
CPU time 1.25 seconds
Started Mar 28 01:18:22 PM PDT 24
Finished Mar 28 01:18:23 PM PDT 24
Peak memory 199772 kb
Host smart-0c4f3e28-7376-46fa-9233-e1088f19badf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729029087 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_hmac_vectors.729029087
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.1987776944
Short name T531
Test name
Test status
Simulation time 53273675246 ps
CPU time 479.09 seconds
Started Mar 28 01:18:23 PM PDT 24
Finished Mar 28 01:26:22 PM PDT 24
Peak memory 200084 kb
Host smart-77ba0e85-0936-4c03-85d9-b8199c22eaf6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987776944 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.1987776944
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2293878309
Short name T313
Test name
Test status
Simulation time 20474003607 ps
CPU time 113.82 seconds
Started Mar 28 01:18:21 PM PDT 24
Finished Mar 28 01:20:15 PM PDT 24
Peak memory 200144 kb
Host smart-d557b829-9848-4a5e-94a2-afc8049aede4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293878309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2293878309
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.124279027
Short name T428
Test name
Test status
Simulation time 15010998 ps
CPU time 0.6 seconds
Started Mar 28 01:15:34 PM PDT 24
Finished Mar 28 01:15:35 PM PDT 24
Peak memory 195624 kb
Host smart-174dac0d-44ab-4182-841b-5a959ad59a47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124279027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.124279027
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3538812215
Short name T544
Test name
Test status
Simulation time 1992621796 ps
CPU time 14.2 seconds
Started Mar 28 01:15:34 PM PDT 24
Finished Mar 28 01:15:48 PM PDT 24
Peak memory 199924 kb
Host smart-69bfebdd-ba27-4c74-9d31-2d6cb61dbe4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3538812215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3538812215
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.614997969
Short name T302
Test name
Test status
Simulation time 5179013652 ps
CPU time 67.58 seconds
Started Mar 28 01:15:30 PM PDT 24
Finished Mar 28 01:16:38 PM PDT 24
Peak memory 200164 kb
Host smart-07ba077a-8aea-40a9-8523-77ee2e0ed9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614997969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.614997969
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1106830870
Short name T153
Test name
Test status
Simulation time 787446591 ps
CPU time 24.91 seconds
Started Mar 28 01:15:32 PM PDT 24
Finished Mar 28 01:15:57 PM PDT 24
Peak memory 200076 kb
Host smart-042195ff-7e79-452a-9b17-06a4509c04d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1106830870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1106830870
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.558271787
Short name T196
Test name
Test status
Simulation time 9036022297 ps
CPU time 116.59 seconds
Started Mar 28 01:15:31 PM PDT 24
Finished Mar 28 01:17:28 PM PDT 24
Peak memory 200096 kb
Host smart-04ebca9d-01f4-4086-9056-dba6c6296c83
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558271787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.558271787
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2300939631
Short name T565
Test name
Test status
Simulation time 22140304132 ps
CPU time 83.77 seconds
Started Mar 28 01:15:34 PM PDT 24
Finished Mar 28 01:16:58 PM PDT 24
Peak memory 200128 kb
Host smart-fb951b2d-9bf9-4266-9463-de3d41df96f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300939631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2300939631
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.390596839
Short name T30
Test name
Test status
Simulation time 111639538 ps
CPU time 0.93 seconds
Started Mar 28 01:15:32 PM PDT 24
Finished Mar 28 01:15:33 PM PDT 24
Peak memory 218268 kb
Host smart-16302f90-59cb-45b5-9c14-a78c2d90f64a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390596839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.390596839
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3393622850
Short name T294
Test name
Test status
Simulation time 683394585 ps
CPU time 5.29 seconds
Started Mar 28 01:15:36 PM PDT 24
Finished Mar 28 01:15:41 PM PDT 24
Peak memory 200064 kb
Host smart-4c27987b-a0f9-4255-9b57-35e102a34866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393622850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3393622850
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.423954558
Short name T167
Test name
Test status
Simulation time 6601026951 ps
CPU time 107.8 seconds
Started Mar 28 01:15:31 PM PDT 24
Finished Mar 28 01:17:19 PM PDT 24
Peak memory 200148 kb
Host smart-2fd16b1f-fd44-496a-8e10-50997f5233ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423954558 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.423954558
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.1768374402
Short name T414
Test name
Test status
Simulation time 37164400249 ps
CPU time 1055.19 seconds
Started Mar 28 01:15:29 PM PDT 24
Finished Mar 28 01:33:05 PM PDT 24
Peak memory 238008 kb
Host smart-cbc14fba-146e-436d-8275-47b4cc95bdf3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1768374402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.1768374402
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.2645919590
Short name T429
Test name
Test status
Simulation time 71001697 ps
CPU time 1.3 seconds
Started Mar 28 01:15:35 PM PDT 24
Finished Mar 28 01:15:36 PM PDT 24
Peak memory 199784 kb
Host smart-e3ddc046-17e0-40b2-b79c-6183921d4aeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645919590 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.2645919590
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.3318765206
Short name T88
Test name
Test status
Simulation time 13693883363 ps
CPU time 434.85 seconds
Started Mar 28 01:15:34 PM PDT 24
Finished Mar 28 01:22:49 PM PDT 24
Peak memory 200104 kb
Host smart-a77b1b46-b999-439a-a9e1-d2d1c975bdfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318765206 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.3318765206
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.685281165
Short name T376
Test name
Test status
Simulation time 8786918210 ps
CPU time 50.86 seconds
Started Mar 28 01:15:30 PM PDT 24
Finished Mar 28 01:16:21 PM PDT 24
Peak memory 200072 kb
Host smart-4d2ad7d2-ab7a-4d7a-9753-26227dc5c78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685281165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.685281165
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.793955155
Short name T41
Test name
Test status
Simulation time 43892184 ps
CPU time 0.57 seconds
Started Mar 28 01:18:40 PM PDT 24
Finished Mar 28 01:18:40 PM PDT 24
Peak memory 195544 kb
Host smart-5b319a38-ce34-4c67-b92d-bda76e3f9d78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793955155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.793955155
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2059506861
Short name T560
Test name
Test status
Simulation time 1727668115 ps
CPU time 64.79 seconds
Started Mar 28 01:18:24 PM PDT 24
Finished Mar 28 01:19:30 PM PDT 24
Peak memory 225264 kb
Host smart-3e318120-58d0-48e3-95ea-429a247e2dc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2059506861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2059506861
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1128356124
Short name T295
Test name
Test status
Simulation time 3332645223 ps
CPU time 45.99 seconds
Started Mar 28 01:18:22 PM PDT 24
Finished Mar 28 01:19:09 PM PDT 24
Peak memory 200140 kb
Host smart-8f437df5-bdc6-429c-9b56-7dd7d606abe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128356124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1128356124
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.1020629182
Short name T288
Test name
Test status
Simulation time 4959293245 ps
CPU time 65.71 seconds
Started Mar 28 01:18:20 PM PDT 24
Finished Mar 28 01:19:26 PM PDT 24
Peak memory 200160 kb
Host smart-2e17daf8-b84f-498c-a9e5-ca08e1f3daa9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1020629182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1020629182
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.773271550
Short name T16
Test name
Test status
Simulation time 17803222482 ps
CPU time 134.3 seconds
Started Mar 28 01:18:25 PM PDT 24
Finished Mar 28 01:20:40 PM PDT 24
Peak memory 200024 kb
Host smart-2dab6d46-1679-4bb2-b180-bf7e18fee641
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773271550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.773271550
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1767776438
Short name T140
Test name
Test status
Simulation time 34064348229 ps
CPU time 73.86 seconds
Started Mar 28 01:18:21 PM PDT 24
Finished Mar 28 01:19:35 PM PDT 24
Peak memory 200104 kb
Host smart-98b25870-fdf2-4989-9f1c-cbaa22a2df7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767776438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1767776438
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.379836087
Short name T441
Test name
Test status
Simulation time 85312722 ps
CPU time 1.12 seconds
Started Mar 28 01:18:23 PM PDT 24
Finished Mar 28 01:18:24 PM PDT 24
Peak memory 200056 kb
Host smart-008583dc-3889-4519-a249-96fc565015d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379836087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.379836087
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1939616607
Short name T239
Test name
Test status
Simulation time 24243679518 ps
CPU time 426.97 seconds
Started Mar 28 01:18:44 PM PDT 24
Finished Mar 28 01:25:51 PM PDT 24
Peak memory 228688 kb
Host smart-928499bb-7e01-4a7b-978f-3a67665b42be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939616607 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1939616607
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.2546620203
Short name T319
Test name
Test status
Simulation time 92188082 ps
CPU time 1.01 seconds
Started Mar 28 01:18:23 PM PDT 24
Finished Mar 28 01:18:24 PM PDT 24
Peak memory 199460 kb
Host smart-25b36f66-56ef-4cda-8093-f1242e46e04e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546620203 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.2546620203
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.1964326175
Short name T266
Test name
Test status
Simulation time 9256319599 ps
CPU time 483.33 seconds
Started Mar 28 01:18:24 PM PDT 24
Finished Mar 28 01:26:27 PM PDT 24
Peak memory 200104 kb
Host smart-621ad866-0529-4d4c-92d1-e1869da36435
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964326175 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.1964326175
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.1367424437
Short name T100
Test name
Test status
Simulation time 166501106 ps
CPU time 8.91 seconds
Started Mar 28 01:18:25 PM PDT 24
Finished Mar 28 01:18:34 PM PDT 24
Peak memory 199988 kb
Host smart-81f6c97e-49c1-4d5e-960d-bde39c385ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367424437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.1367424437
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2663626377
Short name T35
Test name
Test status
Simulation time 19054627 ps
CPU time 0.61 seconds
Started Mar 28 01:18:41 PM PDT 24
Finished Mar 28 01:18:42 PM PDT 24
Peak memory 195620 kb
Host smart-eee03225-0e40-43b2-b271-b68f0c585700
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663626377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2663626377
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.4258188434
Short name T56
Test name
Test status
Simulation time 830249295 ps
CPU time 16.89 seconds
Started Mar 28 01:18:42 PM PDT 24
Finished Mar 28 01:18:59 PM PDT 24
Peak memory 229792 kb
Host smart-345a9859-a5ae-4c24-bbb0-281f51e27fc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4258188434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.4258188434
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.644748952
Short name T540
Test name
Test status
Simulation time 7980185511 ps
CPU time 41.91 seconds
Started Mar 28 01:18:41 PM PDT 24
Finished Mar 28 01:19:23 PM PDT 24
Peak memory 200172 kb
Host smart-5bd021e6-367c-4bc3-bed2-62040f6e187d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644748952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.644748952
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.128476389
Short name T427
Test name
Test status
Simulation time 8139429137 ps
CPU time 117.65 seconds
Started Mar 28 01:18:41 PM PDT 24
Finished Mar 28 01:20:38 PM PDT 24
Peak memory 200216 kb
Host smart-8c7522e9-8e6f-4db5-a292-37bd7818c328
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=128476389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.128476389
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.222663835
Short name T257
Test name
Test status
Simulation time 1689207660 ps
CPU time 21.18 seconds
Started Mar 28 01:18:41 PM PDT 24
Finished Mar 28 01:19:02 PM PDT 24
Peak memory 200072 kb
Host smart-308447e9-7aa7-4e30-bc51-8e5c5d8c1b4e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222663835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.222663835
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.4051737070
Short name T273
Test name
Test status
Simulation time 22414723915 ps
CPU time 89.77 seconds
Started Mar 28 01:18:42 PM PDT 24
Finished Mar 28 01:20:12 PM PDT 24
Peak memory 200180 kb
Host smart-0a40798e-e353-477c-bd5c-be2d8ef88676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051737070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.4051737070
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1083997810
Short name T543
Test name
Test status
Simulation time 26771494 ps
CPU time 0.85 seconds
Started Mar 28 01:18:39 PM PDT 24
Finished Mar 28 01:18:40 PM PDT 24
Peak memory 198436 kb
Host smart-aa4a69b0-6cbc-415d-aa21-95b0b509757a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083997810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1083997810
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.4128673897
Short name T397
Test name
Test status
Simulation time 118417107395 ps
CPU time 1567.28 seconds
Started Mar 28 01:18:41 PM PDT 24
Finished Mar 28 01:44:48 PM PDT 24
Peak memory 200140 kb
Host smart-ff8b8f81-f7de-4c1e-9232-6010b098c60e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128673897 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.4128673897
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.805501605
Short name T182
Test name
Test status
Simulation time 88434646 ps
CPU time 0.99 seconds
Started Mar 28 01:18:43 PM PDT 24
Finished Mar 28 01:18:44 PM PDT 24
Peak memory 198900 kb
Host smart-bf54a928-33d3-4de3-b837-414de6f2b8e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805501605 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_hmac_vectors.805501605
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.1824700898
Short name T207
Test name
Test status
Simulation time 129785711027 ps
CPU time 643.25 seconds
Started Mar 28 01:18:41 PM PDT 24
Finished Mar 28 01:29:24 PM PDT 24
Peak memory 200048 kb
Host smart-19ed6e4a-f08d-4d57-b51b-39154a44d3a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824700898 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.1824700898
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2135529084
Short name T436
Test name
Test status
Simulation time 1316421899 ps
CPU time 32.28 seconds
Started Mar 28 01:18:40 PM PDT 24
Finished Mar 28 01:19:13 PM PDT 24
Peak memory 200068 kb
Host smart-9576f714-0c42-49fb-8c7c-48cbb5c1f40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135529084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2135529084
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2845852333
Short name T502
Test name
Test status
Simulation time 10962477 ps
CPU time 0.59 seconds
Started Mar 28 01:18:41 PM PDT 24
Finished Mar 28 01:18:41 PM PDT 24
Peak memory 194412 kb
Host smart-6b8930f5-4373-4288-ab49-35cbcf3e5f8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845852333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2845852333
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3700212588
Short name T261
Test name
Test status
Simulation time 708952399 ps
CPU time 25.94 seconds
Started Mar 28 01:18:43 PM PDT 24
Finished Mar 28 01:19:09 PM PDT 24
Peak memory 231508 kb
Host smart-dc17b396-d9fa-4935-ac75-b3ed3eeeb4c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3700212588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3700212588
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.2272412558
Short name T537
Test name
Test status
Simulation time 7099426025 ps
CPU time 51.07 seconds
Started Mar 28 01:18:40 PM PDT 24
Finished Mar 28 01:19:31 PM PDT 24
Peak memory 200092 kb
Host smart-384d1201-9f4c-4430-9223-0c630ba2f4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272412558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2272412558
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.547682674
Short name T152
Test name
Test status
Simulation time 11480378177 ps
CPU time 143.05 seconds
Started Mar 28 01:18:44 PM PDT 24
Finished Mar 28 01:21:08 PM PDT 24
Peak memory 199404 kb
Host smart-4dc30785-1c34-4705-b225-52697939bbe9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=547682674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.547682674
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.4126474698
Short name T521
Test name
Test status
Simulation time 31267644560 ps
CPU time 193.33 seconds
Started Mar 28 01:18:40 PM PDT 24
Finished Mar 28 01:21:53 PM PDT 24
Peak memory 200164 kb
Host smart-7717a2dd-73d9-4e7e-a40c-0e9ea6506d3a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126474698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.4126474698
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2643207225
Short name T211
Test name
Test status
Simulation time 5510064819 ps
CPU time 41.35 seconds
Started Mar 28 01:18:40 PM PDT 24
Finished Mar 28 01:19:22 PM PDT 24
Peak memory 200068 kb
Host smart-80b0f476-9889-40f3-8bf6-8dac844abd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643207225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2643207225
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.720987534
Short name T579
Test name
Test status
Simulation time 797571463 ps
CPU time 6.02 seconds
Started Mar 28 01:18:39 PM PDT 24
Finished Mar 28 01:18:45 PM PDT 24
Peak memory 200004 kb
Host smart-86bab10c-142f-48d7-9e53-43b7a1f289db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720987534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.720987534
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.4027429407
Short name T198
Test name
Test status
Simulation time 41616000593 ps
CPU time 190.81 seconds
Started Mar 28 01:18:40 PM PDT 24
Finished Mar 28 01:21:51 PM PDT 24
Peak memory 241012 kb
Host smart-16af2759-88d5-4f1b-82d9-6c7d2ccbde1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027429407 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.4027429407
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.2011353725
Short name T559
Test name
Test status
Simulation time 542695526 ps
CPU time 1.07 seconds
Started Mar 28 01:18:44 PM PDT 24
Finished Mar 28 01:18:46 PM PDT 24
Peak memory 199888 kb
Host smart-5de7c763-c743-451a-9589-1569d3e6b189
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011353725 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.2011353725
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.3546872270
Short name T580
Test name
Test status
Simulation time 65530767988 ps
CPU time 535.32 seconds
Started Mar 28 01:18:41 PM PDT 24
Finished Mar 28 01:27:36 PM PDT 24
Peak memory 200108 kb
Host smart-6ce6ad19-9699-4d9e-8329-d2954f07178c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546872270 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.3546872270
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.199394236
Short name T504
Test name
Test status
Simulation time 18956840740 ps
CPU time 84.51 seconds
Started Mar 28 01:18:42 PM PDT 24
Finished Mar 28 01:20:06 PM PDT 24
Peak memory 200156 kb
Host smart-4cc5345b-4601-472e-aa22-38e138f4e586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199394236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.199394236
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2274432279
Short name T40
Test name
Test status
Simulation time 32036811 ps
CPU time 0.56 seconds
Started Mar 28 01:18:43 PM PDT 24
Finished Mar 28 01:18:44 PM PDT 24
Peak memory 194388 kb
Host smart-60b51cf6-f0d0-4c3f-9fcb-b26db4ef1a60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274432279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2274432279
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.2386201403
Short name T570
Test name
Test status
Simulation time 283972446 ps
CPU time 3.64 seconds
Started Mar 28 01:18:43 PM PDT 24
Finished Mar 28 01:18:47 PM PDT 24
Peak memory 199888 kb
Host smart-7b464dbb-56a4-4c15-8875-94772dabc7cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2386201403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2386201403
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3850304670
Short name T262
Test name
Test status
Simulation time 537863135 ps
CPU time 8.53 seconds
Started Mar 28 01:18:45 PM PDT 24
Finished Mar 28 01:18:53 PM PDT 24
Peak memory 200060 kb
Host smart-2bec9acb-46d1-47c1-b65a-c79a50b9b0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850304670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3850304670
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.3480831385
Short name T326
Test name
Test status
Simulation time 4759765058 ps
CPU time 130.3 seconds
Started Mar 28 01:18:40 PM PDT 24
Finished Mar 28 01:20:51 PM PDT 24
Peak memory 200052 kb
Host smart-13c9e83d-be05-4055-8eb4-c4fd459fef83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3480831385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3480831385
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.551495760
Short name T258
Test name
Test status
Simulation time 2805228680 ps
CPU time 33.72 seconds
Started Mar 28 01:18:42 PM PDT 24
Finished Mar 28 01:19:16 PM PDT 24
Peak memory 200148 kb
Host smart-3edd57f9-2baf-461c-b9ef-6809e1519660
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551495760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.551495760
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.4240764077
Short name T194
Test name
Test status
Simulation time 25810968243 ps
CPU time 129.35 seconds
Started Mar 28 01:18:41 PM PDT 24
Finished Mar 28 01:20:50 PM PDT 24
Peak memory 200220 kb
Host smart-d64643e0-a386-4114-b711-bd85c8b9d7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240764077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.4240764077
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3204110348
Short name T174
Test name
Test status
Simulation time 4081388197 ps
CPU time 7.64 seconds
Started Mar 28 01:18:43 PM PDT 24
Finished Mar 28 01:18:51 PM PDT 24
Peak memory 200052 kb
Host smart-4da0a38b-2344-4aa7-a63e-9eb9ceb53ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204110348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3204110348
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.299105158
Short name T381
Test name
Test status
Simulation time 8980404887 ps
CPU time 134 seconds
Started Mar 28 01:18:43 PM PDT 24
Finished Mar 28 01:20:57 PM PDT 24
Peak memory 200092 kb
Host smart-e530fd36-1557-4ac4-acdc-32be8d3c8af1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299105158 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.299105158
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.978236341
Short name T76
Test name
Test status
Simulation time 109631115 ps
CPU time 1.15 seconds
Started Mar 28 01:18:41 PM PDT 24
Finished Mar 28 01:18:42 PM PDT 24
Peak memory 199668 kb
Host smart-57d1dfc0-5f36-44ab-9de6-62d2dd3ba780
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978236341 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.hmac_test_hmac_vectors.978236341
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.3788102894
Short name T104
Test name
Test status
Simulation time 13016550066 ps
CPU time 444.37 seconds
Started Mar 28 01:18:40 PM PDT 24
Finished Mar 28 01:26:04 PM PDT 24
Peak memory 200032 kb
Host smart-83402a27-6414-4cbd-bf76-b0ec45f8b92a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788102894 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.3788102894
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.2325325548
Short name T364
Test name
Test status
Simulation time 314023598 ps
CPU time 17.89 seconds
Started Mar 28 01:18:41 PM PDT 24
Finished Mar 28 01:18:59 PM PDT 24
Peak memory 200064 kb
Host smart-0f61dd8e-d253-4ce8-9861-f5750d128e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325325548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2325325548
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3333836368
Short name T170
Test name
Test status
Simulation time 15629132 ps
CPU time 0.57 seconds
Started Mar 28 01:18:55 PM PDT 24
Finished Mar 28 01:18:56 PM PDT 24
Peak memory 194616 kb
Host smart-c681ef82-fd5d-4166-a4f5-370407c06fa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333836368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3333836368
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.1560383717
Short name T220
Test name
Test status
Simulation time 3490216829 ps
CPU time 60.31 seconds
Started Mar 28 01:18:45 PM PDT 24
Finished Mar 28 01:19:45 PM PDT 24
Peak memory 241124 kb
Host smart-9d224cb1-4ec2-4eae-8220-5c2882ae84cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1560383717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1560383717
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1107180869
Short name T423
Test name
Test status
Simulation time 1970567766 ps
CPU time 38.76 seconds
Started Mar 28 01:18:42 PM PDT 24
Finished Mar 28 01:19:21 PM PDT 24
Peak memory 200076 kb
Host smart-680b4514-8a4e-40b2-8121-c778e20d633a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107180869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1107180869
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.1365399492
Short name T315
Test name
Test status
Simulation time 543444938 ps
CPU time 31.55 seconds
Started Mar 28 01:18:41 PM PDT 24
Finished Mar 28 01:19:13 PM PDT 24
Peak memory 200124 kb
Host smart-d8a8eb80-c0e6-4932-9760-e749299c91f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1365399492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1365399492
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.516230642
Short name T553
Test name
Test status
Simulation time 3006545789 ps
CPU time 41.65 seconds
Started Mar 28 01:18:43 PM PDT 24
Finished Mar 28 01:19:24 PM PDT 24
Peak memory 200060 kb
Host smart-d4ecf7a7-838d-4d12-8bf0-4294a5104fe8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516230642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.516230642
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.983774341
Short name T600
Test name
Test status
Simulation time 1151671351 ps
CPU time 15.86 seconds
Started Mar 28 01:18:42 PM PDT 24
Finished Mar 28 01:18:58 PM PDT 24
Peak memory 200080 kb
Host smart-c4758b32-e671-4af7-91af-2c9e19fbd532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983774341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.983774341
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2666216629
Short name T308
Test name
Test status
Simulation time 45261221 ps
CPU time 1.3 seconds
Started Mar 28 01:18:41 PM PDT 24
Finished Mar 28 01:18:42 PM PDT 24
Peak memory 200060 kb
Host smart-400c0dc9-593b-4305-b16e-bf0f0e89f097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666216629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2666216629
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.3376253039
Short name T274
Test name
Test status
Simulation time 94406724155 ps
CPU time 1807.53 seconds
Started Mar 28 01:18:43 PM PDT 24
Finished Mar 28 01:48:51 PM PDT 24
Peak memory 248880 kb
Host smart-fe6d4d66-413d-46ed-94ae-7e84c073e1ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376253039 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.3376253039
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.4046331803
Short name T480
Test name
Test status
Simulation time 113982134 ps
CPU time 1.34 seconds
Started Mar 28 01:18:42 PM PDT 24
Finished Mar 28 01:18:43 PM PDT 24
Peak memory 200076 kb
Host smart-66ffdb34-63a7-4ed3-8fb5-a4a531be3965
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046331803 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.4046331803
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.366648963
Short name T46
Test name
Test status
Simulation time 33914752468 ps
CPU time 482.43 seconds
Started Mar 28 01:18:45 PM PDT 24
Finished Mar 28 01:26:47 PM PDT 24
Peak memory 200064 kb
Host smart-8e98ddb3-f87a-49e9-8715-215cf26d5bb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366648963 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.366648963
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.3101026940
Short name T546
Test name
Test status
Simulation time 4692947794 ps
CPU time 47.15 seconds
Started Mar 28 01:18:42 PM PDT 24
Finished Mar 28 01:19:29 PM PDT 24
Peak memory 200160 kb
Host smart-9bc92f57-8409-4946-915c-298c380c0399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101026940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3101026940
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.396851996
Short name T491
Test name
Test status
Simulation time 19989264 ps
CPU time 0.56 seconds
Started Mar 28 01:18:57 PM PDT 24
Finished Mar 28 01:18:57 PM PDT 24
Peak memory 195516 kb
Host smart-3c88d318-f795-460f-b711-432d3214834c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396851996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.396851996
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.2142338939
Short name T256
Test name
Test status
Simulation time 1808739259 ps
CPU time 45.81 seconds
Started Mar 28 01:18:56 PM PDT 24
Finished Mar 28 01:19:42 PM PDT 24
Peak memory 241028 kb
Host smart-d8f7036e-cb44-47b7-b313-022c98eb7bf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2142338939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2142338939
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1249140928
Short name T425
Test name
Test status
Simulation time 1476706718 ps
CPU time 63.48 seconds
Started Mar 28 01:18:59 PM PDT 24
Finished Mar 28 01:20:03 PM PDT 24
Peak memory 200044 kb
Host smart-5ff8fad2-2246-4a90-8e38-5cc25c7e3507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249140928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1249140928
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2032824321
Short name T328
Test name
Test status
Simulation time 3051352797 ps
CPU time 45.25 seconds
Started Mar 28 01:19:00 PM PDT 24
Finished Mar 28 01:19:46 PM PDT 24
Peak memory 200016 kb
Host smart-7be9164c-4811-4abb-92c0-a014b3a18cda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2032824321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2032824321
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3648240925
Short name T519
Test name
Test status
Simulation time 392857290 ps
CPU time 7.17 seconds
Started Mar 28 01:18:57 PM PDT 24
Finished Mar 28 01:19:04 PM PDT 24
Peak memory 200096 kb
Host smart-b6492446-bfef-46a4-b371-2edc8d3979e8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648240925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3648240925
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3249920760
Short name T386
Test name
Test status
Simulation time 192108898 ps
CPU time 12.81 seconds
Started Mar 28 01:18:57 PM PDT 24
Finished Mar 28 01:19:10 PM PDT 24
Peak memory 200016 kb
Host smart-90ce2055-b224-4872-ad37-85e97de76ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249920760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3249920760
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.645436392
Short name T161
Test name
Test status
Simulation time 20059812 ps
CPU time 0.72 seconds
Started Mar 28 01:18:55 PM PDT 24
Finished Mar 28 01:18:56 PM PDT 24
Peak memory 197160 kb
Host smart-4e7dc5a2-4982-474f-9e10-41f4ce168c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645436392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.645436392
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3098011520
Short name T577
Test name
Test status
Simulation time 80917599392 ps
CPU time 367.43 seconds
Started Mar 28 01:18:57 PM PDT 24
Finished Mar 28 01:25:05 PM PDT 24
Peak memory 216116 kb
Host smart-980a64b0-4c10-4a2e-b806-eb4cae9b3946
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098011520 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3098011520
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_stress_all_with_rand_reset.2407593134
Short name T8
Test name
Test status
Simulation time 71368786368 ps
CPU time 982.64 seconds
Started Mar 28 01:19:01 PM PDT 24
Finished Mar 28 01:35:24 PM PDT 24
Peak memory 232896 kb
Host smart-60ff7cd5-eae9-48fd-a410-afa36174edf8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2407593134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all_with_rand_reset.2407593134
Directory /workspace/35.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.281937072
Short name T406
Test name
Test status
Simulation time 85100565 ps
CPU time 1.1 seconds
Started Mar 28 01:18:59 PM PDT 24
Finished Mar 28 01:19:00 PM PDT 24
Peak memory 199360 kb
Host smart-b1160796-3071-4021-b367-5548b433315e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281937072 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_hmac_vectors.281937072
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.3919866626
Short name T505
Test name
Test status
Simulation time 35842607279 ps
CPU time 468.87 seconds
Started Mar 28 01:18:57 PM PDT 24
Finished Mar 28 01:26:47 PM PDT 24
Peak memory 200048 kb
Host smart-f96d075e-e1d5-415a-91bb-708085199b5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919866626 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.3919866626
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2816400617
Short name T26
Test name
Test status
Simulation time 6626639801 ps
CPU time 102.14 seconds
Started Mar 28 01:18:57 PM PDT 24
Finished Mar 28 01:20:39 PM PDT 24
Peak memory 200136 kb
Host smart-b1c6a470-0955-448b-aa0b-b97a6c52eed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816400617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2816400617
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3479468674
Short name T240
Test name
Test status
Simulation time 10867084 ps
CPU time 0.57 seconds
Started Mar 28 01:19:01 PM PDT 24
Finished Mar 28 01:19:02 PM PDT 24
Peak memory 194344 kb
Host smart-d5dfeb64-a342-4dd4-99ad-b4de23f53cf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479468674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3479468674
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1783591174
Short name T507
Test name
Test status
Simulation time 1150634708 ps
CPU time 37.56 seconds
Started Mar 28 01:18:57 PM PDT 24
Finished Mar 28 01:19:35 PM PDT 24
Peak memory 208240 kb
Host smart-d00a9f40-af9d-4b7f-a1e5-e59a9cea099b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1783591174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1783591174
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.160281451
Short name T195
Test name
Test status
Simulation time 3414758303 ps
CPU time 7.68 seconds
Started Mar 28 01:18:57 PM PDT 24
Finished Mar 28 01:19:06 PM PDT 24
Peak memory 200084 kb
Host smart-2dce66e8-3801-4fd0-8d20-1cc016552bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160281451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.160281451
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.760357134
Short name T160
Test name
Test status
Simulation time 343710614 ps
CPU time 19.29 seconds
Started Mar 28 01:18:56 PM PDT 24
Finished Mar 28 01:19:16 PM PDT 24
Peak memory 200056 kb
Host smart-5340f958-4fdc-4ae7-99f3-250f0b887bc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=760357134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.760357134
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2280210570
Short name T264
Test name
Test status
Simulation time 27152834086 ps
CPU time 170.75 seconds
Started Mar 28 01:19:00 PM PDT 24
Finished Mar 28 01:21:51 PM PDT 24
Peak memory 200132 kb
Host smart-30f25624-53a5-4701-8f7e-193c9e325c71
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280210570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2280210570
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.1396226501
Short name T324
Test name
Test status
Simulation time 901088845 ps
CPU time 55.34 seconds
Started Mar 28 01:18:56 PM PDT 24
Finished Mar 28 01:19:51 PM PDT 24
Peak memory 200104 kb
Host smart-a54d9c46-a71a-400a-b1a7-c00a7d4013b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396226501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1396226501
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.3953327784
Short name T390
Test name
Test status
Simulation time 17162284 ps
CPU time 0.76 seconds
Started Mar 28 01:19:01 PM PDT 24
Finished Mar 28 01:19:02 PM PDT 24
Peak memory 197200 kb
Host smart-b5ae1be0-a25b-418f-9317-dc1e74d56e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953327784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.3953327784
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.2335021698
Short name T522
Test name
Test status
Simulation time 1394954410 ps
CPU time 52.92 seconds
Started Mar 28 01:19:01 PM PDT 24
Finished Mar 28 01:19:55 PM PDT 24
Peak memory 199912 kb
Host smart-12d99c1a-ca5f-4cb1-92a5-de16c1932f57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335021698 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2335021698
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.38330675
Short name T354
Test name
Test status
Simulation time 138052825 ps
CPU time 1.02 seconds
Started Mar 28 01:18:56 PM PDT 24
Finished Mar 28 01:18:57 PM PDT 24
Peak memory 198680 kb
Host smart-d041b810-d691-4177-a79f-878e8cc8948c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38330675 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.hmac_test_hmac_vectors.38330675
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.1700859765
Short name T286
Test name
Test status
Simulation time 41690770971 ps
CPU time 588.34 seconds
Started Mar 28 01:18:59 PM PDT 24
Finished Mar 28 01:28:48 PM PDT 24
Peak memory 200064 kb
Host smart-b35b5377-95cd-43c4-9168-24ac2d8c66ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700859765 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.1700859765
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.3786690810
Short name T525
Test name
Test status
Simulation time 1541280854 ps
CPU time 9.59 seconds
Started Mar 28 01:18:56 PM PDT 24
Finished Mar 28 01:19:05 PM PDT 24
Peak memory 200084 kb
Host smart-392e05df-cd27-4270-a56c-004801d84fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786690810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.3786690810
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.743883137
Short name T1
Test name
Test status
Simulation time 10984514 ps
CPU time 0.58 seconds
Started Mar 28 01:18:57 PM PDT 24
Finished Mar 28 01:18:58 PM PDT 24
Peak memory 194584 kb
Host smart-330f493d-9e9b-4e7a-82e1-3c04e60858f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743883137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.743883137
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.3306348807
Short name T355
Test name
Test status
Simulation time 11913772015 ps
CPU time 49.27 seconds
Started Mar 28 01:19:01 PM PDT 24
Finished Mar 28 01:19:51 PM PDT 24
Peak memory 233664 kb
Host smart-59658195-a564-4443-9f6f-1100a6ea35bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3306348807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3306348807
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.352017787
Short name T448
Test name
Test status
Simulation time 2445058711 ps
CPU time 26.27 seconds
Started Mar 28 01:19:01 PM PDT 24
Finished Mar 28 01:19:28 PM PDT 24
Peak memory 200028 kb
Host smart-1da44cea-9f1b-4795-9669-04ed752c675f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352017787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.352017787
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3371964069
Short name T144
Test name
Test status
Simulation time 5406827246 ps
CPU time 80.42 seconds
Started Mar 28 01:18:56 PM PDT 24
Finished Mar 28 01:20:17 PM PDT 24
Peak memory 200112 kb
Host smart-a522f7f2-4d87-4ef5-94c9-944c8abbf460
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3371964069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3371964069
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.4172136670
Short name T49
Test name
Test status
Simulation time 15512341024 ps
CPU time 53.83 seconds
Started Mar 28 01:18:58 PM PDT 24
Finished Mar 28 01:19:52 PM PDT 24
Peak memory 200080 kb
Host smart-f7e66b25-58af-4564-bcdd-35a130e61beb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172136670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.4172136670
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1345971918
Short name T530
Test name
Test status
Simulation time 13296501665 ps
CPU time 56.11 seconds
Started Mar 28 01:18:57 PM PDT 24
Finished Mar 28 01:19:54 PM PDT 24
Peak memory 200116 kb
Host smart-97c9bd64-b961-4313-a0b3-c579cc63f716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345971918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1345971918
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.314267638
Short name T470
Test name
Test status
Simulation time 67914928 ps
CPU time 2.16 seconds
Started Mar 28 01:19:02 PM PDT 24
Finished Mar 28 01:19:04 PM PDT 24
Peak memory 199892 kb
Host smart-b6a812cd-69cd-4595-a77d-36148fd8857e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314267638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.314267638
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.4113372207
Short name T527
Test name
Test status
Simulation time 62537432096 ps
CPU time 245.47 seconds
Started Mar 28 01:18:58 PM PDT 24
Finished Mar 28 01:23:04 PM PDT 24
Peak memory 241124 kb
Host smart-d419f4ed-0f44-4026-b5c8-9eb532d1f655
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113372207 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.4113372207
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.1266468104
Short name T142
Test name
Test status
Simulation time 57200242 ps
CPU time 1.01 seconds
Started Mar 28 01:18:57 PM PDT 24
Finished Mar 28 01:18:58 PM PDT 24
Peak memory 199920 kb
Host smart-69fc7945-36c4-40a9-963e-b5895e2fe58d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266468104 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.1266468104
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.1740734279
Short name T361
Test name
Test status
Simulation time 56023214946 ps
CPU time 544.57 seconds
Started Mar 28 01:18:57 PM PDT 24
Finished Mar 28 01:28:02 PM PDT 24
Peak memory 199980 kb
Host smart-941e41ad-c4d8-4aa2-b325-899e890df526
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740734279 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.1740734279
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1084225047
Short name T175
Test name
Test status
Simulation time 12609061058 ps
CPU time 43.29 seconds
Started Mar 28 01:19:01 PM PDT 24
Finished Mar 28 01:19:45 PM PDT 24
Peak memory 199980 kb
Host smart-24ca21de-e39e-4137-b345-4bf90a2f9358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084225047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1084225047
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3556826336
Short name T252
Test name
Test status
Simulation time 30469805 ps
CPU time 0.58 seconds
Started Mar 28 01:19:22 PM PDT 24
Finished Mar 28 01:19:23 PM PDT 24
Peak memory 195456 kb
Host smart-ae30d3d5-cdda-4e95-b0eb-9caaaf794a8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556826336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3556826336
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3628258037
Short name T445
Test name
Test status
Simulation time 1005916361 ps
CPU time 19.14 seconds
Started Mar 28 01:18:56 PM PDT 24
Finished Mar 28 01:19:15 PM PDT 24
Peak memory 210272 kb
Host smart-9517ab6e-f53a-4b0c-ad2f-0dce9a7b9b7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3628258037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3628258037
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.2656663400
Short name T222
Test name
Test status
Simulation time 1302548521 ps
CPU time 15.46 seconds
Started Mar 28 01:19:23 PM PDT 24
Finished Mar 28 01:19:39 PM PDT 24
Peak memory 200080 kb
Host smart-b7bdc8eb-c0ef-4dca-bcaf-b8d9b2624da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656663400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.2656663400
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.475452565
Short name T206
Test name
Test status
Simulation time 4585307410 ps
CPU time 139.74 seconds
Started Mar 28 01:19:24 PM PDT 24
Finished Mar 28 01:21:44 PM PDT 24
Peak memory 200068 kb
Host smart-f411e0a5-badf-4402-bd99-a73c7f4b46e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=475452565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.475452565
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.698980423
Short name T417
Test name
Test status
Simulation time 10852634681 ps
CPU time 33.74 seconds
Started Mar 28 01:19:24 PM PDT 24
Finished Mar 28 01:19:58 PM PDT 24
Peak memory 200116 kb
Host smart-f51a7d7a-3168-4e14-b3d1-c098e464be2a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698980423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.698980423
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1934662684
Short name T150
Test name
Test status
Simulation time 6139698293 ps
CPU time 125.08 seconds
Started Mar 28 01:18:56 PM PDT 24
Finished Mar 28 01:21:01 PM PDT 24
Peak memory 200100 kb
Host smart-99c1abaa-b358-401c-9420-81bda4bdadaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934662684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1934662684
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3937112507
Short name T304
Test name
Test status
Simulation time 3275242525 ps
CPU time 2.49 seconds
Started Mar 28 01:18:57 PM PDT 24
Finished Mar 28 01:19:00 PM PDT 24
Peak memory 200060 kb
Host smart-0db3207e-331a-4283-9b57-62750bfa6da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937112507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3937112507
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.2858608193
Short name T80
Test name
Test status
Simulation time 1311066659848 ps
CPU time 2159.87 seconds
Started Mar 28 01:19:23 PM PDT 24
Finished Mar 28 01:55:24 PM PDT 24
Peak memory 240968 kb
Host smart-6e9e0efb-e17d-48b1-9d71-250e6a0d17a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858608193 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.2858608193
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.190821086
Short name T479
Test name
Test status
Simulation time 222757816 ps
CPU time 1.21 seconds
Started Mar 28 01:19:23 PM PDT 24
Finished Mar 28 01:19:25 PM PDT 24
Peak memory 199808 kb
Host smart-07f66001-8d6a-4945-8f92-edd00c9a3c63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190821086 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_test_hmac_vectors.190821086
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.897607030
Short name T369
Test name
Test status
Simulation time 8410206661 ps
CPU time 436.52 seconds
Started Mar 28 01:19:24 PM PDT 24
Finished Mar 28 01:26:41 PM PDT 24
Peak memory 200064 kb
Host smart-454fbec7-e160-4196-8d37-0d8b28442182
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897607030 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.897607030
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.850995023
Short name T186
Test name
Test status
Simulation time 1404773266 ps
CPU time 5.14 seconds
Started Mar 28 01:19:22 PM PDT 24
Finished Mar 28 01:19:28 PM PDT 24
Peak memory 200008 kb
Host smart-89b86f88-80e4-4fc4-b5de-c2ea4cd6d3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850995023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.850995023
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2165095436
Short name T299
Test name
Test status
Simulation time 51325565 ps
CPU time 0.56 seconds
Started Mar 28 01:19:23 PM PDT 24
Finished Mar 28 01:19:24 PM PDT 24
Peak memory 195604 kb
Host smart-15a6f791-6bc7-4479-b0a0-ebd98f94311f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165095436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2165095436
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.82604839
Short name T581
Test name
Test status
Simulation time 250910706 ps
CPU time 12.45 seconds
Started Mar 28 01:19:23 PM PDT 24
Finished Mar 28 01:19:36 PM PDT 24
Peak memory 240924 kb
Host smart-d1fa1061-aa9b-415d-bda5-45a92a17948b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=82604839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.82604839
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3568541575
Short name T184
Test name
Test status
Simulation time 15774099218 ps
CPU time 65.51 seconds
Started Mar 28 01:19:23 PM PDT 24
Finished Mar 28 01:20:29 PM PDT 24
Peak memory 200136 kb
Host smart-d95122f8-08b6-4f3c-9a42-63d51dc782d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568541575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3568541575
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3203238457
Short name T589
Test name
Test status
Simulation time 30084132 ps
CPU time 0.69 seconds
Started Mar 28 01:19:21 PM PDT 24
Finished Mar 28 01:19:22 PM PDT 24
Peak memory 198180 kb
Host smart-9680ec63-b9a5-4969-be8d-05aa44b9233f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3203238457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3203238457
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.4283795083
Short name T539
Test name
Test status
Simulation time 3477519708 ps
CPU time 210.86 seconds
Started Mar 28 01:19:24 PM PDT 24
Finished Mar 28 01:22:55 PM PDT 24
Peak memory 200124 kb
Host smart-2948ae84-fb74-4435-b709-8856d3cc21fe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283795083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.4283795083
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.347247979
Short name T550
Test name
Test status
Simulation time 23414501092 ps
CPU time 120.31 seconds
Started Mar 28 01:19:22 PM PDT 24
Finished Mar 28 01:21:23 PM PDT 24
Peak memory 200156 kb
Host smart-0c7f86ec-9884-4fd7-a141-d120252f86fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347247979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.347247979
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3203126632
Short name T312
Test name
Test status
Simulation time 1017650549 ps
CPU time 4.17 seconds
Started Mar 28 01:19:24 PM PDT 24
Finished Mar 28 01:19:28 PM PDT 24
Peak memory 200088 kb
Host smart-f4030538-9f0e-497c-8f74-4a6396234ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203126632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3203126632
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.464243799
Short name T84
Test name
Test status
Simulation time 3151312781 ps
CPU time 43.05 seconds
Started Mar 28 01:19:22 PM PDT 24
Finished Mar 28 01:20:05 PM PDT 24
Peak memory 200152 kb
Host smart-7c1b7d5f-5ff7-4ccf-a9e9-e4d805ea8644
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464243799 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.464243799
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.2572048867
Short name T60
Test name
Test status
Simulation time 56928291 ps
CPU time 1.04 seconds
Started Mar 28 01:19:23 PM PDT 24
Finished Mar 28 01:19:25 PM PDT 24
Peak memory 199540 kb
Host smart-9dfd60f9-5ae0-4372-8c10-97e274d51a56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572048867 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.2572048867
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.1946604382
Short name T574
Test name
Test status
Simulation time 32542030881 ps
CPU time 504.57 seconds
Started Mar 28 01:19:24 PM PDT 24
Finished Mar 28 01:27:49 PM PDT 24
Peak memory 200068 kb
Host smart-c6133f88-d154-4bce-a746-a4c68f6f492e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946604382 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.1946604382
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.1053627242
Short name T463
Test name
Test status
Simulation time 249424886 ps
CPU time 7.97 seconds
Started Mar 28 01:19:22 PM PDT 24
Finished Mar 28 01:19:30 PM PDT 24
Peak memory 200036 kb
Host smart-dd0169ec-ba0b-4fd6-b802-af67b715124c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053627242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.1053627242
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.4221757618
Short name T509
Test name
Test status
Simulation time 80236235 ps
CPU time 0.58 seconds
Started Mar 28 01:15:46 PM PDT 24
Finished Mar 28 01:15:47 PM PDT 24
Peak memory 195608 kb
Host smart-a7c4f439-5550-4080-8a5b-e807c67ae704
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221757618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.4221757618
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1533257671
Short name T316
Test name
Test status
Simulation time 1182443905 ps
CPU time 7.19 seconds
Started Mar 28 01:15:46 PM PDT 24
Finished Mar 28 01:15:53 PM PDT 24
Peak memory 200100 kb
Host smart-e64c6e3a-30b8-4b43-86c8-77fb6322b16b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1533257671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1533257671
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3501439
Short name T380
Test name
Test status
Simulation time 4739564859 ps
CPU time 48.53 seconds
Started Mar 28 01:15:48 PM PDT 24
Finished Mar 28 01:16:38 PM PDT 24
Peak memory 200064 kb
Host smart-a7e42a83-50a9-4bde-935c-5c2dcee9b92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3501439
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.3533959159
Short name T270
Test name
Test status
Simulation time 1097237895 ps
CPU time 65.86 seconds
Started Mar 28 01:15:46 PM PDT 24
Finished Mar 28 01:16:52 PM PDT 24
Peak memory 200096 kb
Host smart-1bc8f245-dbcb-420f-87c3-b87fac996be4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3533959159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.3533959159
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1619113447
Short name T246
Test name
Test status
Simulation time 11852942438 ps
CPU time 80.82 seconds
Started Mar 28 01:15:47 PM PDT 24
Finished Mar 28 01:17:10 PM PDT 24
Peak memory 200156 kb
Host smart-c8e6e603-553a-4090-9009-922ec4d26e45
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619113447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1619113447
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.510914649
Short name T327
Test name
Test status
Simulation time 1070724854 ps
CPU time 57.79 seconds
Started Mar 28 01:15:48 PM PDT 24
Finished Mar 28 01:16:47 PM PDT 24
Peak memory 200056 kb
Host smart-20a318dc-20d5-4213-b66c-4840a07c18ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510914649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.510914649
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2852597954
Short name T33
Test name
Test status
Simulation time 68234501 ps
CPU time 0.95 seconds
Started Mar 28 01:15:47 PM PDT 24
Finished Mar 28 01:15:50 PM PDT 24
Peak memory 218232 kb
Host smart-61fe70c5-04f5-4f58-b034-1e7445879901
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852597954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2852597954
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1363288576
Short name T224
Test name
Test status
Simulation time 296522883 ps
CPU time 4.52 seconds
Started Mar 28 01:15:32 PM PDT 24
Finished Mar 28 01:15:36 PM PDT 24
Peak memory 200036 kb
Host smart-8a822e1d-8f25-4330-93d1-cd53d5c4df83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363288576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1363288576
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1732942552
Short name T155
Test name
Test status
Simulation time 9505728864 ps
CPU time 177.97 seconds
Started Mar 28 01:15:47 PM PDT 24
Finished Mar 28 01:18:47 PM PDT 24
Peak memory 200092 kb
Host smart-6b69c112-7617-46f0-b438-c2fab04b3d23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732942552 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1732942552
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.573329127
Short name T145
Test name
Test status
Simulation time 326329903 ps
CPU time 1.09 seconds
Started Mar 28 01:15:49 PM PDT 24
Finished Mar 28 01:15:50 PM PDT 24
Peak memory 199212 kb
Host smart-e3ce584a-6ca5-4845-adb8-94a403df65d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573329127 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_hmac_vectors.573329127
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.3825127547
Short name T383
Test name
Test status
Simulation time 48500411308 ps
CPU time 395.72 seconds
Started Mar 28 01:15:48 PM PDT 24
Finished Mar 28 01:22:25 PM PDT 24
Peak memory 200108 kb
Host smart-49fd8a3f-dd22-413f-8c1b-6c6b2dcb93c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825127547 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.3825127547
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.893269327
Short name T310
Test name
Test status
Simulation time 3959382637 ps
CPU time 66.29 seconds
Started Mar 28 01:15:47 PM PDT 24
Finished Mar 28 01:16:55 PM PDT 24
Peak memory 200164 kb
Host smart-7ea5e155-0289-406a-bfcc-c5edd271cfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893269327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.893269327
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.205074309
Short name T563
Test name
Test status
Simulation time 22310061 ps
CPU time 0.59 seconds
Started Mar 28 01:19:24 PM PDT 24
Finished Mar 28 01:19:25 PM PDT 24
Peak memory 195648 kb
Host smart-daa8ed24-b572-4f78-b959-ec4401a34c81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205074309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.205074309
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1771756503
Short name T57
Test name
Test status
Simulation time 1278582048 ps
CPU time 52.71 seconds
Started Mar 28 01:19:22 PM PDT 24
Finished Mar 28 01:20:15 PM PDT 24
Peak memory 225556 kb
Host smart-53618485-16cb-4a68-839b-a98c0e819d6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1771756503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1771756503
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1842383880
Short name T18
Test name
Test status
Simulation time 1196495615 ps
CPU time 31.48 seconds
Started Mar 28 01:19:23 PM PDT 24
Finished Mar 28 01:19:55 PM PDT 24
Peak memory 200040 kb
Host smart-9add5dad-a107-484d-8162-e466a6133e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842383880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1842383880
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.936473990
Short name T192
Test name
Test status
Simulation time 1343848950 ps
CPU time 36.75 seconds
Started Mar 28 01:19:23 PM PDT 24
Finished Mar 28 01:20:01 PM PDT 24
Peak memory 200092 kb
Host smart-66a9cdfd-87c4-4053-84b4-9af73ad2fefa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=936473990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.936473990
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.392211914
Short name T242
Test name
Test status
Simulation time 49228752901 ps
CPU time 157.63 seconds
Started Mar 28 01:19:28 PM PDT 24
Finished Mar 28 01:22:06 PM PDT 24
Peak memory 200028 kb
Host smart-53a3b9cd-3eed-41ec-a4a3-1721e801a930
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392211914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.392211914
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.408508937
Short name T271
Test name
Test status
Simulation time 115199526 ps
CPU time 3.43 seconds
Started Mar 28 01:19:23 PM PDT 24
Finished Mar 28 01:19:27 PM PDT 24
Peak memory 200000 kb
Host smart-41b75b7c-f807-4550-a3c5-0925e9a96bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408508937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.408508937
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1797179712
Short name T335
Test name
Test status
Simulation time 237230892 ps
CPU time 3.2 seconds
Started Mar 28 01:19:23 PM PDT 24
Finished Mar 28 01:19:27 PM PDT 24
Peak memory 200004 kb
Host smart-6cc75ff1-f271-4a69-a6a5-ba8e231bdf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797179712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1797179712
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.3070975503
Short name T413
Test name
Test status
Simulation time 346584837656 ps
CPU time 1707.62 seconds
Started Mar 28 01:19:23 PM PDT 24
Finished Mar 28 01:47:51 PM PDT 24
Peak memory 200156 kb
Host smart-807717dc-f11d-4be3-8e3b-9183ecd8c503
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070975503 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3070975503
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_stress_all_with_rand_reset.916703089
Short name T69
Test name
Test status
Simulation time 6579667638 ps
CPU time 182.51 seconds
Started Mar 28 01:19:25 PM PDT 24
Finished Mar 28 01:22:27 PM PDT 24
Peak memory 216560 kb
Host smart-43fe53ba-db42-4bd4-9451-3e9ea5fa6d89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=916703089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all_with_rand_reset.916703089
Directory /workspace/40.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.1167047284
Short name T411
Test name
Test status
Simulation time 270822756 ps
CPU time 1.09 seconds
Started Mar 28 01:19:22 PM PDT 24
Finished Mar 28 01:19:23 PM PDT 24
Peak memory 199180 kb
Host smart-ac83828b-ed84-4b44-8177-68535d71f866
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167047284 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.1167047284
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.4201291826
Short name T78
Test name
Test status
Simulation time 192079954208 ps
CPU time 609.93 seconds
Started Mar 28 01:19:22 PM PDT 24
Finished Mar 28 01:29:33 PM PDT 24
Peak memory 200124 kb
Host smart-cc49de41-65a5-479d-bdcd-5217a8b0731b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201291826 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.4201291826
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.486008499
Short name T188
Test name
Test status
Simulation time 307815606 ps
CPU time 18.43 seconds
Started Mar 28 01:19:25 PM PDT 24
Finished Mar 28 01:19:43 PM PDT 24
Peak memory 200016 kb
Host smart-89b0c2e7-0517-44c1-9222-fa941cdbabaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486008499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.486008499
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2078248450
Short name T473
Test name
Test status
Simulation time 29502005 ps
CPU time 0.56 seconds
Started Mar 28 01:19:40 PM PDT 24
Finished Mar 28 01:19:41 PM PDT 24
Peak memory 195492 kb
Host smart-1e043653-5d32-4206-8a1f-9a4a62fba9a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078248450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2078248450
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2483275260
Short name T283
Test name
Test status
Simulation time 1109279640 ps
CPU time 19.1 seconds
Started Mar 28 01:19:43 PM PDT 24
Finished Mar 28 01:20:03 PM PDT 24
Peak memory 215668 kb
Host smart-3febb46e-25bd-4b1e-9112-8b18a6846566
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2483275260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2483275260
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3764874547
Short name T471
Test name
Test status
Simulation time 545475183 ps
CPU time 9.2 seconds
Started Mar 28 01:19:41 PM PDT 24
Finished Mar 28 01:19:50 PM PDT 24
Peak memory 200072 kb
Host smart-3c61efc2-94d5-4aef-802b-f0ef691b1adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764874547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3764874547
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.4093879243
Short name T551
Test name
Test status
Simulation time 1301099582 ps
CPU time 18.24 seconds
Started Mar 28 01:19:39 PM PDT 24
Finished Mar 28 01:19:57 PM PDT 24
Peak memory 200028 kb
Host smart-7f7d1744-7349-4d21-aa51-cb0b8c255424
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4093879243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.4093879243
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1072340785
Short name T296
Test name
Test status
Simulation time 5038360452 ps
CPU time 145.49 seconds
Started Mar 28 01:19:39 PM PDT 24
Finished Mar 28 01:22:05 PM PDT 24
Peak memory 200136 kb
Host smart-be1cbdb3-4884-4f9f-8a64-14f10821f40f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072340785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1072340785
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.1502010011
Short name T183
Test name
Test status
Simulation time 5494646625 ps
CPU time 54.29 seconds
Started Mar 28 01:19:41 PM PDT 24
Finished Mar 28 01:20:36 PM PDT 24
Peak memory 200064 kb
Host smart-92b8764c-72d3-4659-869f-cea442a1426d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502010011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.1502010011
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1884113775
Short name T214
Test name
Test status
Simulation time 26227330 ps
CPU time 1.13 seconds
Started Mar 28 01:19:23 PM PDT 24
Finished Mar 28 01:19:25 PM PDT 24
Peak memory 200096 kb
Host smart-0f246f86-88c6-4db9-bed6-30ab69150d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884113775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1884113775
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1180424565
Short name T585
Test name
Test status
Simulation time 3447697828 ps
CPU time 175.24 seconds
Started Mar 28 01:19:40 PM PDT 24
Finished Mar 28 01:22:35 PM PDT 24
Peak memory 200088 kb
Host smart-ca0f1cdb-73d0-4f3f-9ff8-9349e94cecfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180424565 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1180424565
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.3555057448
Short name T132
Test name
Test status
Simulation time 324103187 ps
CPU time 1.14 seconds
Started Mar 28 01:19:44 PM PDT 24
Finished Mar 28 01:19:46 PM PDT 24
Peak memory 199996 kb
Host smart-f66b5039-a662-451f-9669-a563ff791ffc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555057448 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.3555057448
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.2919097239
Short name T372
Test name
Test status
Simulation time 11075289595 ps
CPU time 425.99 seconds
Started Mar 28 01:19:40 PM PDT 24
Finished Mar 28 01:26:46 PM PDT 24
Peak memory 199976 kb
Host smart-817c1934-244f-401f-9153-e3f98dbad19c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919097239 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.2919097239
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3704823519
Short name T420
Test name
Test status
Simulation time 20433038765 ps
CPU time 70.27 seconds
Started Mar 28 01:19:42 PM PDT 24
Finished Mar 28 01:20:52 PM PDT 24
Peak memory 200160 kb
Host smart-2eb2c152-3fd3-48ef-901f-7a279d1b6a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704823519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3704823519
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.582164159
Short name T596
Test name
Test status
Simulation time 44502364 ps
CPU time 0.59 seconds
Started Mar 28 01:19:42 PM PDT 24
Finished Mar 28 01:19:44 PM PDT 24
Peak memory 195636 kb
Host smart-d99891d9-cfc6-410c-986f-9287e879d2c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582164159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.582164159
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1776028454
Short name T281
Test name
Test status
Simulation time 549556883 ps
CPU time 14.68 seconds
Started Mar 28 01:19:43 PM PDT 24
Finished Mar 28 01:19:58 PM PDT 24
Peak memory 215912 kb
Host smart-6372b15b-81e7-4473-b2c1-d7007007908d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1776028454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1776028454
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2317106227
Short name T456
Test name
Test status
Simulation time 647918999 ps
CPU time 31.99 seconds
Started Mar 28 01:19:40 PM PDT 24
Finished Mar 28 01:20:12 PM PDT 24
Peak memory 199992 kb
Host smart-00a70ae4-e4dc-49b9-a18e-6b6ff138bf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317106227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2317106227
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.2177211454
Short name T43
Test name
Test status
Simulation time 1373241802 ps
CPU time 79.33 seconds
Started Mar 28 01:19:40 PM PDT 24
Finished Mar 28 01:21:00 PM PDT 24
Peak memory 200060 kb
Host smart-1b6e56e0-d376-40d7-89f6-a67d167785bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2177211454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2177211454
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.1080274157
Short name T277
Test name
Test status
Simulation time 13299518768 ps
CPU time 188.69 seconds
Started Mar 28 01:19:40 PM PDT 24
Finished Mar 28 01:22:49 PM PDT 24
Peak memory 200172 kb
Host smart-8ce12e13-981b-485a-967e-074cdf193d5f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080274157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.1080274157
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1615143957
Short name T79
Test name
Test status
Simulation time 1806796340 ps
CPU time 26.93 seconds
Started Mar 28 01:19:38 PM PDT 24
Finished Mar 28 01:20:06 PM PDT 24
Peak memory 200072 kb
Host smart-af0672b0-f275-429f-b117-7c8ce3372d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615143957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1615143957
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3862930492
Short name T90
Test name
Test status
Simulation time 397806487 ps
CPU time 2.85 seconds
Started Mar 28 01:19:43 PM PDT 24
Finished Mar 28 01:19:46 PM PDT 24
Peak memory 200020 kb
Host smart-47375545-f1c1-4a35-93dd-b163193c760c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862930492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3862930492
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.717997830
Short name T99
Test name
Test status
Simulation time 500232975180 ps
CPU time 763.7 seconds
Started Mar 28 01:19:39 PM PDT 24
Finished Mar 28 01:32:23 PM PDT 24
Peak memory 200068 kb
Host smart-6b8afec4-7017-4593-99e6-bf6b09ad4fc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717997830 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.717997830
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.2067194454
Short name T440
Test name
Test status
Simulation time 38899243 ps
CPU time 1.02 seconds
Started Mar 28 01:19:41 PM PDT 24
Finished Mar 28 01:19:43 PM PDT 24
Peak memory 198256 kb
Host smart-ebf8f215-01dd-4fac-811e-6b0fd27aca42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067194454 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.2067194454
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.3026101421
Short name T344
Test name
Test status
Simulation time 12953833346 ps
CPU time 486.74 seconds
Started Mar 28 01:19:39 PM PDT 24
Finished Mar 28 01:27:46 PM PDT 24
Peak memory 200084 kb
Host smart-97ebf664-b6fa-475b-9e4c-ad83b27d7386
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026101421 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.3026101421
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.2831167028
Short name T601
Test name
Test status
Simulation time 2250766820 ps
CPU time 33.3 seconds
Started Mar 28 01:19:42 PM PDT 24
Finished Mar 28 01:20:16 PM PDT 24
Peak memory 200000 kb
Host smart-53fe6951-b6d4-4a26-ae84-63e3d993f74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831167028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2831167028
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.249741404
Short name T561
Test name
Test status
Simulation time 15033558 ps
CPU time 0.58 seconds
Started Mar 28 01:19:41 PM PDT 24
Finished Mar 28 01:19:42 PM PDT 24
Peak memory 195600 kb
Host smart-adaa2ac9-fb01-4d3b-be16-9e93800e3885
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249741404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.249741404
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1741393298
Short name T238
Test name
Test status
Simulation time 5760616424 ps
CPU time 61.45 seconds
Started Mar 28 01:19:39 PM PDT 24
Finished Mar 28 01:20:40 PM PDT 24
Peak memory 221624 kb
Host smart-7285aec7-6877-4543-9bf0-c7aadd2c5ef9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1741393298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1741393298
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.1472498554
Short name T353
Test name
Test status
Simulation time 1819679000 ps
CPU time 8.06 seconds
Started Mar 28 01:19:40 PM PDT 24
Finished Mar 28 01:19:48 PM PDT 24
Peak memory 200076 kb
Host smart-7b27cbd6-1e76-4cf6-864d-dc8b9dac5666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472498554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1472498554
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2024191630
Short name T434
Test name
Test status
Simulation time 5338901368 ps
CPU time 56.81 seconds
Started Mar 28 01:19:39 PM PDT 24
Finished Mar 28 01:20:36 PM PDT 24
Peak memory 200124 kb
Host smart-c9325541-32e6-4e10-afad-07bb5f2891b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2024191630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2024191630
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.2837216470
Short name T514
Test name
Test status
Simulation time 13185266761 ps
CPU time 54.63 seconds
Started Mar 28 01:19:41 PM PDT 24
Finished Mar 28 01:20:36 PM PDT 24
Peak memory 200144 kb
Host smart-f3d00974-b7e7-47f7-8885-d001514ab0b8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837216470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.2837216470
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.2345681485
Short name T523
Test name
Test status
Simulation time 13138236494 ps
CPU time 48.43 seconds
Started Mar 28 01:19:42 PM PDT 24
Finished Mar 28 01:20:32 PM PDT 24
Peak memory 199976 kb
Host smart-f571262f-9eeb-4ad5-986e-09a2c428b669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345681485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2345681485
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2006520525
Short name T187
Test name
Test status
Simulation time 768279781 ps
CPU time 6.72 seconds
Started Mar 28 01:19:40 PM PDT 24
Finished Mar 28 01:19:47 PM PDT 24
Peak memory 200072 kb
Host smart-8fcebb7f-ea0f-48e0-980e-655387004d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006520525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2006520525
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.2829328574
Short name T86
Test name
Test status
Simulation time 138404914424 ps
CPU time 1939.53 seconds
Started Mar 28 01:19:40 PM PDT 24
Finished Mar 28 01:52:00 PM PDT 24
Peak memory 226684 kb
Host smart-60ffea8b-7866-4dad-a0ff-f4235c4f08c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829328574 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2829328574
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.1259002548
Short name T416
Test name
Test status
Simulation time 208971960 ps
CPU time 1.25 seconds
Started Mar 28 01:19:40 PM PDT 24
Finished Mar 28 01:19:42 PM PDT 24
Peak memory 200000 kb
Host smart-e9ee4815-2331-477d-8302-9e01a2af716b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259002548 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.1259002548
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.4142495673
Short name T38
Test name
Test status
Simulation time 140736080712 ps
CPU time 471.48 seconds
Started Mar 28 01:19:42 PM PDT 24
Finished Mar 28 01:27:34 PM PDT 24
Peak memory 200036 kb
Host smart-fc30bc4b-6944-48f1-b9e7-3eee8611a774
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142495673 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.4142495673
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.3282528028
Short name T452
Test name
Test status
Simulation time 4483505447 ps
CPU time 31.66 seconds
Started Mar 28 01:19:40 PM PDT 24
Finished Mar 28 01:20:12 PM PDT 24
Peak memory 200084 kb
Host smart-4a2b27eb-9473-4c3f-80b5-1d5c533c194e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282528028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3282528028
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3172202378
Short name T338
Test name
Test status
Simulation time 82696952 ps
CPU time 0.54 seconds
Started Mar 28 01:19:41 PM PDT 24
Finished Mar 28 01:19:42 PM PDT 24
Peak memory 195524 kb
Host smart-0eaedd40-5f7f-4edd-8457-928e999666a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172202378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3172202378
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3605434072
Short name T486
Test name
Test status
Simulation time 1451485574 ps
CPU time 51.54 seconds
Started Mar 28 01:19:40 PM PDT 24
Finished Mar 28 01:20:32 PM PDT 24
Peak memory 212352 kb
Host smart-e77ab2cf-f7f2-4e74-ae61-48bfb6400368
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3605434072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3605434072
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3474706149
Short name T332
Test name
Test status
Simulation time 1700018436 ps
CPU time 39.64 seconds
Started Mar 28 01:19:40 PM PDT 24
Finished Mar 28 01:20:20 PM PDT 24
Peak memory 200008 kb
Host smart-82f9d28b-9968-46ff-8002-40752ebcae42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474706149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3474706149
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.3286671712
Short name T384
Test name
Test status
Simulation time 101877567 ps
CPU time 5.88 seconds
Started Mar 28 01:19:42 PM PDT 24
Finished Mar 28 01:19:48 PM PDT 24
Peak memory 199972 kb
Host smart-4c531f21-7f7b-4517-9021-9ff1bab7a28c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3286671712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3286671712
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3352555355
Short name T346
Test name
Test status
Simulation time 4598888210 ps
CPU time 60.15 seconds
Started Mar 28 01:19:39 PM PDT 24
Finished Mar 28 01:20:40 PM PDT 24
Peak memory 200148 kb
Host smart-6124ff34-844c-4192-aaa3-10f4b136fe5a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352555355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3352555355
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1918609354
Short name T595
Test name
Test status
Simulation time 1502371207 ps
CPU time 20.5 seconds
Started Mar 28 01:19:43 PM PDT 24
Finished Mar 28 01:20:04 PM PDT 24
Peak memory 199984 kb
Host smart-2263fbc3-f906-4d67-b334-97ec762d97de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918609354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1918609354
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.1720267733
Short name T528
Test name
Test status
Simulation time 364512819 ps
CPU time 2.8 seconds
Started Mar 28 01:19:40 PM PDT 24
Finished Mar 28 01:19:42 PM PDT 24
Peak memory 200072 kb
Host smart-23cf6954-d42e-4e46-ad62-4db5d309996a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720267733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1720267733
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.335642035
Short name T85
Test name
Test status
Simulation time 335502689135 ps
CPU time 1224.57 seconds
Started Mar 28 01:19:38 PM PDT 24
Finished Mar 28 01:40:03 PM PDT 24
Peak memory 215748 kb
Host smart-195ca3ab-98fe-47e0-bc82-afa2c72af648
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335642035 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.335642035
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.3054115330
Short name T552
Test name
Test status
Simulation time 255052144 ps
CPU time 1.13 seconds
Started Mar 28 01:19:41 PM PDT 24
Finished Mar 28 01:19:43 PM PDT 24
Peak memory 199992 kb
Host smart-ccfdd4f6-1f7d-4081-81d2-6063a128cb56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054115330 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.3054115330
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.2892106227
Short name T173
Test name
Test status
Simulation time 33978500927 ps
CPU time 470.71 seconds
Started Mar 28 01:19:43 PM PDT 24
Finished Mar 28 01:27:34 PM PDT 24
Peak memory 200084 kb
Host smart-881d98a1-da1c-4108-a9ce-f64ee4c38045
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892106227 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.2892106227
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.750930291
Short name T457
Test name
Test status
Simulation time 4874069921 ps
CPU time 95.14 seconds
Started Mar 28 01:19:40 PM PDT 24
Finished Mar 28 01:21:16 PM PDT 24
Peak memory 200124 kb
Host smart-9bc9daf2-f72f-4a4b-8644-f1fb8974f98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750930291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.750930291
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.3574410378
Short name T22
Test name
Test status
Simulation time 60190801 ps
CPU time 0.6 seconds
Started Mar 28 01:19:54 PM PDT 24
Finished Mar 28 01:19:55 PM PDT 24
Peak memory 195580 kb
Host smart-8c65f128-db8b-414a-a0f2-d2b973b44796
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574410378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3574410378
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1703723334
Short name T20
Test name
Test status
Simulation time 908481261 ps
CPU time 17.01 seconds
Started Mar 28 01:19:54 PM PDT 24
Finished Mar 28 01:20:11 PM PDT 24
Peak memory 215948 kb
Host smart-1b5832ec-2630-42c4-be0d-7e9d4f773c24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1703723334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1703723334
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.370353828
Short name T542
Test name
Test status
Simulation time 11643612225 ps
CPU time 45.66 seconds
Started Mar 28 01:19:56 PM PDT 24
Finished Mar 28 01:20:42 PM PDT 24
Peak memory 200104 kb
Host smart-d86cede8-1d29-4baa-8b1d-1efae5bd423e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370353828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.370353828
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1180712591
Short name T323
Test name
Test status
Simulation time 620817118 ps
CPU time 39.72 seconds
Started Mar 28 01:19:54 PM PDT 24
Finished Mar 28 01:20:34 PM PDT 24
Peak memory 200096 kb
Host smart-4d550cc7-7aaa-4cbc-a861-00b63a501c9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1180712591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1180712591
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.2900314433
Short name T267
Test name
Test status
Simulation time 449474902 ps
CPU time 27.44 seconds
Started Mar 28 01:19:55 PM PDT 24
Finished Mar 28 01:20:22 PM PDT 24
Peak memory 200040 kb
Host smart-746e672a-202a-4245-a070-985137c66a3a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900314433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2900314433
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3889189498
Short name T461
Test name
Test status
Simulation time 8619559138 ps
CPU time 83.52 seconds
Started Mar 28 01:19:54 PM PDT 24
Finished Mar 28 01:21:18 PM PDT 24
Peak memory 200128 kb
Host smart-9db459c3-2131-46ff-b915-a966e958a5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889189498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3889189498
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3898782710
Short name T483
Test name
Test status
Simulation time 190030444 ps
CPU time 2.66 seconds
Started Mar 28 01:19:54 PM PDT 24
Finished Mar 28 01:19:57 PM PDT 24
Peak memory 200092 kb
Host smart-93e1f651-2cc4-4926-ae55-ebaff7d79050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898782710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3898782710
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.4184927979
Short name T82
Test name
Test status
Simulation time 111270405138 ps
CPU time 294.79 seconds
Started Mar 28 01:19:54 PM PDT 24
Finished Mar 28 01:24:50 PM PDT 24
Peak memory 200092 kb
Host smart-10ed31d5-6c2b-4d6b-8117-dd6bee78cf53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184927979 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.4184927979
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.229839704
Short name T147
Test name
Test status
Simulation time 88764819 ps
CPU time 1 seconds
Started Mar 28 01:19:56 PM PDT 24
Finished Mar 28 01:19:57 PM PDT 24
Peak memory 199584 kb
Host smart-9174130b-0c89-4835-95d0-ae066781ff33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229839704 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_hmac_vectors.229839704
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.3501694803
Short name T157
Test name
Test status
Simulation time 28498898892 ps
CPU time 407.15 seconds
Started Mar 28 01:19:54 PM PDT 24
Finished Mar 28 01:26:42 PM PDT 24
Peak memory 200048 kb
Host smart-9542fea9-2ec4-49b8-9260-a42380e36817
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501694803 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.3501694803
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.2654001669
Short name T36
Test name
Test status
Simulation time 1510398166 ps
CPU time 15.93 seconds
Started Mar 28 01:19:53 PM PDT 24
Finished Mar 28 01:20:09 PM PDT 24
Peak memory 200032 kb
Host smart-c8299384-4d26-4c76-9699-2d4dbde914ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654001669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2654001669
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.997060286
Short name T554
Test name
Test status
Simulation time 12692326 ps
CPU time 0.6 seconds
Started Mar 28 01:19:58 PM PDT 24
Finished Mar 28 01:19:59 PM PDT 24
Peak memory 195592 kb
Host smart-2759b348-b4c8-4181-b149-1c7824c41cf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997060286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.997060286
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.2899711661
Short name T178
Test name
Test status
Simulation time 1553691514 ps
CPU time 68.81 seconds
Started Mar 28 01:19:56 PM PDT 24
Finished Mar 28 01:21:05 PM PDT 24
Peak memory 224988 kb
Host smart-1b30b775-9730-4599-acb2-ce1b139a9d1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2899711661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2899711661
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2166926596
Short name T341
Test name
Test status
Simulation time 204017717 ps
CPU time 9.83 seconds
Started Mar 28 01:19:55 PM PDT 24
Finished Mar 28 01:20:05 PM PDT 24
Peak memory 199908 kb
Host smart-2d4e686b-17af-47d9-8a36-827ea7b8b422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166926596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2166926596
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3637307724
Short name T363
Test name
Test status
Simulation time 12402953235 ps
CPU time 194.31 seconds
Started Mar 28 01:19:56 PM PDT 24
Finished Mar 28 01:23:11 PM PDT 24
Peak memory 200184 kb
Host smart-d7462dee-d769-4da3-8320-1218470c3617
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3637307724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3637307724
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2746454243
Short name T374
Test name
Test status
Simulation time 107553070708 ps
CPU time 158.53 seconds
Started Mar 28 01:19:55 PM PDT 24
Finished Mar 28 01:22:34 PM PDT 24
Peak memory 200124 kb
Host smart-aa40ae60-9ade-4ce0-86eb-f5b6840345b0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746454243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2746454243
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1675470153
Short name T135
Test name
Test status
Simulation time 1002231868 ps
CPU time 31.47 seconds
Started Mar 28 01:19:55 PM PDT 24
Finished Mar 28 01:20:27 PM PDT 24
Peak memory 200036 kb
Host smart-8dee6eb6-921a-4255-b3de-581694467d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675470153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1675470153
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.1295354033
Short name T401
Test name
Test status
Simulation time 4502972890 ps
CPU time 5.16 seconds
Started Mar 28 01:19:55 PM PDT 24
Finished Mar 28 01:20:00 PM PDT 24
Peak memory 200080 kb
Host smart-fe88927c-2a4f-4ae5-8d79-8207a0415846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295354033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1295354033
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2000489769
Short name T311
Test name
Test status
Simulation time 34118312867 ps
CPU time 861.12 seconds
Started Mar 28 01:19:54 PM PDT 24
Finished Mar 28 01:34:16 PM PDT 24
Peak memory 216508 kb
Host smart-9dc92655-6e69-4241-ade6-44a4b5d592f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000489769 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2000489769
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.4275409255
Short name T278
Test name
Test status
Simulation time 62829415 ps
CPU time 1.23 seconds
Started Mar 28 01:19:58 PM PDT 24
Finished Mar 28 01:19:59 PM PDT 24
Peak memory 200028 kb
Host smart-3b59096f-1aa6-4343-88f8-fef5c97245bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275409255 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.4275409255
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.2262599916
Short name T389
Test name
Test status
Simulation time 8959652401 ps
CPU time 532.28 seconds
Started Mar 28 01:19:55 PM PDT 24
Finished Mar 28 01:28:48 PM PDT 24
Peak memory 200100 kb
Host smart-55676e6e-cc81-4de5-8870-74b64fbc31f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262599916 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.2262599916
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1937235711
Short name T366
Test name
Test status
Simulation time 2512472836 ps
CPU time 35.95 seconds
Started Mar 28 01:19:55 PM PDT 24
Finished Mar 28 01:20:31 PM PDT 24
Peak memory 200120 kb
Host smart-12bff72a-7b2c-4f31-a141-297f4f7d87d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937235711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1937235711
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3353530642
Short name T73
Test name
Test status
Simulation time 28171433 ps
CPU time 0.55 seconds
Started Mar 28 01:19:59 PM PDT 24
Finished Mar 28 01:20:00 PM PDT 24
Peak memory 195568 kb
Host smart-985314e2-2327-4e3c-846a-ab1b3f9f3e2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353530642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3353530642
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.503702404
Short name T204
Test name
Test status
Simulation time 3572420051 ps
CPU time 32.36 seconds
Started Mar 28 01:19:57 PM PDT 24
Finished Mar 28 01:20:30 PM PDT 24
Peak memory 208300 kb
Host smart-e6b6aedd-8ab8-4e97-9da9-c759d6da0fd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=503702404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.503702404
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3573909052
Short name T533
Test name
Test status
Simulation time 2162141837 ps
CPU time 55.92 seconds
Started Mar 28 01:19:58 PM PDT 24
Finished Mar 28 01:20:54 PM PDT 24
Peak memory 200192 kb
Host smart-133efbd7-4e23-402a-a16e-e880177cc981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573909052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3573909052
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.416849863
Short name T582
Test name
Test status
Simulation time 1474115287 ps
CPU time 91.18 seconds
Started Mar 28 01:19:57 PM PDT 24
Finished Mar 28 01:21:28 PM PDT 24
Peak memory 200084 kb
Host smart-561a0302-521c-4e55-8751-6b1d11d65777
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=416849863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.416849863
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.3386626175
Short name T163
Test name
Test status
Simulation time 3105374061 ps
CPU time 89.87 seconds
Started Mar 28 01:19:59 PM PDT 24
Finished Mar 28 01:21:29 PM PDT 24
Peak memory 200204 kb
Host smart-f6410f18-e41b-4c2d-8f86-fb4cdddfb43b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386626175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3386626175
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.4081782781
Short name T496
Test name
Test status
Simulation time 19532341015 ps
CPU time 43.45 seconds
Started Mar 28 01:19:55 PM PDT 24
Finished Mar 28 01:20:38 PM PDT 24
Peak memory 200164 kb
Host smart-8a92ce34-2aae-4bbb-8a70-cb3aa42545ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081782781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.4081782781
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2472178502
Short name T6
Test name
Test status
Simulation time 726691933 ps
CPU time 2.83 seconds
Started Mar 28 01:19:55 PM PDT 24
Finished Mar 28 01:19:58 PM PDT 24
Peak memory 200024 kb
Host smart-121800b7-93d5-48c5-aa59-0d4192ffa10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472178502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2472178502
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3653100039
Short name T236
Test name
Test status
Simulation time 23384100290 ps
CPU time 1225.5 seconds
Started Mar 28 01:19:59 PM PDT 24
Finished Mar 28 01:40:25 PM PDT 24
Peak memory 215724 kb
Host smart-0a401f16-9bc4-4d3f-b7bf-34f179f9c421
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653100039 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3653100039
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.1881336646
Short name T197
Test name
Test status
Simulation time 33195938 ps
CPU time 1.11 seconds
Started Mar 28 01:19:55 PM PDT 24
Finished Mar 28 01:19:57 PM PDT 24
Peak memory 198644 kb
Host smart-b91e2608-68ba-49a7-99b8-c3640f112b58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881336646 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.1881336646
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.799433923
Short name T371
Test name
Test status
Simulation time 101097555859 ps
CPU time 474.16 seconds
Started Mar 28 01:19:59 PM PDT 24
Finished Mar 28 01:27:54 PM PDT 24
Peak memory 200152 kb
Host smart-1123fa20-5072-40c8-a7fc-d4701e5ff296
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799433923 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.799433923
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.968549813
Short name T213
Test name
Test status
Simulation time 1177999492 ps
CPU time 23.88 seconds
Started Mar 28 01:19:59 PM PDT 24
Finished Mar 28 01:20:23 PM PDT 24
Peak memory 200140 kb
Host smart-78a836f2-1098-486d-bee4-1d004147fc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968549813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.968549813
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.4019253445
Short name T229
Test name
Test status
Simulation time 14028307 ps
CPU time 0.6 seconds
Started Mar 28 01:20:08 PM PDT 24
Finished Mar 28 01:20:09 PM PDT 24
Peak memory 195500 kb
Host smart-c804639a-65ad-4bbe-907a-ea6767d6ca45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019253445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.4019253445
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.1899629434
Short name T547
Test name
Test status
Simulation time 796073227 ps
CPU time 6.82 seconds
Started Mar 28 01:20:10 PM PDT 24
Finished Mar 28 01:20:17 PM PDT 24
Peak memory 200072 kb
Host smart-e50b6d02-4b95-4ae0-89d7-a5f24b142f73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1899629434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.1899629434
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.1561790249
Short name T465
Test name
Test status
Simulation time 6756421354 ps
CPU time 36.29 seconds
Started Mar 28 01:20:07 PM PDT 24
Finished Mar 28 01:20:44 PM PDT 24
Peak memory 200100 kb
Host smart-2ab98ece-94dc-43d1-a8ba-80e6627a2b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561790249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.1561790249
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3836511818
Short name T387
Test name
Test status
Simulation time 195942056 ps
CPU time 3.05 seconds
Started Mar 28 01:20:09 PM PDT 24
Finished Mar 28 01:20:12 PM PDT 24
Peak memory 200052 kb
Host smart-40c072fd-0d29-48da-abb9-9b291c2a5b33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3836511818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3836511818
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1822516129
Short name T51
Test name
Test status
Simulation time 6437449610 ps
CPU time 86.31 seconds
Started Mar 28 01:20:08 PM PDT 24
Finished Mar 28 01:21:35 PM PDT 24
Peak memory 200056 kb
Host smart-74a6dbe1-81e9-46de-b68c-2a808982b5cd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822516129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1822516129
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.625232800
Short name T225
Test name
Test status
Simulation time 11977119527 ps
CPU time 85.29 seconds
Started Mar 28 01:20:07 PM PDT 24
Finished Mar 28 01:21:33 PM PDT 24
Peak memory 200092 kb
Host smart-66129c81-8a61-4ecc-ac9f-13e9b259d823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625232800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.625232800
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1808578472
Short name T149
Test name
Test status
Simulation time 610063525 ps
CPU time 6.58 seconds
Started Mar 28 01:19:58 PM PDT 24
Finished Mar 28 01:20:05 PM PDT 24
Peak memory 199944 kb
Host smart-38982962-d346-472d-b47c-4895d9b8b999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808578472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1808578472
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.208469741
Short name T289
Test name
Test status
Simulation time 17822724358 ps
CPU time 125.22 seconds
Started Mar 28 01:20:09 PM PDT 24
Finished Mar 28 01:22:14 PM PDT 24
Peak memory 200096 kb
Host smart-797632fc-99f5-43ec-928d-af894a0f6e09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208469741 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.208469741
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.2355814460
Short name T340
Test name
Test status
Simulation time 78329405 ps
CPU time 1.04 seconds
Started Mar 28 01:20:10 PM PDT 24
Finished Mar 28 01:20:11 PM PDT 24
Peak memory 199672 kb
Host smart-784f67dd-1ac0-4c0c-9687-5d79f7121fa2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355814460 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.2355814460
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.96351153
Short name T555
Test name
Test status
Simulation time 12526520296 ps
CPU time 407.25 seconds
Started Mar 28 01:20:09 PM PDT 24
Finished Mar 28 01:26:57 PM PDT 24
Peak memory 200092 kb
Host smart-d7c3b360-4cc8-4a0a-a3ca-c75eb24d1068
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96351153 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.96351153
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3389636829
Short name T284
Test name
Test status
Simulation time 2384710499 ps
CPU time 34.25 seconds
Started Mar 28 01:20:08 PM PDT 24
Finished Mar 28 01:20:43 PM PDT 24
Peak memory 200156 kb
Host smart-0ce50b0a-b71d-4763-8f60-3c3ff42528e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389636829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3389636829
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2928016606
Short name T478
Test name
Test status
Simulation time 35458279 ps
CPU time 0.59 seconds
Started Mar 28 01:20:08 PM PDT 24
Finished Mar 28 01:20:09 PM PDT 24
Peak memory 195500 kb
Host smart-191be1f4-34c7-41cc-ba4d-5f19ec5ba474
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928016606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2928016606
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.601900843
Short name T356
Test name
Test status
Simulation time 1499555340 ps
CPU time 29.97 seconds
Started Mar 28 01:20:10 PM PDT 24
Finished Mar 28 01:20:40 PM PDT 24
Peak memory 232820 kb
Host smart-412ecee9-668e-4f16-9935-43363b728f1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=601900843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.601900843
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3420357475
Short name T583
Test name
Test status
Simulation time 3312325496 ps
CPU time 42.35 seconds
Started Mar 28 01:20:09 PM PDT 24
Finished Mar 28 01:20:52 PM PDT 24
Peak memory 200172 kb
Host smart-af4f7f91-b145-4d28-bbdd-19aa16071af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420357475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3420357475
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.1075508967
Short name T549
Test name
Test status
Simulation time 2023363555 ps
CPU time 31.77 seconds
Started Mar 28 01:20:10 PM PDT 24
Finished Mar 28 01:20:42 PM PDT 24
Peak memory 200092 kb
Host smart-fb2a9c5d-33ec-4b83-bd99-e493ee6bdc90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1075508967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1075508967
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2976117721
Short name T395
Test name
Test status
Simulation time 3116760096 ps
CPU time 73.09 seconds
Started Mar 28 01:20:09 PM PDT 24
Finished Mar 28 01:21:22 PM PDT 24
Peak memory 200112 kb
Host smart-8ba51345-4afa-4078-8c1f-010baa9d32aa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976117721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2976117721
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.321751617
Short name T399
Test name
Test status
Simulation time 9653453861 ps
CPU time 30.02 seconds
Started Mar 28 01:20:07 PM PDT 24
Finished Mar 28 01:20:37 PM PDT 24
Peak memory 200168 kb
Host smart-c5d0fda0-d3dd-498b-b349-f75d3514b35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321751617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.321751617
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.1194295356
Short name T42
Test name
Test status
Simulation time 215967803 ps
CPU time 6.83 seconds
Started Mar 28 01:20:07 PM PDT 24
Finished Mar 28 01:20:14 PM PDT 24
Peak memory 200052 kb
Host smart-1123c8bb-f145-43f0-bdcc-fe050d559472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194295356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1194295356
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.3466650938
Short name T146
Test name
Test status
Simulation time 35986354235 ps
CPU time 342.72 seconds
Started Mar 28 01:20:09 PM PDT 24
Finished Mar 28 01:25:51 PM PDT 24
Peak memory 200080 kb
Host smart-7ada7f1b-3153-4fbc-a60c-30aec1c83eb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466650938 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.3466650938
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.920328911
Short name T535
Test name
Test status
Simulation time 29314117 ps
CPU time 0.98 seconds
Started Mar 28 01:20:08 PM PDT 24
Finished Mar 28 01:20:09 PM PDT 24
Peak memory 199936 kb
Host smart-5d5cce71-4c69-42be-816a-466cb6cda158
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920328911 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_hmac_vectors.920328911
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.2760782815
Short name T2
Test name
Test status
Simulation time 158013223308 ps
CPU time 455.93 seconds
Started Mar 28 01:20:08 PM PDT 24
Finished Mar 28 01:27:45 PM PDT 24
Peak memory 200104 kb
Host smart-65caf0ab-f080-4100-8798-25c149e2e46f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760782815 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.2760782815
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3446346691
Short name T365
Test name
Test status
Simulation time 1036029205 ps
CPU time 47.65 seconds
Started Mar 28 01:20:09 PM PDT 24
Finished Mar 28 01:20:57 PM PDT 24
Peak memory 200028 kb
Host smart-37c8f1b4-5f7c-4b96-8afd-c7a11cfa1485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446346691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3446346691
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.472664679
Short name T485
Test name
Test status
Simulation time 88627598 ps
CPU time 0.58 seconds
Started Mar 28 01:15:48 PM PDT 24
Finished Mar 28 01:15:50 PM PDT 24
Peak memory 194556 kb
Host smart-da824842-7c1e-4c4b-929a-9ef93290a278
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472664679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.472664679
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1507329812
Short name T285
Test name
Test status
Simulation time 1104595267 ps
CPU time 37.93 seconds
Started Mar 28 01:15:46 PM PDT 24
Finished Mar 28 01:16:24 PM PDT 24
Peak memory 208280 kb
Host smart-3063de87-e491-4312-8609-ef91640427ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1507329812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1507329812
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3484161213
Short name T19
Test name
Test status
Simulation time 748369444 ps
CPU time 40.73 seconds
Started Mar 28 01:15:47 PM PDT 24
Finished Mar 28 01:16:30 PM PDT 24
Peak memory 200068 kb
Host smart-fc43d643-8e20-4976-b0a0-0eede86ee586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484161213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3484161213
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1804351244
Short name T168
Test name
Test status
Simulation time 1992648109 ps
CPU time 29.51 seconds
Started Mar 28 01:15:47 PM PDT 24
Finished Mar 28 01:16:19 PM PDT 24
Peak memory 200040 kb
Host smart-ece850c3-4777-4834-98cc-7cce7cc2fb10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1804351244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1804351244
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.458227732
Short name T227
Test name
Test status
Simulation time 4017911417 ps
CPU time 56.16 seconds
Started Mar 28 01:15:47 PM PDT 24
Finished Mar 28 01:16:45 PM PDT 24
Peak memory 199980 kb
Host smart-00ee3c4f-4e9b-4398-abf8-8ac0a78a9084
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458227732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.458227732
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.2051354474
Short name T216
Test name
Test status
Simulation time 3032283326 ps
CPU time 42.28 seconds
Started Mar 28 01:15:45 PM PDT 24
Finished Mar 28 01:16:27 PM PDT 24
Peak memory 200152 kb
Host smart-6a3a66ef-eaba-4eb7-a028-613b15ee1d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051354474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.2051354474
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1518368779
Short name T409
Test name
Test status
Simulation time 158248974 ps
CPU time 4.66 seconds
Started Mar 28 01:15:45 PM PDT 24
Finished Mar 28 01:15:50 PM PDT 24
Peak memory 200024 kb
Host smart-1a68d2ca-0398-4074-a406-6a5d871b0ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518368779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1518368779
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.2514580885
Short name T58
Test name
Test status
Simulation time 97605716413 ps
CPU time 1549.17 seconds
Started Mar 28 01:15:47 PM PDT 24
Finished Mar 28 01:41:38 PM PDT 24
Peak memory 208364 kb
Host smart-e1844a4f-8eef-4435-814c-7ce1bca4541d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514580885 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.2514580885
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.2786961402
Short name T474
Test name
Test status
Simulation time 145080283 ps
CPU time 1.26 seconds
Started Mar 28 01:15:45 PM PDT 24
Finished Mar 28 01:15:46 PM PDT 24
Peak memory 200036 kb
Host smart-e96646f2-2577-4a17-9b9e-dd7afb907a17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786961402 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.2786961402
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.2483205060
Short name T141
Test name
Test status
Simulation time 24050853285 ps
CPU time 435.99 seconds
Started Mar 28 01:15:46 PM PDT 24
Finished Mar 28 01:23:02 PM PDT 24
Peak memory 200080 kb
Host smart-b544ce11-1855-48da-83ec-fa8963c9afd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483205060 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.2483205060
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.1280115848
Short name T575
Test name
Test status
Simulation time 17582359958 ps
CPU time 66.3 seconds
Started Mar 28 01:15:48 PM PDT 24
Finished Mar 28 01:16:56 PM PDT 24
Peak memory 200160 kb
Host smart-f2972b24-b4eb-4a10-88c0-5b081563910c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280115848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.1280115848
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.305963927
Short name T557
Test name
Test status
Simulation time 45071881 ps
CPU time 0.64 seconds
Started Mar 28 01:16:03 PM PDT 24
Finished Mar 28 01:16:05 PM PDT 24
Peak memory 195452 kb
Host smart-112e919b-8458-404e-8dbe-3518c48feb9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305963927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.305963927
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.4232292564
Short name T520
Test name
Test status
Simulation time 490666863 ps
CPU time 13.04 seconds
Started Mar 28 01:15:47 PM PDT 24
Finished Mar 28 01:16:02 PM PDT 24
Peak memory 208228 kb
Host smart-7d877d7a-6b6e-4097-b5d4-594ea4b85311
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4232292564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.4232292564
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.695235525
Short name T594
Test name
Test status
Simulation time 788764137 ps
CPU time 41.22 seconds
Started Mar 28 01:15:46 PM PDT 24
Finished Mar 28 01:16:27 PM PDT 24
Peak memory 200076 kb
Host smart-144193ff-d9b3-4f57-a921-381b13ed6b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695235525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.695235525
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1775803262
Short name T44
Test name
Test status
Simulation time 1508596944 ps
CPU time 32.62 seconds
Started Mar 28 01:15:46 PM PDT 24
Finished Mar 28 01:16:18 PM PDT 24
Peak memory 200080 kb
Host smart-e25d795c-7873-49f3-a281-170be31d395a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1775803262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1775803262
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3429495982
Short name T185
Test name
Test status
Simulation time 9130320284 ps
CPU time 87.77 seconds
Started Mar 28 01:15:47 PM PDT 24
Finished Mar 28 01:17:17 PM PDT 24
Peak memory 200152 kb
Host smart-604a8ddc-d2a9-4ee9-8198-5d5138d82a26
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429495982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3429495982
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3364498044
Short name T177
Test name
Test status
Simulation time 1828009318 ps
CPU time 28.12 seconds
Started Mar 28 01:15:45 PM PDT 24
Finished Mar 28 01:16:13 PM PDT 24
Peak memory 200092 kb
Host smart-0195c727-7404-4c53-8a35-62c05d563992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364498044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3364498044
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.492455564
Short name T394
Test name
Test status
Simulation time 524140135 ps
CPU time 2.84 seconds
Started Mar 28 01:15:45 PM PDT 24
Finished Mar 28 01:15:48 PM PDT 24
Peak memory 199972 kb
Host smart-b0fc4dcb-664e-4932-a2fe-4b930bd65be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492455564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.492455564
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.1406768901
Short name T569
Test name
Test status
Simulation time 1144006710 ps
CPU time 23.86 seconds
Started Mar 28 01:16:00 PM PDT 24
Finished Mar 28 01:16:25 PM PDT 24
Peak memory 200068 kb
Host smart-af25ee3f-53c8-462f-8ecf-216da1b96505
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406768901 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1406768901
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.4203969449
Short name T564
Test name
Test status
Simulation time 43975447 ps
CPU time 1.23 seconds
Started Mar 28 01:16:02 PM PDT 24
Finished Mar 28 01:16:04 PM PDT 24
Peak memory 199412 kb
Host smart-803c6fa6-5fee-4317-911d-337b21f3bb46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203969449 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.4203969449
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.3664767657
Short name T74
Test name
Test status
Simulation time 40137952226 ps
CPU time 493.46 seconds
Started Mar 28 01:16:01 PM PDT 24
Finished Mar 28 01:24:15 PM PDT 24
Peak memory 200040 kb
Host smart-f630c36f-a902-484d-9acd-0ea7b4d57f14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664767657 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.3664767657
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.3648549046
Short name T501
Test name
Test status
Simulation time 2427685307 ps
CPU time 39.75 seconds
Started Mar 28 01:15:47 PM PDT 24
Finished Mar 28 01:16:29 PM PDT 24
Peak memory 200176 kb
Host smart-3366e740-08ad-40b3-9536-2cad2f06e346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648549046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3648549046
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/63.hmac_stress_all_with_rand_reset.2433990287
Short name T53
Test name
Test status
Simulation time 5423733089 ps
CPU time 305.19 seconds
Started Mar 28 01:20:24 PM PDT 24
Finished Mar 28 01:25:30 PM PDT 24
Peak memory 216556 kb
Host smart-5c05b32e-a93c-46aa-9281-724339a34212
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2433990287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.hmac_stress_all_with_rand_reset.2433990287
Directory /workspace/63.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.23537885
Short name T357
Test name
Test status
Simulation time 13247901 ps
CPU time 0.57 seconds
Started Mar 28 01:16:04 PM PDT 24
Finished Mar 28 01:16:05 PM PDT 24
Peak memory 195568 kb
Host smart-edb0da5b-96d1-4ecd-9306-4b0898a03aba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23537885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.23537885
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1539785122
Short name T497
Test name
Test status
Simulation time 405006997 ps
CPU time 18.67 seconds
Started Mar 28 01:16:01 PM PDT 24
Finished Mar 28 01:16:21 PM PDT 24
Peak memory 240964 kb
Host smart-17711dc5-8918-4793-8413-b3477e31fe92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1539785122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1539785122
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3131598291
Short name T158
Test name
Test status
Simulation time 1322601914 ps
CPU time 14.16 seconds
Started Mar 28 01:16:01 PM PDT 24
Finished Mar 28 01:16:15 PM PDT 24
Peak memory 199940 kb
Host smart-44d32f27-c5ec-48d5-8243-e7425aa415fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131598291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3131598291
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2239671910
Short name T532
Test name
Test status
Simulation time 3538803719 ps
CPU time 99.3 seconds
Started Mar 28 01:16:01 PM PDT 24
Finished Mar 28 01:17:41 PM PDT 24
Peak memory 200144 kb
Host smart-91c5574d-162c-40bc-b5c1-70dc7ddc0a18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2239671910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2239671910
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2640954873
Short name T97
Test name
Test status
Simulation time 1294444034 ps
CPU time 66.76 seconds
Started Mar 28 01:16:02 PM PDT 24
Finished Mar 28 01:17:09 PM PDT 24
Peak memory 200076 kb
Host smart-53426865-af2e-4f31-931f-4f179ae6d417
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640954873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2640954873
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.4283809956
Short name T517
Test name
Test status
Simulation time 3616260812 ps
CPU time 68.5 seconds
Started Mar 28 01:16:01 PM PDT 24
Finished Mar 28 01:17:10 PM PDT 24
Peak memory 200036 kb
Host smart-4c1a9baf-8bd5-401d-a878-6de7111c6774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283809956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.4283809956
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.3736065267
Short name T378
Test name
Test status
Simulation time 309022963 ps
CPU time 2.52 seconds
Started Mar 28 01:16:00 PM PDT 24
Finished Mar 28 01:16:04 PM PDT 24
Peak memory 200032 kb
Host smart-e8c40d0d-0179-4fbd-9897-7e1d0699ba2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736065267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3736065267
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1535758729
Short name T83
Test name
Test status
Simulation time 25602425998 ps
CPU time 334.21 seconds
Started Mar 28 01:16:03 PM PDT 24
Finished Mar 28 01:21:39 PM PDT 24
Peak memory 200120 kb
Host smart-2e106359-cae9-428b-af81-95d1d91daab2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535758729 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1535758729
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.3561695894
Short name T499
Test name
Test status
Simulation time 31267327 ps
CPU time 1.28 seconds
Started Mar 28 01:16:03 PM PDT 24
Finished Mar 28 01:16:04 PM PDT 24
Peak memory 200012 kb
Host smart-b59d7e04-8ed6-4f87-bf1c-760762370ddd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561695894 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.3561695894
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.445553807
Short name T75
Test name
Test status
Simulation time 7471096838 ps
CPU time 392.87 seconds
Started Mar 28 01:16:02 PM PDT 24
Finished Mar 28 01:22:36 PM PDT 24
Peak memory 200088 kb
Host smart-91419e4d-aa63-446b-a69e-23d9df0efe2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445553807 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.445553807
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.3598820877
Short name T459
Test name
Test status
Simulation time 3004729848 ps
CPU time 57.29 seconds
Started Mar 28 01:16:03 PM PDT 24
Finished Mar 28 01:17:00 PM PDT 24
Peak memory 200088 kb
Host smart-5342df54-a01b-400a-91b7-c552bcdcc54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598820877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3598820877
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/78.hmac_stress_all_with_rand_reset.1038706944
Short name T68
Test name
Test status
Simulation time 102581127841 ps
CPU time 734.24 seconds
Started Mar 28 01:20:25 PM PDT 24
Finished Mar 28 01:32:40 PM PDT 24
Peak memory 216612 kb
Host smart-2c3271fc-e14e-45fc-b489-254554b4eebb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1038706944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.hmac_stress_all_with_rand_reset.1038706944
Directory /workspace/78.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3350201585
Short name T500
Test name
Test status
Simulation time 15211480 ps
CPU time 0.61 seconds
Started Mar 28 01:16:03 PM PDT 24
Finished Mar 28 01:16:05 PM PDT 24
Peak memory 195608 kb
Host smart-5bf5d4f6-5645-4da0-9d9c-44656efd43c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350201585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3350201585
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2595260164
Short name T568
Test name
Test status
Simulation time 7516248454 ps
CPU time 58.2 seconds
Started Mar 28 01:16:05 PM PDT 24
Finished Mar 28 01:17:03 PM PDT 24
Peak memory 220460 kb
Host smart-6a66af3a-9d87-4b85-8557-43e7cbd3f2d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2595260164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2595260164
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2521806799
Short name T351
Test name
Test status
Simulation time 11157598906 ps
CPU time 28.33 seconds
Started Mar 28 01:16:04 PM PDT 24
Finished Mar 28 01:16:33 PM PDT 24
Peak memory 200096 kb
Host smart-bd22dae9-9871-47e2-9350-314ae96f3162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521806799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2521806799
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3764844584
Short name T373
Test name
Test status
Simulation time 937100482 ps
CPU time 29.3 seconds
Started Mar 28 01:16:04 PM PDT 24
Finished Mar 28 01:16:34 PM PDT 24
Peak memory 200132 kb
Host smart-5ed12d61-3406-49c2-9311-ad721d5d631a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3764844584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3764844584
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.455720529
Short name T385
Test name
Test status
Simulation time 12163217546 ps
CPU time 164.63 seconds
Started Mar 28 01:16:03 PM PDT 24
Finished Mar 28 01:18:49 PM PDT 24
Peak memory 200116 kb
Host smart-bbd8aa4b-eae1-4a22-956b-cd2787aa506d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455720529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.455720529
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3571010311
Short name T137
Test name
Test status
Simulation time 6658240050 ps
CPU time 81.37 seconds
Started Mar 28 01:16:04 PM PDT 24
Finished Mar 28 01:17:26 PM PDT 24
Peak memory 200172 kb
Host smart-cb4fbe4c-7710-404e-9cdd-5c92e29d9ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571010311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3571010311
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1363594610
Short name T516
Test name
Test status
Simulation time 894706836 ps
CPU time 4.92 seconds
Started Mar 28 01:16:03 PM PDT 24
Finished Mar 28 01:16:10 PM PDT 24
Peak memory 200076 kb
Host smart-0fd6b4ab-9be0-4238-8bbd-a0f45973e1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363594610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1363594610
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2367138332
Short name T599
Test name
Test status
Simulation time 11793821283 ps
CPU time 36.13 seconds
Started Mar 28 01:16:04 PM PDT 24
Finished Mar 28 01:16:41 PM PDT 24
Peak memory 200100 kb
Host smart-2f226eb0-b6e3-498e-95e3-b68377b823bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367138332 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2367138332
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.2774361923
Short name T156
Test name
Test status
Simulation time 28899429 ps
CPU time 1.15 seconds
Started Mar 28 01:16:04 PM PDT 24
Finished Mar 28 01:16:06 PM PDT 24
Peak memory 199856 kb
Host smart-93308d4f-418b-4298-a33c-c9f9c7f364a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774361923 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.2774361923
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.129743570
Short name T169
Test name
Test status
Simulation time 159243159082 ps
CPU time 452.66 seconds
Started Mar 28 01:16:03 PM PDT 24
Finished Mar 28 01:23:38 PM PDT 24
Peak memory 200124 kb
Host smart-d78f58b2-f3a5-4691-819e-67e63ca0ce39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129743570 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.129743570
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.21270588
Short name T176
Test name
Test status
Simulation time 1042773450 ps
CPU time 17.25 seconds
Started Mar 28 01:16:04 PM PDT 24
Finished Mar 28 01:16:22 PM PDT 24
Peak memory 200020 kb
Host smart-efc6e996-0bad-43ee-9e1e-3f7a17fa3017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21270588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.21270588
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/88.hmac_stress_all_with_rand_reset.4084653258
Short name T403
Test name
Test status
Simulation time 54042872162 ps
CPU time 727.17 seconds
Started Mar 28 01:20:45 PM PDT 24
Finished Mar 28 01:32:52 PM PDT 24
Peak memory 226824 kb
Host smart-08eab8c6-2ba5-42bc-922b-2ca53c11eab7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4084653258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.hmac_stress_all_with_rand_reset.4084653258
Directory /workspace/88.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1155850101
Short name T396
Test name
Test status
Simulation time 19373391 ps
CPU time 0.6 seconds
Started Mar 28 01:16:18 PM PDT 24
Finished Mar 28 01:16:18 PM PDT 24
Peak memory 195468 kb
Host smart-7218d0bd-7388-4374-bb3b-6c024dcbbf17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155850101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1155850101
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.4005947683
Short name T287
Test name
Test status
Simulation time 1340110109 ps
CPU time 57.18 seconds
Started Mar 28 01:16:20 PM PDT 24
Finished Mar 28 01:17:18 PM PDT 24
Peak memory 226076 kb
Host smart-90316a76-4641-43eb-bf9b-e8faf37a7636
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4005947683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.4005947683
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3174492452
Short name T29
Test name
Test status
Simulation time 4795495541 ps
CPU time 17.39 seconds
Started Mar 28 01:16:23 PM PDT 24
Finished Mar 28 01:16:40 PM PDT 24
Peak memory 200008 kb
Host smart-0b6d5581-4a54-4a31-b93e-31e66edbc88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174492452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3174492452
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.2745087806
Short name T59
Test name
Test status
Simulation time 2543796520 ps
CPU time 156.44 seconds
Started Mar 28 01:16:17 PM PDT 24
Finished Mar 28 01:18:54 PM PDT 24
Peak memory 200136 kb
Host smart-d7c7ee71-0cb4-48a2-8355-7e9e3ad8a29a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2745087806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2745087806
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.2800611910
Short name T438
Test name
Test status
Simulation time 31637847621 ps
CPU time 200.63 seconds
Started Mar 28 01:16:18 PM PDT 24
Finished Mar 28 01:19:38 PM PDT 24
Peak memory 200116 kb
Host smart-5c388f3d-c3ac-4467-b66a-feb0a75726cc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800611910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2800611910
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.1329872644
Short name T426
Test name
Test status
Simulation time 93245449701 ps
CPU time 64.44 seconds
Started Mar 28 01:16:22 PM PDT 24
Finished Mar 28 01:17:27 PM PDT 24
Peak memory 200032 kb
Host smart-4953f4e6-117d-47ec-8624-0999e189cb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329872644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1329872644
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3082529071
Short name T244
Test name
Test status
Simulation time 235756388 ps
CPU time 3.3 seconds
Started Mar 28 01:16:16 PM PDT 24
Finished Mar 28 01:16:20 PM PDT 24
Peak memory 200072 kb
Host smart-baf04a08-59d8-4853-b18e-2bf00e97bf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082529071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3082529071
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.4227951090
Short name T347
Test name
Test status
Simulation time 45922546187 ps
CPU time 614.09 seconds
Started Mar 28 01:16:18 PM PDT 24
Finished Mar 28 01:26:32 PM PDT 24
Peak memory 208308 kb
Host smart-5572385c-a6cc-44ba-adcb-1ece9cc16906
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227951090 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.4227951090
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.1878792592
Short name T591
Test name
Test status
Simulation time 193602567124 ps
CPU time 973.23 seconds
Started Mar 28 01:16:22 PM PDT 24
Finished Mar 28 01:32:36 PM PDT 24
Peak memory 241112 kb
Host smart-35bd3cfd-817b-42f2-9cd1-7bd2e498b59c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1878792592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.1878792592
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.887464034
Short name T4
Test name
Test status
Simulation time 43878603 ps
CPU time 1.05 seconds
Started Mar 28 01:16:17 PM PDT 24
Finished Mar 28 01:16:18 PM PDT 24
Peak memory 199612 kb
Host smart-1db5b2fc-c2f1-41fc-bd07-f75b3342e6f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887464034 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.hmac_test_hmac_vectors.887464034
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.3995927443
Short name T263
Test name
Test status
Simulation time 27024038254 ps
CPU time 559.5 seconds
Started Mar 28 01:16:16 PM PDT 24
Finished Mar 28 01:25:35 PM PDT 24
Peak memory 200064 kb
Host smart-206421ac-8a96-4d1e-bcf4-7c68b0e52334
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995927443 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.3995927443
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.1527041133
Short name T375
Test name
Test status
Simulation time 20501589063 ps
CPU time 73.29 seconds
Started Mar 28 01:16:17 PM PDT 24
Finished Mar 28 01:17:30 PM PDT 24
Peak memory 200156 kb
Host smart-7fa8f05b-b644-43fd-9f51-c3762a2cf94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527041133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1527041133
Directory /workspace/9.hmac_wipe_secret/latest
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