Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	12943630	1			T1	115		T3	6722		T4	9903
all_values[1]	12943630	1			T1	115		T3	6722		T4	9903
all_values[2]	12943630	1			T1	115		T3	6722		T4	9903

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101078

1

T1

15

T4

489

T5

51

auto[1]

38729812

1

T1

330

T3

20166

T4

29220

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36661502

1

T1

330

T3

20153

T4

29669

auto[1]

2169388

1

T1

15

T3

13

T4

40

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	35093	1			T4	88		T5	33		T8	311
all_values[0]	auto[0]	auto[1]	411	1			T4	2		T5	7		T8	4
all_values[0]	auto[1]	auto[0]	12865628	1			T1	100		T3	6709		T4	9775
all_values[0]	auto[1]	auto[1]	42498	1			T1	15		T3	13		T4	38
all_values[1]	auto[0]	auto[0]	33009	1			T1	15		T4	309		T5	1
all_values[1]	auto[0]	auto[1]	179	1			T5	1		T9	1		T13	1
all_values[1]	auto[1]	auto[0]	12910112	1			T1	100		T3	6722		T4	9594
all_values[1]	auto[1]	auto[1]	330	1			T5	3		T13	1		T14	4
all_values[2]	auto[0]	auto[0]	28331	1			T4	90		T5	9		T9	4
all_values[2]	auto[0]	auto[1]	4055	1			T13	2		T14	2		T63	2
all_values[2]	auto[1]	auto[0]	10789329	1			T1	115		T3	6722		T4	9813
all_values[2]	auto[1]	auto[1]	2121915	1			T18	8634		T9	7053		T17	2348