Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6078643

1

T1

555

T3

4093

T4

4850

auto[1]

2186003

1

T1

96

T3

2599

T4

4962

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2157708

1

T1

262

T3

2859

T4

6089

auto[1]

6106938

1

T1

389

T3

3833

T4

3723

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5471533

1

T1

265

T3

3990

T4

3650

auto[1]

2793113

1

T1

386

T3

2702

T4

6162

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	5558425	1			T1	395		T3	6053		T4	9059
fifo_depth[1]	403573	1			T1	20		T3	362		T4	473
fifo_depth[2]	329601	1			T1	34		T3	184		T4	209
fifo_depth[3]	265667	1			T1	20		T3	70		T4	60
fifo_depth[4]	227658	1			T1	89		T3	19		T4	8
fifo_depth[5]	200495	1			T1	16		T3	4		T4	2
fifo_depth[6]	189851	1			T1	25		T5	28		T6	1018
fifo_depth[7]	165139	1			T1	12		T4	1		T5	8
fifo_depth[8]	145046	1			T1	35		T5	6		T6	766
fifo_depth[9]	100161	1			T1	2		T6	539		T8	417
fifo_depth[10]	74676	1			T1	2		T6	363		T8	249
fifo_depth[11]	45332	1			T1	1		T6	179		T8	167
fifo_depth[12]	41449	1			T6	98		T8	80		T9	2
fifo_depth[13]	21136	1			T6	37		T8	37		T9	1
fifo_depth[14]	26036	1			T6	17		T8	16		T27	11
fifo_depth[15]	16694	1			T6	6		T8	4		T13	158
fifo_depth[16]	63636	1			T6	3		T8	3		T27	2

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2786068

1

T1

256

T3

639

T4

753

auto[1]

5478578

1

T1

395

T3

6053

T4

9059

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8184799

1

T1

651

T3

6692

T4

9812

auto[1]

79847

1

T13

1267

T19

1035

T20

7

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

164763

1

T1

68

T3

220

T4

57

auto[0]

auto[0]

auto[0]

auto[1]

170639

1

T4

100

T5

82

T8

555

auto[0]

auto[0]

auto[1]

auto[0]

883731

1

T1

47

T3

15

T4

69

auto[0]

auto[0]

auto[1]

auto[1]

169430

1

T1

13

T3

135

T4

63

auto[0]

auto[1]

auto[0]

auto[0]

364451

1

T1

50

T4

117

T5

172

auto[0]

auto[1]

auto[0]

auto[1]

333824

1

T3

42

T4

191

T5

119

auto[0]

auto[1]

auto[1]

auto[0]

334771

1

T1

53

T3

144

T4

133

auto[0]

auto[1]

auto[1]

auto[1]

364459

1

T1

25

T3

83

T4

23

auto[1]

auto[0]

auto[0]

auto[0]

215437

1

T1

79

T3

2207

T4

657

auto[1]

auto[0]

auto[0]

auto[1]

220774

1

T4

1093

T5

875

T8

322

auto[1]

auto[0]

auto[1]

auto[0]

3419951

1

T1

47

T3

164

T4

886

auto[1]

auto[0]

auto[1]

auto[1]

226808

1

T1

11

T3

1249

T4

725

auto[1]

auto[1]

auto[0]

auto[0]

349369

1

T1

65

T4

1378

T5

1387

auto[1]

auto[1]

auto[0]

auto[1]

338451

1

T3

390

T4

2496

T5

1011

auto[1]

auto[1]

auto[1]

auto[0]

346170

1

T1

146

T3

1343

T4

1553

auto[1]

auto[1]

auto[1]

auto[1]

361618

1

T1

47

T3

700

T4

271

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

371336

1

T1

147

T3

2427

T4

714

auto[0]

auto[0]

auto[0]

auto[1]

383458

1

T4

1193

T5

957

T8

877

auto[0]

auto[0]

auto[1]

auto[0]

4295143

1

T1

94

T3

179

T4

955

auto[0]

auto[0]

auto[1]

auto[1]

388028

1

T1

24

T3

1384

T4

788

auto[0]

auto[1]

auto[0]

auto[0]

701966

1

T1

115

T4

1495

T5

1559

auto[0]

auto[1]

auto[0]

auto[1]

661896

1

T3

432

T4

2687

T5

1130

auto[0]

auto[1]

auto[1]

auto[0]

671005

1

T1

199

T3

1487

T4

1686

auto[0]

auto[1]

auto[1]

auto[1]

711967

1

T1

72

T3

783

T4

294

auto[1]

auto[0]

auto[0]

auto[0]

8864

1

T13

26

T19

48

T20

2

auto[1]

auto[0]

auto[0]

auto[1]

7955

1

T19

203

T20

1

T54

2

auto[1]

auto[0]

auto[1]

auto[0]

8539

1

T19

87

T10

1

T54

1

auto[1]

auto[0]

auto[1]

auto[1]

8210

1

T13

34

T19

173

T20

1

auto[1]

auto[1]

auto[0]

auto[0]

11854

1

T13

1149

T19

127

T20

1

auto[1]

auto[1]

auto[0]

auto[1]

10379

1

T13

1

T20

1

T55

1

auto[1]

auto[1]

auto[1]

auto[0]

9936

1

T19

36

T20

1

T55

1

auto[1]

auto[1]

auto[1]

auto[1]

14110

1

T13

57

T19

361

T21

2

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	224301	1			T1	79		T3	2207		T4	657
fifo_depth[0]	auto[0]	auto[0]	auto[1]	228729	1			T4	1093		T5	875		T8	322
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3428490	1			T1	47		T3	164		T4	886
fifo_depth[0]	auto[0]	auto[1]	auto[1]	235018	1			T1	11		T3	1249		T4	725
fifo_depth[0]	auto[1]	auto[0]	auto[0]	361223	1			T1	65		T4	1378		T5	1387
fifo_depth[0]	auto[1]	auto[0]	auto[1]	348830	1			T3	390		T4	2496		T5	1011
fifo_depth[0]	auto[1]	auto[1]	auto[0]	356106	1			T1	146		T3	1343		T4	1553
fifo_depth[0]	auto[1]	auto[1]	auto[1]	375728	1			T1	47		T3	700		T4	271
fifo_depth[1]	auto[0]	auto[0]	auto[0]	16043	1			T1	5		T3	126		T4	33
fifo_depth[1]	auto[0]	auto[0]	auto[1]	16377	1			T4	56		T5	29		T8	71
fifo_depth[1]	auto[0]	auto[1]	auto[0]	201556	1			T1	5		T3	9		T4	48
fifo_depth[1]	auto[0]	auto[1]	auto[1]	16690	1			T1	2		T3	74		T4	34
fifo_depth[1]	auto[1]	auto[0]	auto[0]	38403	1			T1	6		T4	69		T5	60
fifo_depth[1]	auto[1]	auto[0]	auto[1]	37187	1			T3	21		T4	126		T5	45
fifo_depth[1]	auto[1]	auto[1]	auto[0]	38008	1			T3	77		T4	93		T5	24
fifo_depth[1]	auto[1]	auto[1]	auto[1]	39309	1			T1	2		T3	55		T4	14
fifo_depth[2]	auto[0]	auto[0]	auto[0]	13304	1			T1	6		T3	63		T4	21
fifo_depth[2]	auto[0]	auto[0]	auto[1]	14034	1			T4	28		T5	21		T8	60
fifo_depth[2]	auto[0]	auto[1]	auto[0]	151972	1			T1	6		T3	6		T4	17
fifo_depth[2]	auto[0]	auto[1]	auto[1]	14209	1			T1	2		T3	33		T4	21
fifo_depth[2]	auto[1]	auto[0]	auto[0]	34173	1			T1	10		T4	34		T5	33
fifo_depth[2]	auto[1]	auto[0]	auto[1]	33194	1			T3	17		T4	52		T5	31
fifo_depth[2]	auto[1]	auto[1]	auto[0]	34201	1			T1	1		T3	50		T4	29
fifo_depth[2]	auto[1]	auto[1]	auto[1]	34514	1			T1	9		T3	15		T4	7
fifo_depth[3]	auto[0]	auto[0]	auto[0]	10481	1			T1	3		T3	24		T4	2
fifo_depth[3]	auto[0]	auto[0]	auto[1]	11038	1			T4	14		T5	9		T8	64
fifo_depth[3]	auto[0]	auto[1]	auto[0]	112931	1			T1	6		T4	1		T5	12
fifo_depth[3]	auto[0]	auto[1]	auto[1]	11200	1			T1	2		T3	18		T4	8
fifo_depth[3]	auto[1]	auto[0]	auto[0]	30490	1			T1	9		T4	14		T5	15
fifo_depth[3]	auto[1]	auto[0]	auto[1]	29286	1			T3	4		T4	12		T5	21
fifo_depth[3]	auto[1]	auto[1]	auto[0]	29852	1			T3	14		T4	9		T5	8
fifo_depth[3]	auto[1]	auto[1]	auto[1]	30389	1			T3	10		T5	21		T6	171
fifo_depth[4]	auto[0]	auto[0]	auto[0]	9754	1			T1	13		T3	7		T4	1
fifo_depth[4]	auto[0]	auto[0]	auto[1]	10338	1			T4	2		T5	22		T8	69
fifo_depth[4]	auto[0]	auto[1]	auto[0]	81696	1			T1	11		T4	1		T5	7
fifo_depth[4]	auto[0]	auto[1]	auto[1]	10802	1			T1	3		T3	8		T5	34
fifo_depth[4]	auto[1]	auto[0]	auto[0]	29685	1			T1	10		T5	53		T6	64
fifo_depth[4]	auto[1]	auto[0]	auto[1]	27925	1			T4	1		T5	10		T6	510
fifo_depth[4]	auto[1]	auto[1]	auto[0]	28171	1			T1	47		T3	2		T4	2
fifo_depth[4]	auto[1]	auto[1]	auto[1]	29287	1			T1	5		T3	2		T4	1
fifo_depth[5]	auto[0]	auto[0]	auto[0]	8481	1			T1	3		T5	1		T8	67
fifo_depth[5]	auto[0]	auto[0]	auto[1]	9083	1			T5	1		T8	54		T9	29
fifo_depth[5]	auto[0]	auto[1]	auto[0]	66895	1			T1	3		T4	2		T5	3
fifo_depth[5]	auto[0]	auto[1]	auto[1]	8982	1			T1	2		T3	2		T5	13
fifo_depth[5]	auto[1]	auto[0]	auto[0]	27042	1			T1	7		T5	8		T6	66
fifo_depth[5]	auto[1]	auto[0]	auto[1]	26644	1			T5	6		T6	515		T8	37
fifo_depth[5]	auto[1]	auto[1]	auto[0]	26425	1			T1	1		T3	1		T5	1
fifo_depth[5]	auto[1]	auto[1]	auto[1]	26943	1			T3	1		T5	10		T6	155
fifo_depth[6]	auto[0]	auto[0]	auto[0]	8517	1			T1	10		T5	4		T8	51
fifo_depth[6]	auto[0]	auto[0]	auto[1]	8964	1			T8	70		T9	36		T25	1
fifo_depth[6]	auto[0]	auto[1]	auto[0]	58120	1			T1	4		T5	3		T8	101
fifo_depth[6]	auto[0]	auto[1]	auto[1]	8940	1			T1	1		T5	11		T8	73
fifo_depth[6]	auto[1]	auto[0]	auto[0]	27140	1			T1	4		T5	3		T6	58
fifo_depth[6]	auto[1]	auto[0]	auto[1]	25226	1			T5	4		T6	511		T8	33
fifo_depth[6]	auto[1]	auto[1]	auto[0]	26154	1			T1	2		T5	1		T6	296
fifo_depth[6]	auto[1]	auto[1]	auto[1]	26790	1			T1	4		T5	2		T6	153
fifo_depth[7]	auto[0]	auto[0]	auto[0]	7737	1			T1	5		T5	1		T8	58
fifo_depth[7]	auto[0]	auto[0]	auto[1]	8004	1			T8	52		T9	7		T27	55
fifo_depth[7]	auto[0]	auto[1]	auto[0]	45611	1			T1	7		T5	2		T8	92
fifo_depth[7]	auto[0]	auto[1]	auto[1]	7683	1			T5	3		T8	71		T75	1
fifo_depth[7]	auto[1]	auto[0]	auto[0]	24402	1			T6	47		T8	148		T9	14
fifo_depth[7]	auto[1]	auto[0]	auto[1]	23740	1			T5	1		T6	500		T8	39
fifo_depth[7]	auto[1]	auto[1]	auto[0]	23911	1			T6	254		T7	4		T8	89
fifo_depth[7]	auto[1]	auto[1]	auto[1]	24051	1			T4	1		T5	1		T6	141
fifo_depth[8]	auto[0]	auto[0]	auto[0]	7665	1			T1	21		T8	49		T9	4
fifo_depth[8]	auto[0]	auto[0]	auto[1]	7690	1			T8	36		T9	17		T27	33
fifo_depth[8]	auto[0]	auto[1]	auto[0]	36073	1			T1	4		T5	1		T8	79
fifo_depth[8]	auto[0]	auto[1]	auto[1]	7834	1			T5	2		T8	54		T9	4
fifo_depth[8]	auto[1]	auto[0]	auto[0]	22353	1			T1	4		T6	36		T8	128
fifo_depth[8]	auto[1]	auto[0]	auto[1]	20110	1			T5	1		T6	370		T8	23
fifo_depth[8]	auto[1]	auto[1]	auto[0]	21704	1			T1	2		T6	232		T8	76
fifo_depth[8]	auto[1]	auto[1]	auto[1]	21617	1			T1	4		T5	2		T6	128
fifo_depth[9]	auto[0]	auto[0]	auto[0]	5349	1			T8	31		T9	1		T27	92
fifo_depth[9]	auto[0]	auto[0]	auto[1]	5285	1			T8	31		T9	2		T27	34
fifo_depth[9]	auto[0]	auto[1]	auto[0]	23377	1			T1	1		T8	61		T9	4
fifo_depth[9]	auto[0]	auto[1]	auto[1]	5087	1			T1	1		T8	44		T13	86
fifo_depth[9]	auto[1]	auto[0]	auto[0]	15443	1			T6	25		T8	89		T9	2
fifo_depth[9]	auto[1]	auto[0]	auto[1]	14914	1			T6	277		T8	20		T9	4
fifo_depth[9]	auto[1]	auto[1]	auto[0]	15404	1			T6	149		T8	56		T9	2
fifo_depth[9]	auto[1]	auto[1]	auto[1]	15302	1			T6	88		T8	85		T9	3
fifo_depth[10]	auto[0]	auto[0]	auto[0]	4276	1			T1	1		T8	23		T9	2
fifo_depth[10]	auto[0]	auto[0]	auto[1]	4179	1			T8	19		T9	1		T27	17
fifo_depth[10]	auto[0]	auto[1]	auto[0]	15953	1			T8	36		T9	5		T27	34
fifo_depth[10]	auto[0]	auto[1]	auto[1]	4811	1			T8	30		T13	44		T14	1
fifo_depth[10]	auto[1]	auto[0]	auto[0]	11847	1			T6	26		T8	64		T9	2
fifo_depth[10]	auto[1]	auto[0]	auto[1]	10670	1			T6	178		T8	9		T9	6
fifo_depth[10]	auto[1]	auto[1]	auto[0]	11272	1			T6	105		T8	29		T27	9
fifo_depth[10]	auto[1]	auto[1]	auto[1]	11668	1			T1	1		T6	54		T8	39
fifo_depth[11]	auto[0]	auto[0]	auto[0]	3012	1			T1	1		T8	16		T27	38
fifo_depth[11]	auto[0]	auto[0]	auto[1]	2994	1			T8	17		T27	12		T13	1
fifo_depth[11]	auto[0]	auto[1]	auto[0]	9315	1			T8	17		T9	1		T27	13
fifo_depth[11]	auto[0]	auto[1]	auto[1]	2648	1			T8	21		T13	27		T14	2
fifo_depth[11]	auto[1]	auto[0]	auto[0]	7040	1			T6	5		T8	32		T9	3
fifo_depth[11]	auto[1]	auto[0]	auto[1]	6295	1			T6	99		T8	10		T27	7
fifo_depth[11]	auto[1]	auto[1]	auto[0]	7100	1			T6	51		T8	19		T27	7
fifo_depth[11]	auto[1]	auto[1]	auto[1]	6928	1			T6	24		T8	35		T27	11
fifo_depth[12]	auto[0]	auto[0]	auto[0]	3613	1			T8	12		T27	14		T13	1
fifo_depth[12]	auto[0]	auto[0]	auto[1]	3903	1			T8	7		T27	6		T14	7
fifo_depth[12]	auto[0]	auto[1]	auto[0]	7222	1			T8	10		T9	1		T27	5
fifo_depth[12]	auto[0]	auto[1]	auto[1]	3427	1			T8	13		T13	23		T60	6
fifo_depth[12]	auto[1]	auto[0]	auto[0]	7056	1			T6	3		T8	18		T9	1
fifo_depth[12]	auto[1]	auto[0]	auto[1]	4357	1			T6	44		T8	2		T15	5
fifo_depth[12]	auto[1]	auto[1]	auto[0]	6049	1			T6	33		T8	8		T27	5
fifo_depth[12]	auto[1]	auto[1]	auto[1]	5822	1			T6	18		T8	10		T27	9
fifo_depth[13]	auto[0]	auto[0]	auto[0]	2009	1			T8	2		T27	9		T13	9
fifo_depth[13]	auto[0]	auto[0]	auto[1]	2257	1			T8	4		T27	2		T13	1
fifo_depth[13]	auto[0]	auto[1]	auto[0]	3406	1			T8	8		T27	2		T13	53
fifo_depth[13]	auto[0]	auto[1]	auto[1]	1804	1			T8	7		T13	5		T60	5
fifo_depth[13]	auto[1]	auto[0]	auto[0]	3081	1			T6	2		T8	10		T27	2
fifo_depth[13]	auto[1]	auto[0]	auto[1]	2261	1			T6	22		T8	1		T13	22
fifo_depth[13]	auto[1]	auto[1]	auto[0]	3310	1			T6	9		T8	3		T9	1
fifo_depth[13]	auto[1]	auto[1]	auto[1]	3008	1			T6	4		T8	2		T27	3
fifo_depth[14]	auto[0]	auto[0]	auto[0]	2754	1			T27	6		T13	9		T60	1
fifo_depth[14]	auto[0]	auto[0]	auto[1]	2810	1			T8	1		T13	3		T61	1
fifo_depth[14]	auto[0]	auto[1]	auto[0]	3437	1			T8	2		T27	2		T13	19
fifo_depth[14]	auto[0]	auto[1]	auto[1]	3350	1			T8	3		T13	2		T60	2
fifo_depth[14]	auto[1]	auto[0]	auto[0]	4465	1			T6	1		T8	2		T13	20
fifo_depth[14]	auto[1]	auto[0]	auto[1]	2324	1			T6	8		T27	1		T15	1
fifo_depth[14]	auto[1]	auto[1]	auto[0]	3392	1			T6	6		T8	5		T13	52
fifo_depth[14]	auto[1]	auto[1]	auto[1]	3504	1			T6	2		T8	3		T27	2
fifo_depth[15]	auto[0]	auto[0]	auto[0]	2035	1			T13	9		T60	1		T19	8
fifo_depth[15]	auto[0]	auto[0]	auto[1]	2126	1			T60	1		T61	4		T19	118
fifo_depth[15]	auto[0]	auto[1]	auto[0]	2050	1			T13	3		T28	1		T19	9
fifo_depth[15]	auto[0]	auto[1]	auto[1]	1997	1			T19	85		T10	1		T12	2
fifo_depth[15]	auto[1]	auto[0]	auto[0]	2376	1			T8	1		T13	8		T59	3
fifo_depth[15]	auto[1]	auto[0]	auto[1]	1406	1			T6	2		T13	4		T26	5
fifo_depth[15]	auto[1]	auto[1]	auto[0]	2376	1			T6	1		T13	78		T59	5
fifo_depth[15]	auto[1]	auto[1]	auto[1]	2328	1			T6	3		T8	3		T13	56
fifo_depth[16]	auto[0]	auto[0]	auto[0]	6578	1			T27	2		T13	73		T19	301
fifo_depth[16]	auto[0]	auto[0]	auto[1]	7225	1			T61	1		T19	852		T11	9
fifo_depth[16]	auto[0]	auto[1]	auto[0]	10405	1			T8	1		T13	1		T19	301
fifo_depth[16]	auto[0]	auto[1]	auto[1]	7164	1			T8	1		T13	2		T19	87
fifo_depth[16]	auto[1]	auto[0]	auto[0]	6947	1			T13	5		T59	1		T19	246
fifo_depth[16]	auto[1]	auto[0]	auto[1]	6401	1			T6	3		T13	1		T26	5
fifo_depth[16]	auto[1]	auto[1]	auto[0]	7661	1			T13	41		T60	1		T19	36
fifo_depth[16]	auto[1]	auto[1]	auto[1]	11255	1			T8	1		T13	185		T26	1