Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	12943630	1			T1	115		T3	6722		T4	9903
all_pins[1]	12943630	1			T1	115		T3	6722		T4	9903
all_pins[2]	12943630	1			T1	115		T3	6722		T4	9903

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	36665075	1			T1	330		T3	20152		T4	29670
values[0x1]	2165815	1			T1	15		T3	14		T4	39
transitions[0x0=>0x1]	2165676	1			T1	15		T3	14		T4	39
transitions[0x1=>0x0]	2165691	1			T1	15		T3	14		T4	39

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	12900082	1			T1	100		T3	6708		T4	9864
all_pins[0]	values[0x1]	43548	1			T1	15		T3	14		T4	39
all_pins[0]	transitions[0x0=>0x1]	43488	1			T1	15		T3	14		T4	39
all_pins[0]	transitions[0x1=>0x0]	2121870	1			T18	8634		T9	7053		T17	2348
all_pins[1]	values[0x0]	12943278	1			T1	115		T3	6722		T4	9903
all_pins[1]	values[0x1]	352	1			T5	3		T13	1		T14	4
all_pins[1]	transitions[0x0=>0x1]	312	1			T5	2		T14	3		T63	3
all_pins[1]	transitions[0x1=>0x0]	43508	1			T1	15		T3	14		T4	39
all_pins[2]	values[0x0]	10821715	1			T1	115		T3	6722		T4	9903
all_pins[2]	values[0x1]	2121915	1			T18	8634		T9	7053		T17	2348
all_pins[2]	transitions[0x0=>0x1]	2121876	1			T18	8634		T9	7053		T17	2348
all_pins[2]	transitions[0x1=>0x0]	313	1			T5	3		T13	1		T14	2