Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	18	0	18	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	18	0	18	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	847	1			T5	7		T9	4		T13	4
all_values[1]	847	1			T5	7		T9	4		T13	4
all_values[2]	847	1			T5	7		T9	4		T13	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1297

1

T5

13

T9

7

T13

8

auto[1]

1244

1

T5

8

T9

5

T13

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

868

1

T5

8

T9

9

T13

5

auto[1]

1673

1

T5

13

T9

3

T13

7

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1416

1

T5

14

T9

10

T13

6

auto[1]

1125

1

T5

7

T9

2

T13

6

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	18	0	18	100.00
Automatically Generated Cross Bins	18	0	18	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

164

1

T5

2

T9

1

T13

2

all_values[0]

auto[0]

auto[0]

auto[1]

97

1

T5

3

T14

2

T63

1

all_values[0]

auto[0]

auto[1]

auto[0]

114

1

T9

3

T63

5

T11

2

all_values[0]

auto[0]

auto[1]

auto[1]

78

1

T5

1

T14

1

T63

2

all_values[0]

auto[1]

auto[0]

auto[1]

196

1

T13

1

T14

3

T63

2

all_values[0]

auto[1]

auto[1]

auto[1]

198

1

T5

1

T13

1

T14

4

all_values[1]

auto[0]

auto[0]

auto[0]

137

1

T5

1

T9

2

T14

1

all_values[1]

auto[0]

auto[0]

auto[1]

100

1

T9

1

T13

1

T14

1

all_values[1]

auto[0]

auto[1]

auto[0]

141

1

T13

1

T63

5

T97

2

all_values[1]

auto[0]

auto[1]

auto[1]

111

1

T5

2

T14

2

T63

2

all_values[1]

auto[1]

auto[0]

auto[1]

180

1

T5

2

T9

1

T13

1

all_values[1]

auto[1]

auto[1]

auto[1]

178

1

T5

2

T13

1

T14

3

all_values[2]

auto[0]

auto[0]

auto[0]

161

1

T5

3

T9

1

T13

1

all_values[2]

auto[0]

auto[0]

auto[1]

85

1

T63

1

T11

1

T31

1

all_values[2]

auto[0]

auto[1]

auto[0]

151

1

T5

2

T9

2

T13

1

all_values[2]

auto[0]

auto[1]

auto[1]

77

1

T14

2

T63

1

T97

3

all_values[2]

auto[1]

auto[0]

auto[1]

177

1

T5

2

T9

1

T13

2

all_values[2]

auto[1]

auto[1]

auto[1]

196

1

T14

2

T63

3

T97

7

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal