Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.55 92.46 85.17 100.00 73.68 85.93 99.49 69.08


Total test records in report: 731
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T534 /workspace/coverage/default/38.hmac_long_msg.3599980444 Mar 31 01:02:39 PM PDT 24 Mar 31 01:03:00 PM PDT 24 1505187809 ps
T535 /workspace/coverage/default/7.hmac_back_pressure.365253838 Mar 31 01:00:51 PM PDT 24 Mar 31 01:01:54 PM PDT 24 1611884600 ps
T536 /workspace/coverage/default/41.hmac_error.3749955762 Mar 31 01:02:51 PM PDT 24 Mar 31 01:05:28 PM PDT 24 12683163900 ps
T35 /workspace/coverage/default/3.hmac_sec_cm.2751685590 Mar 31 01:00:40 PM PDT 24 Mar 31 01:00:42 PM PDT 24 66500803 ps
T537 /workspace/coverage/default/22.hmac_alert_test.146442070 Mar 31 01:01:38 PM PDT 24 Mar 31 01:01:38 PM PDT 24 205091124 ps
T538 /workspace/coverage/default/17.hmac_burst_wr.1744652891 Mar 31 01:01:08 PM PDT 24 Mar 31 01:01:14 PM PDT 24 481013668 ps
T539 /workspace/coverage/default/32.hmac_smoke.775982860 Mar 31 01:02:13 PM PDT 24 Mar 31 01:02:18 PM PDT 24 517808900 ps
T540 /workspace/coverage/default/36.hmac_error.1547796383 Mar 31 01:02:32 PM PDT 24 Mar 31 01:03:53 PM PDT 24 8882165482 ps
T541 /workspace/coverage/default/30.hmac_wipe_secret.1802877333 Mar 31 01:02:10 PM PDT 24 Mar 31 01:02:41 PM PDT 24 8705166269 ps
T542 /workspace/coverage/default/6.hmac_datapath_stress.829184865 Mar 31 01:00:52 PM PDT 24 Mar 31 01:01:33 PM PDT 24 2375264721 ps
T36 /workspace/coverage/default/2.hmac_sec_cm.3656922579 Mar 31 01:00:33 PM PDT 24 Mar 31 01:00:34 PM PDT 24 79832020 ps
T543 /workspace/coverage/default/49.hmac_error.948845213 Mar 31 01:03:29 PM PDT 24 Mar 31 01:05:18 PM PDT 24 10791462151 ps
T544 /workspace/coverage/default/8.hmac_error.4235186534 Mar 31 01:00:49 PM PDT 24 Mar 31 01:03:20 PM PDT 24 2867750591 ps
T545 /workspace/coverage/default/18.hmac_alert_test.3014558208 Mar 31 01:01:24 PM PDT 24 Mar 31 01:01:25 PM PDT 24 12245472 ps
T546 /workspace/coverage/default/22.hmac_burst_wr.3761554636 Mar 31 01:01:34 PM PDT 24 Mar 31 01:02:44 PM PDT 24 2819608721 ps
T547 /workspace/coverage/default/34.hmac_test_sha_vectors.3085624378 Mar 31 01:02:26 PM PDT 24 Mar 31 01:11:31 PM PDT 24 201546923006 ps
T37 /workspace/coverage/default/0.hmac_sec_cm.425373714 Mar 31 01:00:27 PM PDT 24 Mar 31 01:00:28 PM PDT 24 192181586 ps
T548 /workspace/coverage/default/34.hmac_back_pressure.4066569302 Mar 31 01:02:20 PM PDT 24 Mar 31 01:03:00 PM PDT 24 4253054407 ps
T549 /workspace/coverage/default/36.hmac_alert_test.2056726466 Mar 31 01:02:32 PM PDT 24 Mar 31 01:02:34 PM PDT 24 14664249 ps
T550 /workspace/coverage/default/32.hmac_alert_test.4012163774 Mar 31 01:02:22 PM PDT 24 Mar 31 01:02:23 PM PDT 24 14536979 ps
T551 /workspace/coverage/default/21.hmac_burst_wr.3647966806 Mar 31 01:01:32 PM PDT 24 Mar 31 01:01:34 PM PDT 24 116133964 ps
T552 /workspace/coverage/default/33.hmac_burst_wr.4272869942 Mar 31 01:02:22 PM PDT 24 Mar 31 01:03:18 PM PDT 24 1037009744 ps
T553 /workspace/coverage/default/6.hmac_test_hmac_vectors.1761819702 Mar 31 01:00:49 PM PDT 24 Mar 31 01:00:50 PM PDT 24 78372774 ps
T554 /workspace/coverage/default/35.hmac_stress_all.1972479178 Mar 31 01:02:27 PM PDT 24 Mar 31 01:14:10 PM PDT 24 391069689705 ps
T555 /workspace/coverage/default/12.hmac_alert_test.1996370093 Mar 31 01:00:55 PM PDT 24 Mar 31 01:00:56 PM PDT 24 52899538 ps
T556 /workspace/coverage/default/3.hmac_smoke.1684212856 Mar 31 01:00:37 PM PDT 24 Mar 31 01:00:43 PM PDT 24 1062924351 ps
T557 /workspace/coverage/default/31.hmac_burst_wr.1037661261 Mar 31 01:02:14 PM PDT 24 Mar 31 01:02:48 PM PDT 24 2262218409 ps
T558 /workspace/coverage/default/47.hmac_alert_test.4185111652 Mar 31 01:03:30 PM PDT 24 Mar 31 01:03:31 PM PDT 24 20400700 ps
T559 /workspace/coverage/default/45.hmac_test_hmac_vectors.323813772 Mar 31 01:03:20 PM PDT 24 Mar 31 01:03:22 PM PDT 24 225318175 ps
T560 /workspace/coverage/default/4.hmac_back_pressure.2169637598 Mar 31 01:00:42 PM PDT 24 Mar 31 01:01:15 PM PDT 24 5333082901 ps
T561 /workspace/coverage/default/25.hmac_smoke.2065667072 Mar 31 01:01:45 PM PDT 24 Mar 31 01:01:49 PM PDT 24 511853071 ps
T562 /workspace/coverage/default/3.hmac_back_pressure.3523256172 Mar 31 01:00:37 PM PDT 24 Mar 31 01:00:52 PM PDT 24 854383643 ps
T563 /workspace/coverage/default/36.hmac_burst_wr.128355638 Mar 31 01:02:28 PM PDT 24 Mar 31 01:02:48 PM PDT 24 1307638457 ps
T564 /workspace/coverage/default/10.hmac_burst_wr.4159759012 Mar 31 01:00:56 PM PDT 24 Mar 31 01:01:30 PM PDT 24 1607589315 ps
T565 /workspace/coverage/default/42.hmac_wipe_secret.3537241446 Mar 31 01:03:04 PM PDT 24 Mar 31 01:03:18 PM PDT 24 1261964125 ps
T566 /workspace/coverage/default/37.hmac_long_msg.3012369955 Mar 31 01:02:45 PM PDT 24 Mar 31 01:03:46 PM PDT 24 2019542358 ps
T567 /workspace/coverage/default/20.hmac_wipe_secret.3894305075 Mar 31 01:01:28 PM PDT 24 Mar 31 01:01:39 PM PDT 24 285052561 ps
T568 /workspace/coverage/default/41.hmac_back_pressure.2509465878 Mar 31 01:02:53 PM PDT 24 Mar 31 01:03:08 PM PDT 24 1952220589 ps
T569 /workspace/coverage/default/42.hmac_stress_all.1936072074 Mar 31 01:03:00 PM PDT 24 Mar 31 01:29:02 PM PDT 24 128809366322 ps
T570 /workspace/coverage/default/45.hmac_datapath_stress.3490115109 Mar 31 01:03:13 PM PDT 24 Mar 31 01:04:42 PM PDT 24 5993436881 ps
T571 /workspace/coverage/default/31.hmac_test_sha_vectors.2190926324 Mar 31 01:02:13 PM PDT 24 Mar 31 01:09:20 PM PDT 24 25137701026 ps
T572 /workspace/coverage/default/33.hmac_long_msg.1957767124 Mar 31 01:02:22 PM PDT 24 Mar 31 01:03:40 PM PDT 24 1394691656 ps
T573 /workspace/coverage/default/13.hmac_test_hmac_vectors.12946526 Mar 31 01:01:03 PM PDT 24 Mar 31 01:01:05 PM PDT 24 259321558 ps
T574 /workspace/coverage/default/32.hmac_stress_all.2071422731 Mar 31 01:02:13 PM PDT 24 Mar 31 01:15:04 PM PDT 24 57238263724 ps
T575 /workspace/coverage/default/21.hmac_test_hmac_vectors.79172151 Mar 31 01:01:32 PM PDT 24 Mar 31 01:01:33 PM PDT 24 448348287 ps
T576 /workspace/coverage/default/16.hmac_error.3275598217 Mar 31 01:01:05 PM PDT 24 Mar 31 01:03:50 PM PDT 24 89328200573 ps
T577 /workspace/coverage/default/9.hmac_smoke.422119762 Mar 31 01:00:57 PM PDT 24 Mar 31 01:01:01 PM PDT 24 1265846629 ps
T578 /workspace/coverage/default/41.hmac_wipe_secret.3330191816 Mar 31 01:03:04 PM PDT 24 Mar 31 01:04:08 PM PDT 24 6774893261 ps
T579 /workspace/coverage/default/1.hmac_long_msg.4128336226 Mar 31 01:00:27 PM PDT 24 Mar 31 01:01:48 PM PDT 24 11459009025 ps
T580 /workspace/coverage/default/49.hmac_alert_test.3325398006 Mar 31 01:03:41 PM PDT 24 Mar 31 01:03:42 PM PDT 24 11416299 ps
T581 /workspace/coverage/default/43.hmac_wipe_secret.3860488489 Mar 31 01:03:06 PM PDT 24 Mar 31 01:04:26 PM PDT 24 39842246509 ps
T582 /workspace/coverage/default/16.hmac_smoke.1172211770 Mar 31 01:01:05 PM PDT 24 Mar 31 01:01:09 PM PDT 24 247832793 ps
T583 /workspace/coverage/default/1.hmac_stress_all.3315079795 Mar 31 01:00:33 PM PDT 24 Mar 31 01:04:32 PM PDT 24 18514256149 ps
T73 /workspace/coverage/default/170.hmac_stress_all_with_rand_reset.4102939562 Mar 31 01:04:25 PM PDT 24 Mar 31 01:06:43 PM PDT 24 11567424862 ps
T584 /workspace/coverage/default/12.hmac_test_hmac_vectors.577986676 Mar 31 01:00:58 PM PDT 24 Mar 31 01:00:59 PM PDT 24 45564054 ps
T585 /workspace/coverage/default/14.hmac_smoke.3775677772 Mar 31 01:01:03 PM PDT 24 Mar 31 01:01:09 PM PDT 24 294472618 ps
T586 /workspace/coverage/default/181.hmac_stress_all_with_rand_reset.3780918835 Mar 31 01:04:35 PM PDT 24 Mar 31 01:20:41 PM PDT 24 22203076983 ps
T587 /workspace/coverage/default/30.hmac_alert_test.4289135146 Mar 31 01:02:12 PM PDT 24 Mar 31 01:02:13 PM PDT 24 23040033 ps
T588 /workspace/coverage/default/12.hmac_back_pressure.548704865 Mar 31 01:00:55 PM PDT 24 Mar 31 01:01:36 PM PDT 24 11366071642 ps
T589 /workspace/coverage/default/36.hmac_long_msg.3006556415 Mar 31 01:02:27 PM PDT 24 Mar 31 01:03:53 PM PDT 24 20709568182 ps
T590 /workspace/coverage/default/30.hmac_burst_wr.3378917786 Mar 31 01:02:12 PM PDT 24 Mar 31 01:02:34 PM PDT 24 428326620 ps
T591 /workspace/coverage/default/0.hmac_error.169362640 Mar 31 01:00:28 PM PDT 24 Mar 31 01:03:33 PM PDT 24 13210097598 ps
T592 /workspace/coverage/default/46.hmac_wipe_secret.1045566838 Mar 31 01:03:17 PM PDT 24 Mar 31 01:03:23 PM PDT 24 252655374 ps
T593 /workspace/coverage/default/46.hmac_datapath_stress.3779113835 Mar 31 01:03:19 PM PDT 24 Mar 31 01:04:22 PM PDT 24 1231299192 ps
T594 /workspace/coverage/default/29.hmac_long_msg.596838332 Mar 31 01:02:06 PM PDT 24 Mar 31 01:03:23 PM PDT 24 1289421268 ps
T595 /workspace/coverage/default/46.hmac_smoke.3935918513 Mar 31 01:03:19 PM PDT 24 Mar 31 01:03:24 PM PDT 24 659753746 ps
T67 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3295424093 Mar 31 12:27:25 PM PDT 24 Mar 31 12:27:26 PM PDT 24 154847826 ps
T68 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1710232371 Mar 31 12:27:31 PM PDT 24 Mar 31 12:27:32 PM PDT 24 26224992 ps
T596 /workspace/coverage/cover_reg_top/39.hmac_intr_test.979845159 Mar 31 12:27:41 PM PDT 24 Mar 31 12:27:42 PM PDT 24 51636648 ps
T69 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.823954856 Mar 31 12:26:55 PM PDT 24 Mar 31 12:26:56 PM PDT 24 51157197 ps
T597 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2949470905 Mar 31 12:27:04 PM PDT 24 Mar 31 12:27:06 PM PDT 24 502190133 ps
T85 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.42429001 Mar 31 12:26:58 PM PDT 24 Mar 31 12:27:03 PM PDT 24 107841880 ps
T598 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2488729980 Mar 31 12:27:18 PM PDT 24 Mar 31 12:27:19 PM PDT 24 13622291 ps
T599 /workspace/coverage/cover_reg_top/3.hmac_intr_test.1424018783 Mar 31 12:26:56 PM PDT 24 Mar 31 12:26:57 PM PDT 24 17521013 ps
T600 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2469797695 Mar 31 12:27:11 PM PDT 24 Mar 31 12:27:15 PM PDT 24 816786692 ps
T601 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1766595376 Mar 31 12:27:00 PM PDT 24 Mar 31 12:27:06 PM PDT 24 33177371 ps
T86 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2924502271 Mar 31 12:27:07 PM PDT 24 Mar 31 12:27:08 PM PDT 24 16532637 ps
T602 /workspace/coverage/cover_reg_top/18.hmac_intr_test.3649254685 Mar 31 12:27:18 PM PDT 24 Mar 31 12:27:19 PM PDT 24 118429482 ps
T64 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3368508541 Mar 31 12:27:03 PM PDT 24 Mar 31 12:27:07 PM PDT 24 480267274 ps
T603 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2531386771 Mar 31 12:26:54 PM PDT 24 Mar 31 12:26:55 PM PDT 24 41369126 ps
T604 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1784895158 Mar 31 12:26:56 PM PDT 24 Mar 31 12:26:57 PM PDT 24 613391934 ps
T605 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1326268913 Mar 31 12:26:57 PM PDT 24 Mar 31 12:26:57 PM PDT 24 119313869 ps
T606 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.4135742093 Mar 31 12:27:05 PM PDT 24 Mar 31 12:27:06 PM PDT 24 89234678 ps
T607 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.591943291 Mar 31 12:26:43 PM PDT 24 Mar 31 12:26:44 PM PDT 24 76774054 ps
T608 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1125114203 Mar 31 12:26:54 PM PDT 24 Mar 31 12:26:57 PM PDT 24 244503309 ps
T609 /workspace/coverage/cover_reg_top/23.hmac_intr_test.1361819451 Mar 31 12:26:57 PM PDT 24 Mar 31 12:27:03 PM PDT 24 16202017 ps
T610 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2062050951 Mar 31 12:27:41 PM PDT 24 Mar 31 12:27:42 PM PDT 24 27198152 ps
T65 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2139072068 Mar 31 12:26:57 PM PDT 24 Mar 31 12:26:59 PM PDT 24 69914156 ps
T66 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1125276216 Mar 31 12:27:00 PM PDT 24 Mar 31 12:27:03 PM PDT 24 362419104 ps
T611 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3624010014 Mar 31 12:27:09 PM PDT 24 Mar 31 12:27:11 PM PDT 24 67987985 ps
T612 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3284810636 Mar 31 12:27:10 PM PDT 24 Mar 31 12:27:10 PM PDT 24 39055443 ps
T613 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2877545351 Mar 31 12:26:51 PM PDT 24 Mar 31 12:26:53 PM PDT 24 136327892 ps
T614 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3546592134 Mar 31 12:27:01 PM PDT 24 Mar 31 12:27:04 PM PDT 24 846088077 ps
T615 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3587677664 Mar 31 12:26:58 PM PDT 24 Mar 31 12:27:00 PM PDT 24 35061486 ps
T616 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2168070146 Mar 31 12:26:57 PM PDT 24 Mar 31 12:26:58 PM PDT 24 45217675 ps
T98 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3973520149 Mar 31 12:27:46 PM PDT 24 Mar 31 12:27:50 PM PDT 24 243579491 ps
T617 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.879436590 Mar 31 12:27:00 PM PDT 24 Mar 31 12:27:02 PM PDT 24 197067977 ps
T618 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3581420583 Mar 31 12:27:42 PM PDT 24 Mar 31 12:27:45 PM PDT 24 208845429 ps
T619 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2827384689 Mar 31 12:27:00 PM PDT 24 Mar 31 12:27:00 PM PDT 24 16186008 ps
T620 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.137746251 Mar 31 12:27:00 PM PDT 24 Mar 31 12:27:04 PM PDT 24 368646078 ps
T621 /workspace/coverage/cover_reg_top/0.hmac_intr_test.364837734 Mar 31 12:26:58 PM PDT 24 Mar 31 12:26:59 PM PDT 24 55374463 ps
T99 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3990250790 Mar 31 12:26:56 PM PDT 24 Mar 31 12:26:59 PM PDT 24 616030515 ps
T622 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.122545816 Mar 31 12:26:57 PM PDT 24 Mar 31 12:26:58 PM PDT 24 85868682 ps
T623 /workspace/coverage/cover_reg_top/1.hmac_intr_test.2934172402 Mar 31 12:26:57 PM PDT 24 Mar 31 12:26:58 PM PDT 24 14594649 ps
T624 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1774604740 Mar 31 12:27:00 PM PDT 24 Mar 31 12:27:00 PM PDT 24 60334548 ps
T625 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2042882257 Mar 31 12:26:55 PM PDT 24 Mar 31 12:26:56 PM PDT 24 40444725 ps
T626 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1165281622 Mar 31 12:26:58 PM PDT 24 Mar 31 12:26:59 PM PDT 24 19020425 ps
T627 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1924879403 Mar 31 12:26:52 PM PDT 24 Mar 31 12:26:53 PM PDT 24 14406853 ps
T87 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1140921378 Mar 31 12:27:00 PM PDT 24 Mar 31 12:27:01 PM PDT 24 17710676 ps
T628 /workspace/coverage/cover_reg_top/31.hmac_intr_test.1809034872 Mar 31 12:27:14 PM PDT 24 Mar 31 12:27:15 PM PDT 24 54104318 ps
T88 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1789621377 Mar 31 12:26:58 PM PDT 24 Mar 31 12:26:59 PM PDT 24 27027469 ps
T629 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3831009631 Mar 31 12:27:12 PM PDT 24 Mar 31 12:27:18 PM PDT 24 19013298 ps
T89 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2018204585 Mar 31 12:26:58 PM PDT 24 Mar 31 12:26:59 PM PDT 24 50224382 ps
T630 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3250788901 Mar 31 12:26:58 PM PDT 24 Mar 31 12:27:01 PM PDT 24 91566880 ps
T631 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.121597234 Mar 31 12:26:51 PM PDT 24 Mar 31 12:26:52 PM PDT 24 401279942 ps
T632 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.12193076 Mar 31 12:27:00 PM PDT 24 Mar 31 12:27:02 PM PDT 24 51028403 ps
T633 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2154710638 Mar 31 12:27:35 PM PDT 24 Mar 31 12:27:35 PM PDT 24 78061109 ps
T634 /workspace/coverage/cover_reg_top/16.hmac_intr_test.2043427516 Mar 31 12:27:02 PM PDT 24 Mar 31 12:27:02 PM PDT 24 23300242 ps
T635 /workspace/coverage/cover_reg_top/24.hmac_intr_test.3351547217 Mar 31 12:27:51 PM PDT 24 Mar 31 12:27:53 PM PDT 24 17155170 ps
T636 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2333792553 Mar 31 12:26:52 PM PDT 24 Mar 31 12:26:53 PM PDT 24 125679905 ps
T637 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.504896397 Mar 31 12:26:57 PM PDT 24 Mar 31 12:27:00 PM PDT 24 36628738 ps
T638 /workspace/coverage/cover_reg_top/38.hmac_intr_test.3877986 Mar 31 12:27:03 PM PDT 24 Mar 31 12:27:05 PM PDT 24 32128034 ps
T100 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3097711115 Mar 31 12:27:01 PM PDT 24 Mar 31 12:27:05 PM PDT 24 447815802 ps
T639 /workspace/coverage/cover_reg_top/46.hmac_intr_test.776504252 Mar 31 12:27:00 PM PDT 24 Mar 31 12:27:00 PM PDT 24 30511963 ps
T640 /workspace/coverage/cover_reg_top/49.hmac_intr_test.4262538436 Mar 31 12:27:05 PM PDT 24 Mar 31 12:27:06 PM PDT 24 25951627 ps
T641 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2167775914 Mar 31 12:27:00 PM PDT 24 Mar 31 12:27:07 PM PDT 24 29358349 ps
T642 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3600588463 Mar 31 12:26:55 PM PDT 24 Mar 31 12:26:57 PM PDT 24 91085535 ps
T90 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3011678221 Mar 31 12:26:50 PM PDT 24 Mar 31 12:26:51 PM PDT 24 22267666 ps
T643 /workspace/coverage/cover_reg_top/13.hmac_intr_test.4119801547 Mar 31 12:26:46 PM PDT 24 Mar 31 12:26:47 PM PDT 24 25290030 ps
T91 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4244234479 Mar 31 12:26:53 PM PDT 24 Mar 31 12:26:59 PM PDT 24 2121033809 ps
T644 /workspace/coverage/cover_reg_top/11.hmac_intr_test.551288342 Mar 31 12:26:43 PM PDT 24 Mar 31 12:26:43 PM PDT 24 17757259 ps
T645 /workspace/coverage/cover_reg_top/42.hmac_intr_test.4030606332 Mar 31 12:27:01 PM PDT 24 Mar 31 12:27:02 PM PDT 24 37574094 ps
T646 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.425589534 Mar 31 12:27:47 PM PDT 24 Mar 31 12:27:49 PM PDT 24 180292900 ps
T647 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.590598236 Mar 31 12:26:51 PM PDT 24 Mar 31 12:26:53 PM PDT 24 155537183 ps
T92 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2808872274 Mar 31 12:26:46 PM PDT 24 Mar 31 12:26:54 PM PDT 24 610012813 ps
T648 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1591337489 Mar 31 12:26:51 PM PDT 24 Mar 31 12:26:57 PM PDT 24 1475135929 ps
T649 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2974112494 Mar 31 12:26:53 PM PDT 24 Mar 31 12:26:54 PM PDT 24 14658783 ps
T650 /workspace/coverage/cover_reg_top/48.hmac_intr_test.431073223 Mar 31 12:27:13 PM PDT 24 Mar 31 12:27:14 PM PDT 24 23909527 ps
T651 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4263976672 Mar 31 12:26:57 PM PDT 24 Mar 31 12:27:00 PM PDT 24 528669026 ps
T107 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2670063560 Mar 31 12:26:52 PM PDT 24 Mar 31 12:26:54 PM PDT 24 406992470 ps
T652 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2501554604 Mar 31 12:27:00 PM PDT 24 Mar 31 12:27:02 PM PDT 24 366966405 ps
T653 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1626995321 Mar 31 12:26:51 PM PDT 24 Mar 31 12:26:52 PM PDT 24 48366970 ps
T654 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1181860428 Mar 31 12:26:55 PM PDT 24 Mar 31 12:26:59 PM PDT 24 262396778 ps
T655 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.919352928 Mar 31 12:27:01 PM PDT 24 Mar 31 12:27:13 PM PDT 24 29185506 ps
T656 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1032371617 Mar 31 12:26:48 PM PDT 24 Mar 31 12:37:46 PM PDT 24 240626423004 ps
T108 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1828048721 Mar 31 12:26:53 PM PDT 24 Mar 31 12:26:56 PM PDT 24 834248550 ps
T105 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2432602935 Mar 31 12:27:01 PM PDT 24 Mar 31 12:27:05 PM PDT 24 242707182 ps
T657 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2528552846 Mar 31 12:26:54 PM PDT 24 Mar 31 12:26:55 PM PDT 24 21170484 ps
T658 /workspace/coverage/cover_reg_top/36.hmac_intr_test.1844486606 Mar 31 12:26:57 PM PDT 24 Mar 31 12:26:58 PM PDT 24 12485955 ps
T93 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3890201382 Mar 31 12:26:49 PM PDT 24 Mar 31 12:26:55 PM PDT 24 33905771 ps
T659 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3150664206 Mar 31 12:26:44 PM PDT 24 Mar 31 12:26:46 PM PDT 24 123641269 ps
T660 /workspace/coverage/cover_reg_top/4.hmac_intr_test.1036263499 Mar 31 12:26:56 PM PDT 24 Mar 31 12:26:57 PM PDT 24 52680297 ps
T661 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3203313383 Mar 31 12:26:48 PM PDT 24 Mar 31 12:26:49 PM PDT 24 23484674 ps
T94 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1125204727 Mar 31 12:26:54 PM PDT 24 Mar 31 12:26:54 PM PDT 24 106262451 ps
T95 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.829081547 Mar 31 12:27:00 PM PDT 24 Mar 31 12:27:01 PM PDT 24 35316980 ps
T662 /workspace/coverage/cover_reg_top/33.hmac_intr_test.1241354495 Mar 31 12:27:07 PM PDT 24 Mar 31 12:27:08 PM PDT 24 13974359 ps
T663 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2573495277 Mar 31 12:27:04 PM PDT 24 Mar 31 12:27:05 PM PDT 24 31444260 ps
T664 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1002459195 Mar 31 12:27:04 PM PDT 24 Mar 31 12:27:06 PM PDT 24 519975947 ps
T665 /workspace/coverage/cover_reg_top/26.hmac_intr_test.702884708 Mar 31 12:26:53 PM PDT 24 Mar 31 12:26:54 PM PDT 24 36264533 ps
T666 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3412140241 Mar 31 12:27:42 PM PDT 24 Mar 31 12:27:44 PM PDT 24 363813589 ps
T667 /workspace/coverage/cover_reg_top/45.hmac_intr_test.3187699283 Mar 31 12:27:33 PM PDT 24 Mar 31 12:27:33 PM PDT 24 14734584 ps
T96 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3826815176 Mar 31 12:26:52 PM PDT 24 Mar 31 12:26:54 PM PDT 24 206344161 ps
T668 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.698725159 Mar 31 12:27:01 PM PDT 24 Mar 31 12:27:03 PM PDT 24 136577845 ps
T669 /workspace/coverage/cover_reg_top/40.hmac_intr_test.86427697 Mar 31 12:27:32 PM PDT 24 Mar 31 12:27:33 PM PDT 24 54799706 ps
T106 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1484477652 Mar 31 12:27:22 PM PDT 24 Mar 31 12:27:25 PM PDT 24 500952757 ps
T670 /workspace/coverage/cover_reg_top/2.hmac_intr_test.3214754918 Mar 31 12:26:48 PM PDT 24 Mar 31 12:26:49 PM PDT 24 38484542 ps
T671 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3788667285 Mar 31 12:27:01 PM PDT 24 Mar 31 12:27:06 PM PDT 24 1309334461 ps
T672 /workspace/coverage/cover_reg_top/32.hmac_intr_test.4240292279 Mar 31 12:26:52 PM PDT 24 Mar 31 12:26:52 PM PDT 24 25121826 ps
T673 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.330269281 Mar 31 12:27:01 PM PDT 24 Mar 31 12:27:01 PM PDT 24 47933201 ps
T674 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3503729018 Mar 31 12:27:00 PM PDT 24 Mar 31 12:27:01 PM PDT 24 13642349 ps
T675 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.396763681 Mar 31 12:26:57 PM PDT 24 Mar 31 12:26:57 PM PDT 24 18795933 ps
T676 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.4147816133 Mar 31 12:26:52 PM PDT 24 Mar 31 12:26:53 PM PDT 24 24689458 ps
T677 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3783187703 Mar 31 12:26:55 PM PDT 24 Mar 31 12:26:57 PM PDT 24 106766515 ps
T678 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3169614526 Mar 31 12:26:46 PM PDT 24 Mar 31 12:26:48 PM PDT 24 113722954 ps
T679 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.303188903 Mar 31 12:26:52 PM PDT 24 Mar 31 12:26:55 PM PDT 24 63885765 ps
T680 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.291442050 Mar 31 12:27:37 PM PDT 24 Mar 31 12:27:38 PM PDT 24 21708489 ps
T681 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.836108874 Mar 31 12:26:55 PM PDT 24 Mar 31 12:26:57 PM PDT 24 1116578189 ps
T682 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.983260229 Mar 31 12:27:01 PM PDT 24 Mar 31 12:27:13 PM PDT 24 293370715 ps
T683 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3893716402 Mar 31 12:26:50 PM PDT 24 Mar 31 12:26:52 PM PDT 24 211804286 ps
T684 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3932412512 Mar 31 12:26:50 PM PDT 24 Mar 31 12:26:51 PM PDT 24 18968894 ps
T685 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.201603931 Mar 31 12:27:01 PM PDT 24 Mar 31 12:27:03 PM PDT 24 133584791 ps
T686 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3088603948 Mar 31 12:26:59 PM PDT 24 Mar 31 12:27:00 PM PDT 24 14791489 ps
T687 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1012515008 Mar 31 12:26:54 PM PDT 24 Mar 31 12:26:56 PM PDT 24 68224972 ps
T688 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1282958288 Mar 31 12:26:59 PM PDT 24 Mar 31 12:27:02 PM PDT 24 46332262 ps
T689 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2715833211 Mar 31 12:26:51 PM PDT 24 Mar 31 12:26:53 PM PDT 24 143980385 ps
T690 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3334824160 Mar 31 12:26:54 PM PDT 24 Mar 31 12:26:57 PM PDT 24 153426496 ps
T691 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.946030060 Mar 31 12:26:51 PM PDT 24 Mar 31 12:26:54 PM PDT 24 254522109 ps
T692 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2249839528 Mar 31 12:26:43 PM PDT 24 Mar 31 12:26:47 PM PDT 24 215032748 ps
T693 /workspace/coverage/cover_reg_top/37.hmac_intr_test.3943306839 Mar 31 12:27:51 PM PDT 24 Mar 31 12:27:53 PM PDT 24 13719381 ps
T694 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.802446169 Mar 31 12:26:53 PM PDT 24 Mar 31 12:26:56 PM PDT 24 96847071 ps
T695 /workspace/coverage/cover_reg_top/8.hmac_intr_test.321647346 Mar 31 12:26:55 PM PDT 24 Mar 31 12:26:56 PM PDT 24 17358211 ps
T696 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.669114484 Mar 31 12:26:52 PM PDT 24 Mar 31 12:26:55 PM PDT 24 331713063 ps
T101 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2852231308 Mar 31 12:26:49 PM PDT 24 Mar 31 12:26:53 PM PDT 24 132463683 ps
T697 /workspace/coverage/cover_reg_top/7.hmac_intr_test.70123328 Mar 31 12:27:12 PM PDT 24 Mar 31 12:27:13 PM PDT 24 11203766 ps
T698 /workspace/coverage/cover_reg_top/22.hmac_intr_test.2774534521 Mar 31 12:26:58 PM PDT 24 Mar 31 12:26:58 PM PDT 24 11265523 ps
T699 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.607815845 Mar 31 12:26:48 PM PDT 24 Mar 31 12:26:52 PM PDT 24 1006278615 ps
T700 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3597182675 Mar 31 12:27:00 PM PDT 24 Mar 31 12:27:04 PM PDT 24 239817833 ps
T701 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2835324017 Mar 31 12:27:02 PM PDT 24 Mar 31 12:27:08 PM PDT 24 161240384 ps
T702 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.161945815 Mar 31 12:26:54 PM PDT 24 Mar 31 12:26:56 PM PDT 24 36180839 ps
T703 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.4090781356 Mar 31 12:26:55 PM PDT 24 Mar 31 12:26:56 PM PDT 24 31523067 ps
T704 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2665945257 Mar 31 12:27:01 PM PDT 24 Mar 31 12:27:03 PM PDT 24 36612232 ps
T705 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2997223634 Mar 31 12:26:46 PM PDT 24 Mar 31 12:26:48 PM PDT 24 34432470 ps
T706 /workspace/coverage/cover_reg_top/47.hmac_intr_test.2626517279 Mar 31 12:26:59 PM PDT 24 Mar 31 12:27:00 PM PDT 24 12384922 ps
T707 /workspace/coverage/cover_reg_top/44.hmac_intr_test.1292341642 Mar 31 12:27:05 PM PDT 24 Mar 31 12:27:05 PM PDT 24 17064136 ps
T708 /workspace/coverage/cover_reg_top/17.hmac_intr_test.2435312443 Mar 31 12:27:08 PM PDT 24 Mar 31 12:27:09 PM PDT 24 25002084 ps
T709 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.218518275 Mar 31 12:26:47 PM PDT 24 Mar 31 12:26:51 PM PDT 24 206268050 ps
T102 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.74214907 Mar 31 12:27:02 PM PDT 24 Mar 31 12:27:10 PM PDT 24 215213268 ps
T710 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.4206529691 Mar 31 12:26:45 PM PDT 24 Mar 31 12:26:47 PM PDT 24 410921271 ps
T711 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1015510917 Mar 31 12:27:37 PM PDT 24 Mar 31 12:27:53 PM PDT 24 4222494958 ps
T712 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1263441402 Mar 31 12:27:03 PM PDT 24 Mar 31 12:27:06 PM PDT 24 305069711 ps
T713 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3745553983 Mar 31 12:26:49 PM PDT 24 Mar 31 12:26:59 PM PDT 24 822196540 ps
T714 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2365298646 Mar 31 12:26:53 PM PDT 24 Mar 31 12:26:57 PM PDT 24 629327739 ps
T715 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3287116039 Mar 31 12:27:17 PM PDT 24 Mar 31 12:27:19 PM PDT 24 120029440 ps
T716 /workspace/coverage/cover_reg_top/5.hmac_intr_test.133768340 Mar 31 12:26:59 PM PDT 24 Mar 31 12:27:00 PM PDT 24 43519643 ps
T717 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.738730927 Mar 31 12:27:00 PM PDT 24 Mar 31 12:27:02 PM PDT 24 84102540 ps
T718 /workspace/coverage/cover_reg_top/25.hmac_intr_test.1105033911 Mar 31 12:26:54 PM PDT 24 Mar 31 12:26:55 PM PDT 24 47159672 ps
T103 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1377951124 Mar 31 12:26:57 PM PDT 24 Mar 31 12:27:01 PM PDT 24 223278934 ps
T719 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.511269299 Mar 31 12:26:44 PM PDT 24 Mar 31 12:26:48 PM PDT 24 1090205870 ps
T104 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2391522029 Mar 31 12:26:57 PM PDT 24 Mar 31 12:27:01 PM PDT 24 119214358 ps
T720 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1467254920 Mar 31 12:26:53 PM PDT 24 Mar 31 12:26:55 PM PDT 24 307980330 ps
T721 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3504303690 Mar 31 12:26:45 PM PDT 24 Mar 31 12:26:46 PM PDT 24 174363017 ps
T722 /workspace/coverage/cover_reg_top/14.hmac_intr_test.767843464 Mar 31 12:26:49 PM PDT 24 Mar 31 12:26:50 PM PDT 24 17754984 ps
T723 /workspace/coverage/cover_reg_top/10.hmac_intr_test.3257596114 Mar 31 12:26:49 PM PDT 24 Mar 31 12:26:50 PM PDT 24 119394511 ps
T724 /workspace/coverage/cover_reg_top/35.hmac_intr_test.2452281639 Mar 31 12:26:53 PM PDT 24 Mar 31 12:26:54 PM PDT 24 95603507 ps
T725 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1286767887 Mar 31 12:26:48 PM PDT 24 Mar 31 12:26:49 PM PDT 24 323016886 ps
T726 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3268992252 Mar 31 12:27:01 PM PDT 24 Mar 31 12:27:07 PM PDT 24 1413607554 ps
T727 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2246819486 Mar 31 12:26:53 PM PDT 24 Mar 31 12:26:55 PM PDT 24 23231574 ps
T728 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2088820878 Mar 31 12:26:46 PM PDT 24 Mar 31 12:26:50 PM PDT 24 274123128 ps
T729 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.473693048 Mar 31 12:26:53 PM PDT 24 Mar 31 12:26:54 PM PDT 24 143823482 ps
T730 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1040879149 Mar 31 12:27:05 PM PDT 24 Mar 31 12:27:05 PM PDT 24 56920240 ps
T731 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.66668629 Mar 31 12:26:44 PM PDT 24 Mar 31 12:26:51 PM PDT 24 77736567 ps

Test location /workspace/coverage/default/41.hmac_long_msg.2957644094
Short name T3
Test name
Test status
Simulation time 12411969852 ps
CPU time 47.39 seconds
Started Mar 31 01:02:51 PM PDT 24
Finished Mar 31 01:03:39 PM PDT 24
Peak memory 199700 kb
Host smart-e7550ee8-d775-4254-a8a2-d6b6823f03c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957644094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.2957644094
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_stress_all_with_rand_reset.1002102590
Short name T9
Test name
Test status
Simulation time 21774206996 ps
CPU time 425.78 seconds
Started Mar 31 01:02:14 PM PDT 24
Finished Mar 31 01:09:20 PM PDT 24
Peak memory 207900 kb
Host smart-8b94b49b-7058-46cf-ae01-ecda9d9d643d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1002102590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all_with_rand_reset.1002102590
Directory /workspace/30.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1859250454
Short name T13
Test name
Test status
Simulation time 24063123793 ps
CPU time 1345.68 seconds
Started Mar 31 01:02:59 PM PDT 24
Finished Mar 31 01:25:25 PM PDT 24
Peak memory 234368 kb
Host smart-a19651aa-212d-40a9-9af6-7d0b3a4e113d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859250454 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1859250454
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.636175043
Short name T33
Test name
Test status
Simulation time 31821124 ps
CPU time 0.78 seconds
Started Mar 31 01:00:35 PM PDT 24
Finished Mar 31 01:00:36 PM PDT 24
Peak memory 218128 kb
Host smart-b10debdd-a7d4-45b0-a53e-3b7160afa9ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636175043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.636175043
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3368508541
Short name T64
Test name
Test status
Simulation time 480267274 ps
CPU time 3.85 seconds
Started Mar 31 12:27:03 PM PDT 24
Finished Mar 31 12:27:07 PM PDT 24
Peak memory 199116 kb
Host smart-233d77de-1a90-4720-93ec-af03fc8c67f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368508541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3368508541
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/4.hmac_stress_all.3906013957
Short name T205
Test name
Test status
Simulation time 84512780612 ps
CPU time 1233.9 seconds
Started Mar 31 01:00:41 PM PDT 24
Finished Mar 31 01:21:15 PM PDT 24
Peak memory 208924 kb
Host smart-b18880fe-6518-4249-85d4-c16de1bfdf15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906013957 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.3906013957
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/169.hmac_stress_all_with_rand_reset.3535248572
Short name T52
Test name
Test status
Simulation time 100399081260 ps
CPU time 1251.99 seconds
Started Mar 31 01:04:32 PM PDT 24
Finished Mar 31 01:25:24 PM PDT 24
Peak memory 240712 kb
Host smart-4d7f6a45-7dcc-40e3-a494-302ebd4072f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3535248572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.hmac_stress_all_with_rand_reset.3535248572
Directory /workspace/169.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2808872274
Short name T92
Test name
Test status
Simulation time 610012813 ps
CPU time 8.1 seconds
Started Mar 31 12:26:46 PM PDT 24
Finished Mar 31 12:26:54 PM PDT 24
Peak memory 198752 kb
Host smart-41a28f31-7b18-477e-8d4b-3fded254ac4f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808872274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2808872274
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2739733667
Short name T5
Test name
Test status
Simulation time 15891638600 ps
CPU time 116.18 seconds
Started Mar 31 01:01:30 PM PDT 24
Finished Mar 31 01:03:26 PM PDT 24
Peak memory 199716 kb
Host smart-b05d5255-ca47-4152-99c4-10e572eba79c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739733667 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2739733667
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_alert_test.473339491
Short name T156
Test name
Test status
Simulation time 39327186 ps
CPU time 0.59 seconds
Started Mar 31 01:00:56 PM PDT 24
Finished Mar 31 01:00:57 PM PDT 24
Peak memory 195060 kb
Host smart-cef1b5b2-be96-4374-a070-159b52b34375
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473339491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.473339491
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2432602935
Short name T105
Test name
Test status
Simulation time 242707182 ps
CPU time 4.04 seconds
Started Mar 31 12:27:01 PM PDT 24
Finished Mar 31 12:27:05 PM PDT 24
Peak memory 199112 kb
Host smart-0b9fedb0-135b-4531-a0ae-0754b66bd7cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432602935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2432602935
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2391522029
Short name T104
Test name
Test status
Simulation time 119214358 ps
CPU time 3.77 seconds
Started Mar 31 12:26:57 PM PDT 24
Finished Mar 31 12:27:01 PM PDT 24
Peak memory 199124 kb
Host smart-11844ddd-5755-47a2-8836-e34eb7222975
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391522029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2391522029
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/13.hmac_long_msg.3851189310
Short name T134
Test name
Test status
Simulation time 1458046512 ps
CPU time 86.55 seconds
Started Mar 31 01:00:57 PM PDT 24
Finished Mar 31 01:02:24 PM PDT 24
Peak memory 199596 kb
Host smart-43aef94a-7625-4cf1-a76c-f23fc4fbf213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851189310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.3851189310
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/136.hmac_stress_all_with_rand_reset.3404165197
Short name T51
Test name
Test status
Simulation time 96838743543 ps
CPU time 1229.86 seconds
Started Mar 31 01:04:17 PM PDT 24
Finished Mar 31 01:24:47 PM PDT 24
Peak memory 248088 kb
Host smart-2b190d83-19a3-4e79-9a74-b711001c9adb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3404165197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.hmac_stress_all_with_rand_reset.3404165197
Directory /workspace/136.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3268992252
Short name T726
Test name
Test status
Simulation time 1413607554 ps
CPU time 5.42 seconds
Started Mar 31 12:27:01 PM PDT 24
Finished Mar 31 12:27:07 PM PDT 24
Peak memory 198092 kb
Host smart-c6298790-5c2d-4d77-b4c5-2ebe4be2250d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268992252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3268992252
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1784895158
Short name T604
Test name
Test status
Simulation time 613391934 ps
CPU time 0.99 seconds
Started Mar 31 12:26:56 PM PDT 24
Finished Mar 31 12:26:57 PM PDT 24
Peak memory 198896 kb
Host smart-e46601e4-9643-44df-bf90-5d58747c5a05
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784895158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1784895158
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3600588463
Short name T642
Test name
Test status
Simulation time 91085535 ps
CPU time 2.24 seconds
Started Mar 31 12:26:55 PM PDT 24
Finished Mar 31 12:26:57 PM PDT 24
Peak memory 199124 kb
Host smart-e7814e5f-9eac-4f9f-bf9a-40bd9a74bbab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600588463 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.3600588463
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1789621377
Short name T88
Test name
Test status
Simulation time 27027469 ps
CPU time 0.68 seconds
Started Mar 31 12:26:58 PM PDT 24
Finished Mar 31 12:26:59 PM PDT 24
Peak memory 196684 kb
Host smart-72e1e836-f58a-499a-98cd-c5261d17720e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789621377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1789621377
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.364837734
Short name T621
Test name
Test status
Simulation time 55374463 ps
CPU time 0.61 seconds
Started Mar 31 12:26:58 PM PDT 24
Finished Mar 31 12:26:59 PM PDT 24
Peak memory 193756 kb
Host smart-52bb468a-ad9d-4cb5-921f-1813419c0e49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364837734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.364837734
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1286767887
Short name T725
Test name
Test status
Simulation time 323016886 ps
CPU time 1.77 seconds
Started Mar 31 12:26:48 PM PDT 24
Finished Mar 31 12:26:49 PM PDT 24
Peak memory 198808 kb
Host smart-667c2fcd-e831-4b83-bfc7-69b7ba78b6e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286767887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.1286767887
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.607815845
Short name T699
Test name
Test status
Simulation time 1006278615 ps
CPU time 4.5 seconds
Started Mar 31 12:26:48 PM PDT 24
Finished Mar 31 12:26:52 PM PDT 24
Peak memory 199208 kb
Host smart-3825f2e0-43ef-4ab9-83e9-f4310ad4b169
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607815845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.607815845
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2852231308
Short name T101
Test name
Test status
Simulation time 132463683 ps
CPU time 3.98 seconds
Started Mar 31 12:26:49 PM PDT 24
Finished Mar 31 12:26:53 PM PDT 24
Peak memory 199148 kb
Host smart-78313bd5-dc38-436b-bdb3-1ea90900e864
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852231308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2852231308
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.42429001
Short name T85
Test name
Test status
Simulation time 107841880 ps
CPU time 5.58 seconds
Started Mar 31 12:26:58 PM PDT 24
Finished Mar 31 12:27:03 PM PDT 24
Peak memory 198468 kb
Host smart-767ea1ea-8355-43db-aaab-28af407c0937
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42429001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.42429001
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1591337489
Short name T648
Test name
Test status
Simulation time 1475135929 ps
CPU time 5.59 seconds
Started Mar 31 12:26:51 PM PDT 24
Finished Mar 31 12:26:57 PM PDT 24
Peak memory 197976 kb
Host smart-fdb4b487-1835-45d0-bddb-2e1e23a3f06c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591337489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1591337489
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3826815176
Short name T96
Test name
Test status
Simulation time 206344161 ps
CPU time 0.95 seconds
Started Mar 31 12:26:52 PM PDT 24
Finished Mar 31 12:26:54 PM PDT 24
Peak memory 198252 kb
Host smart-7760779c-8433-47cf-9685-1c1a48905d12
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826815176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3826815176
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2877545351
Short name T613
Test name
Test status
Simulation time 136327892 ps
CPU time 2.28 seconds
Started Mar 31 12:26:51 PM PDT 24
Finished Mar 31 12:26:53 PM PDT 24
Peak memory 199172 kb
Host smart-9208f3a3-d5cc-4ae4-a561-4659dd1e1b04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877545351 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2877545351
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.330269281
Short name T673
Test name
Test status
Simulation time 47933201 ps
CPU time 0.68 seconds
Started Mar 31 12:27:01 PM PDT 24
Finished Mar 31 12:27:01 PM PDT 24
Peak memory 196892 kb
Host smart-a7c9c4bb-4c2c-4e4e-89dc-c718a0eda95d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330269281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.330269281
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2934172402
Short name T623
Test name
Test status
Simulation time 14594649 ps
CPU time 0.6 seconds
Started Mar 31 12:26:57 PM PDT 24
Finished Mar 31 12:26:58 PM PDT 24
Peak memory 193824 kb
Host smart-14958469-8d32-452f-a11d-a747802876b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934172402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2934172402
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2835324017
Short name T701
Test name
Test status
Simulation time 161240384 ps
CPU time 1.11 seconds
Started Mar 31 12:27:02 PM PDT 24
Finished Mar 31 12:27:08 PM PDT 24
Peak memory 197228 kb
Host smart-96d6feac-74f8-46b1-b3a4-f6bb1a896eb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835324017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2835324017
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1125114203
Short name T608
Test name
Test status
Simulation time 244503309 ps
CPU time 2.86 seconds
Started Mar 31 12:26:54 PM PDT 24
Finished Mar 31 12:26:57 PM PDT 24
Peak memory 199136 kb
Host smart-03531587-a823-4854-a2c5-bb4675d83cdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125114203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1125114203
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2088820878
Short name T728
Test name
Test status
Simulation time 274123128 ps
CPU time 4.26 seconds
Started Mar 31 12:26:46 PM PDT 24
Finished Mar 31 12:26:50 PM PDT 24
Peak memory 199076 kb
Host smart-8b73c95c-1519-4a60-8787-d00482b6a4e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088820878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2088820878
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2168070146
Short name T616
Test name
Test status
Simulation time 45217675 ps
CPU time 1.31 seconds
Started Mar 31 12:26:57 PM PDT 24
Finished Mar 31 12:26:58 PM PDT 24
Peak memory 199096 kb
Host smart-5b9bca2a-cf73-4666-a82c-77b3423c2005
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168070146 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2168070146
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.396763681
Short name T675
Test name
Test status
Simulation time 18795933 ps
CPU time 0.67 seconds
Started Mar 31 12:26:57 PM PDT 24
Finished Mar 31 12:26:57 PM PDT 24
Peak memory 196704 kb
Host smart-3dfe877c-f851-43b8-8594-679d2bb7d40d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396763681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.396763681
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3257596114
Short name T723
Test name
Test status
Simulation time 119394511 ps
CPU time 0.62 seconds
Started Mar 31 12:26:49 PM PDT 24
Finished Mar 31 12:26:50 PM PDT 24
Peak memory 193776 kb
Host smart-601f6e9b-5152-4866-bfb8-cd80c635e437
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257596114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3257596114
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.591943291
Short name T607
Test name
Test status
Simulation time 76774054 ps
CPU time 1.05 seconds
Started Mar 31 12:26:43 PM PDT 24
Finished Mar 31 12:26:44 PM PDT 24
Peak memory 199104 kb
Host smart-8f9117af-3e82-4347-82ad-791ae70302c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591943291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr
_outstanding.591943291
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1012515008
Short name T687
Test name
Test status
Simulation time 68224972 ps
CPU time 1.83 seconds
Started Mar 31 12:26:54 PM PDT 24
Finished Mar 31 12:26:56 PM PDT 24
Peak memory 199176 kb
Host smart-c7393955-5dff-47fd-ac59-fb51d27042e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012515008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1012515008
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1828048721
Short name T108
Test name
Test status
Simulation time 834248550 ps
CPU time 3.32 seconds
Started Mar 31 12:26:53 PM PDT 24
Finished Mar 31 12:26:56 PM PDT 24
Peak memory 199228 kb
Host smart-6bad4f3f-5f4d-495b-b560-3c0042bc2800
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828048721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1828048721
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.669114484
Short name T696
Test name
Test status
Simulation time 331713063 ps
CPU time 2.15 seconds
Started Mar 31 12:26:52 PM PDT 24
Finished Mar 31 12:26:55 PM PDT 24
Peak memory 199188 kb
Host smart-dc84b91a-dde5-4fa2-a3c2-11d97da247f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669114484 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.669114484
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3503729018
Short name T674
Test name
Test status
Simulation time 13642349 ps
CPU time 0.69 seconds
Started Mar 31 12:27:00 PM PDT 24
Finished Mar 31 12:27:01 PM PDT 24
Peak memory 197096 kb
Host smart-81dbff31-78e8-41c2-8afc-ca8ff8696fbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503729018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3503729018
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.551288342
Short name T644
Test name
Test status
Simulation time 17757259 ps
CPU time 0.58 seconds
Started Mar 31 12:26:43 PM PDT 24
Finished Mar 31 12:26:43 PM PDT 24
Peak memory 194268 kb
Host smart-87aabcfa-4f7e-476a-91a7-f0f4fd58134e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551288342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.551288342
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3287116039
Short name T715
Test name
Test status
Simulation time 120029440 ps
CPU time 2.39 seconds
Started Mar 31 12:27:17 PM PDT 24
Finished Mar 31 12:27:19 PM PDT 24
Peak memory 199148 kb
Host smart-887be8ee-02d1-4883-9e99-ef4e378309c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287116039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3287116039
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1181860428
Short name T654
Test name
Test status
Simulation time 262396778 ps
CPU time 3.48 seconds
Started Mar 31 12:26:55 PM PDT 24
Finished Mar 31 12:26:59 PM PDT 24
Peak memory 199144 kb
Host smart-5dc1e2bb-b8c3-4581-8e39-8e33de4d55dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181860428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1181860428
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3990250790
Short name T99
Test name
Test status
Simulation time 616030515 ps
CPU time 2.73 seconds
Started Mar 31 12:26:56 PM PDT 24
Finished Mar 31 12:26:59 PM PDT 24
Peak memory 199060 kb
Host smart-dfa90762-0510-4a16-998f-7a4482d8f225
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990250790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3990250790
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3581420583
Short name T618
Test name
Test status
Simulation time 208845429 ps
CPU time 2.39 seconds
Started Mar 31 12:27:42 PM PDT 24
Finished Mar 31 12:27:45 PM PDT 24
Peak memory 199128 kb
Host smart-eb97c43c-e1bf-4cee-9bda-066f234c0622
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581420583 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.3581420583
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3932412512
Short name T684
Test name
Test status
Simulation time 18968894 ps
CPU time 0.77 seconds
Started Mar 31 12:26:50 PM PDT 24
Finished Mar 31 12:26:51 PM PDT 24
Peak memory 198376 kb
Host smart-24b12ab6-7460-44a0-b5f2-400a58adaadb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932412512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3932412512
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2333792553
Short name T636
Test name
Test status
Simulation time 125679905 ps
CPU time 0.54 seconds
Started Mar 31 12:26:52 PM PDT 24
Finished Mar 31 12:26:53 PM PDT 24
Peak memory 193948 kb
Host smart-69d9bbef-1c4f-43ea-af58-651eedc74fdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333792553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2333792553
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3203313383
Short name T661
Test name
Test status
Simulation time 23484674 ps
CPU time 1.13 seconds
Started Mar 31 12:26:48 PM PDT 24
Finished Mar 31 12:26:49 PM PDT 24
Peak memory 198648 kb
Host smart-c0c90a60-3721-4d5a-a49a-0188862466e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203313383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.3203313383
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1263441402
Short name T712
Test name
Test status
Simulation time 305069711 ps
CPU time 2.79 seconds
Started Mar 31 12:27:03 PM PDT 24
Finished Mar 31 12:27:06 PM PDT 24
Peak memory 199128 kb
Host smart-9ecf11a5-8b6e-48cf-823e-fba671c68d46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263441402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1263441402
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3250788901
Short name T630
Test name
Test status
Simulation time 91566880 ps
CPU time 2.76 seconds
Started Mar 31 12:26:58 PM PDT 24
Finished Mar 31 12:27:01 PM PDT 24
Peak memory 199036 kb
Host smart-4bf6572d-e14b-4209-b4b5-cc910dab45da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250788901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3250788901
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2501554604
Short name T652
Test name
Test status
Simulation time 366966405 ps
CPU time 1.48 seconds
Started Mar 31 12:27:00 PM PDT 24
Finished Mar 31 12:27:02 PM PDT 24
Peak memory 199172 kb
Host smart-09c91821-aa6b-485f-b274-74f9a4710b03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501554604 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2501554604
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.4090781356
Short name T703
Test name
Test status
Simulation time 31523067 ps
CPU time 0.85 seconds
Started Mar 31 12:26:55 PM PDT 24
Finished Mar 31 12:26:56 PM PDT 24
Peak memory 198432 kb
Host smart-49858395-d97e-4fab-baf9-5da498536851
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090781356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.4090781356
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.4119801547
Short name T643
Test name
Test status
Simulation time 25290030 ps
CPU time 0.55 seconds
Started Mar 31 12:26:46 PM PDT 24
Finished Mar 31 12:26:47 PM PDT 24
Peak memory 193996 kb
Host smart-3b68c248-a9b0-40b7-9c67-0fd13a9dd5f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119801547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.4119801547
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3546592134
Short name T614
Test name
Test status
Simulation time 846088077 ps
CPU time 2.19 seconds
Started Mar 31 12:27:01 PM PDT 24
Finished Mar 31 12:27:04 PM PDT 24
Peak memory 199056 kb
Host smart-cf1f80e8-88cc-4cb6-bd09-b51d2ac5bde9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546592134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3546592134
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3624010014
Short name T611
Test name
Test status
Simulation time 67987985 ps
CPU time 1.53 seconds
Started Mar 31 12:27:09 PM PDT 24
Finished Mar 31 12:27:11 PM PDT 24
Peak memory 199204 kb
Host smart-d0c1b254-f97a-498b-b255-8186d2f91eb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624010014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3624010014
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2949470905
Short name T597
Test name
Test status
Simulation time 502190133 ps
CPU time 2.28 seconds
Started Mar 31 12:27:04 PM PDT 24
Finished Mar 31 12:27:06 PM PDT 24
Peak memory 199164 kb
Host smart-70404633-3c37-4528-8f8f-af90b6c88f82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949470905 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2949470905
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2827384689
Short name T619
Test name
Test status
Simulation time 16186008 ps
CPU time 0.69 seconds
Started Mar 31 12:27:00 PM PDT 24
Finished Mar 31 12:27:00 PM PDT 24
Peak memory 196444 kb
Host smart-9cc91458-138c-4eb9-bc8d-9d0b2aa4320c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827384689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2827384689
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.767843464
Short name T722
Test name
Test status
Simulation time 17754984 ps
CPU time 0.57 seconds
Started Mar 31 12:26:49 PM PDT 24
Finished Mar 31 12:26:50 PM PDT 24
Peak memory 193968 kb
Host smart-a7df7f44-e2eb-43d7-a6d8-9eaf8fae8232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767843464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.767843464
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3412140241
Short name T666
Test name
Test status
Simulation time 363813589 ps
CPU time 1.09 seconds
Started Mar 31 12:27:42 PM PDT 24
Finished Mar 31 12:27:44 PM PDT 24
Peak memory 197416 kb
Host smart-312b360c-7bb4-46e2-98af-d663eed10020
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412140241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3412140241
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2469797695
Short name T600
Test name
Test status
Simulation time 816786692 ps
CPU time 3.52 seconds
Started Mar 31 12:27:11 PM PDT 24
Finished Mar 31 12:27:15 PM PDT 24
Peak memory 199140 kb
Host smart-aba232ce-d4dd-4fb0-8e54-baf590811aa7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469797695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2469797695
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1484477652
Short name T106
Test name
Test status
Simulation time 500952757 ps
CPU time 2.73 seconds
Started Mar 31 12:27:22 PM PDT 24
Finished Mar 31 12:27:25 PM PDT 24
Peak memory 199096 kb
Host smart-4ed7ff5b-2396-4b43-be75-8982fd234295
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484477652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1484477652
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.504896397
Short name T637
Test name
Test status
Simulation time 36628738 ps
CPU time 2.16 seconds
Started Mar 31 12:26:57 PM PDT 24
Finished Mar 31 12:27:00 PM PDT 24
Peak memory 199128 kb
Host smart-ec13f907-5266-4354-b5e7-047b6a288851
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504896397 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.504896397
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1140921378
Short name T87
Test name
Test status
Simulation time 17710676 ps
CPU time 0.79 seconds
Started Mar 31 12:27:00 PM PDT 24
Finished Mar 31 12:27:01 PM PDT 24
Peak memory 198400 kb
Host smart-7ac1933c-a1fb-4422-a62e-408efb052241
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140921378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1140921378
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1626995321
Short name T653
Test name
Test status
Simulation time 48366970 ps
CPU time 0.58 seconds
Started Mar 31 12:26:51 PM PDT 24
Finished Mar 31 12:26:52 PM PDT 24
Peak memory 193712 kb
Host smart-eface965-7fd2-4eca-9762-065a1e6a25f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626995321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1626995321
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.425589534
Short name T646
Test name
Test status
Simulation time 180292900 ps
CPU time 1.66 seconds
Started Mar 31 12:27:47 PM PDT 24
Finished Mar 31 12:27:49 PM PDT 24
Peak memory 199060 kb
Host smart-e4ad109c-262c-48cf-a55f-1d118ee4f22b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425589534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr
_outstanding.425589534
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.983260229
Short name T682
Test name
Test status
Simulation time 293370715 ps
CPU time 1.61 seconds
Started Mar 31 12:27:01 PM PDT 24
Finished Mar 31 12:27:13 PM PDT 24
Peak memory 199172 kb
Host smart-83dadf3e-9d04-42de-a2c8-8105ea2455bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983260229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.983260229
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.919352928
Short name T655
Test name
Test status
Simulation time 29185506 ps
CPU time 1.64 seconds
Started Mar 31 12:27:01 PM PDT 24
Finished Mar 31 12:27:13 PM PDT 24
Peak memory 199160 kb
Host smart-ccb3aa80-be7b-427d-9421-4bad088f2d61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919352928 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.919352928
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1125204727
Short name T94
Test name
Test status
Simulation time 106262451 ps
CPU time 0.89 seconds
Started Mar 31 12:26:54 PM PDT 24
Finished Mar 31 12:26:54 PM PDT 24
Peak memory 198216 kb
Host smart-a7ea2607-6284-404a-ba17-8b0c689d0c9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125204727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1125204727
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.2043427516
Short name T634
Test name
Test status
Simulation time 23300242 ps
CPU time 0.55 seconds
Started Mar 31 12:27:02 PM PDT 24
Finished Mar 31 12:27:02 PM PDT 24
Peak memory 193728 kb
Host smart-b84f8bd2-5d77-488f-ae84-6ef0645a7fc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043427516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2043427516
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.4135742093
Short name T606
Test name
Test status
Simulation time 89234678 ps
CPU time 1 seconds
Started Mar 31 12:27:05 PM PDT 24
Finished Mar 31 12:27:06 PM PDT 24
Peak memory 198976 kb
Host smart-2387fa27-7620-4fd0-a540-e4299735233d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135742093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.4135742093
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.802446169
Short name T694
Test name
Test status
Simulation time 96847071 ps
CPU time 2.38 seconds
Started Mar 31 12:26:53 PM PDT 24
Finished Mar 31 12:26:56 PM PDT 24
Peak memory 199160 kb
Host smart-96d6c248-d594-400e-a661-e9331a25d9a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802446169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.802446169
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3973520149
Short name T98
Test name
Test status
Simulation time 243579491 ps
CPU time 3.78 seconds
Started Mar 31 12:27:46 PM PDT 24
Finished Mar 31 12:27:50 PM PDT 24
Peak memory 199088 kb
Host smart-e5ca0be4-c1dd-44e9-8605-2b3278dea78e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973520149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3973520149
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2665945257
Short name T704
Test name
Test status
Simulation time 36612232 ps
CPU time 2.24 seconds
Started Mar 31 12:27:01 PM PDT 24
Finished Mar 31 12:27:03 PM PDT 24
Peak memory 199156 kb
Host smart-4adea4f3-7aaf-4d13-aab2-816fdaea5e0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665945257 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2665945257
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2531386771
Short name T603
Test name
Test status
Simulation time 41369126 ps
CPU time 0.66 seconds
Started Mar 31 12:26:54 PM PDT 24
Finished Mar 31 12:26:55 PM PDT 24
Peak memory 196700 kb
Host smart-acc4e74c-4e42-4856-ae6a-417e36e92655
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531386771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2531386771
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2435312443
Short name T708
Test name
Test status
Simulation time 25002084 ps
CPU time 0.56 seconds
Started Mar 31 12:27:08 PM PDT 24
Finished Mar 31 12:27:09 PM PDT 24
Peak memory 193820 kb
Host smart-7ecaee29-df15-473f-8e1c-1478a2e0b01d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435312443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2435312443
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.879436590
Short name T617
Test name
Test status
Simulation time 197067977 ps
CPU time 1.82 seconds
Started Mar 31 12:27:00 PM PDT 24
Finished Mar 31 12:27:02 PM PDT 24
Peak memory 199112 kb
Host smart-db0c0bf2-70d2-4500-aee1-ba86c7966c47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879436590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr
_outstanding.879436590
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.137746251
Short name T620
Test name
Test status
Simulation time 368646078 ps
CPU time 3.57 seconds
Started Mar 31 12:27:00 PM PDT 24
Finished Mar 31 12:27:04 PM PDT 24
Peak memory 199156 kb
Host smart-30f794c6-a2f0-4e64-8efa-5d827a36ad83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137746251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.137746251
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.738730927
Short name T717
Test name
Test status
Simulation time 84102540 ps
CPU time 1.75 seconds
Started Mar 31 12:27:00 PM PDT 24
Finished Mar 31 12:27:02 PM PDT 24
Peak memory 199060 kb
Host smart-baba632b-ac42-4417-bf9c-322b4604bbc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738730927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.738730927
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2167775914
Short name T641
Test name
Test status
Simulation time 29358349 ps
CPU time 1.81 seconds
Started Mar 31 12:27:00 PM PDT 24
Finished Mar 31 12:27:07 PM PDT 24
Peak memory 199244 kb
Host smart-55f0669e-5d2a-4e15-9115-556fedcf2e3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167775914 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2167775914
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2573495277
Short name T663
Test name
Test status
Simulation time 31444260 ps
CPU time 0.91 seconds
Started Mar 31 12:27:04 PM PDT 24
Finished Mar 31 12:27:05 PM PDT 24
Peak memory 198912 kb
Host smart-0b9bb02d-a96f-4275-86ff-77fd7be92315
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573495277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2573495277
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3649254685
Short name T602
Test name
Test status
Simulation time 118429482 ps
CPU time 0.56 seconds
Started Mar 31 12:27:18 PM PDT 24
Finished Mar 31 12:27:19 PM PDT 24
Peak memory 193796 kb
Host smart-233cd337-7d3a-49f6-af57-be45db99a475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649254685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3649254685
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.291442050
Short name T680
Test name
Test status
Simulation time 21708489 ps
CPU time 1.11 seconds
Started Mar 31 12:27:37 PM PDT 24
Finished Mar 31 12:27:38 PM PDT 24
Peak memory 198360 kb
Host smart-8a5e445f-a9af-4546-86c8-1fa9f7e3589e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291442050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.291442050
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4263976672
Short name T651
Test name
Test status
Simulation time 528669026 ps
CPU time 2.81 seconds
Started Mar 31 12:26:57 PM PDT 24
Finished Mar 31 12:27:00 PM PDT 24
Peak memory 199164 kb
Host smart-8e268dda-d19f-4766-9b7c-2f9c308a8a0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263976672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.4263976672
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2246819486
Short name T727
Test name
Test status
Simulation time 23231574 ps
CPU time 1.24 seconds
Started Mar 31 12:26:53 PM PDT 24
Finished Mar 31 12:26:55 PM PDT 24
Peak memory 199160 kb
Host smart-6d560dab-50bd-429f-96f9-bae0e9fae76d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246819486 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.2246819486
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2924502271
Short name T86
Test name
Test status
Simulation time 16532637 ps
CPU time 0.8 seconds
Started Mar 31 12:27:07 PM PDT 24
Finished Mar 31 12:27:08 PM PDT 24
Peak memory 198376 kb
Host smart-a666e426-7328-49bb-a049-f5b38451eaa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924502271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2924502271
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2154710638
Short name T633
Test name
Test status
Simulation time 78061109 ps
CPU time 0.55 seconds
Started Mar 31 12:27:35 PM PDT 24
Finished Mar 31 12:27:35 PM PDT 24
Peak memory 193716 kb
Host smart-2355c226-49c8-48a2-a77f-cff32877a232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154710638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2154710638
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1002459195
Short name T664
Test name
Test status
Simulation time 519975947 ps
CPU time 2.19 seconds
Started Mar 31 12:27:04 PM PDT 24
Finished Mar 31 12:27:06 PM PDT 24
Peak memory 198800 kb
Host smart-41be3dae-abe7-413a-add2-7e1bdca41966
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002459195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1002459195
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2997223634
Short name T705
Test name
Test status
Simulation time 34432470 ps
CPU time 1.81 seconds
Started Mar 31 12:26:46 PM PDT 24
Finished Mar 31 12:26:48 PM PDT 24
Peak memory 199108 kb
Host smart-1b281aa0-c8c3-4e8f-937d-88541a67d33c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997223634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2997223634
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1377951124
Short name T103
Test name
Test status
Simulation time 223278934 ps
CPU time 4.18 seconds
Started Mar 31 12:26:57 PM PDT 24
Finished Mar 31 12:27:01 PM PDT 24
Peak memory 199108 kb
Host smart-322f7154-b60a-411b-a3fb-f0062de4237b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377951124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1377951124
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.303188903
Short name T679
Test name
Test status
Simulation time 63885765 ps
CPU time 2.93 seconds
Started Mar 31 12:26:52 PM PDT 24
Finished Mar 31 12:26:55 PM PDT 24
Peak memory 199056 kb
Host smart-9a1cd0d7-86e0-471c-9694-b671adc720d9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303188903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.303188903
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1015510917
Short name T711
Test name
Test status
Simulation time 4222494958 ps
CPU time 15.79 seconds
Started Mar 31 12:27:37 PM PDT 24
Finished Mar 31 12:27:53 PM PDT 24
Peak memory 198232 kb
Host smart-edc27981-ec70-4580-a65e-3dbe93ecf875
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015510917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.1015510917
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3890201382
Short name T93
Test name
Test status
Simulation time 33905771 ps
CPU time 0.87 seconds
Started Mar 31 12:26:49 PM PDT 24
Finished Mar 31 12:26:55 PM PDT 24
Peak memory 198160 kb
Host smart-a2bea06f-0fd3-49cb-a952-6362fb75d167
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890201382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3890201382
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.122545816
Short name T622
Test name
Test status
Simulation time 85868682 ps
CPU time 1.25 seconds
Started Mar 31 12:26:57 PM PDT 24
Finished Mar 31 12:26:58 PM PDT 24
Peak memory 199216 kb
Host smart-dff59e5d-3d03-4e18-b34f-b4a624b3c2ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122545816 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.122545816
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1710232371
Short name T68
Test name
Test status
Simulation time 26224992 ps
CPU time 0.83 seconds
Started Mar 31 12:27:31 PM PDT 24
Finished Mar 31 12:27:32 PM PDT 24
Peak memory 198936 kb
Host smart-e0fa44d9-5942-4e71-a931-c5ba23415726
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710232371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1710232371
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.3214754918
Short name T670
Test name
Test status
Simulation time 38484542 ps
CPU time 0.56 seconds
Started Mar 31 12:26:48 PM PDT 24
Finished Mar 31 12:26:49 PM PDT 24
Peak memory 193748 kb
Host smart-548fcace-eaf3-4065-96fa-e2f389736213
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214754918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3214754918
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1282958288
Short name T688
Test name
Test status
Simulation time 46332262 ps
CPU time 2.07 seconds
Started Mar 31 12:26:59 PM PDT 24
Finished Mar 31 12:27:02 PM PDT 24
Peak memory 199008 kb
Host smart-2e570ddf-5708-41a6-a145-01e79bbd93f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282958288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1282958288
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3597182675
Short name T700
Test name
Test status
Simulation time 239817833 ps
CPU time 3.77 seconds
Started Mar 31 12:27:00 PM PDT 24
Finished Mar 31 12:27:04 PM PDT 24
Peak memory 199156 kb
Host smart-b86eedb5-2ff1-4711-8a7e-aaec2f628b5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597182675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3597182675
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.12193076
Short name T632
Test name
Test status
Simulation time 51028403 ps
CPU time 1.62 seconds
Started Mar 31 12:27:00 PM PDT 24
Finished Mar 31 12:27:02 PM PDT 24
Peak memory 199100 kb
Host smart-0eba53e4-91ea-4ca4-a1ab-d50ca257efac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12193076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.12193076
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1774604740
Short name T624
Test name
Test status
Simulation time 60334548 ps
CPU time 0.6 seconds
Started Mar 31 12:27:00 PM PDT 24
Finished Mar 31 12:27:00 PM PDT 24
Peak memory 193996 kb
Host smart-5b2634b9-cfd6-4960-a438-a0b53c6e2403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774604740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1774604740
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3831009631
Short name T629
Test name
Test status
Simulation time 19013298 ps
CPU time 0.61 seconds
Started Mar 31 12:27:12 PM PDT 24
Finished Mar 31 12:27:18 PM PDT 24
Peak memory 193992 kb
Host smart-6c9eeb90-8530-419c-b82c-1209111cac8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831009631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3831009631
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.2774534521
Short name T698
Test name
Test status
Simulation time 11265523 ps
CPU time 0.55 seconds
Started Mar 31 12:26:58 PM PDT 24
Finished Mar 31 12:26:58 PM PDT 24
Peak memory 193976 kb
Host smart-65ff6b76-068a-43f3-a583-82faae8eba00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774534521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.2774534521
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1361819451
Short name T609
Test name
Test status
Simulation time 16202017 ps
CPU time 0.62 seconds
Started Mar 31 12:26:57 PM PDT 24
Finished Mar 31 12:27:03 PM PDT 24
Peak memory 194028 kb
Host smart-d3d060d9-7aa5-490c-a795-4c0007dad661
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361819451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1361819451
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3351547217
Short name T635
Test name
Test status
Simulation time 17155170 ps
CPU time 0.61 seconds
Started Mar 31 12:27:51 PM PDT 24
Finished Mar 31 12:27:53 PM PDT 24
Peak memory 193972 kb
Host smart-d5c12df3-ba22-41d7-8b99-ff3493880161
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351547217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3351547217
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1105033911
Short name T718
Test name
Test status
Simulation time 47159672 ps
CPU time 0.57 seconds
Started Mar 31 12:26:54 PM PDT 24
Finished Mar 31 12:26:55 PM PDT 24
Peak memory 193800 kb
Host smart-c54f09ac-1a57-4eee-84a2-692ba34d1bcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105033911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1105033911
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.702884708
Short name T665
Test name
Test status
Simulation time 36264533 ps
CPU time 0.6 seconds
Started Mar 31 12:26:53 PM PDT 24
Finished Mar 31 12:26:54 PM PDT 24
Peak memory 194068 kb
Host smart-ea2fa2c9-d7cd-4796-8a32-c6995a807042
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702884708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.702884708
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1924879403
Short name T627
Test name
Test status
Simulation time 14406853 ps
CPU time 0.57 seconds
Started Mar 31 12:26:52 PM PDT 24
Finished Mar 31 12:26:53 PM PDT 24
Peak memory 193740 kb
Host smart-d5af6dfb-fa85-4f1b-b4c2-19da6d686925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924879403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1924879403
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2042882257
Short name T625
Test name
Test status
Simulation time 40444725 ps
CPU time 0.58 seconds
Started Mar 31 12:26:55 PM PDT 24
Finished Mar 31 12:26:56 PM PDT 24
Peak memory 193684 kb
Host smart-74fc68c5-31de-4527-ab96-b5957f3a075b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042882257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2042882257
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2062050951
Short name T610
Test name
Test status
Simulation time 27198152 ps
CPU time 0.6 seconds
Started Mar 31 12:27:41 PM PDT 24
Finished Mar 31 12:27:42 PM PDT 24
Peak memory 193728 kb
Host smart-14b420c8-f287-43a0-ac42-f550456d737e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062050951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2062050951
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4244234479
Short name T91
Test name
Test status
Simulation time 2121033809 ps
CPU time 5.94 seconds
Started Mar 31 12:26:53 PM PDT 24
Finished Mar 31 12:26:59 PM PDT 24
Peak memory 198564 kb
Host smart-0874b2d9-a77e-47fb-8ff8-42f4a4957935
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244234479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.4244234479
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3745553983
Short name T713
Test name
Test status
Simulation time 822196540 ps
CPU time 9.47 seconds
Started Mar 31 12:26:49 PM PDT 24
Finished Mar 31 12:26:59 PM PDT 24
Peak memory 198136 kb
Host smart-fe195cb1-aaa4-44a6-a9e0-5c0692c81b61
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745553983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3745553983
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1326268913
Short name T605
Test name
Test status
Simulation time 119313869 ps
CPU time 0.71 seconds
Started Mar 31 12:26:57 PM PDT 24
Finished Mar 31 12:26:57 PM PDT 24
Peak memory 196540 kb
Host smart-8a4e0727-49f5-4472-9826-bd146817fc2d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326268913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1326268913
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.698725159
Short name T668
Test name
Test status
Simulation time 136577845 ps
CPU time 1.84 seconds
Started Mar 31 12:27:01 PM PDT 24
Finished Mar 31 12:27:03 PM PDT 24
Peak memory 199092 kb
Host smart-93bbc247-42de-4786-8285-a7f381b4799b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698725159 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.698725159
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2018204585
Short name T89
Test name
Test status
Simulation time 50224382 ps
CPU time 0.86 seconds
Started Mar 31 12:26:58 PM PDT 24
Finished Mar 31 12:26:59 PM PDT 24
Peak memory 198460 kb
Host smart-38823f72-32fb-49da-86ce-016abe2c520a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018204585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2018204585
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.1424018783
Short name T599
Test name
Test status
Simulation time 17521013 ps
CPU time 0.68 seconds
Started Mar 31 12:26:56 PM PDT 24
Finished Mar 31 12:26:57 PM PDT 24
Peak memory 193772 kb
Host smart-32461ad6-c22f-41b5-8492-ca6ab3c32de9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424018783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.1424018783
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3169614526
Short name T678
Test name
Test status
Simulation time 113722954 ps
CPU time 2.24 seconds
Started Mar 31 12:26:46 PM PDT 24
Finished Mar 31 12:26:48 PM PDT 24
Peak memory 198896 kb
Host smart-8112443e-d8c3-41fe-8fd3-cfadebfdf58a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169614526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3169614526
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.121597234
Short name T631
Test name
Test status
Simulation time 401279942 ps
CPU time 1.23 seconds
Started Mar 31 12:26:51 PM PDT 24
Finished Mar 31 12:26:52 PM PDT 24
Peak memory 199468 kb
Host smart-ee27929e-121c-4cd1-b5ad-cdf40ace1f57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121597234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.121597234
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.74214907
Short name T102
Test name
Test status
Simulation time 215213268 ps
CPU time 2.75 seconds
Started Mar 31 12:27:02 PM PDT 24
Finished Mar 31 12:27:10 PM PDT 24
Peak memory 199052 kb
Host smart-555e5d4d-6c0b-4abb-a1f4-e0641a44ba93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74214907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.74214907
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1040879149
Short name T730
Test name
Test status
Simulation time 56920240 ps
CPU time 0.57 seconds
Started Mar 31 12:27:05 PM PDT 24
Finished Mar 31 12:27:05 PM PDT 24
Peak memory 193708 kb
Host smart-52e720b5-7c54-4812-8472-cd5dcc6cf7e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040879149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1040879149
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1809034872
Short name T628
Test name
Test status
Simulation time 54104318 ps
CPU time 0.59 seconds
Started Mar 31 12:27:14 PM PDT 24
Finished Mar 31 12:27:15 PM PDT 24
Peak memory 193728 kb
Host smart-38977cd0-dcca-474c-a14f-9b5c20a6cb54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809034872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1809034872
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.4240292279
Short name T672
Test name
Test status
Simulation time 25121826 ps
CPU time 0.55 seconds
Started Mar 31 12:26:52 PM PDT 24
Finished Mar 31 12:26:52 PM PDT 24
Peak memory 193740 kb
Host smart-e48465c8-6b5c-4ca6-8c92-07ce41166457
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240292279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.4240292279
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.1241354495
Short name T662
Test name
Test status
Simulation time 13974359 ps
CPU time 0.59 seconds
Started Mar 31 12:27:07 PM PDT 24
Finished Mar 31 12:27:08 PM PDT 24
Peak memory 193684 kb
Host smart-3eb57b32-1c59-4f3b-943c-176b461e85ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241354495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1241354495
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3284810636
Short name T612
Test name
Test status
Simulation time 39055443 ps
CPU time 0.58 seconds
Started Mar 31 12:27:10 PM PDT 24
Finished Mar 31 12:27:10 PM PDT 24
Peak memory 193800 kb
Host smart-c6cdfbc6-757d-430d-ab7a-a3928877bafe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284810636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3284810636
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2452281639
Short name T724
Test name
Test status
Simulation time 95603507 ps
CPU time 0.6 seconds
Started Mar 31 12:26:53 PM PDT 24
Finished Mar 31 12:26:54 PM PDT 24
Peak memory 193804 kb
Host smart-8c76e546-6891-4572-8ae4-3ea185409467
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452281639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2452281639
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.1844486606
Short name T658
Test name
Test status
Simulation time 12485955 ps
CPU time 0.53 seconds
Started Mar 31 12:26:57 PM PDT 24
Finished Mar 31 12:26:58 PM PDT 24
Peak memory 193744 kb
Host smart-53bf7190-51d3-482e-83c4-dee95b077d9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844486606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1844486606
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.3943306839
Short name T693
Test name
Test status
Simulation time 13719381 ps
CPU time 0.56 seconds
Started Mar 31 12:27:51 PM PDT 24
Finished Mar 31 12:27:53 PM PDT 24
Peak memory 193788 kb
Host smart-7c0cc730-eeb3-4f5d-90c8-9b8746f88eb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943306839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.3943306839
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.3877986
Short name T638
Test name
Test status
Simulation time 32128034 ps
CPU time 0.62 seconds
Started Mar 31 12:27:03 PM PDT 24
Finished Mar 31 12:27:05 PM PDT 24
Peak memory 194012 kb
Host smart-1a066423-d1e9-4ed9-af99-eb3d6ae3e027
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3877986
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.979845159
Short name T596
Test name
Test status
Simulation time 51636648 ps
CPU time 0.58 seconds
Started Mar 31 12:27:41 PM PDT 24
Finished Mar 31 12:27:42 PM PDT 24
Peak memory 193700 kb
Host smart-e053e9f9-0233-46d3-8747-fccb001b574a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979845159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.979845159
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2365298646
Short name T714
Test name
Test status
Simulation time 629327739 ps
CPU time 3.42 seconds
Started Mar 31 12:26:53 PM PDT 24
Finished Mar 31 12:26:57 PM PDT 24
Peak memory 197876 kb
Host smart-adf529ad-7bf3-426e-9b85-a2b8adf11fad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365298646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2365298646
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3788667285
Short name T671
Test name
Test status
Simulation time 1309334461 ps
CPU time 5.39 seconds
Started Mar 31 12:27:01 PM PDT 24
Finished Mar 31 12:27:06 PM PDT 24
Peak memory 197980 kb
Host smart-1992e2b6-744d-482c-a05b-1afa69e0df60
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788667285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3788667285
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3504303690
Short name T721
Test name
Test status
Simulation time 174363017 ps
CPU time 0.98 seconds
Started Mar 31 12:26:45 PM PDT 24
Finished Mar 31 12:26:46 PM PDT 24
Peak memory 198964 kb
Host smart-2ff2ddad-06c3-4625-95a7-0c3ae500b0bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504303690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3504303690
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3783187703
Short name T677
Test name
Test status
Simulation time 106766515 ps
CPU time 2.37 seconds
Started Mar 31 12:26:55 PM PDT 24
Finished Mar 31 12:26:57 PM PDT 24
Peak memory 199172 kb
Host smart-3e4b8d11-7759-4024-b866-941d9076e1b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783187703 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3783187703
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.823954856
Short name T69
Test name
Test status
Simulation time 51157197 ps
CPU time 0.67 seconds
Started Mar 31 12:26:55 PM PDT 24
Finished Mar 31 12:26:56 PM PDT 24
Peak memory 196608 kb
Host smart-8ae46264-088a-49a8-b54a-8445a2c095b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823954856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.823954856
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.1036263499
Short name T660
Test name
Test status
Simulation time 52680297 ps
CPU time 0.62 seconds
Started Mar 31 12:26:56 PM PDT 24
Finished Mar 31 12:26:57 PM PDT 24
Peak memory 193948 kb
Host smart-553cb29b-4ebb-4108-94e3-8b02f24d34ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036263499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1036263499
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3150664206
Short name T659
Test name
Test status
Simulation time 123641269 ps
CPU time 1.5 seconds
Started Mar 31 12:26:44 PM PDT 24
Finished Mar 31 12:26:46 PM PDT 24
Peak memory 198792 kb
Host smart-add0e25e-f56e-4ed3-94bf-4c853ad67023
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150664206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3150664206
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3334824160
Short name T690
Test name
Test status
Simulation time 153426496 ps
CPU time 2.02 seconds
Started Mar 31 12:26:54 PM PDT 24
Finished Mar 31 12:26:57 PM PDT 24
Peak memory 199144 kb
Host smart-2f8680bf-980d-4979-b050-eec04cda5901
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334824160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3334824160
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1467254920
Short name T720
Test name
Test status
Simulation time 307980330 ps
CPU time 2.7 seconds
Started Mar 31 12:26:53 PM PDT 24
Finished Mar 31 12:26:55 PM PDT 24
Peak memory 199088 kb
Host smart-e6932163-53ce-476e-b9ca-df65afe93213
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467254920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1467254920
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.86427697
Short name T669
Test name
Test status
Simulation time 54799706 ps
CPU time 0.56 seconds
Started Mar 31 12:27:32 PM PDT 24
Finished Mar 31 12:27:33 PM PDT 24
Peak memory 193732 kb
Host smart-b3b7cdb2-9a08-4eac-af1c-947fa904b3cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86427697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.86427697
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2974112494
Short name T649
Test name
Test status
Simulation time 14658783 ps
CPU time 0.56 seconds
Started Mar 31 12:26:53 PM PDT 24
Finished Mar 31 12:26:54 PM PDT 24
Peak memory 193704 kb
Host smart-97e5f276-b919-4954-9865-5c1e93058cf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974112494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2974112494
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.4030606332
Short name T645
Test name
Test status
Simulation time 37574094 ps
CPU time 0.54 seconds
Started Mar 31 12:27:01 PM PDT 24
Finished Mar 31 12:27:02 PM PDT 24
Peak memory 193720 kb
Host smart-20530d7a-b4e1-40bf-abce-3ccf30676530
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030606332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.4030606332
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2488729980
Short name T598
Test name
Test status
Simulation time 13622291 ps
CPU time 0.55 seconds
Started Mar 31 12:27:18 PM PDT 24
Finished Mar 31 12:27:19 PM PDT 24
Peak memory 194072 kb
Host smart-1d0c420f-b73c-4343-b3d7-fc42ab98e5eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488729980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2488729980
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.1292341642
Short name T707
Test name
Test status
Simulation time 17064136 ps
CPU time 0.6 seconds
Started Mar 31 12:27:05 PM PDT 24
Finished Mar 31 12:27:05 PM PDT 24
Peak memory 193816 kb
Host smart-c6d4f2d0-f436-4c8e-a435-f747ef341576
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292341642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.1292341642
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3187699283
Short name T667
Test name
Test status
Simulation time 14734584 ps
CPU time 0.59 seconds
Started Mar 31 12:27:33 PM PDT 24
Finished Mar 31 12:27:33 PM PDT 24
Peak memory 193776 kb
Host smart-f07923a1-06b8-4479-8069-0c52789512d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187699283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3187699283
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.776504252
Short name T639
Test name
Test status
Simulation time 30511963 ps
CPU time 0.58 seconds
Started Mar 31 12:27:00 PM PDT 24
Finished Mar 31 12:27:00 PM PDT 24
Peak memory 194000 kb
Host smart-281dbb5f-79f2-4917-a98b-3282ab683864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776504252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.776504252
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.2626517279
Short name T706
Test name
Test status
Simulation time 12384922 ps
CPU time 0.56 seconds
Started Mar 31 12:26:59 PM PDT 24
Finished Mar 31 12:27:00 PM PDT 24
Peak memory 194000 kb
Host smart-efccfce1-2ae1-4e20-8f28-5091094de1e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626517279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2626517279
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.431073223
Short name T650
Test name
Test status
Simulation time 23909527 ps
CPU time 0.55 seconds
Started Mar 31 12:27:13 PM PDT 24
Finished Mar 31 12:27:14 PM PDT 24
Peak memory 193728 kb
Host smart-60aa40a2-6cb5-4593-b05d-37e909923f5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431073223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.431073223
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.4262538436
Short name T640
Test name
Test status
Simulation time 25951627 ps
CPU time 0.56 seconds
Started Mar 31 12:27:05 PM PDT 24
Finished Mar 31 12:27:06 PM PDT 24
Peak memory 193972 kb
Host smart-981928fa-3210-4a1d-85e5-d7163da78821
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262538436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.4262538436
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.836108874
Short name T681
Test name
Test status
Simulation time 1116578189 ps
CPU time 2.31 seconds
Started Mar 31 12:26:55 PM PDT 24
Finished Mar 31 12:26:57 PM PDT 24
Peak memory 199212 kb
Host smart-51fe05b4-845e-4f08-b1ed-043c690e8f83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836108874 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.836108874
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1766595376
Short name T601
Test name
Test status
Simulation time 33177371 ps
CPU time 0.67 seconds
Started Mar 31 12:27:00 PM PDT 24
Finished Mar 31 12:27:06 PM PDT 24
Peak memory 196612 kb
Host smart-29b6ef02-27ff-418f-827d-51495f01f18e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766595376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1766595376
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.133768340
Short name T716
Test name
Test status
Simulation time 43519643 ps
CPU time 0.57 seconds
Started Mar 31 12:26:59 PM PDT 24
Finished Mar 31 12:27:00 PM PDT 24
Peak memory 193720 kb
Host smart-48a160b5-208c-485e-b0b3-005228d93929
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133768340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.133768340
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.4147816133
Short name T676
Test name
Test status
Simulation time 24689458 ps
CPU time 1.1 seconds
Started Mar 31 12:26:52 PM PDT 24
Finished Mar 31 12:26:53 PM PDT 24
Peak memory 199360 kb
Host smart-8c2894b2-34d3-4a5f-87b9-3ee5f5672427
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147816133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.4147816133
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2249839528
Short name T692
Test name
Test status
Simulation time 215032748 ps
CPU time 3.86 seconds
Started Mar 31 12:26:43 PM PDT 24
Finished Mar 31 12:26:47 PM PDT 24
Peak memory 199144 kb
Host smart-110bf09a-fa49-4be7-aadf-363f9a9f42ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249839528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.2249839528
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3097711115
Short name T100
Test name
Test status
Simulation time 447815802 ps
CPU time 4.31 seconds
Started Mar 31 12:27:01 PM PDT 24
Finished Mar 31 12:27:05 PM PDT 24
Peak memory 199116 kb
Host smart-398559b2-bbe4-4cea-acdd-c54023061ade
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097711115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3097711115
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2715833211
Short name T689
Test name
Test status
Simulation time 143980385 ps
CPU time 1.84 seconds
Started Mar 31 12:26:51 PM PDT 24
Finished Mar 31 12:26:53 PM PDT 24
Peak memory 199164 kb
Host smart-e930cf0f-3f47-437c-837d-435e1926e285
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715833211 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.2715833211
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.829081547
Short name T95
Test name
Test status
Simulation time 35316980 ps
CPU time 0.8 seconds
Started Mar 31 12:27:00 PM PDT 24
Finished Mar 31 12:27:01 PM PDT 24
Peak memory 198508 kb
Host smart-27bbdc2d-4cf6-4d68-9215-e5d1e94d43f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829081547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.829081547
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3088603948
Short name T686
Test name
Test status
Simulation time 14791489 ps
CPU time 0.57 seconds
Started Mar 31 12:26:59 PM PDT 24
Finished Mar 31 12:27:00 PM PDT 24
Peak memory 193820 kb
Host smart-b3afc671-4aa7-4889-9b69-2d301ef9aa54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088603948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3088603948
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.4206529691
Short name T710
Test name
Test status
Simulation time 410921271 ps
CPU time 1.91 seconds
Started Mar 31 12:26:45 PM PDT 24
Finished Mar 31 12:26:47 PM PDT 24
Peak memory 198792 kb
Host smart-ccb7c476-f4a9-4529-a816-1b6bb7999639
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206529691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.4206529691
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.218518275
Short name T709
Test name
Test status
Simulation time 206268050 ps
CPU time 3.5 seconds
Started Mar 31 12:26:47 PM PDT 24
Finished Mar 31 12:26:51 PM PDT 24
Peak memory 199140 kb
Host smart-07b2f2df-3f16-4373-84fb-90e727713122
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218518275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.218518275
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.511269299
Short name T719
Test name
Test status
Simulation time 1090205870 ps
CPU time 4.21 seconds
Started Mar 31 12:26:44 PM PDT 24
Finished Mar 31 12:26:48 PM PDT 24
Peak memory 199116 kb
Host smart-e8131b04-c0b1-43b2-9306-3ff398dc6f35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511269299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.511269299
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.590598236
Short name T647
Test name
Test status
Simulation time 155537183 ps
CPU time 1.9 seconds
Started Mar 31 12:26:51 PM PDT 24
Finished Mar 31 12:26:53 PM PDT 24
Peak memory 199140 kb
Host smart-0f6f6a1e-fbbb-4ca3-81c7-a04d358d01b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590598236 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.590598236
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3011678221
Short name T90
Test name
Test status
Simulation time 22267666 ps
CPU time 0.73 seconds
Started Mar 31 12:26:50 PM PDT 24
Finished Mar 31 12:26:51 PM PDT 24
Peak memory 196820 kb
Host smart-a1e36449-15e1-44b4-9f44-7459a91cf2d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011678221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3011678221
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.70123328
Short name T697
Test name
Test status
Simulation time 11203766 ps
CPU time 0.6 seconds
Started Mar 31 12:27:12 PM PDT 24
Finished Mar 31 12:27:13 PM PDT 24
Peak memory 193788 kb
Host smart-2fe3d93c-21e3-4af6-a35c-387b6c331d6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70123328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.70123328
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3587677664
Short name T615
Test name
Test status
Simulation time 35061486 ps
CPU time 1.59 seconds
Started Mar 31 12:26:58 PM PDT 24
Finished Mar 31 12:27:00 PM PDT 24
Peak memory 199088 kb
Host smart-d0bfcec7-49e4-43e3-8a5c-6113b8f59b2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587677664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3587677664
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.161945815
Short name T702
Test name
Test status
Simulation time 36180839 ps
CPU time 1.91 seconds
Started Mar 31 12:26:54 PM PDT 24
Finished Mar 31 12:26:56 PM PDT 24
Peak memory 199200 kb
Host smart-ef12b6a1-93f5-4247-bf05-b77a44347d3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161945815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.161945815
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1125276216
Short name T66
Test name
Test status
Simulation time 362419104 ps
CPU time 2.78 seconds
Started Mar 31 12:27:00 PM PDT 24
Finished Mar 31 12:27:03 PM PDT 24
Peak memory 199084 kb
Host smart-ced7e28f-c60c-4ae1-bcc0-f4f8303112ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125276216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1125276216
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.946030060
Short name T691
Test name
Test status
Simulation time 254522109 ps
CPU time 2.69 seconds
Started Mar 31 12:26:51 PM PDT 24
Finished Mar 31 12:26:54 PM PDT 24
Peak memory 199136 kb
Host smart-c4e4fb9b-45c3-415e-9310-483469bdc149
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946030060 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.946030060
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.473693048
Short name T729
Test name
Test status
Simulation time 143823482 ps
CPU time 0.93 seconds
Started Mar 31 12:26:53 PM PDT 24
Finished Mar 31 12:26:54 PM PDT 24
Peak memory 198540 kb
Host smart-fe76f6c5-8538-49ba-aed8-ae53c0b0494a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473693048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.473693048
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.321647346
Short name T695
Test name
Test status
Simulation time 17358211 ps
CPU time 0.63 seconds
Started Mar 31 12:26:55 PM PDT 24
Finished Mar 31 12:26:56 PM PDT 24
Peak memory 193752 kb
Host smart-34f53ecb-e79d-479f-9a5c-8cbdc246da05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321647346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.321647346
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.66668629
Short name T731
Test name
Test status
Simulation time 77736567 ps
CPU time 1.71 seconds
Started Mar 31 12:26:44 PM PDT 24
Finished Mar 31 12:26:51 PM PDT 24
Peak memory 199064 kb
Host smart-d313f1db-8257-4a16-a52d-ff122148b929
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66668629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_o
utstanding.66668629
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.201603931
Short name T685
Test name
Test status
Simulation time 133584791 ps
CPU time 2.6 seconds
Started Mar 31 12:27:01 PM PDT 24
Finished Mar 31 12:27:03 PM PDT 24
Peak memory 199140 kb
Host smart-05a7ce21-9234-4d42-8940-74fdedff2832
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201603931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.201603931
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2139072068
Short name T65
Test name
Test status
Simulation time 69914156 ps
CPU time 1.66 seconds
Started Mar 31 12:26:57 PM PDT 24
Finished Mar 31 12:26:59 PM PDT 24
Peak memory 199084 kb
Host smart-7d31e083-080a-4f73-bd2f-fcfb335f3269
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139072068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.2139072068
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1032371617
Short name T656
Test name
Test status
Simulation time 240626423004 ps
CPU time 658.39 seconds
Started Mar 31 12:26:48 PM PDT 24
Finished Mar 31 12:37:46 PM PDT 24
Peak memory 223828 kb
Host smart-48697ae9-5909-4dee-b876-0653c978f5a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032371617 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1032371617
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1165281622
Short name T626
Test name
Test status
Simulation time 19020425 ps
CPU time 0.77 seconds
Started Mar 31 12:26:58 PM PDT 24
Finished Mar 31 12:26:59 PM PDT 24
Peak memory 198020 kb
Host smart-634b1e06-db19-48d0-ba80-9026ebbf2873
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165281622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1165281622
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2528552846
Short name T657
Test name
Test status
Simulation time 21170484 ps
CPU time 0.58 seconds
Started Mar 31 12:26:54 PM PDT 24
Finished Mar 31 12:26:55 PM PDT 24
Peak memory 193996 kb
Host smart-91effc91-2492-4283-b57f-adcd2d495a73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528552846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2528552846
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3295424093
Short name T67
Test name
Test status
Simulation time 154847826 ps
CPU time 1.22 seconds
Started Mar 31 12:27:25 PM PDT 24
Finished Mar 31 12:27:26 PM PDT 24
Peak memory 197448 kb
Host smart-849c45a2-4ef5-482b-b699-e46a10619212
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295424093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.3295424093
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3893716402
Short name T683
Test name
Test status
Simulation time 211804286 ps
CPU time 1.73 seconds
Started Mar 31 12:26:50 PM PDT 24
Finished Mar 31 12:26:52 PM PDT 24
Peak memory 199148 kb
Host smart-5466f375-70d4-4559-8dd2-497b718fda8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893716402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.3893716402
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2670063560
Short name T107
Test name
Test status
Simulation time 406992470 ps
CPU time 1.85 seconds
Started Mar 31 12:26:52 PM PDT 24
Finished Mar 31 12:26:54 PM PDT 24
Peak memory 199156 kb
Host smart-bfeba837-512a-4e45-8ac5-714173582f5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670063560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2670063560
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1207573404
Short name T401
Test name
Test status
Simulation time 53859492 ps
CPU time 0.63 seconds
Started Mar 31 01:00:29 PM PDT 24
Finished Mar 31 01:00:30 PM PDT 24
Peak memory 195224 kb
Host smart-fd525d90-2c88-48b2-a237-11cd9d2eb1e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207573404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1207573404
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.149034102
Short name T194
Test name
Test status
Simulation time 19047602353 ps
CPU time 45.26 seconds
Started Mar 31 01:00:28 PM PDT 24
Finished Mar 31 01:01:14 PM PDT 24
Peak memory 232052 kb
Host smart-d2a3dfe5-c21a-4c75-8520-8bd3a9b794ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=149034102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.149034102
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.891917155
Short name T162
Test name
Test status
Simulation time 1080862110 ps
CPU time 19.15 seconds
Started Mar 31 01:00:28 PM PDT 24
Finished Mar 31 01:00:47 PM PDT 24
Peak memory 199664 kb
Host smart-13ceb817-3ca2-443c-8919-6614f35c0be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891917155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.891917155
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.3967947618
Short name T322
Test name
Test status
Simulation time 60349255405 ps
CPU time 193.91 seconds
Started Mar 31 01:00:28 PM PDT 24
Finished Mar 31 01:03:42 PM PDT 24
Peak memory 199708 kb
Host smart-9bba2aee-87e5-46d8-8c1e-4d020ba4be5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3967947618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3967947618
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.169362640
Short name T591
Test name
Test status
Simulation time 13210097598 ps
CPU time 184.98 seconds
Started Mar 31 01:00:28 PM PDT 24
Finished Mar 31 01:03:33 PM PDT 24
Peak memory 199744 kb
Host smart-b8a4e29a-13a6-4277-a8c9-f432056bd01e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169362640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.169362640
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3492406896
Short name T445
Test name
Test status
Simulation time 13903754681 ps
CPU time 108.35 seconds
Started Mar 31 01:00:28 PM PDT 24
Finished Mar 31 01:02:16 PM PDT 24
Peak memory 199572 kb
Host smart-9a0223d7-efd2-4059-9a4c-ca425789c3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492406896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3492406896
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.425373714
Short name T37
Test name
Test status
Simulation time 192181586 ps
CPU time 0.94 seconds
Started Mar 31 01:00:27 PM PDT 24
Finished Mar 31 01:00:28 PM PDT 24
Peak memory 218008 kb
Host smart-029b81cf-fd8a-4b90-9ca4-978a8a3a59c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425373714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.425373714
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.3985523241
Short name T483
Test name
Test status
Simulation time 384334645 ps
CPU time 5.11 seconds
Started Mar 31 01:00:30 PM PDT 24
Finished Mar 31 01:00:36 PM PDT 24
Peak memory 199560 kb
Host smart-37fdfe31-f30b-45d8-a8d3-78d47638ccb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985523241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3985523241
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.1636358740
Short name T236
Test name
Test status
Simulation time 186729947867 ps
CPU time 588.01 seconds
Started Mar 31 01:00:29 PM PDT 24
Finished Mar 31 01:10:18 PM PDT 24
Peak memory 212840 kb
Host smart-fb474bcf-6a73-4fb8-a237-204811265da7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636358740 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.1636358740
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.139551230
Short name T210
Test name
Test status
Simulation time 208160451 ps
CPU time 1.05 seconds
Started Mar 31 01:00:30 PM PDT 24
Finished Mar 31 01:00:32 PM PDT 24
Peak memory 199208 kb
Host smart-4fe75e97-fc95-4307-9ec9-4633cfca40d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139551230 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_hmac_vectors.139551230
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.3389044077
Short name T398
Test name
Test status
Simulation time 37432382354 ps
CPU time 464.18 seconds
Started Mar 31 01:00:28 PM PDT 24
Finished Mar 31 01:08:12 PM PDT 24
Peak memory 199644 kb
Host smart-00238ee3-160d-4c43-8875-53c711c9b1b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389044077 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.3389044077
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1610099410
Short name T262
Test name
Test status
Simulation time 787671941 ps
CPU time 19.98 seconds
Started Mar 31 01:00:27 PM PDT 24
Finished Mar 31 01:00:47 PM PDT 24
Peak memory 199532 kb
Host smart-31add83c-a485-49ad-b7c7-0e9b0bf5b2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610099410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1610099410
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.1793886263
Short name T430
Test name
Test status
Simulation time 14020842 ps
CPU time 0.55 seconds
Started Mar 31 01:00:34 PM PDT 24
Finished Mar 31 01:00:35 PM PDT 24
Peak memory 194276 kb
Host smart-4ca07e3d-c90a-4b31-a204-4877aee30b8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793886263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1793886263
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.2299587277
Short name T274
Test name
Test status
Simulation time 821770080 ps
CPU time 19.05 seconds
Started Mar 31 01:00:27 PM PDT 24
Finished Mar 31 01:00:47 PM PDT 24
Peak memory 228900 kb
Host smart-3a7f8a36-5766-48f4-b795-62ea6d0965b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2299587277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.2299587277
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3442333815
Short name T292
Test name
Test status
Simulation time 468992853 ps
CPU time 4.62 seconds
Started Mar 31 01:00:33 PM PDT 24
Finished Mar 31 01:00:38 PM PDT 24
Peak memory 199576 kb
Host smart-88938d75-2ca0-4c6e-b7b1-2eedd5b01da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442333815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3442333815
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1446189107
Short name T378
Test name
Test status
Simulation time 3780713722 ps
CPU time 55.68 seconds
Started Mar 31 01:00:33 PM PDT 24
Finished Mar 31 01:01:29 PM PDT 24
Peak memory 199644 kb
Host smart-c39d3cb9-67dd-48c4-b328-b4379fbd4d76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1446189107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1446189107
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.2493327570
Short name T459
Test name
Test status
Simulation time 1519275781 ps
CPU time 90.96 seconds
Started Mar 31 01:00:34 PM PDT 24
Finished Mar 31 01:02:05 PM PDT 24
Peak memory 199676 kb
Host smart-9b9ec8fb-23b8-4504-b366-454ef632676f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493327570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2493327570
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.4128336226
Short name T579
Test name
Test status
Simulation time 11459009025 ps
CPU time 80.53 seconds
Started Mar 31 01:00:27 PM PDT 24
Finished Mar 31 01:01:48 PM PDT 24
Peak memory 199744 kb
Host smart-d7dc90dd-50fe-4ea9-983e-4f7de2fca6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128336226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.4128336226
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_smoke.2272748576
Short name T120
Test name
Test status
Simulation time 86676030 ps
CPU time 2.97 seconds
Started Mar 31 01:00:30 PM PDT 24
Finished Mar 31 01:00:33 PM PDT 24
Peak memory 199580 kb
Host smart-d9a13739-4975-466e-83c2-f9dca1ad8868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272748576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2272748576
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3315079795
Short name T583
Test name
Test status
Simulation time 18514256149 ps
CPU time 238.24 seconds
Started Mar 31 01:00:33 PM PDT 24
Finished Mar 31 01:04:32 PM PDT 24
Peak memory 226892 kb
Host smart-52a2058a-9ace-432e-8b4c-59f2027cb12a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315079795 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3315079795
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.1860550668
Short name T460
Test name
Test status
Simulation time 292217383 ps
CPU time 1.36 seconds
Started Mar 31 01:00:33 PM PDT 24
Finished Mar 31 01:00:35 PM PDT 24
Peak memory 199620 kb
Host smart-2b532e73-384f-4778-a161-d5b6f509b820
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860550668 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.1860550668
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.2046365423
Short name T512
Test name
Test status
Simulation time 49982522356 ps
CPU time 454.1 seconds
Started Mar 31 01:00:32 PM PDT 24
Finished Mar 31 01:08:06 PM PDT 24
Peak memory 199644 kb
Host smart-8fa6bf53-a5c5-4b7c-bad5-3be13ed152e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046365423 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.2046365423
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.2519808577
Short name T155
Test name
Test status
Simulation time 11044068559 ps
CPU time 47.76 seconds
Started Mar 31 01:00:35 PM PDT 24
Finished Mar 31 01:01:23 PM PDT 24
Peak memory 199876 kb
Host smart-aa8bee48-1ce5-4ece-9ad2-dc5dbe567ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519808577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2519808577
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1820731095
Short name T318
Test name
Test status
Simulation time 492646537 ps
CPU time 18.82 seconds
Started Mar 31 01:00:57 PM PDT 24
Finished Mar 31 01:01:16 PM PDT 24
Peak memory 207864 kb
Host smart-3bc455fc-62e7-4cfd-9923-df2ef7d8dc38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1820731095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1820731095
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.4159759012
Short name T564
Test name
Test status
Simulation time 1607589315 ps
CPU time 33.63 seconds
Started Mar 31 01:00:56 PM PDT 24
Finished Mar 31 01:01:30 PM PDT 24
Peak memory 199660 kb
Host smart-43787e4e-95dd-48a0-ae42-d26709d7b665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159759012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.4159759012
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.512336170
Short name T186
Test name
Test status
Simulation time 1160944130 ps
CPU time 72.42 seconds
Started Mar 31 01:00:57 PM PDT 24
Finished Mar 31 01:02:09 PM PDT 24
Peak memory 199592 kb
Host smart-e85522d3-a709-498e-9b2d-456e87fc24f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=512336170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.512336170
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3911984066
Short name T365
Test name
Test status
Simulation time 2533289179 ps
CPU time 149.77 seconds
Started Mar 31 01:01:00 PM PDT 24
Finished Mar 31 01:03:30 PM PDT 24
Peak memory 199732 kb
Host smart-fec61a69-90bf-4212-914e-ad405c57a18c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911984066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3911984066
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.2541064943
Short name T226
Test name
Test status
Simulation time 18969683193 ps
CPU time 95.81 seconds
Started Mar 31 01:00:54 PM PDT 24
Finished Mar 31 01:02:30 PM PDT 24
Peak memory 199740 kb
Host smart-4471b705-8e84-4820-8586-b62310caac4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541064943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2541064943
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.4068133701
Short name T300
Test name
Test status
Simulation time 426960099 ps
CPU time 6.4 seconds
Started Mar 31 01:00:55 PM PDT 24
Finished Mar 31 01:01:01 PM PDT 24
Peak memory 199664 kb
Host smart-f79115a2-3550-4b2f-806b-9303d3f3963d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068133701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.4068133701
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3177760659
Short name T256
Test name
Test status
Simulation time 17997440685 ps
CPU time 974.61 seconds
Started Mar 31 01:00:55 PM PDT 24
Finished Mar 31 01:17:10 PM PDT 24
Peak memory 199768 kb
Host smart-b35a11c6-8ab0-4aaa-98ac-f80cb639f219
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177760659 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3177760659
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.2063191445
Short name T454
Test name
Test status
Simulation time 85615966 ps
CPU time 1.08 seconds
Started Mar 31 01:00:56 PM PDT 24
Finished Mar 31 01:00:57 PM PDT 24
Peak memory 199036 kb
Host smart-68cc3ffe-6792-43e2-9058-fa81d2af3489
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063191445 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.2063191445
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.1071353481
Short name T311
Test name
Test status
Simulation time 494045553688 ps
CPU time 453.91 seconds
Started Mar 31 01:00:55 PM PDT 24
Finished Mar 31 01:08:29 PM PDT 24
Peak memory 199700 kb
Host smart-6eb676c3-0558-4279-b1d0-486d6bfd4892
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071353481 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.1071353481
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.3866481658
Short name T271
Test name
Test status
Simulation time 687596074 ps
CPU time 22.84 seconds
Started Mar 31 01:00:55 PM PDT 24
Finished Mar 31 01:01:18 PM PDT 24
Peak memory 199660 kb
Host smart-da8cd995-5810-4a64-8bb8-f0d9afd392d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866481658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.3866481658
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3484289436
Short name T199
Test name
Test status
Simulation time 14166427 ps
CPU time 0.57 seconds
Started Mar 31 01:00:57 PM PDT 24
Finished Mar 31 01:00:57 PM PDT 24
Peak memory 195232 kb
Host smart-383a4103-93e3-4377-a999-3f3542eed510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484289436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3484289436
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.4174516418
Short name T223
Test name
Test status
Simulation time 3260280632 ps
CPU time 31.8 seconds
Started Mar 31 01:00:56 PM PDT 24
Finished Mar 31 01:01:29 PM PDT 24
Peak memory 232248 kb
Host smart-40adbf62-2440-4869-8f37-95cc288ad0e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4174516418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.4174516418
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.2510756521
Short name T302
Test name
Test status
Simulation time 1498417363 ps
CPU time 31.87 seconds
Started Mar 31 01:00:57 PM PDT 24
Finished Mar 31 01:01:29 PM PDT 24
Peak memory 199652 kb
Host smart-fa6d1fca-1cab-422d-8906-f2fa67766399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510756521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.2510756521
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.4250134486
Short name T177
Test name
Test status
Simulation time 11382889634 ps
CPU time 140.64 seconds
Started Mar 31 01:00:55 PM PDT 24
Finished Mar 31 01:03:16 PM PDT 24
Peak memory 199700 kb
Host smart-073b1d67-3f2a-4986-8ddd-59e1375ad27f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4250134486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.4250134486
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2943765294
Short name T203
Test name
Test status
Simulation time 17012973117 ps
CPU time 119.37 seconds
Started Mar 31 01:00:56 PM PDT 24
Finished Mar 31 01:02:56 PM PDT 24
Peak memory 199748 kb
Host smart-34407156-cae5-4f06-a9ce-54cc2f476c53
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943765294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2943765294
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1319512392
Short name T315
Test name
Test status
Simulation time 1326558411 ps
CPU time 79.42 seconds
Started Mar 31 01:00:57 PM PDT 24
Finished Mar 31 01:02:17 PM PDT 24
Peak memory 199644 kb
Host smart-bc8a5f24-7807-408b-8112-e55eca548fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319512392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1319512392
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2978433822
Short name T142
Test name
Test status
Simulation time 232143372 ps
CPU time 1.85 seconds
Started Mar 31 01:00:55 PM PDT 24
Finished Mar 31 01:00:57 PM PDT 24
Peak memory 199636 kb
Host smart-5b2636b7-8492-4419-820e-7e6247a99921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978433822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2978433822
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3363841593
Short name T78
Test name
Test status
Simulation time 48273949560 ps
CPU time 155.85 seconds
Started Mar 31 01:00:57 PM PDT 24
Finished Mar 31 01:03:33 PM PDT 24
Peak memory 224304 kb
Host smart-40222f8e-5234-4c5a-b675-7f043971361b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363841593 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3363841593
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.3312872669
Short name T503
Test name
Test status
Simulation time 50900845 ps
CPU time 1.09 seconds
Started Mar 31 01:00:58 PM PDT 24
Finished Mar 31 01:00:59 PM PDT 24
Peak memory 199052 kb
Host smart-00679c6f-186f-45cf-8208-2297bc088492
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312872669 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.3312872669
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.2879538113
Short name T140
Test name
Test status
Simulation time 18362926838 ps
CPU time 510.26 seconds
Started Mar 31 01:00:57 PM PDT 24
Finished Mar 31 01:09:27 PM PDT 24
Peak memory 199640 kb
Host smart-8199a734-7e84-468c-aaf5-c30ce226ccaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879538113 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.2879538113
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.4006170959
Short name T410
Test name
Test status
Simulation time 5757760705 ps
CPU time 86.66 seconds
Started Mar 31 01:00:55 PM PDT 24
Finished Mar 31 01:02:22 PM PDT 24
Peak memory 199688 kb
Host smart-c9c62cb6-c96b-4a91-a141-1cf85e68d531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006170959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.4006170959
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1996370093
Short name T555
Test name
Test status
Simulation time 52899538 ps
CPU time 0.58 seconds
Started Mar 31 01:00:55 PM PDT 24
Finished Mar 31 01:00:56 PM PDT 24
Peak memory 194076 kb
Host smart-000f0e7e-474e-45c0-b6b2-4baf7dc4135e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996370093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1996370093
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.548704865
Short name T588
Test name
Test status
Simulation time 11366071642 ps
CPU time 40.87 seconds
Started Mar 31 01:00:55 PM PDT 24
Finished Mar 31 01:01:36 PM PDT 24
Peak memory 221256 kb
Host smart-4daa5219-15f7-48d2-bd67-d382d336e0b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=548704865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.548704865
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.3137571559
Short name T167
Test name
Test status
Simulation time 9231853413 ps
CPU time 35.93 seconds
Started Mar 31 01:00:56 PM PDT 24
Finished Mar 31 01:01:32 PM PDT 24
Peak memory 199696 kb
Host smart-30acb9ca-fb1a-42ca-ac64-40bb8841a149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137571559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.3137571559
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.4228994578
Short name T428
Test name
Test status
Simulation time 47375780 ps
CPU time 0.66 seconds
Started Mar 31 01:00:57 PM PDT 24
Finished Mar 31 01:00:58 PM PDT 24
Peak memory 196940 kb
Host smart-8d3ac186-7e8c-4c32-9add-c2f310933be9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4228994578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.4228994578
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1732432870
Short name T411
Test name
Test status
Simulation time 305228966 ps
CPU time 4.92 seconds
Started Mar 31 01:00:54 PM PDT 24
Finished Mar 31 01:01:00 PM PDT 24
Peak memory 199488 kb
Host smart-a5fc2972-4b35-4452-8822-992667ea274a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732432870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1732432870
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1185653412
Short name T412
Test name
Test status
Simulation time 3521129257 ps
CPU time 49.76 seconds
Started Mar 31 01:00:58 PM PDT 24
Finished Mar 31 01:01:48 PM PDT 24
Peak memory 199680 kb
Host smart-0b802d29-7ee3-4dd1-a327-104af4e494ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185653412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1185653412
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.942733965
Short name T213
Test name
Test status
Simulation time 76134263 ps
CPU time 1.48 seconds
Started Mar 31 01:00:54 PM PDT 24
Finished Mar 31 01:00:55 PM PDT 24
Peak memory 199656 kb
Host smart-43599231-346b-43e2-b0a4-f1f1cccd5a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942733965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.942733965
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1922842191
Short name T83
Test name
Test status
Simulation time 36856193232 ps
CPU time 513.07 seconds
Started Mar 31 01:00:57 PM PDT 24
Finished Mar 31 01:09:30 PM PDT 24
Peak memory 238116 kb
Host smart-621c06ab-aa91-45be-9983-0b43f761dd4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922842191 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1922842191
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.577986676
Short name T584
Test name
Test status
Simulation time 45564054 ps
CPU time 1.05 seconds
Started Mar 31 01:00:58 PM PDT 24
Finished Mar 31 01:00:59 PM PDT 24
Peak memory 198188 kb
Host smart-53425d86-9487-4264-bb6d-b6f3729b9844
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577986676 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_hmac_vectors.577986676
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.3793964887
Short name T325
Test name
Test status
Simulation time 85332248397 ps
CPU time 507.45 seconds
Started Mar 31 01:00:58 PM PDT 24
Finished Mar 31 01:09:26 PM PDT 24
Peak memory 199624 kb
Host smart-40743eda-62d6-4ef5-9dc6-2880c32e945f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793964887 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.3793964887
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.641238216
Short name T395
Test name
Test status
Simulation time 6256071541 ps
CPU time 17.69 seconds
Started Mar 31 01:00:59 PM PDT 24
Finished Mar 31 01:01:17 PM PDT 24
Peak memory 199684 kb
Host smart-bd69ede5-a37d-4cd9-987d-51dd0ca376fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641238216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.641238216
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.493933713
Short name T362
Test name
Test status
Simulation time 39491805 ps
CPU time 0.58 seconds
Started Mar 31 01:01:08 PM PDT 24
Finished Mar 31 01:01:08 PM PDT 24
Peak memory 194384 kb
Host smart-af8fe5d3-2c9d-4fbc-a27d-025a147e8158
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493933713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.493933713
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1780240036
Short name T55
Test name
Test status
Simulation time 1616233747 ps
CPU time 38.54 seconds
Started Mar 31 01:00:54 PM PDT 24
Finished Mar 31 01:01:33 PM PDT 24
Peak memory 224636 kb
Host smart-94a5315d-abd8-43a8-a149-95994b26cc62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1780240036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1780240036
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.3281931428
Short name T183
Test name
Test status
Simulation time 679308641 ps
CPU time 3.41 seconds
Started Mar 31 01:01:02 PM PDT 24
Finished Mar 31 01:01:06 PM PDT 24
Peak memory 199524 kb
Host smart-f0492c6d-ca55-4c6c-8115-a1f614a41b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281931428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3281931428
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.3397448851
Short name T500
Test name
Test status
Simulation time 913142010 ps
CPU time 49.66 seconds
Started Mar 31 01:01:01 PM PDT 24
Finished Mar 31 01:01:50 PM PDT 24
Peak memory 199644 kb
Host smart-387b9097-7776-4a44-b40a-bb86cf8224ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3397448851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.3397448851
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.3778508965
Short name T441
Test name
Test status
Simulation time 3251081642 ps
CPU time 189 seconds
Started Mar 31 01:01:02 PM PDT 24
Finished Mar 31 01:04:12 PM PDT 24
Peak memory 199736 kb
Host smart-a07ebbc9-0c1c-42fc-8d36-b4065247a654
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778508965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3778508965
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_smoke.901121474
Short name T139
Test name
Test status
Simulation time 503435239 ps
CPU time 6.02 seconds
Started Mar 31 01:01:00 PM PDT 24
Finished Mar 31 01:01:07 PM PDT 24
Peak memory 199616 kb
Host smart-5dc5a5d4-1143-42b2-b0d6-a81fbbc405ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901121474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.901121474
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.1978844260
Short name T63
Test name
Test status
Simulation time 153026290182 ps
CPU time 1021.63 seconds
Started Mar 31 01:01:02 PM PDT 24
Finished Mar 31 01:18:04 PM PDT 24
Peak memory 240320 kb
Host smart-25187c15-bcef-4567-8724-1a051e468c57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978844260 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1978844260
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.12946526
Short name T573
Test name
Test status
Simulation time 259321558 ps
CPU time 1.39 seconds
Started Mar 31 01:01:03 PM PDT 24
Finished Mar 31 01:01:05 PM PDT 24
Peak memory 199616 kb
Host smart-eb61519d-a7df-4d40-8e2d-0a7445eda3b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12946526 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.hmac_test_hmac_vectors.12946526
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.358708845
Short name T306
Test name
Test status
Simulation time 34305291264 ps
CPU time 450.09 seconds
Started Mar 31 01:01:03 PM PDT 24
Finished Mar 31 01:08:34 PM PDT 24
Peak memory 199692 kb
Host smart-bae2db4d-3cf9-46d2-bda8-608a6f8b8e6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358708845 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.358708845
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2843973921
Short name T305
Test name
Test status
Simulation time 918447452 ps
CPU time 40.7 seconds
Started Mar 31 01:01:03 PM PDT 24
Finished Mar 31 01:01:43 PM PDT 24
Peak memory 199648 kb
Host smart-46faa8a9-ea90-4131-9428-34c81ac845a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843973921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2843973921
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/134.hmac_stress_all_with_rand_reset.2282758886
Short name T70
Test name
Test status
Simulation time 47002537174 ps
CPU time 1648.78 seconds
Started Mar 31 01:04:15 PM PDT 24
Finished Mar 31 01:31:45 PM PDT 24
Peak memory 216132 kb
Host smart-d2784272-4144-4830-97c1-012e5f93878b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2282758886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.hmac_stress_all_with_rand_reset.2282758886
Directory /workspace/134.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2808484982
Short name T249
Test name
Test status
Simulation time 34469320 ps
CPU time 0.6 seconds
Started Mar 31 01:01:04 PM PDT 24
Finished Mar 31 01:01:05 PM PDT 24
Peak memory 195108 kb
Host smart-be7d84d1-8aec-4250-94c0-2b05aad3da21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808484982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2808484982
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2877370167
Short name T20
Test name
Test status
Simulation time 2814543464 ps
CPU time 55.01 seconds
Started Mar 31 01:01:04 PM PDT 24
Finished Mar 31 01:01:59 PM PDT 24
Peak memory 224272 kb
Host smart-83c65f99-bc4e-465b-a02a-ffe91805971f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2877370167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2877370167
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2633752190
Short name T521
Test name
Test status
Simulation time 578394898 ps
CPU time 19.85 seconds
Started Mar 31 01:01:05 PM PDT 24
Finished Mar 31 01:01:26 PM PDT 24
Peak memory 199596 kb
Host smart-d876e143-cbea-45ba-bf71-d40822370a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633752190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2633752190
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.4160058548
Short name T124
Test name
Test status
Simulation time 1568536013 ps
CPU time 62.48 seconds
Started Mar 31 01:01:02 PM PDT 24
Finished Mar 31 01:02:04 PM PDT 24
Peak memory 199708 kb
Host smart-e33ee52b-b62b-4102-9362-55293e5c9e5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4160058548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.4160058548
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.1392994692
Short name T321
Test name
Test status
Simulation time 2072898234 ps
CPU time 115.47 seconds
Started Mar 31 01:01:02 PM PDT 24
Finished Mar 31 01:02:58 PM PDT 24
Peak memory 199648 kb
Host smart-22b8a70f-4b68-4866-858b-cba00a7e1d3d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392994692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1392994692
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.3084255712
Short name T457
Test name
Test status
Simulation time 1312541468 ps
CPU time 20.38 seconds
Started Mar 31 01:01:05 PM PDT 24
Finished Mar 31 01:01:25 PM PDT 24
Peak memory 199628 kb
Host smart-f357ebde-7248-48f4-a8a8-b04f6b5a01ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084255712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3084255712
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3775677772
Short name T585
Test name
Test status
Simulation time 294472618 ps
CPU time 5.16 seconds
Started Mar 31 01:01:03 PM PDT 24
Finished Mar 31 01:01:09 PM PDT 24
Peak memory 199616 kb
Host smart-68e74d95-afe8-48b4-bdcc-8ac194e9aba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775677772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3775677772
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.667264707
Short name T349
Test name
Test status
Simulation time 10381667352 ps
CPU time 588.29 seconds
Started Mar 31 01:01:11 PM PDT 24
Finished Mar 31 01:10:59 PM PDT 24
Peak memory 224344 kb
Host smart-3f3491cc-4912-4510-a9ea-ed5dbbca428c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667264707 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.667264707
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.2876020896
Short name T159
Test name
Test status
Simulation time 83536261 ps
CPU time 1.18 seconds
Started Mar 31 01:01:03 PM PDT 24
Finished Mar 31 01:01:04 PM PDT 24
Peak memory 199076 kb
Host smart-20eecb5a-41a0-4117-92a6-0da925fb6aac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876020896 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.2876020896
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.3006538420
Short name T308
Test name
Test status
Simulation time 31057852325 ps
CPU time 428.39 seconds
Started Mar 31 01:01:06 PM PDT 24
Finished Mar 31 01:08:15 PM PDT 24
Peak memory 199568 kb
Host smart-10720c84-0fc4-4cac-87d3-fa6996f79bef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006538420 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.3006538420
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2128823081
Short name T193
Test name
Test status
Simulation time 3374445342 ps
CPU time 64.29 seconds
Started Mar 31 01:01:11 PM PDT 24
Finished Mar 31 01:02:15 PM PDT 24
Peak memory 199736 kb
Host smart-60b73bb4-e0eb-4966-808d-8d05c22acb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128823081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2128823081
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.4247557963
Short name T116
Test name
Test status
Simulation time 166270158 ps
CPU time 0.57 seconds
Started Mar 31 01:01:03 PM PDT 24
Finished Mar 31 01:01:04 PM PDT 24
Peak memory 194124 kb
Host smart-143220da-1a8d-490e-93d6-561f81938688
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247557963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.4247557963
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3886901024
Short name T261
Test name
Test status
Simulation time 1525491300 ps
CPU time 56.47 seconds
Started Mar 31 01:01:02 PM PDT 24
Finished Mar 31 01:01:59 PM PDT 24
Peak memory 231604 kb
Host smart-c665ab7d-5fbd-4dfd-9166-4a45cd3a8c06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3886901024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3886901024
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.550804441
Short name T462
Test name
Test status
Simulation time 2778145234 ps
CPU time 35.33 seconds
Started Mar 31 01:01:06 PM PDT 24
Finished Mar 31 01:01:42 PM PDT 24
Peak memory 199712 kb
Host smart-2c08e208-45be-4bfe-a3ae-cf1eb56ba86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550804441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.550804441
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1305237066
Short name T386
Test name
Test status
Simulation time 3906707434 ps
CPU time 50.05 seconds
Started Mar 31 01:01:03 PM PDT 24
Finished Mar 31 01:01:53 PM PDT 24
Peak memory 199680 kb
Host smart-8ce2ce5d-35d9-4a16-874f-486b3d4c1be2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1305237066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1305237066
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.3048765739
Short name T314
Test name
Test status
Simulation time 970302684 ps
CPU time 54.82 seconds
Started Mar 31 01:01:08 PM PDT 24
Finished Mar 31 01:02:03 PM PDT 24
Peak memory 199052 kb
Host smart-e7873488-5457-400e-bfaa-5a54a27e0735
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048765739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3048765739
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1531874891
Short name T491
Test name
Test status
Simulation time 205566159 ps
CPU time 3.95 seconds
Started Mar 31 01:01:04 PM PDT 24
Finished Mar 31 01:01:08 PM PDT 24
Peak memory 199604 kb
Host smart-82d4ba45-9e54-4fbd-8e73-0d500a318ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531874891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1531874891
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2673711706
Short name T133
Test name
Test status
Simulation time 54056706 ps
CPU time 1.19 seconds
Started Mar 31 01:01:05 PM PDT 24
Finished Mar 31 01:01:07 PM PDT 24
Peak memory 199540 kb
Host smart-0453e250-f39e-47fe-a7a8-9daf006396fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673711706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2673711706
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.896881775
Short name T528
Test name
Test status
Simulation time 495565447449 ps
CPU time 1468.45 seconds
Started Mar 31 01:01:11 PM PDT 24
Finished Mar 31 01:25:40 PM PDT 24
Peak memory 199756 kb
Host smart-ef64284a-cd37-4336-b1fb-23367a523375
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896881775 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.896881775
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.1780395001
Short name T347
Test name
Test status
Simulation time 108803264 ps
CPU time 1.15 seconds
Started Mar 31 01:01:06 PM PDT 24
Finished Mar 31 01:01:08 PM PDT 24
Peak memory 199280 kb
Host smart-7e7bc945-d65e-4837-a89b-780c51d00b43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780395001 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.1780395001
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.581222586
Short name T245
Test name
Test status
Simulation time 174389533248 ps
CPU time 570.31 seconds
Started Mar 31 01:01:04 PM PDT 24
Finished Mar 31 01:10:35 PM PDT 24
Peak memory 199700 kb
Host smart-29ceee6e-a5a0-4c82-bc2e-99e051cbda26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581222586 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.581222586
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1840901706
Short name T41
Test name
Test status
Simulation time 4291043340 ps
CPU time 34.72 seconds
Started Mar 31 01:01:05 PM PDT 24
Finished Mar 31 01:01:40 PM PDT 24
Peak memory 199636 kb
Host smart-9c44c3d8-0487-46cf-8574-8bd292eb2bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840901706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1840901706
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.4049902129
Short name T246
Test name
Test status
Simulation time 16826322 ps
CPU time 0.61 seconds
Started Mar 31 01:01:10 PM PDT 24
Finished Mar 31 01:01:11 PM PDT 24
Peak memory 195316 kb
Host smart-8e152d7f-11a9-426e-ba9f-ba2bd23de92c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049902129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.4049902129
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1596629447
Short name T493
Test name
Test status
Simulation time 18721335739 ps
CPU time 41.75 seconds
Started Mar 31 01:01:04 PM PDT 24
Finished Mar 31 01:01:46 PM PDT 24
Peak memory 207916 kb
Host smart-4f984d5f-93ed-4ffb-8f49-e693d20fc8f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1596629447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1596629447
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.3148655730
Short name T335
Test name
Test status
Simulation time 998015483 ps
CPU time 5.58 seconds
Started Mar 31 01:01:03 PM PDT 24
Finished Mar 31 01:01:09 PM PDT 24
Peak memory 199532 kb
Host smart-67490d12-8108-42bf-acaf-2629b12f64ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148655730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.3148655730
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.688618887
Short name T251
Test name
Test status
Simulation time 3612198544 ps
CPU time 108.13 seconds
Started Mar 31 01:01:05 PM PDT 24
Finished Mar 31 01:02:53 PM PDT 24
Peak memory 199652 kb
Host smart-ffb557aa-4f33-46d3-9102-12fdfe339cbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=688618887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.688618887
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.3275598217
Short name T576
Test name
Test status
Simulation time 89328200573 ps
CPU time 164.49 seconds
Started Mar 31 01:01:05 PM PDT 24
Finished Mar 31 01:03:50 PM PDT 24
Peak memory 199648 kb
Host smart-3e02d948-3c32-4430-a7f4-c65fc352af0f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275598217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3275598217
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1355940064
Short name T227
Test name
Test status
Simulation time 2254681916 ps
CPU time 40.55 seconds
Started Mar 31 01:01:04 PM PDT 24
Finished Mar 31 01:01:45 PM PDT 24
Peak memory 199636 kb
Host smart-68f3e2cd-0525-4016-88f4-d462de3e80c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355940064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1355940064
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.1172211770
Short name T582
Test name
Test status
Simulation time 247832793 ps
CPU time 3.28 seconds
Started Mar 31 01:01:05 PM PDT 24
Finished Mar 31 01:01:09 PM PDT 24
Peak memory 199636 kb
Host smart-8a441040-3425-47fa-8def-0d79a21f9ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172211770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1172211770
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.664299932
Short name T464
Test name
Test status
Simulation time 26087310848 ps
CPU time 716.4 seconds
Started Mar 31 01:01:12 PM PDT 24
Finished Mar 31 01:13:09 PM PDT 24
Peak memory 199672 kb
Host smart-a4d92cce-3390-422a-9049-3698b816d6da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664299932 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.664299932
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.3634457140
Short name T255
Test name
Test status
Simulation time 31520867 ps
CPU time 1.26 seconds
Started Mar 31 01:01:12 PM PDT 24
Finished Mar 31 01:01:13 PM PDT 24
Peak memory 199524 kb
Host smart-6cf9e088-20a3-4ba2-b251-a12457345c4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634457140 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.3634457140
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.3561408672
Short name T507
Test name
Test status
Simulation time 86101778560 ps
CPU time 567.92 seconds
Started Mar 31 01:01:11 PM PDT 24
Finished Mar 31 01:10:39 PM PDT 24
Peak memory 199672 kb
Host smart-af70a501-576d-4b4e-ab91-ffb161551221
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561408672 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.3561408672
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1871735309
Short name T312
Test name
Test status
Simulation time 7984087942 ps
CPU time 42.94 seconds
Started Mar 31 01:01:08 PM PDT 24
Finished Mar 31 01:01:51 PM PDT 24
Peak memory 199728 kb
Host smart-ce348947-dcd3-4410-a730-22f53be1356c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871735309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1871735309
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.344740545
Short name T323
Test name
Test status
Simulation time 22945651 ps
CPU time 0.57 seconds
Started Mar 31 01:01:16 PM PDT 24
Finished Mar 31 01:01:17 PM PDT 24
Peak memory 194152 kb
Host smart-10e9bb53-a90a-42c3-af5c-f861aa092436
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344740545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.344740545
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.466425456
Short name T54
Test name
Test status
Simulation time 2864887949 ps
CPU time 26.39 seconds
Started Mar 31 01:01:09 PM PDT 24
Finished Mar 31 01:01:36 PM PDT 24
Peak memory 216068 kb
Host smart-5d9fe2e1-1907-4825-93f2-0ccf6d2d2515
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=466425456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.466425456
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1744652891
Short name T538
Test name
Test status
Simulation time 481013668 ps
CPU time 4.99 seconds
Started Mar 31 01:01:08 PM PDT 24
Finished Mar 31 01:01:14 PM PDT 24
Peak memory 199548 kb
Host smart-ff69bc00-e5db-48ee-b26a-64bd4b9ba89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744652891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1744652891
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.1948620657
Short name T525
Test name
Test status
Simulation time 2720875226 ps
CPU time 38.13 seconds
Started Mar 31 01:01:11 PM PDT 24
Finished Mar 31 01:01:50 PM PDT 24
Peak memory 199704 kb
Host smart-0d8ea1ab-3fcc-4236-a7c6-aa7708f5e71b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1948620657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1948620657
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.3994329742
Short name T29
Test name
Test status
Simulation time 10536358224 ps
CPU time 43.23 seconds
Started Mar 31 01:01:08 PM PDT 24
Finished Mar 31 01:01:52 PM PDT 24
Peak memory 199572 kb
Host smart-b45e5f8a-de72-4fcb-913c-54f12c66db69
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994329742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.3994329742
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.524209936
Short name T294
Test name
Test status
Simulation time 7197703447 ps
CPU time 85.3 seconds
Started Mar 31 01:01:09 PM PDT 24
Finished Mar 31 01:02:34 PM PDT 24
Peak memory 199636 kb
Host smart-7c867de5-0e43-4cb3-8c43-550ee4733a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524209936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.524209936
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2606746326
Short name T279
Test name
Test status
Simulation time 49095319 ps
CPU time 1.28 seconds
Started Mar 31 01:01:08 PM PDT 24
Finished Mar 31 01:01:10 PM PDT 24
Peak memory 199652 kb
Host smart-aef79282-2339-4420-8c9d-929342a19b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606746326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2606746326
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.1286398604
Short name T243
Test name
Test status
Simulation time 48650153577 ps
CPU time 649.31 seconds
Started Mar 31 01:01:17 PM PDT 24
Finished Mar 31 01:12:06 PM PDT 24
Peak memory 199748 kb
Host smart-f21de08d-fd52-40c0-a8bf-806b0fbfdfbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286398604 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.1286398604
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.79657290
Short name T478
Test name
Test status
Simulation time 160155503 ps
CPU time 1.09 seconds
Started Mar 31 01:01:10 PM PDT 24
Finished Mar 31 01:01:11 PM PDT 24
Peak memory 199124 kb
Host smart-77144c02-2130-4668-b242-df284e45d3dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79657290 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.hmac_test_hmac_vectors.79657290
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.358800260
Short name T295
Test name
Test status
Simulation time 10193274000 ps
CPU time 454.24 seconds
Started Mar 31 01:01:09 PM PDT 24
Finished Mar 31 01:08:43 PM PDT 24
Peak memory 199708 kb
Host smart-313cbde3-c2d1-4e68-b6e9-b22238473dab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358800260 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.358800260
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3855341895
Short name T494
Test name
Test status
Simulation time 18893005507 ps
CPU time 70.28 seconds
Started Mar 31 01:01:08 PM PDT 24
Finished Mar 31 01:02:19 PM PDT 24
Peak memory 199628 kb
Host smart-b71efd02-2170-4377-8cf1-521e5c3b5118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855341895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3855341895
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/170.hmac_stress_all_with_rand_reset.4102939562
Short name T73
Test name
Test status
Simulation time 11567424862 ps
CPU time 137.8 seconds
Started Mar 31 01:04:25 PM PDT 24
Finished Mar 31 01:06:43 PM PDT 24
Peak memory 215824 kb
Host smart-dcb0085c-7509-40d3-be56-7776b3c34c76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4102939562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.hmac_stress_all_with_rand_reset.4102939562
Directory /workspace/170.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3014558208
Short name T545
Test name
Test status
Simulation time 12245472 ps
CPU time 0.58 seconds
Started Mar 31 01:01:24 PM PDT 24
Finished Mar 31 01:01:25 PM PDT 24
Peak memory 194160 kb
Host smart-e60bbc2e-133c-4d95-b32c-0b80e3f4384e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014558208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3014558208
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.715004927
Short name T175
Test name
Test status
Simulation time 1509420916 ps
CPU time 64.76 seconds
Started Mar 31 01:01:15 PM PDT 24
Finished Mar 31 01:02:20 PM PDT 24
Peak memory 240368 kb
Host smart-d65ad0ed-10b8-4795-b8f6-44b09b11ad30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=715004927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.715004927
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1267917800
Short name T366
Test name
Test status
Simulation time 5068848532 ps
CPU time 65.14 seconds
Started Mar 31 01:01:15 PM PDT 24
Finished Mar 31 01:02:20 PM PDT 24
Peak memory 199684 kb
Host smart-3998aa82-b7ec-464a-aede-ece7228c7536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267917800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1267917800
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2105049396
Short name T282
Test name
Test status
Simulation time 1278580074 ps
CPU time 21.63 seconds
Started Mar 31 01:01:17 PM PDT 24
Finished Mar 31 01:01:38 PM PDT 24
Peak memory 199688 kb
Host smart-6f3482ad-f26d-4eef-8867-2d792daab7f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2105049396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2105049396
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.2142398870
Short name T42
Test name
Test status
Simulation time 1104703424 ps
CPU time 63.61 seconds
Started Mar 31 01:01:17 PM PDT 24
Finished Mar 31 01:02:20 PM PDT 24
Peak memory 199684 kb
Host smart-d157626d-60a7-4299-84b8-ce7039bb1c4d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142398870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2142398870
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.974409672
Short name T200
Test name
Test status
Simulation time 1000384150 ps
CPU time 16.36 seconds
Started Mar 31 01:01:16 PM PDT 24
Finished Mar 31 01:01:33 PM PDT 24
Peak memory 199584 kb
Host smart-85a215dd-bd29-425b-ad50-3f6dcc888c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974409672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.974409672
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.1273039022
Short name T368
Test name
Test status
Simulation time 994923087 ps
CPU time 3.51 seconds
Started Mar 31 01:01:16 PM PDT 24
Finished Mar 31 01:01:20 PM PDT 24
Peak memory 199644 kb
Host smart-cb7dc2b3-3f07-4d2a-966b-58c4bbb20914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273039022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1273039022
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3258569698
Short name T50
Test name
Test status
Simulation time 52175126908 ps
CPU time 746.98 seconds
Started Mar 31 01:01:19 PM PDT 24
Finished Mar 31 01:13:46 PM PDT 24
Peak memory 199452 kb
Host smart-7a3eeb33-0be8-4fa7-9176-c315affb2500
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258569698 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3258569698
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.3560148193
Short name T374
Test name
Test status
Simulation time 232910784 ps
CPU time 1.32 seconds
Started Mar 31 01:01:19 PM PDT 24
Finished Mar 31 01:01:21 PM PDT 24
Peak memory 199236 kb
Host smart-01db4681-0000-485c-9774-5585699c4811
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560148193 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.3560148193
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.3573979508
Short name T253
Test name
Test status
Simulation time 15175679556 ps
CPU time 477.44 seconds
Started Mar 31 01:01:18 PM PDT 24
Finished Mar 31 01:09:15 PM PDT 24
Peak memory 199660 kb
Host smart-dc604e50-deea-4479-9b5b-f83be396238e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573979508 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.3573979508
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.3386347237
Short name T367
Test name
Test status
Simulation time 4954746212 ps
CPU time 72.32 seconds
Started Mar 31 01:01:17 PM PDT 24
Finished Mar 31 01:02:30 PM PDT 24
Peak memory 199700 kb
Host smart-b4ba1307-f4e1-4339-87f4-039703cb90a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386347237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3386347237
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/181.hmac_stress_all_with_rand_reset.3780918835
Short name T586
Test name
Test status
Simulation time 22203076983 ps
CPU time 965.11 seconds
Started Mar 31 01:04:35 PM PDT 24
Finished Mar 31 01:20:41 PM PDT 24
Peak memory 210476 kb
Host smart-5ba8681a-9180-4525-bd1a-fd01a4f1343e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3780918835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.hmac_stress_all_with_rand_reset.3780918835
Directory /workspace/181.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.665469575
Short name T252
Test name
Test status
Simulation time 24267131 ps
CPU time 0.56 seconds
Started Mar 31 01:01:26 PM PDT 24
Finished Mar 31 01:01:26 PM PDT 24
Peak memory 194108 kb
Host smart-ff4d14c1-1c30-470f-8bb1-3d723173257e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665469575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.665469575
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2658117803
Short name T345
Test name
Test status
Simulation time 141180722 ps
CPU time 4.86 seconds
Started Mar 31 01:01:23 PM PDT 24
Finished Mar 31 01:01:28 PM PDT 24
Peak memory 199636 kb
Host smart-cf9f1c07-c8b4-4810-8c1d-f2333bae74a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2658117803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2658117803
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1018716126
Short name T344
Test name
Test status
Simulation time 514838252 ps
CPU time 27.52 seconds
Started Mar 31 01:01:26 PM PDT 24
Finished Mar 31 01:01:53 PM PDT 24
Peak memory 199652 kb
Host smart-d16345c8-2b38-4a49-9062-14948949e29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018716126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1018716126
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.457785458
Short name T158
Test name
Test status
Simulation time 3467833783 ps
CPU time 100.64 seconds
Started Mar 31 01:01:28 PM PDT 24
Finished Mar 31 01:03:09 PM PDT 24
Peak memory 199652 kb
Host smart-0cc772a8-9012-4e95-b6ee-c249fdcd171f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=457785458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.457785458
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.4271966922
Short name T381
Test name
Test status
Simulation time 9943270011 ps
CPU time 136.71 seconds
Started Mar 31 01:01:23 PM PDT 24
Finished Mar 31 01:03:39 PM PDT 24
Peak memory 199712 kb
Host smart-d2df2c6d-48c8-4951-87c6-e1a6a9cde338
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271966922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.4271966922
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.3917754845
Short name T324
Test name
Test status
Simulation time 139912821 ps
CPU time 8.32 seconds
Started Mar 31 01:01:26 PM PDT 24
Finished Mar 31 01:01:34 PM PDT 24
Peak memory 199648 kb
Host smart-9f3c2287-dc62-46b0-adf6-4f433ed64bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917754845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3917754845
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.4114357343
Short name T523
Test name
Test status
Simulation time 194563207 ps
CPU time 2.77 seconds
Started Mar 31 01:01:28 PM PDT 24
Finished Mar 31 01:01:31 PM PDT 24
Peak memory 199580 kb
Host smart-a74b215e-5313-4948-98b0-9bb151a942a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114357343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.4114357343
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.2585664785
Short name T277
Test name
Test status
Simulation time 79713995197 ps
CPU time 237.12 seconds
Started Mar 31 01:01:23 PM PDT 24
Finished Mar 31 01:05:20 PM PDT 24
Peak memory 199652 kb
Host smart-cba9f546-ac52-4d4b-a699-d32d9fafb943
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585664785 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2585664785
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.173231807
Short name T146
Test name
Test status
Simulation time 32191789 ps
CPU time 1.2 seconds
Started Mar 31 01:01:28 PM PDT 24
Finished Mar 31 01:01:30 PM PDT 24
Peak memory 199584 kb
Host smart-0c86c725-514d-4da7-9b52-9c7e31042403
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173231807 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_hmac_vectors.173231807
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.2166956967
Short name T456
Test name
Test status
Simulation time 28639836399 ps
CPU time 522.75 seconds
Started Mar 31 01:01:26 PM PDT 24
Finished Mar 31 01:10:09 PM PDT 24
Peak memory 199616 kb
Host smart-46f90cf2-e2df-4473-b111-950da7fad624
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166956967 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.2166956967
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.2405700073
Short name T216
Test name
Test status
Simulation time 6552521931 ps
CPU time 19.9 seconds
Started Mar 31 01:01:23 PM PDT 24
Finished Mar 31 01:01:43 PM PDT 24
Peak memory 199716 kb
Host smart-3b6fde91-2742-4507-a967-b42cb3779ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405700073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.2405700073
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/199.hmac_stress_all_with_rand_reset.3959382030
Short name T11
Test name
Test status
Simulation time 15277253006 ps
CPU time 401.81 seconds
Started Mar 31 01:04:45 PM PDT 24
Finished Mar 31 01:11:28 PM PDT 24
Peak memory 207936 kb
Host smart-52acb31b-7d80-4c5e-bf64-11bf8eab87c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3959382030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.hmac_stress_all_with_rand_reset.3959382030
Directory /workspace/199.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1223964082
Short name T23
Test name
Test status
Simulation time 108869244 ps
CPU time 0.56 seconds
Started Mar 31 01:00:33 PM PDT 24
Finished Mar 31 01:00:34 PM PDT 24
Peak memory 195216 kb
Host smart-1c4982d2-ca87-41a9-ab84-464d88684410
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223964082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1223964082
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1030493721
Short name T333
Test name
Test status
Simulation time 1552757406 ps
CPU time 37.39 seconds
Started Mar 31 01:00:33 PM PDT 24
Finished Mar 31 01:01:11 PM PDT 24
Peak memory 215264 kb
Host smart-98577df8-9eda-4084-8f6d-e688b6e8e1dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1030493721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1030493721
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2357704971
Short name T19
Test name
Test status
Simulation time 927455329 ps
CPU time 48.47 seconds
Started Mar 31 01:00:33 PM PDT 24
Finished Mar 31 01:01:22 PM PDT 24
Peak memory 199656 kb
Host smart-e6691b95-a0f1-48c8-b072-c59a68359229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357704971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2357704971
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.1697985398
Short name T416
Test name
Test status
Simulation time 1873425179 ps
CPU time 119.16 seconds
Started Mar 31 01:00:38 PM PDT 24
Finished Mar 31 01:02:38 PM PDT 24
Peak memory 199628 kb
Host smart-10b46354-a42b-476d-b786-bbdf120a54c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1697985398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1697985398
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.4200277363
Short name T529
Test name
Test status
Simulation time 13955437122 ps
CPU time 140.62 seconds
Started Mar 31 01:00:37 PM PDT 24
Finished Mar 31 01:02:58 PM PDT 24
Peak memory 199704 kb
Host smart-1d513c46-5669-4a50-aa20-c0120faaba1f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200277363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.4200277363
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.2780697460
Short name T242
Test name
Test status
Simulation time 2507163484 ps
CPU time 13.26 seconds
Started Mar 31 01:00:33 PM PDT 24
Finished Mar 31 01:00:47 PM PDT 24
Peak memory 199604 kb
Host smart-e6435ad8-8062-4cab-8777-402d3f69f2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780697460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2780697460
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3656922579
Short name T36
Test name
Test status
Simulation time 79832020 ps
CPU time 0.81 seconds
Started Mar 31 01:00:33 PM PDT 24
Finished Mar 31 01:00:34 PM PDT 24
Peak memory 218056 kb
Host smart-56651843-789d-4d85-99c5-dfc9556531d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656922579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3656922579
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.254854330
Short name T376
Test name
Test status
Simulation time 46345536 ps
CPU time 1.69 seconds
Started Mar 31 01:00:34 PM PDT 24
Finished Mar 31 01:00:36 PM PDT 24
Peak memory 199640 kb
Host smart-5239a4e4-2bc3-428a-a7d2-7d95b63779ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254854330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.254854330
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3075457408
Short name T224
Test name
Test status
Simulation time 661585704306 ps
CPU time 1839.99 seconds
Started Mar 31 01:00:36 PM PDT 24
Finished Mar 31 01:31:16 PM PDT 24
Peak memory 207936 kb
Host smart-c2408643-e48e-4c9c-934c-a2b9224a2afa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075457408 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3075457408
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.3711269294
Short name T154
Test name
Test status
Simulation time 109562281 ps
CPU time 1.01 seconds
Started Mar 31 01:00:34 PM PDT 24
Finished Mar 31 01:00:35 PM PDT 24
Peak memory 198868 kb
Host smart-08cea7cc-00b5-4ab6-96b7-2de1e757b65d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711269294 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.3711269294
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.3517227090
Short name T132
Test name
Test status
Simulation time 30938959912 ps
CPU time 435.15 seconds
Started Mar 31 01:00:34 PM PDT 24
Finished Mar 31 01:07:49 PM PDT 24
Peak memory 199656 kb
Host smart-c26fb33f-ae95-465d-aff8-49762da02489
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517227090 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.3517227090
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.1674322255
Short name T184
Test name
Test status
Simulation time 6671950917 ps
CPU time 76.91 seconds
Started Mar 31 01:00:37 PM PDT 24
Finished Mar 31 01:01:55 PM PDT 24
Peak memory 199680 kb
Host smart-798f9312-d1a5-4fb6-ac6f-793deee79f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674322255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1674322255
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2948447950
Short name T269
Test name
Test status
Simulation time 15711190 ps
CPU time 0.57 seconds
Started Mar 31 01:01:34 PM PDT 24
Finished Mar 31 01:01:35 PM PDT 24
Peak memory 194124 kb
Host smart-e4e65de4-7ab2-4f58-8b1d-10aaf8a557e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948447950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2948447950
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.429521207
Short name T470
Test name
Test status
Simulation time 1835066611 ps
CPU time 38.02 seconds
Started Mar 31 01:01:30 PM PDT 24
Finished Mar 31 01:02:08 PM PDT 24
Peak memory 207840 kb
Host smart-0cdcb699-b021-4cf7-b1ae-0fdc9534424b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=429521207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.429521207
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.761241521
Short name T1
Test name
Test status
Simulation time 621271069 ps
CPU time 13.67 seconds
Started Mar 31 01:01:30 PM PDT 24
Finished Mar 31 01:01:43 PM PDT 24
Peak memory 199660 kb
Host smart-de0ad75c-eddf-485d-9b5f-d3b670318ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761241521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.761241521
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1121625018
Short name T123
Test name
Test status
Simulation time 93844197 ps
CPU time 2.56 seconds
Started Mar 31 01:01:31 PM PDT 24
Finished Mar 31 01:01:34 PM PDT 24
Peak memory 199620 kb
Host smart-d0546673-3615-4e59-acf6-f63f5cd85327
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1121625018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1121625018
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.214576345
Short name T346
Test name
Test status
Simulation time 2886883765 ps
CPU time 165.58 seconds
Started Mar 31 01:01:32 PM PDT 24
Finished Mar 31 01:04:17 PM PDT 24
Peak memory 199696 kb
Host smart-93290f60-8c14-4b37-a2b6-4e1d1d09b25e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214576345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.214576345
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2283043305
Short name T399
Test name
Test status
Simulation time 3961952495 ps
CPU time 58.12 seconds
Started Mar 31 01:01:31 PM PDT 24
Finished Mar 31 01:02:29 PM PDT 24
Peak memory 199608 kb
Host smart-97f1019c-e8e9-41f8-b885-dfaad86ed03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283043305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2283043305
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1684812014
Short name T173
Test name
Test status
Simulation time 442045667 ps
CPU time 6.75 seconds
Started Mar 31 01:01:21 PM PDT 24
Finished Mar 31 01:01:28 PM PDT 24
Peak memory 199636 kb
Host smart-3cf6a1eb-3c43-4101-bdd5-3741ed2c3de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684812014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1684812014
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2085690234
Short name T281
Test name
Test status
Simulation time 20703876478 ps
CPU time 1082.08 seconds
Started Mar 31 01:01:32 PM PDT 24
Finished Mar 31 01:19:34 PM PDT 24
Peak memory 199228 kb
Host smart-1c2a92d6-5835-42da-a111-51dfb64f803b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085690234 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2085690234
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.3389526598
Short name T510
Test name
Test status
Simulation time 60389947 ps
CPU time 1.25 seconds
Started Mar 31 01:01:30 PM PDT 24
Finished Mar 31 01:01:31 PM PDT 24
Peak memory 198664 kb
Host smart-b1c65f0f-1573-4025-9374-e86fed1b5872
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389526598 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.3389526598
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.2058043289
Short name T187
Test name
Test status
Simulation time 27547673955 ps
CPU time 482.34 seconds
Started Mar 31 01:01:34 PM PDT 24
Finished Mar 31 01:09:36 PM PDT 24
Peak memory 199636 kb
Host smart-b8b1e10f-db24-4e36-931b-174ba15de48a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058043289 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.2058043289
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3894305075
Short name T567
Test name
Test status
Simulation time 285052561 ps
CPU time 10.62 seconds
Started Mar 31 01:01:28 PM PDT 24
Finished Mar 31 01:01:39 PM PDT 24
Peak memory 199640 kb
Host smart-ecb521fa-2edd-4d77-958a-0758ee730019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894305075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3894305075
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.847007936
Short name T237
Test name
Test status
Simulation time 52904130 ps
CPU time 0.63 seconds
Started Mar 31 01:01:30 PM PDT 24
Finished Mar 31 01:01:31 PM PDT 24
Peak memory 194852 kb
Host smart-21d7e526-35c7-4de0-8d68-a7184878e86e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847007936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.847007936
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3110797863
Short name T170
Test name
Test status
Simulation time 6479927940 ps
CPU time 43.2 seconds
Started Mar 31 01:01:30 PM PDT 24
Finished Mar 31 01:02:14 PM PDT 24
Peak memory 232448 kb
Host smart-1eed2a70-b050-4afc-ba2d-39094215f1e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3110797863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3110797863
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3647966806
Short name T551
Test name
Test status
Simulation time 116133964 ps
CPU time 1.45 seconds
Started Mar 31 01:01:32 PM PDT 24
Finished Mar 31 01:01:34 PM PDT 24
Peak memory 199636 kb
Host smart-1c5b2cf9-30d7-48e9-b0a9-1c5b98543c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647966806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3647966806
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.2809046739
Short name T257
Test name
Test status
Simulation time 720333357 ps
CPU time 20.99 seconds
Started Mar 31 01:01:30 PM PDT 24
Finished Mar 31 01:01:51 PM PDT 24
Peak memory 199584 kb
Host smart-4a44939e-980d-4f4f-a508-b86478be931b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2809046739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2809046739
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3635569576
Short name T47
Test name
Test status
Simulation time 4858051061 ps
CPU time 67.39 seconds
Started Mar 31 01:01:30 PM PDT 24
Finished Mar 31 01:02:37 PM PDT 24
Peak memory 199664 kb
Host smart-324ac2db-b238-4b3c-ba95-3d26bbab8c26
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635569576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3635569576
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2098631886
Short name T151
Test name
Test status
Simulation time 9001429805 ps
CPU time 32.62 seconds
Started Mar 31 01:01:29 PM PDT 24
Finished Mar 31 01:02:02 PM PDT 24
Peak memory 199716 kb
Host smart-ada56039-5a2a-401a-a1be-accc7e4a50ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098631886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2098631886
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.401937785
Short name T310
Test name
Test status
Simulation time 404442510 ps
CPU time 1.53 seconds
Started Mar 31 01:01:34 PM PDT 24
Finished Mar 31 01:01:36 PM PDT 24
Peak memory 199600 kb
Host smart-db1f523a-3680-44f3-9853-cf3cf30d1eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401937785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.401937785
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.79172151
Short name T575
Test name
Test status
Simulation time 448348287 ps
CPU time 1.09 seconds
Started Mar 31 01:01:32 PM PDT 24
Finished Mar 31 01:01:33 PM PDT 24
Peak memory 197628 kb
Host smart-77665ddf-9cc1-4065-bae0-a49c28da44b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79172151 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.hmac_test_hmac_vectors.79172151
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.1743511415
Short name T174
Test name
Test status
Simulation time 49089331107 ps
CPU time 448.67 seconds
Started Mar 31 01:01:32 PM PDT 24
Finished Mar 31 01:09:01 PM PDT 24
Peak memory 199672 kb
Host smart-b71a4b32-6aa6-49ff-8f4b-00fc98c8a152
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743511415 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.1743511415
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.4032195685
Short name T117
Test name
Test status
Simulation time 8123422578 ps
CPU time 32.11 seconds
Started Mar 31 01:01:29 PM PDT 24
Finished Mar 31 01:02:01 PM PDT 24
Peak memory 199728 kb
Host smart-2b863a80-7ddc-4084-bde2-0b3718f5beb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032195685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.4032195685
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.146442070
Short name T537
Test name
Test status
Simulation time 205091124 ps
CPU time 0.58 seconds
Started Mar 31 01:01:38 PM PDT 24
Finished Mar 31 01:01:38 PM PDT 24
Peak memory 195132 kb
Host smart-e622cd3f-b9ae-44f4-89d4-8fbfe3ef909b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146442070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.146442070
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.468106440
Short name T520
Test name
Test status
Simulation time 1023723044 ps
CPU time 34.97 seconds
Started Mar 31 01:01:30 PM PDT 24
Finished Mar 31 01:02:05 PM PDT 24
Peak memory 215264 kb
Host smart-828403b3-5efc-4d2e-972f-aedf0b9d4a8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=468106440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.468106440
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.3761554636
Short name T546
Test name
Test status
Simulation time 2819608721 ps
CPU time 70.7 seconds
Started Mar 31 01:01:34 PM PDT 24
Finished Mar 31 01:02:44 PM PDT 24
Peak memory 199648 kb
Host smart-79412a83-7ecd-4f0a-9cd7-ef3913a1e73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761554636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.3761554636
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.2230027921
Short name T6
Test name
Test status
Simulation time 3203423126 ps
CPU time 96.2 seconds
Started Mar 31 01:01:31 PM PDT 24
Finished Mar 31 01:03:07 PM PDT 24
Peak memory 199732 kb
Host smart-1a29efe6-3941-45cf-9ab6-d5de97fe787f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2230027921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2230027921
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.3511085122
Short name T16
Test name
Test status
Simulation time 485994101 ps
CPU time 13.43 seconds
Started Mar 31 01:01:43 PM PDT 24
Finished Mar 31 01:01:57 PM PDT 24
Peak memory 199580 kb
Host smart-30b19d2c-56a4-4377-8166-8f43aae21094
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511085122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3511085122
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.445582850
Short name T185
Test name
Test status
Simulation time 5350221411 ps
CPU time 15.82 seconds
Started Mar 31 01:01:29 PM PDT 24
Finished Mar 31 01:01:45 PM PDT 24
Peak memory 199632 kb
Host smart-6b0b7868-f69c-4222-a4e7-51dc0d9e5dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445582850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.445582850
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1233063869
Short name T272
Test name
Test status
Simulation time 185368335 ps
CPU time 0.93 seconds
Started Mar 31 01:01:31 PM PDT 24
Finished Mar 31 01:01:32 PM PDT 24
Peak memory 197804 kb
Host smart-dfe749cb-d6e9-410b-971b-0d5bf42464e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233063869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1233063869
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.711685131
Short name T97
Test name
Test status
Simulation time 45526790177 ps
CPU time 837.91 seconds
Started Mar 31 01:01:40 PM PDT 24
Finished Mar 31 01:15:38 PM PDT 24
Peak memory 199716 kb
Host smart-b6fdafc3-88c1-4478-9d00-e991888ff3e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711685131 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.711685131
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.2936250066
Short name T127
Test name
Test status
Simulation time 49518287 ps
CPU time 1.01 seconds
Started Mar 31 01:01:37 PM PDT 24
Finished Mar 31 01:01:38 PM PDT 24
Peak memory 198952 kb
Host smart-b987cc52-3f90-4171-9a8c-d56f664fabc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936250066 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.2936250066
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.3324189121
Short name T519
Test name
Test status
Simulation time 8443427216 ps
CPU time 455.52 seconds
Started Mar 31 01:01:37 PM PDT 24
Finished Mar 31 01:09:13 PM PDT 24
Peak memory 199652 kb
Host smart-72a23306-185f-41f6-98a6-a8f2f0bc30d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324189121 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.3324189121
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2961202567
Short name T533
Test name
Test status
Simulation time 3555851828 ps
CPU time 40.36 seconds
Started Mar 31 01:01:37 PM PDT 24
Finished Mar 31 01:02:18 PM PDT 24
Peak memory 199704 kb
Host smart-e920df26-1f07-4c88-9886-caec037aa922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961202567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2961202567
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.1214863945
Short name T517
Test name
Test status
Simulation time 12266993 ps
CPU time 0.58 seconds
Started Mar 31 01:01:36 PM PDT 24
Finished Mar 31 01:01:37 PM PDT 24
Peak memory 195116 kb
Host smart-4b575de6-224a-4d73-8e94-fe26ea59c352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214863945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1214863945
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.98504462
Short name T267
Test name
Test status
Simulation time 1883041780 ps
CPU time 32.49 seconds
Started Mar 31 01:01:37 PM PDT 24
Finished Mar 31 01:02:10 PM PDT 24
Peak memory 207696 kb
Host smart-678d82a1-30b1-401d-969e-2e33adaa4bc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=98504462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.98504462
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.3864777105
Short name T340
Test name
Test status
Simulation time 1733466552 ps
CPU time 33.52 seconds
Started Mar 31 01:01:38 PM PDT 24
Finished Mar 31 01:02:11 PM PDT 24
Peak memory 199632 kb
Host smart-8a1524f8-bc03-4a5f-b98c-0fe375a401b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864777105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3864777105
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1790570563
Short name T358
Test name
Test status
Simulation time 9353465183 ps
CPU time 137.33 seconds
Started Mar 31 01:01:38 PM PDT 24
Finished Mar 31 01:03:56 PM PDT 24
Peak memory 199680 kb
Host smart-64fa546a-e58e-4eb7-8761-321ae701a935
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1790570563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1790570563
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2157852648
Short name T307
Test name
Test status
Simulation time 2993557393 ps
CPU time 163.05 seconds
Started Mar 31 01:01:37 PM PDT 24
Finished Mar 31 01:04:20 PM PDT 24
Peak memory 199628 kb
Host smart-b884bee8-81ee-45fd-b08e-982299b08eb4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157852648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2157852648
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.9842640
Short name T241
Test name
Test status
Simulation time 1738106673 ps
CPU time 105.3 seconds
Started Mar 31 01:01:37 PM PDT 24
Finished Mar 31 01:03:23 PM PDT 24
Peak memory 199636 kb
Host smart-4ef2dab0-d368-46d4-bbb1-ce3e5acd3522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9842640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.9842640
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2871958989
Short name T356
Test name
Test status
Simulation time 97793420 ps
CPU time 1.95 seconds
Started Mar 31 01:01:39 PM PDT 24
Finished Mar 31 01:01:41 PM PDT 24
Peak memory 199628 kb
Host smart-b25a355b-27f2-439e-89ff-616b78232ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871958989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2871958989
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3926751225
Short name T288
Test name
Test status
Simulation time 74823756121 ps
CPU time 869.7 seconds
Started Mar 31 01:01:38 PM PDT 24
Finished Mar 31 01:16:08 PM PDT 24
Peak memory 240620 kb
Host smart-6f522268-f6a8-44eb-8b15-b3fbea5e47c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926751225 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3926751225
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.2904295176
Short name T275
Test name
Test status
Simulation time 209992843 ps
CPU time 1.28 seconds
Started Mar 31 01:01:39 PM PDT 24
Finished Mar 31 01:01:41 PM PDT 24
Peak memory 199472 kb
Host smart-14d1bb05-e534-4dea-98c9-6e237b802f7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904295176 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.2904295176
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.3412418910
Short name T18
Test name
Test status
Simulation time 39100015055 ps
CPU time 506.43 seconds
Started Mar 31 01:01:39 PM PDT 24
Finished Mar 31 01:10:06 PM PDT 24
Peak memory 199636 kb
Host smart-b6d9c158-43ff-44f7-b3db-58d0819ce2ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412418910 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.3412418910
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2111829496
Short name T316
Test name
Test status
Simulation time 37983740847 ps
CPU time 94.12 seconds
Started Mar 31 01:01:38 PM PDT 24
Finished Mar 31 01:03:12 PM PDT 24
Peak memory 199688 kb
Host smart-a72bf8f5-4fbf-4e00-87a6-41892e0d1d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111829496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2111829496
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.4236803414
Short name T320
Test name
Test status
Simulation time 15882973 ps
CPU time 0.6 seconds
Started Mar 31 01:01:46 PM PDT 24
Finished Mar 31 01:01:46 PM PDT 24
Peak memory 195156 kb
Host smart-1f636164-31d2-4a06-8d7d-04d3fecd67c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236803414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.4236803414
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1350034794
Short name T56
Test name
Test status
Simulation time 961131525 ps
CPU time 11.48 seconds
Started Mar 31 01:01:47 PM PDT 24
Finished Mar 31 01:01:58 PM PDT 24
Peak memory 216036 kb
Host smart-3ba82d61-b332-457f-af1b-5e6e064c36d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1350034794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1350034794
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1982401215
Short name T235
Test name
Test status
Simulation time 779616281 ps
CPU time 6.58 seconds
Started Mar 31 01:01:45 PM PDT 24
Finished Mar 31 01:01:52 PM PDT 24
Peak memory 199500 kb
Host smart-a9cc4b78-994c-46ca-98b7-00ebbdf421c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982401215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1982401215
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.485520084
Short name T136
Test name
Test status
Simulation time 1719847717 ps
CPU time 105.39 seconds
Started Mar 31 01:01:43 PM PDT 24
Finished Mar 31 01:03:29 PM PDT 24
Peak memory 199556 kb
Host smart-b4a0b232-35a2-40be-997d-7edb53ad4137
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=485520084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.485520084
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.1832421020
Short name T53
Test name
Test status
Simulation time 17755828447 ps
CPU time 232.78 seconds
Started Mar 31 01:01:44 PM PDT 24
Finished Mar 31 01:05:37 PM PDT 24
Peak memory 199736 kb
Host smart-65e3d664-2681-41ce-b742-c88262428e41
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832421020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1832421020
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.198073162
Short name T60
Test name
Test status
Simulation time 5257417396 ps
CPU time 83.8 seconds
Started Mar 31 01:01:38 PM PDT 24
Finished Mar 31 01:03:02 PM PDT 24
Peak memory 199640 kb
Host smart-7be88a24-53a2-4ff0-85db-505006586774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198073162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.198073162
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1610433328
Short name T135
Test name
Test status
Simulation time 819267069 ps
CPU time 3.73 seconds
Started Mar 31 01:01:37 PM PDT 24
Finished Mar 31 01:01:41 PM PDT 24
Peak memory 199656 kb
Host smart-b22392dc-1ca5-4b43-b56d-803e9e33e984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610433328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1610433328
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.2916083286
Short name T396
Test name
Test status
Simulation time 100299563737 ps
CPU time 297.67 seconds
Started Mar 31 01:01:43 PM PDT 24
Finished Mar 31 01:06:40 PM PDT 24
Peak memory 215216 kb
Host smart-639a9228-be75-4ad1-81b7-ad03816f7402
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916083286 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2916083286
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.1294456346
Short name T371
Test name
Test status
Simulation time 114500594 ps
CPU time 0.97 seconds
Started Mar 31 01:01:45 PM PDT 24
Finished Mar 31 01:01:46 PM PDT 24
Peak memory 197828 kb
Host smart-658dc80b-a97c-4500-9ff6-3f5b3dfe16a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294456346 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.1294456346
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.3570008059
Short name T178
Test name
Test status
Simulation time 16738064387 ps
CPU time 448.14 seconds
Started Mar 31 01:01:42 PM PDT 24
Finished Mar 31 01:09:10 PM PDT 24
Peak memory 199704 kb
Host smart-84ac8688-bcb9-49ae-857d-c25ab44c48b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570008059 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.3570008059
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3101612710
Short name T357
Test name
Test status
Simulation time 516826332 ps
CPU time 12.6 seconds
Started Mar 31 01:01:44 PM PDT 24
Finished Mar 31 01:01:57 PM PDT 24
Peak memory 199664 kb
Host smart-d0e2f90c-4b60-4716-86cb-d7580b265977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101612710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3101612710
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.1468745541
Short name T214
Test name
Test status
Simulation time 22794871 ps
CPU time 0.62 seconds
Started Mar 31 01:01:55 PM PDT 24
Finished Mar 31 01:01:56 PM PDT 24
Peak memory 195212 kb
Host smart-ea49da71-5fca-4318-b1f5-d52f89ea4569
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468745541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1468745541
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1189188634
Short name T471
Test name
Test status
Simulation time 1005717613 ps
CPU time 35.49 seconds
Started Mar 31 01:01:45 PM PDT 24
Finished Mar 31 01:02:21 PM PDT 24
Peak memory 207820 kb
Host smart-107bccbc-131b-4caa-89d7-6392f863bf05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1189188634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1189188634
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.134291732
Short name T225
Test name
Test status
Simulation time 2041085823 ps
CPU time 53.05 seconds
Started Mar 31 01:01:46 PM PDT 24
Finished Mar 31 01:02:39 PM PDT 24
Peak memory 199536 kb
Host smart-12b16210-13ad-4a9f-8c3e-4e6fad69c6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134291732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.134291732
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.4260843170
Short name T39
Test name
Test status
Simulation time 205801643 ps
CPU time 1.43 seconds
Started Mar 31 01:01:44 PM PDT 24
Finished Mar 31 01:01:46 PM PDT 24
Peak memory 198740 kb
Host smart-3aaf6dd9-ff7f-47ae-b245-fc46db9bf8c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4260843170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.4260843170
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.631447791
Short name T495
Test name
Test status
Simulation time 5730091966 ps
CPU time 156.22 seconds
Started Mar 31 01:01:45 PM PDT 24
Finished Mar 31 01:04:22 PM PDT 24
Peak memory 199684 kb
Host smart-40918e13-24a6-4898-adbf-a33d59641552
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631447791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.631447791
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2964603950
Short name T222
Test name
Test status
Simulation time 296410158 ps
CPU time 18.5 seconds
Started Mar 31 01:01:47 PM PDT 24
Finished Mar 31 01:02:05 PM PDT 24
Peak memory 199604 kb
Host smart-6d12a11c-65a9-4371-90af-8564f59e97b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964603950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2964603950
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2065667072
Short name T561
Test name
Test status
Simulation time 511853071 ps
CPU time 4.1 seconds
Started Mar 31 01:01:45 PM PDT 24
Finished Mar 31 01:01:49 PM PDT 24
Peak memory 199620 kb
Host smart-31651880-2172-4597-b391-6ee339e07f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065667072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2065667072
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.4017280772
Short name T364
Test name
Test status
Simulation time 44405647711 ps
CPU time 410.09 seconds
Started Mar 31 01:01:44 PM PDT 24
Finished Mar 31 01:08:34 PM PDT 24
Peak memory 227248 kb
Host smart-67aa6125-c1c4-4587-a823-209bd09331a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017280772 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.4017280772
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.4114862584
Short name T77
Test name
Test status
Simulation time 300141835 ps
CPU time 1.44 seconds
Started Mar 31 01:01:45 PM PDT 24
Finished Mar 31 01:01:46 PM PDT 24
Peak memory 199556 kb
Host smart-57036aa9-83d5-41d1-b3f7-7c0ff95972ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114862584 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.4114862584
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.643531386
Short name T221
Test name
Test status
Simulation time 38223030943 ps
CPU time 441.25 seconds
Started Mar 31 01:01:46 PM PDT 24
Finished Mar 31 01:09:07 PM PDT 24
Peak memory 199616 kb
Host smart-d559db2d-19a0-4a64-b344-20a3afa22198
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643531386 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.643531386
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.23707282
Short name T405
Test name
Test status
Simulation time 4907128099 ps
CPU time 98.41 seconds
Started Mar 31 01:01:43 PM PDT 24
Finished Mar 31 01:03:21 PM PDT 24
Peak memory 199720 kb
Host smart-fc00752d-9ba9-4580-8e44-40971824989f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23707282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.23707282
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1650518347
Short name T290
Test name
Test status
Simulation time 12002926 ps
CPU time 0.58 seconds
Started Mar 31 01:01:54 PM PDT 24
Finished Mar 31 01:01:55 PM PDT 24
Peak memory 195116 kb
Host smart-47cf702b-f8d8-496c-bf94-2de6f87fc8b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650518347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1650518347
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.761687775
Short name T524
Test name
Test status
Simulation time 715058745 ps
CPU time 25.82 seconds
Started Mar 31 01:01:54 PM PDT 24
Finished Mar 31 01:02:20 PM PDT 24
Peak memory 207828 kb
Host smart-588fddf4-c536-445e-930f-c6e21d4ea53a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=761687775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.761687775
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.142404618
Short name T518
Test name
Test status
Simulation time 227327831 ps
CPU time 5.32 seconds
Started Mar 31 01:01:55 PM PDT 24
Finished Mar 31 01:02:01 PM PDT 24
Peak memory 199620 kb
Host smart-9c8a6f21-32f4-4d36-8c6b-cc4d31de31d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142404618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.142404618
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.4113048347
Short name T126
Test name
Test status
Simulation time 5453097178 ps
CPU time 91.26 seconds
Started Mar 31 01:01:54 PM PDT 24
Finished Mar 31 01:03:26 PM PDT 24
Peak memory 199724 kb
Host smart-4052e323-bcba-441e-92c6-a290f40813a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4113048347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.4113048347
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.20322298
Short name T330
Test name
Test status
Simulation time 7670266539 ps
CPU time 102.46 seconds
Started Mar 31 01:01:53 PM PDT 24
Finished Mar 31 01:03:36 PM PDT 24
Peak memory 199744 kb
Host smart-c859ccac-c68e-4a7a-a683-1d35a6a93138
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20322298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.20322298
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1038487592
Short name T332
Test name
Test status
Simulation time 14318391434 ps
CPU time 54.42 seconds
Started Mar 31 01:01:56 PM PDT 24
Finished Mar 31 01:02:50 PM PDT 24
Peak memory 199624 kb
Host smart-64f625d2-9886-4c66-911d-9e02d761c0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038487592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1038487592
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.788416277
Short name T273
Test name
Test status
Simulation time 529876816 ps
CPU time 4.24 seconds
Started Mar 31 01:01:56 PM PDT 24
Finished Mar 31 01:02:00 PM PDT 24
Peak memory 199660 kb
Host smart-1d3f4511-9367-433b-9457-f270b91237ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788416277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.788416277
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.619010073
Short name T468
Test name
Test status
Simulation time 51864224631 ps
CPU time 2205.7 seconds
Started Mar 31 01:01:52 PM PDT 24
Finished Mar 31 01:38:38 PM PDT 24
Peak memory 240832 kb
Host smart-08d97791-ca8e-4cd2-8592-20265d6516df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619010073 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.619010073
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.2502404172
Short name T403
Test name
Test status
Simulation time 83801135 ps
CPU time 1.04 seconds
Started Mar 31 01:01:53 PM PDT 24
Finished Mar 31 01:01:54 PM PDT 24
Peak memory 198772 kb
Host smart-f716031e-51c7-4c80-96b5-47dc5b1ef4a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502404172 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.2502404172
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.3608395769
Short name T480
Test name
Test status
Simulation time 8573126883 ps
CPU time 477.66 seconds
Started Mar 31 01:01:55 PM PDT 24
Finished Mar 31 01:09:53 PM PDT 24
Peak memory 199600 kb
Host smart-f5246a93-99a5-445b-b0e8-40b6fa14dc5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608395769 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.3608395769
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2161194311
Short name T309
Test name
Test status
Simulation time 21474603887 ps
CPU time 80.98 seconds
Started Mar 31 01:01:55 PM PDT 24
Finished Mar 31 01:03:16 PM PDT 24
Peak memory 199576 kb
Host smart-df7f560e-2e45-4902-ab40-49e16ee09a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161194311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2161194311
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.714194944
Short name T109
Test name
Test status
Simulation time 67006067 ps
CPU time 0.59 seconds
Started Mar 31 01:02:05 PM PDT 24
Finished Mar 31 01:02:06 PM PDT 24
Peak memory 195140 kb
Host smart-de29de7a-6e36-40fb-b724-c922e34f61a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714194944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.714194944
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1890378461
Short name T501
Test name
Test status
Simulation time 1300020871 ps
CPU time 44.95 seconds
Started Mar 31 01:01:55 PM PDT 24
Finished Mar 31 01:02:41 PM PDT 24
Peak memory 232388 kb
Host smart-c73f6004-e3c2-459f-852f-bc02ce7768d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1890378461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1890378461
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.1056747231
Short name T266
Test name
Test status
Simulation time 2312075184 ps
CPU time 48.65 seconds
Started Mar 31 01:02:07 PM PDT 24
Finished Mar 31 01:02:56 PM PDT 24
Peak memory 199668 kb
Host smart-98657f22-541b-42d7-82fa-01b6330c18a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056747231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.1056747231
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3837575007
Short name T389
Test name
Test status
Simulation time 691442245 ps
CPU time 43.8 seconds
Started Mar 31 01:01:53 PM PDT 24
Finished Mar 31 01:02:37 PM PDT 24
Peak memory 199556 kb
Host smart-fcc71450-6b56-4607-880d-055f0b77cc96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3837575007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3837575007
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2550989576
Short name T475
Test name
Test status
Simulation time 42472705736 ps
CPU time 129.35 seconds
Started Mar 31 01:02:05 PM PDT 24
Finished Mar 31 01:04:15 PM PDT 24
Peak memory 199664 kb
Host smart-b370657e-d7bc-4162-9ad4-f26563594697
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550989576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2550989576
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2096517853
Short name T474
Test name
Test status
Simulation time 1725741567 ps
CPU time 101.52 seconds
Started Mar 31 01:01:52 PM PDT 24
Finished Mar 31 01:03:34 PM PDT 24
Peak memory 199628 kb
Host smart-3b13dc68-735d-428c-aaa4-61c651342438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096517853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2096517853
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2592871065
Short name T461
Test name
Test status
Simulation time 203178437 ps
CPU time 6.18 seconds
Started Mar 31 01:01:54 PM PDT 24
Finished Mar 31 01:02:01 PM PDT 24
Peak memory 199556 kb
Host smart-76612a50-0818-49cd-8f21-cdd151e7e963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592871065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2592871065
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.1983963734
Short name T25
Test name
Test status
Simulation time 2623676419 ps
CPU time 57.43 seconds
Started Mar 31 01:02:07 PM PDT 24
Finished Mar 31 01:03:05 PM PDT 24
Peak memory 199696 kb
Host smart-8a331892-5224-4038-93da-6d3d87ddc2aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983963734 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.1983963734
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.135126046
Short name T511
Test name
Test status
Simulation time 55296834 ps
CPU time 1.1 seconds
Started Mar 31 01:02:01 PM PDT 24
Finished Mar 31 01:02:03 PM PDT 24
Peak memory 198892 kb
Host smart-cf7748db-7a73-4773-afc5-67df3fd623d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135126046 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_hmac_vectors.135126046
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.3303700294
Short name T388
Test name
Test status
Simulation time 16730474899 ps
CPU time 491.43 seconds
Started Mar 31 01:01:59 PM PDT 24
Finished Mar 31 01:10:11 PM PDT 24
Peak memory 199640 kb
Host smart-16adf2f8-521e-4a37-93a4-f987131ca8af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303700294 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.3303700294
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1506321974
Short name T394
Test name
Test status
Simulation time 2131079305 ps
CPU time 33.98 seconds
Started Mar 31 01:02:01 PM PDT 24
Finished Mar 31 01:02:35 PM PDT 24
Peak memory 199648 kb
Host smart-8104c71a-a9dd-4dc3-bdf5-7dc029ee667e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506321974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1506321974
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2538216601
Short name T208
Test name
Test status
Simulation time 15038059 ps
CPU time 0.63 seconds
Started Mar 31 01:02:00 PM PDT 24
Finished Mar 31 01:02:01 PM PDT 24
Peak memory 195204 kb
Host smart-62195d6f-7a2b-493c-a5c7-c38a03a3c066
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538216601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2538216601
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3692650502
Short name T360
Test name
Test status
Simulation time 1302901284 ps
CPU time 23.3 seconds
Started Mar 31 01:02:07 PM PDT 24
Finished Mar 31 01:02:31 PM PDT 24
Peak memory 207796 kb
Host smart-4f354211-5f51-462e-9d21-fa29c56b3242
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3692650502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3692650502
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3170474328
Short name T469
Test name
Test status
Simulation time 8786007068 ps
CPU time 37.97 seconds
Started Mar 31 01:02:02 PM PDT 24
Finished Mar 31 01:02:41 PM PDT 24
Peak memory 199700 kb
Host smart-3dcd0ff8-62c6-4057-ba71-498a01a42bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170474328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3170474328
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3013275648
Short name T426
Test name
Test status
Simulation time 626666467 ps
CPU time 17.67 seconds
Started Mar 31 01:02:05 PM PDT 24
Finished Mar 31 01:02:24 PM PDT 24
Peak memory 199508 kb
Host smart-004136c0-b7de-4286-88ce-26a5f43064a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3013275648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3013275648
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1044213530
Short name T43
Test name
Test status
Simulation time 6500595086 ps
CPU time 87.95 seconds
Started Mar 31 01:02:01 PM PDT 24
Finished Mar 31 01:03:30 PM PDT 24
Peak memory 199728 kb
Host smart-c759fcf1-c0a6-451e-ad0b-5096c2de49b9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044213530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1044213530
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.3521331955
Short name T239
Test name
Test status
Simulation time 3842611845 ps
CPU time 17.49 seconds
Started Mar 31 01:01:59 PM PDT 24
Finished Mar 31 01:02:16 PM PDT 24
Peak memory 199724 kb
Host smart-5af8b8d4-477a-48d4-8103-95f0e8603b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521331955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3521331955
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3790707442
Short name T131
Test name
Test status
Simulation time 65409772 ps
CPU time 1.13 seconds
Started Mar 31 01:01:58 PM PDT 24
Finished Mar 31 01:02:00 PM PDT 24
Peak memory 199612 kb
Host smart-6208a212-5900-42d7-9068-a6c5fe20fbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790707442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3790707442
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.1063927289
Short name T31
Test name
Test status
Simulation time 1795792246769 ps
CPU time 1571.96 seconds
Started Mar 31 01:02:00 PM PDT 24
Finished Mar 31 01:28:12 PM PDT 24
Peak memory 227760 kb
Host smart-6bf78bee-07fe-4b96-8c5f-5c7d97fce3d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063927289 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.1063927289
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.3617386993
Short name T336
Test name
Test status
Simulation time 123033711 ps
CPU time 1.3 seconds
Started Mar 31 01:02:01 PM PDT 24
Finished Mar 31 01:02:03 PM PDT 24
Peak memory 199292 kb
Host smart-11622ee4-d152-43b3-bed4-01c29f833ab6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617386993 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.3617386993
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.3153496247
Short name T515
Test name
Test status
Simulation time 32363501995 ps
CPU time 580.29 seconds
Started Mar 31 01:02:01 PM PDT 24
Finished Mar 31 01:11:41 PM PDT 24
Peak memory 199664 kb
Host smart-506b7e7d-ac12-4cc6-af70-491374104537
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153496247 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.3153496247
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.611642821
Short name T61
Test name
Test status
Simulation time 983786609 ps
CPU time 18.92 seconds
Started Mar 31 01:02:03 PM PDT 24
Finished Mar 31 01:02:22 PM PDT 24
Peak memory 199652 kb
Host smart-78c096d0-73dc-419e-9cf9-af90cdd60733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611642821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.611642821
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.165129151
Short name T434
Test name
Test status
Simulation time 26763390 ps
CPU time 0.6 seconds
Started Mar 31 01:02:06 PM PDT 24
Finished Mar 31 01:02:07 PM PDT 24
Peak memory 195208 kb
Host smart-3ee679e3-7997-4c2b-ae3b-ecb5187cd6f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165129151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.165129151
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1845605924
Short name T532
Test name
Test status
Simulation time 1155386931 ps
CPU time 45.46 seconds
Started Mar 31 01:02:06 PM PDT 24
Finished Mar 31 01:02:52 PM PDT 24
Peak memory 225264 kb
Host smart-35a58489-1f76-4ed2-8e49-f36d730a1a91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1845605924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1845605924
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.1279706562
Short name T408
Test name
Test status
Simulation time 3676148178 ps
CPU time 45.39 seconds
Started Mar 31 01:02:07 PM PDT 24
Finished Mar 31 01:02:53 PM PDT 24
Peak memory 199740 kb
Host smart-62810b61-57b7-448b-a42d-6be92d782919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279706562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1279706562
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1077996243
Short name T343
Test name
Test status
Simulation time 2250800411 ps
CPU time 65.95 seconds
Started Mar 31 01:02:07 PM PDT 24
Finished Mar 31 01:03:14 PM PDT 24
Peak memory 199752 kb
Host smart-31e7c84f-8fbc-49c7-9b7d-94b4a6e97ff1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1077996243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1077996243
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.52375816
Short name T438
Test name
Test status
Simulation time 152936580 ps
CPU time 10.07 seconds
Started Mar 31 01:02:09 PM PDT 24
Finished Mar 31 01:02:19 PM PDT 24
Peak memory 199448 kb
Host smart-d509df0c-0e3c-4558-b51b-5eb6e8da3988
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52375816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.52375816
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.596838332
Short name T594
Test name
Test status
Simulation time 1289421268 ps
CPU time 76.42 seconds
Started Mar 31 01:02:06 PM PDT 24
Finished Mar 31 01:03:23 PM PDT 24
Peak memory 199680 kb
Host smart-5a88919d-8c09-40ee-b6f7-2686a45e62c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596838332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.596838332
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.1985799977
Short name T382
Test name
Test status
Simulation time 548833248 ps
CPU time 1.21 seconds
Started Mar 31 01:02:07 PM PDT 24
Finished Mar 31 01:02:08 PM PDT 24
Peak memory 199616 kb
Host smart-8b0e0b9d-7107-45fb-afb0-20ae9a75d8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985799977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1985799977
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2655948974
Short name T79
Test name
Test status
Simulation time 56042518337 ps
CPU time 433.78 seconds
Started Mar 31 01:02:08 PM PDT 24
Finished Mar 31 01:09:22 PM PDT 24
Peak memory 240668 kb
Host smart-fb930d78-eee8-4079-b5f1-6085fce6cf8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655948974 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2655948974
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.3549608211
Short name T338
Test name
Test status
Simulation time 261888202 ps
CPU time 1.41 seconds
Started Mar 31 01:02:07 PM PDT 24
Finished Mar 31 01:02:09 PM PDT 24
Peak memory 199660 kb
Host smart-41a751ea-7f40-4bbc-93a3-7b9dca33cc8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549608211 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.3549608211
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.36995365
Short name T171
Test name
Test status
Simulation time 7999642570 ps
CPU time 461.57 seconds
Started Mar 31 01:02:13 PM PDT 24
Finished Mar 31 01:09:54 PM PDT 24
Peak memory 199640 kb
Host smart-e1b97e13-14d2-4783-bda6-19b14c37022d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36995365 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.36995365
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1145691786
Short name T496
Test name
Test status
Simulation time 44180153510 ps
CPU time 64.87 seconds
Started Mar 31 01:02:07 PM PDT 24
Finished Mar 31 01:03:12 PM PDT 24
Peak memory 199716 kb
Host smart-b2ddc6d2-a9b1-4978-a539-8e5d0241b7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145691786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1145691786
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.111646736
Short name T112
Test name
Test status
Simulation time 12663091 ps
CPU time 0.6 seconds
Started Mar 31 01:00:41 PM PDT 24
Finished Mar 31 01:00:42 PM PDT 24
Peak memory 195172 kb
Host smart-fc6ee42b-5e0a-4628-869d-d7689d70c70a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111646736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.111646736
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3523256172
Short name T562
Test name
Test status
Simulation time 854383643 ps
CPU time 14.23 seconds
Started Mar 31 01:00:37 PM PDT 24
Finished Mar 31 01:00:52 PM PDT 24
Peak memory 216012 kb
Host smart-42b839d3-e2a7-4ce4-b722-e63c07273b07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3523256172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3523256172
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.4095956698
Short name T260
Test name
Test status
Simulation time 3322477733 ps
CPU time 10.78 seconds
Started Mar 31 01:00:33 PM PDT 24
Finished Mar 31 01:00:44 PM PDT 24
Peak memory 199636 kb
Host smart-afa4368b-f63a-4a28-a53a-b6e0c78ef8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095956698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.4095956698
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3917937095
Short name T331
Test name
Test status
Simulation time 1817885794 ps
CPU time 98.74 seconds
Started Mar 31 01:00:34 PM PDT 24
Finished Mar 31 01:02:13 PM PDT 24
Peak memory 199644 kb
Host smart-c8a63551-4da1-4efa-bc88-4b3656475cfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3917937095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3917937095
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.3499884087
Short name T490
Test name
Test status
Simulation time 1498442244 ps
CPU time 84.37 seconds
Started Mar 31 01:00:37 PM PDT 24
Finished Mar 31 01:02:02 PM PDT 24
Peak memory 199660 kb
Host smart-2344677c-f666-4524-9fbc-340f4c0c7c95
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499884087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.3499884087
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2014373895
Short name T476
Test name
Test status
Simulation time 6932771875 ps
CPU time 63.17 seconds
Started Mar 31 01:00:34 PM PDT 24
Finished Mar 31 01:01:37 PM PDT 24
Peak memory 199700 kb
Host smart-b4d58bdf-c21c-4d0d-b29c-d208223b2355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014373895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2014373895
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2751685590
Short name T35
Test name
Test status
Simulation time 66500803 ps
CPU time 0.92 seconds
Started Mar 31 01:00:40 PM PDT 24
Finished Mar 31 01:00:42 PM PDT 24
Peak memory 218116 kb
Host smart-6ed18f64-ce43-4002-9d9e-e912919c3453
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751685590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2751685590
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.1684212856
Short name T556
Test name
Test status
Simulation time 1062924351 ps
CPU time 4.92 seconds
Started Mar 31 01:00:37 PM PDT 24
Finished Mar 31 01:00:43 PM PDT 24
Peak memory 199656 kb
Host smart-ab066679-98ec-49f6-b879-63c68502ab25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684212856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1684212856
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1778490886
Short name T387
Test name
Test status
Simulation time 101156879834 ps
CPU time 1877.87 seconds
Started Mar 31 01:00:37 PM PDT 24
Finished Mar 31 01:31:56 PM PDT 24
Peak memory 207920 kb
Host smart-7301e43c-4765-4089-99ba-f44c394c96a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778490886 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1778490886
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.4157028261
Short name T406
Test name
Test status
Simulation time 140287615 ps
CPU time 1.34 seconds
Started Mar 31 01:00:36 PM PDT 24
Finished Mar 31 01:00:38 PM PDT 24
Peak memory 199580 kb
Host smart-74f60f9d-b511-4281-841f-db94760cab83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157028261 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.4157028261
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.2623819954
Short name T443
Test name
Test status
Simulation time 56192542605 ps
CPU time 499.92 seconds
Started Mar 31 01:00:32 PM PDT 24
Finished Mar 31 01:08:52 PM PDT 24
Peak memory 199636 kb
Host smart-f10c52d3-3841-4691-995a-9e8c4f935f5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623819954 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.2623819954
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.698488004
Short name T370
Test name
Test status
Simulation time 1509862579 ps
CPU time 62.55 seconds
Started Mar 31 01:00:37 PM PDT 24
Finished Mar 31 01:01:40 PM PDT 24
Peak memory 199656 kb
Host smart-5388ef20-2e1e-4713-9120-fb1acdeb9337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698488004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.698488004
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.4289135146
Short name T587
Test name
Test status
Simulation time 23040033 ps
CPU time 0.58 seconds
Started Mar 31 01:02:12 PM PDT 24
Finished Mar 31 01:02:13 PM PDT 24
Peak memory 194160 kb
Host smart-54359a92-a57e-490c-8ef3-984099469033
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289135146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.4289135146
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2151193065
Short name T181
Test name
Test status
Simulation time 689875723 ps
CPU time 25.69 seconds
Started Mar 31 01:02:08 PM PDT 24
Finished Mar 31 01:02:34 PM PDT 24
Peak memory 215680 kb
Host smart-7e48d134-c65c-41ed-af5d-fb8116b390c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2151193065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2151193065
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3378917786
Short name T590
Test name
Test status
Simulation time 428326620 ps
CPU time 21.92 seconds
Started Mar 31 01:02:12 PM PDT 24
Finished Mar 31 01:02:34 PM PDT 24
Peak memory 199584 kb
Host smart-95df3de4-223c-4bb4-bdc0-7922a5714603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378917786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3378917786
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.1885887726
Short name T147
Test name
Test status
Simulation time 2830682218 ps
CPU time 68.33 seconds
Started Mar 31 01:02:12 PM PDT 24
Finished Mar 31 01:03:20 PM PDT 24
Peak memory 199680 kb
Host smart-def307f4-025c-4601-af92-cb2f8d313b52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1885887726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1885887726
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1707357267
Short name T270
Test name
Test status
Simulation time 63131255391 ps
CPU time 185.64 seconds
Started Mar 31 01:02:12 PM PDT 24
Finished Mar 31 01:05:17 PM PDT 24
Peak memory 199680 kb
Host smart-3185dd06-aeb2-4335-8e2b-3f5e28ddb00f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707357267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1707357267
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3379791931
Short name T141
Test name
Test status
Simulation time 36451900546 ps
CPU time 114.88 seconds
Started Mar 31 01:02:09 PM PDT 24
Finished Mar 31 01:04:04 PM PDT 24
Peak memory 199564 kb
Host smart-e258ac62-51b2-4371-8355-54fb81042434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379791931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3379791931
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2968944371
Short name T240
Test name
Test status
Simulation time 233001925 ps
CPU time 1.5 seconds
Started Mar 31 01:02:11 PM PDT 24
Finished Mar 31 01:02:13 PM PDT 24
Peak memory 199636 kb
Host smart-406cec53-97a1-4edd-a2b9-f701e8a66a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968944371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2968944371
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.3724253059
Short name T465
Test name
Test status
Simulation time 33990110042 ps
CPU time 596.09 seconds
Started Mar 31 01:02:06 PM PDT 24
Finished Mar 31 01:12:03 PM PDT 24
Peak memory 199628 kb
Host smart-35e033b4-02b7-4a7c-8ea4-0ad694991c34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724253059 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.3724253059
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.1810619780
Short name T130
Test name
Test status
Simulation time 30637266 ps
CPU time 1.17 seconds
Started Mar 31 01:02:10 PM PDT 24
Finished Mar 31 01:02:11 PM PDT 24
Peak memory 199612 kb
Host smart-fca39ad0-375e-4322-acf3-3d43390f99b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810619780 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.1810619780
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.3552455177
Short name T248
Test name
Test status
Simulation time 81484363691 ps
CPU time 497.9 seconds
Started Mar 31 01:02:08 PM PDT 24
Finished Mar 31 01:10:26 PM PDT 24
Peak memory 199688 kb
Host smart-723af1a6-d1d1-449d-bea2-be13099d046c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552455177 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.3552455177
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.1802877333
Short name T541
Test name
Test status
Simulation time 8705166269 ps
CPU time 30.35 seconds
Started Mar 31 01:02:10 PM PDT 24
Finished Mar 31 01:02:41 PM PDT 24
Peak memory 199684 kb
Host smart-5a664a61-9a87-4aa0-bec3-24e03ac88b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802877333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.1802877333
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2073202063
Short name T508
Test name
Test status
Simulation time 11318214 ps
CPU time 0.59 seconds
Started Mar 31 01:02:13 PM PDT 24
Finished Mar 31 01:02:14 PM PDT 24
Peak memory 194160 kb
Host smart-57ec73d7-7b3c-4fe5-90ff-a5fe8d12511e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073202063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2073202063
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2927741544
Short name T449
Test name
Test status
Simulation time 799055366 ps
CPU time 35.78 seconds
Started Mar 31 01:02:14 PM PDT 24
Finished Mar 31 01:02:50 PM PDT 24
Peak memory 232496 kb
Host smart-aa6ce76c-9b95-44d7-91af-db4d9187e5ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2927741544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2927741544
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1037661261
Short name T557
Test name
Test status
Simulation time 2262218409 ps
CPU time 33.45 seconds
Started Mar 31 01:02:14 PM PDT 24
Finished Mar 31 01:02:48 PM PDT 24
Peak memory 199720 kb
Host smart-4dbe32ed-1cc0-4ba2-8e1b-f5961a8ea0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037661261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1037661261
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2219136613
Short name T458
Test name
Test status
Simulation time 1631297614 ps
CPU time 98.92 seconds
Started Mar 31 01:02:13 PM PDT 24
Finished Mar 31 01:03:52 PM PDT 24
Peak memory 199592 kb
Host smart-2fccd2fb-bb8b-4db9-9dc1-de382100a0db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2219136613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2219136613
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3049476882
Short name T121
Test name
Test status
Simulation time 1703394974 ps
CPU time 31.21 seconds
Started Mar 31 01:02:13 PM PDT 24
Finished Mar 31 01:02:44 PM PDT 24
Peak memory 199684 kb
Host smart-43585a32-39c5-4976-b076-f1f05c92a067
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049476882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3049476882
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.245837085
Short name T202
Test name
Test status
Simulation time 4486006571 ps
CPU time 14.3 seconds
Started Mar 31 01:02:14 PM PDT 24
Finished Mar 31 01:02:28 PM PDT 24
Peak memory 199736 kb
Host smart-8a980f22-563d-409b-897e-0434d56696a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245837085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.245837085
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2670336803
Short name T128
Test name
Test status
Simulation time 552275555 ps
CPU time 6.71 seconds
Started Mar 31 01:02:15 PM PDT 24
Finished Mar 31 01:02:22 PM PDT 24
Peak memory 199620 kb
Host smart-aa0d48a0-65cf-4ad9-9e74-ea899c377ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670336803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2670336803
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.465739113
Short name T80
Test name
Test status
Simulation time 176011603992 ps
CPU time 632.78 seconds
Started Mar 31 01:02:14 PM PDT 24
Finished Mar 31 01:12:47 PM PDT 24
Peak memory 216004 kb
Host smart-fd230ae7-bb16-4df7-adf9-6d795d7bd5a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465739113 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.465739113
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.619033686
Short name T329
Test name
Test status
Simulation time 307675056 ps
CPU time 1.4 seconds
Started Mar 31 01:02:14 PM PDT 24
Finished Mar 31 01:02:16 PM PDT 24
Peak memory 199668 kb
Host smart-84a1e66f-9be0-4f12-b6a7-9f5e081815a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619033686 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_hmac_vectors.619033686
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.2190926324
Short name T571
Test name
Test status
Simulation time 25137701026 ps
CPU time 426.5 seconds
Started Mar 31 01:02:13 PM PDT 24
Finished Mar 31 01:09:20 PM PDT 24
Peak memory 199636 kb
Host smart-b53f7316-32f9-4bc6-8398-e755ea285a01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190926324 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.2190926324
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.614626675
Short name T463
Test name
Test status
Simulation time 26585854754 ps
CPU time 92.15 seconds
Started Mar 31 01:02:14 PM PDT 24
Finished Mar 31 01:03:46 PM PDT 24
Peak memory 199692 kb
Host smart-0e414a60-5a96-495c-9816-15f36daba39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614626675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.614626675
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.4012163774
Short name T550
Test name
Test status
Simulation time 14536979 ps
CPU time 0.59 seconds
Started Mar 31 01:02:22 PM PDT 24
Finished Mar 31 01:02:23 PM PDT 24
Peak memory 195184 kb
Host smart-9388cc0e-118d-49a6-b8d2-b949103382b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012163774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.4012163774
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.761513579
Short name T385
Test name
Test status
Simulation time 659697085 ps
CPU time 4.8 seconds
Started Mar 31 01:02:14 PM PDT 24
Finished Mar 31 01:02:19 PM PDT 24
Peak memory 199604 kb
Host smart-99602b58-e1fc-4866-a729-0579cc89da4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=761513579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.761513579
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.2133565918
Short name T526
Test name
Test status
Simulation time 6462395861 ps
CPU time 25.97 seconds
Started Mar 31 01:02:13 PM PDT 24
Finished Mar 31 01:02:39 PM PDT 24
Peak memory 199688 kb
Host smart-3daf1f9c-d2bb-45fa-8b0a-b4d41dca056e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133565918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2133565918
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3465218258
Short name T182
Test name
Test status
Simulation time 1100361033 ps
CPU time 27.59 seconds
Started Mar 31 01:02:16 PM PDT 24
Finished Mar 31 01:02:44 PM PDT 24
Peak memory 199612 kb
Host smart-51db69cc-48a5-4577-834a-20c804acf3b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3465218258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3465218258
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.2306762240
Short name T195
Test name
Test status
Simulation time 23185636862 ps
CPU time 145.57 seconds
Started Mar 31 01:02:14 PM PDT 24
Finished Mar 31 01:04:39 PM PDT 24
Peak memory 199732 kb
Host smart-33f3029f-a2ad-4d79-80ef-65a93dbd3b07
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306762240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2306762240
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.1067572376
Short name T291
Test name
Test status
Simulation time 9886255147 ps
CPU time 47.06 seconds
Started Mar 31 01:02:13 PM PDT 24
Finished Mar 31 01:03:00 PM PDT 24
Peak memory 199636 kb
Host smart-821cc697-bbd7-4400-8e17-52ebdda0f1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067572376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1067572376
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.775982860
Short name T539
Test name
Test status
Simulation time 517808900 ps
CPU time 4.15 seconds
Started Mar 31 01:02:13 PM PDT 24
Finished Mar 31 01:02:18 PM PDT 24
Peak memory 199644 kb
Host smart-de65bd4d-b3d8-4add-8ce4-1467acd88414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775982860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.775982860
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.2071422731
Short name T574
Test name
Test status
Simulation time 57238263724 ps
CPU time 770.29 seconds
Started Mar 31 01:02:13 PM PDT 24
Finished Mar 31 01:15:04 PM PDT 24
Peak memory 215392 kb
Host smart-61e764a4-7c85-4ed2-b882-8fab04417558
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071422731 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2071422731
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.1755489025
Short name T7
Test name
Test status
Simulation time 225001091 ps
CPU time 1.03 seconds
Started Mar 31 01:02:13 PM PDT 24
Finished Mar 31 01:02:14 PM PDT 24
Peak memory 198916 kb
Host smart-4f3ab692-5d68-4953-8aee-9a4fbc8164e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755489025 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.1755489025
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.3232366848
Short name T489
Test name
Test status
Simulation time 126643814968 ps
CPU time 424.6 seconds
Started Mar 31 01:02:14 PM PDT 24
Finished Mar 31 01:09:18 PM PDT 24
Peak memory 199636 kb
Host smart-8f0d9e36-597d-4660-a4a3-becc6a4cb908
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232366848 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.3232366848
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1935880408
Short name T74
Test name
Test status
Simulation time 1221621446 ps
CPU time 9.79 seconds
Started Mar 31 01:02:16 PM PDT 24
Finished Mar 31 01:02:26 PM PDT 24
Peak memory 199616 kb
Host smart-58fc1fdc-1d84-4600-98e8-d824716dc6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935880408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1935880408
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.4007331674
Short name T189
Test name
Test status
Simulation time 12943479 ps
CPU time 0.6 seconds
Started Mar 31 01:02:21 PM PDT 24
Finished Mar 31 01:02:21 PM PDT 24
Peak memory 195172 kb
Host smart-6bb838bc-9193-4f12-894c-6616f67ccdb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007331674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.4007331674
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.72870189
Short name T179
Test name
Test status
Simulation time 1287068598 ps
CPU time 24.37 seconds
Started Mar 31 01:02:20 PM PDT 24
Finished Mar 31 01:02:45 PM PDT 24
Peak memory 207888 kb
Host smart-c9ad3fa7-4315-4c09-ab81-e1d065847800
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=72870189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.72870189
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.4272869942
Short name T552
Test name
Test status
Simulation time 1037009744 ps
CPU time 55.8 seconds
Started Mar 31 01:02:22 PM PDT 24
Finished Mar 31 01:03:18 PM PDT 24
Peak memory 199580 kb
Host smart-cf701728-3fec-4b34-889c-1f231f137d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272869942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.4272869942
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1812010354
Short name T198
Test name
Test status
Simulation time 9102554595 ps
CPU time 135.83 seconds
Started Mar 31 01:02:21 PM PDT 24
Finished Mar 31 01:04:37 PM PDT 24
Peak memory 199676 kb
Host smart-0ceb8fce-e130-4d40-ac7c-5191fd9ac9b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1812010354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1812010354
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.696879358
Short name T48
Test name
Test status
Simulation time 16343725780 ps
CPU time 167.86 seconds
Started Mar 31 01:02:23 PM PDT 24
Finished Mar 31 01:05:11 PM PDT 24
Peak memory 199612 kb
Host smart-5aa4aea7-fcfc-4f50-86ba-ec874f581234
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696879358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.696879358
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.1957767124
Short name T572
Test name
Test status
Simulation time 1394691656 ps
CPU time 78.06 seconds
Started Mar 31 01:02:22 PM PDT 24
Finished Mar 31 01:03:40 PM PDT 24
Peak memory 199680 kb
Host smart-182c5433-2482-468e-9932-2a0b7e37450f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957767124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1957767124
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.349632728
Short name T317
Test name
Test status
Simulation time 65379196 ps
CPU time 1.31 seconds
Started Mar 31 01:02:19 PM PDT 24
Finished Mar 31 01:02:20 PM PDT 24
Peak memory 199536 kb
Host smart-04d33301-a8ac-4729-bb21-8619529637a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349632728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.349632728
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.425394172
Short name T298
Test name
Test status
Simulation time 54365927072 ps
CPU time 850.66 seconds
Started Mar 31 01:02:22 PM PDT 24
Finished Mar 31 01:16:32 PM PDT 24
Peak memory 199708 kb
Host smart-d066793a-955e-4b5f-ba61-2bb87a780944
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425394172 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.425394172
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.1110900081
Short name T264
Test name
Test status
Simulation time 176598765 ps
CPU time 1.25 seconds
Started Mar 31 01:02:23 PM PDT 24
Finished Mar 31 01:02:24 PM PDT 24
Peak memory 199564 kb
Host smart-54df8f1b-bd49-4feb-97b3-20335ccf3272
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110900081 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.1110900081
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.2009662322
Short name T172
Test name
Test status
Simulation time 7755321099 ps
CPU time 432.7 seconds
Started Mar 31 01:02:19 PM PDT 24
Finished Mar 31 01:09:32 PM PDT 24
Peak memory 199708 kb
Host smart-d27c2066-1dcb-4c39-8f1d-24001be4aba0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009662322 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.2009662322
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.3517288675
Short name T327
Test name
Test status
Simulation time 1528297505 ps
CPU time 22 seconds
Started Mar 31 01:02:19 PM PDT 24
Finished Mar 31 01:02:41 PM PDT 24
Peak memory 199656 kb
Host smart-c3849965-2b00-40ee-85f5-5507f7c717f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517288675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3517288675
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.1181904334
Short name T2
Test name
Test status
Simulation time 42374447 ps
CPU time 0.6 seconds
Started Mar 31 01:02:26 PM PDT 24
Finished Mar 31 01:02:28 PM PDT 24
Peak memory 195156 kb
Host smart-8bffde6d-7354-49bf-a94b-2a5b53fc67b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181904334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1181904334
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.4066569302
Short name T548
Test name
Test status
Simulation time 4253054407 ps
CPU time 39.15 seconds
Started Mar 31 01:02:20 PM PDT 24
Finished Mar 31 01:03:00 PM PDT 24
Peak memory 215584 kb
Host smart-4816f935-dea2-417d-8016-0e28e0d5223a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4066569302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.4066569302
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2087105406
Short name T453
Test name
Test status
Simulation time 2560283512 ps
CPU time 31.42 seconds
Started Mar 31 01:02:20 PM PDT 24
Finished Mar 31 01:02:52 PM PDT 24
Peak memory 199736 kb
Host smart-d6c5e48b-c27f-4d92-884c-77a6ee41e940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087105406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2087105406
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.4178867391
Short name T111
Test name
Test status
Simulation time 2076464476 ps
CPU time 116.92 seconds
Started Mar 31 01:02:24 PM PDT 24
Finished Mar 31 01:04:21 PM PDT 24
Peak memory 199608 kb
Host smart-4ebb8b7f-d418-4b60-a719-a69c631686ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4178867391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.4178867391
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.19315374
Short name T280
Test name
Test status
Simulation time 454891768 ps
CPU time 4.85 seconds
Started Mar 31 01:02:24 PM PDT 24
Finished Mar 31 01:02:29 PM PDT 24
Peak memory 199564 kb
Host smart-f28a7896-8da2-467d-baa4-b407a99c9c1a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19315374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.19315374
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3514802716
Short name T176
Test name
Test status
Simulation time 1107106699 ps
CPU time 63.18 seconds
Started Mar 31 01:02:21 PM PDT 24
Finished Mar 31 01:03:24 PM PDT 24
Peak memory 199600 kb
Host smart-abf00844-2edd-4b2c-8ee3-07ba738df08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514802716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3514802716
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2340120349
Short name T361
Test name
Test status
Simulation time 146855037 ps
CPU time 2.2 seconds
Started Mar 31 01:02:23 PM PDT 24
Finished Mar 31 01:02:25 PM PDT 24
Peak memory 199640 kb
Host smart-756f6b91-7efe-4836-826b-686e44ea272d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340120349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2340120349
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.1289421253
Short name T229
Test name
Test status
Simulation time 287190362061 ps
CPU time 1284.23 seconds
Started Mar 31 01:02:28 PM PDT 24
Finished Mar 31 01:23:52 PM PDT 24
Peak memory 199748 kb
Host smart-e85b4915-6c86-413c-a54c-7e996876445d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289421253 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1289421253
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.2640227579
Short name T113
Test name
Test status
Simulation time 80887618 ps
CPU time 1.38 seconds
Started Mar 31 01:02:28 PM PDT 24
Finished Mar 31 01:02:30 PM PDT 24
Peak memory 199288 kb
Host smart-a4445e73-a409-4805-99be-513b6d4a3d5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640227579 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.2640227579
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.3085624378
Short name T547
Test name
Test status
Simulation time 201546923006 ps
CPU time 544.95 seconds
Started Mar 31 01:02:26 PM PDT 24
Finished Mar 31 01:11:31 PM PDT 24
Peak memory 199680 kb
Host smart-73e54e71-dbf7-4b03-bc01-83e385192b05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085624378 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.3085624378
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.3314793882
Short name T433
Test name
Test status
Simulation time 9161487105 ps
CPU time 34.01 seconds
Started Mar 31 01:02:26 PM PDT 24
Finished Mar 31 01:03:00 PM PDT 24
Peak memory 199640 kb
Host smart-79eb81ea-5635-4cf5-a44a-90ea7105f498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314793882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3314793882
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.420144782
Short name T22
Test name
Test status
Simulation time 15801302 ps
CPU time 0.6 seconds
Started Mar 31 01:02:28 PM PDT 24
Finished Mar 31 01:02:28 PM PDT 24
Peak memory 195164 kb
Host smart-9f8dc847-5788-4a5e-949a-8b3af77dd326
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420144782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.420144782
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1826459385
Short name T397
Test name
Test status
Simulation time 1397592619 ps
CPU time 5.39 seconds
Started Mar 31 01:02:29 PM PDT 24
Finished Mar 31 01:02:35 PM PDT 24
Peak memory 199536 kb
Host smart-a444ee12-6279-4971-aca3-cdfda246f087
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1826459385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1826459385
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2477195949
Short name T180
Test name
Test status
Simulation time 522840803 ps
CPU time 13.46 seconds
Started Mar 31 01:02:28 PM PDT 24
Finished Mar 31 01:02:42 PM PDT 24
Peak memory 199660 kb
Host smart-45ff83b2-1926-4931-b6ea-7e0fda7f0d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477195949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2477195949
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.956912717
Short name T337
Test name
Test status
Simulation time 5135805133 ps
CPU time 54.99 seconds
Started Mar 31 01:02:28 PM PDT 24
Finished Mar 31 01:03:24 PM PDT 24
Peak memory 199548 kb
Host smart-197c25be-11d2-480a-8e77-6e3eb1f70c65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=956912717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.956912717
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.1157560635
Short name T422
Test name
Test status
Simulation time 3553903848 ps
CPU time 180.97 seconds
Started Mar 31 01:02:28 PM PDT 24
Finished Mar 31 01:05:29 PM PDT 24
Peak memory 199856 kb
Host smart-6697ad0f-5171-438b-904b-93e377652c84
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157560635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1157560635
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3036469485
Short name T432
Test name
Test status
Simulation time 972922882 ps
CPU time 54.21 seconds
Started Mar 31 01:02:28 PM PDT 24
Finished Mar 31 01:03:23 PM PDT 24
Peak memory 199816 kb
Host smart-62871c4a-7ff6-4ea9-ba38-7c739dde6fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036469485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3036469485
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.200498950
Short name T165
Test name
Test status
Simulation time 227053412 ps
CPU time 2.9 seconds
Started Mar 31 01:02:26 PM PDT 24
Finished Mar 31 01:02:30 PM PDT 24
Peak memory 199528 kb
Host smart-dcf30ac4-1838-4299-8c85-9f57c30254f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200498950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.200498950
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.1972479178
Short name T554
Test name
Test status
Simulation time 391069689705 ps
CPU time 703.29 seconds
Started Mar 31 01:02:27 PM PDT 24
Finished Mar 31 01:14:10 PM PDT 24
Peak memory 232480 kb
Host smart-e7dc4930-8913-4294-8141-7a605d0cfe59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972479178 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1972479178
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.754921881
Short name T160
Test name
Test status
Simulation time 30883348 ps
CPU time 1.18 seconds
Started Mar 31 01:02:28 PM PDT 24
Finished Mar 31 01:02:30 PM PDT 24
Peak memory 199704 kb
Host smart-39a98c96-4c0d-45ed-966a-7ad7cd1e7124
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754921881 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_hmac_vectors.754921881
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.2597380750
Short name T419
Test name
Test status
Simulation time 8142426482 ps
CPU time 460.5 seconds
Started Mar 31 01:02:27 PM PDT 24
Finished Mar 31 01:10:08 PM PDT 24
Peak memory 199704 kb
Host smart-30a63a17-28b7-461a-bcde-24838467be8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597380750 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.2597380750
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.4017874365
Short name T297
Test name
Test status
Simulation time 10279375142 ps
CPU time 68.05 seconds
Started Mar 31 01:02:27 PM PDT 24
Finished Mar 31 01:03:36 PM PDT 24
Peak memory 199684 kb
Host smart-f5a8a8a2-648f-48d9-b297-6064968c79a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017874365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.4017874365
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2056726466
Short name T549
Test name
Test status
Simulation time 14664249 ps
CPU time 0.58 seconds
Started Mar 31 01:02:32 PM PDT 24
Finished Mar 31 01:02:34 PM PDT 24
Peak memory 194900 kb
Host smart-6d843dd0-526b-4807-9306-84917cb09f6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056726466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2056726466
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.2066890671
Short name T231
Test name
Test status
Simulation time 4227435861 ps
CPU time 41.73 seconds
Started Mar 31 01:02:29 PM PDT 24
Finished Mar 31 01:03:11 PM PDT 24
Peak memory 225340 kb
Host smart-d015732f-8b57-4ff2-8f14-f73ae1b7a6b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2066890671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2066890671
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.128355638
Short name T563
Test name
Test status
Simulation time 1307638457 ps
CPU time 19.78 seconds
Started Mar 31 01:02:28 PM PDT 24
Finished Mar 31 01:02:48 PM PDT 24
Peak memory 199624 kb
Host smart-0a2ed9ff-79cc-46e9-808f-88ed64d340b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128355638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.128355638
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1010200417
Short name T161
Test name
Test status
Simulation time 989692359 ps
CPU time 23.29 seconds
Started Mar 31 01:02:28 PM PDT 24
Finished Mar 31 01:02:52 PM PDT 24
Peak memory 199544 kb
Host smart-28d9d8fa-2877-474d-9fdc-8334f99f942c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1010200417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1010200417
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1547796383
Short name T540
Test name
Test status
Simulation time 8882165482 ps
CPU time 79.02 seconds
Started Mar 31 01:02:32 PM PDT 24
Finished Mar 31 01:03:53 PM PDT 24
Peak memory 199724 kb
Host smart-65167424-34a4-4992-ac8c-6dcc035d6c69
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547796383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1547796383
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3006556415
Short name T589
Test name
Test status
Simulation time 20709568182 ps
CPU time 84.97 seconds
Started Mar 31 01:02:27 PM PDT 24
Finished Mar 31 01:03:53 PM PDT 24
Peak memory 199720 kb
Host smart-9e224c70-41ff-43ad-be18-66b434b22f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006556415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3006556415
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.1317194183
Short name T425
Test name
Test status
Simulation time 673365396 ps
CPU time 2.76 seconds
Started Mar 31 01:02:28 PM PDT 24
Finished Mar 31 01:02:31 PM PDT 24
Peak memory 199780 kb
Host smart-3515ad42-ac32-4721-a959-1e9563e11348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317194183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1317194183
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.2808016388
Short name T502
Test name
Test status
Simulation time 19400080714 ps
CPU time 136.97 seconds
Started Mar 31 01:02:45 PM PDT 24
Finished Mar 31 01:05:02 PM PDT 24
Peak memory 199636 kb
Host smart-9a6d3b2d-45e8-48ad-8cfc-c6b4f70424e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808016388 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2808016388
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.544668241
Short name T446
Test name
Test status
Simulation time 103841823 ps
CPU time 1.21 seconds
Started Mar 31 01:02:31 PM PDT 24
Finished Mar 31 01:02:33 PM PDT 24
Peak memory 199676 kb
Host smart-5f63334c-222a-4562-8bf2-4c4a5d1a9b7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544668241 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.hmac_test_hmac_vectors.544668241
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.108580732
Short name T153
Test name
Test status
Simulation time 8245083977 ps
CPU time 464.32 seconds
Started Mar 31 01:02:31 PM PDT 24
Finished Mar 31 01:10:16 PM PDT 24
Peak memory 199584 kb
Host smart-ebb67def-160b-47e2-90fe-495ef1cfbe51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108580732 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.108580732
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.4110401171
Short name T220
Test name
Test status
Simulation time 17268301445 ps
CPU time 47.27 seconds
Started Mar 31 01:02:33 PM PDT 24
Finished Mar 31 01:03:21 PM PDT 24
Peak memory 199728 kb
Host smart-ffd8830d-6ddf-477a-88a9-c035021813cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110401171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.4110401171
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.4253828644
Short name T359
Test name
Test status
Simulation time 18433659 ps
CPU time 0.61 seconds
Started Mar 31 01:02:44 PM PDT 24
Finished Mar 31 01:02:44 PM PDT 24
Peak memory 194864 kb
Host smart-91f2c475-28f0-49a2-932b-56c68ff2ea59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253828644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.4253828644
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1046447255
Short name T201
Test name
Test status
Simulation time 1497982729 ps
CPU time 12.29 seconds
Started Mar 31 01:02:32 PM PDT 24
Finished Mar 31 01:02:45 PM PDT 24
Peak memory 215336 kb
Host smart-1215aed1-71cf-4c10-9e9b-c8594a9e7d83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1046447255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1046447255
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.314236492
Short name T75
Test name
Test status
Simulation time 2392262585 ps
CPU time 35.93 seconds
Started Mar 31 01:02:33 PM PDT 24
Finished Mar 31 01:03:10 PM PDT 24
Peak memory 199724 kb
Host smart-faf56666-ed0d-4f8f-b18e-b84078c98dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314236492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.314236492
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.103641882
Short name T157
Test name
Test status
Simulation time 2602814392 ps
CPU time 159.52 seconds
Started Mar 31 01:02:32 PM PDT 24
Finished Mar 31 01:05:13 PM PDT 24
Peak memory 199696 kb
Host smart-57a53033-d788-4d16-bb22-1b42030c4612
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=103641882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.103641882
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3786791730
Short name T455
Test name
Test status
Simulation time 17286649237 ps
CPU time 245.58 seconds
Started Mar 31 01:02:35 PM PDT 24
Finished Mar 31 01:06:41 PM PDT 24
Peak memory 199736 kb
Host smart-a85bc9a2-c7b6-43f2-984a-a1820519bcf2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786791730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3786791730
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3012369955
Short name T566
Test name
Test status
Simulation time 2019542358 ps
CPU time 61.43 seconds
Started Mar 31 01:02:45 PM PDT 24
Finished Mar 31 01:03:46 PM PDT 24
Peak memory 199576 kb
Host smart-f83de606-6b95-4c6c-99b7-502fd4b43da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012369955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3012369955
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2952794644
Short name T436
Test name
Test status
Simulation time 174156388 ps
CPU time 5.39 seconds
Started Mar 31 01:02:37 PM PDT 24
Finished Mar 31 01:02:42 PM PDT 24
Peak memory 199592 kb
Host smart-cea06423-c3ad-4e7a-b122-d60290f5283d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952794644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2952794644
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2283378942
Short name T355
Test name
Test status
Simulation time 771020048195 ps
CPU time 1919.82 seconds
Started Mar 31 01:02:39 PM PDT 24
Finished Mar 31 01:34:39 PM PDT 24
Peak memory 224316 kb
Host smart-5df50e2c-316a-4de5-a255-9fa56fdc8da3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283378942 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2283378942
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.197468810
Short name T284
Test name
Test status
Simulation time 355090066 ps
CPU time 1.16 seconds
Started Mar 31 01:02:38 PM PDT 24
Finished Mar 31 01:02:40 PM PDT 24
Peak memory 199136 kb
Host smart-b00a32db-9532-4b64-9c3e-93e8a1d98134
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197468810 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_hmac_vectors.197468810
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.3748435503
Short name T342
Test name
Test status
Simulation time 27272473252 ps
CPU time 389.02 seconds
Started Mar 31 01:02:33 PM PDT 24
Finished Mar 31 01:09:02 PM PDT 24
Peak memory 199676 kb
Host smart-d546e5a2-3b9a-4bbf-a247-4444cd3cf943
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748435503 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.3748435503
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3710249950
Short name T506
Test name
Test status
Simulation time 1738754494 ps
CPU time 67.79 seconds
Started Mar 31 01:02:33 PM PDT 24
Finished Mar 31 01:03:41 PM PDT 24
Peak memory 199640 kb
Host smart-7120826f-0d5e-4900-8278-3ffcbdd44e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710249950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3710249950
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.2138090937
Short name T254
Test name
Test status
Simulation time 62920457 ps
CPU time 0.59 seconds
Started Mar 31 01:02:40 PM PDT 24
Finished Mar 31 01:02:41 PM PDT 24
Peak memory 195212 kb
Host smart-1a8ecbde-2d26-4b22-b25f-b6e9821f8b80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138090937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.2138090937
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.429765383
Short name T40
Test name
Test status
Simulation time 2480775957 ps
CPU time 22.95 seconds
Started Mar 31 01:02:39 PM PDT 24
Finished Mar 31 01:03:03 PM PDT 24
Peak memory 207908 kb
Host smart-fcd05844-0f5c-4ec5-a8cb-2e30039f92c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=429765383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.429765383
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.470865703
Short name T285
Test name
Test status
Simulation time 1800049850 ps
CPU time 9.63 seconds
Started Mar 31 01:02:39 PM PDT 24
Finished Mar 31 01:02:49 PM PDT 24
Peak memory 199696 kb
Host smart-311be0b8-3d5a-479b-a185-d19ed161ac9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470865703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.470865703
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2055218922
Short name T125
Test name
Test status
Simulation time 7632930804 ps
CPU time 100.05 seconds
Started Mar 31 01:02:42 PM PDT 24
Finished Mar 31 01:04:22 PM PDT 24
Peak memory 199700 kb
Host smart-ff8c30be-9f06-4ed6-a55e-1b2c2a5acabd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2055218922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2055218922
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2305817917
Short name T380
Test name
Test status
Simulation time 6206548063 ps
CPU time 90.95 seconds
Started Mar 31 01:02:39 PM PDT 24
Finished Mar 31 01:04:10 PM PDT 24
Peak memory 199700 kb
Host smart-75727bdc-f285-4b64-b3f4-4f4a520d5996
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305817917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2305817917
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3599980444
Short name T534
Test name
Test status
Simulation time 1505187809 ps
CPU time 20.67 seconds
Started Mar 31 01:02:39 PM PDT 24
Finished Mar 31 01:03:00 PM PDT 24
Peak memory 199620 kb
Host smart-c23531af-6121-4f07-a99a-ad93276168bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599980444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3599980444
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1595569500
Short name T409
Test name
Test status
Simulation time 392641074 ps
CPU time 3.81 seconds
Started Mar 31 01:02:43 PM PDT 24
Finished Mar 31 01:02:47 PM PDT 24
Peak memory 199636 kb
Host smart-e1bc7ac7-8846-48f2-9eaf-3eb6c037c772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595569500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1595569500
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.3517755949
Short name T486
Test name
Test status
Simulation time 143071327495 ps
CPU time 497.75 seconds
Started Mar 31 01:02:38 PM PDT 24
Finished Mar 31 01:10:56 PM PDT 24
Peak memory 225500 kb
Host smart-6c53c1d3-d5f0-4948-baaa-4f3f5957a410
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517755949 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3517755949
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.1091223087
Short name T492
Test name
Test status
Simulation time 152830617 ps
CPU time 1.04 seconds
Started Mar 31 01:02:39 PM PDT 24
Finished Mar 31 01:02:41 PM PDT 24
Peak memory 199084 kb
Host smart-ff01aae5-3321-4e40-942f-bc93f9c75c2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091223087 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.1091223087
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.1374852490
Short name T24
Test name
Test status
Simulation time 465106029456 ps
CPU time 492.13 seconds
Started Mar 31 01:02:42 PM PDT 24
Finished Mar 31 01:10:55 PM PDT 24
Peak memory 199648 kb
Host smart-ac192408-8076-4dd1-b872-7dd97fd52fb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374852490 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.1374852490
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.328654287
Short name T137
Test name
Test status
Simulation time 3873479926 ps
CPU time 44.51 seconds
Started Mar 31 01:02:39 PM PDT 24
Finished Mar 31 01:03:24 PM PDT 24
Peak memory 199732 kb
Host smart-42a72b70-fd9d-4c22-9972-b25bc2e0be92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328654287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.328654287
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2968561154
Short name T232
Test name
Test status
Simulation time 102918092 ps
CPU time 0.6 seconds
Started Mar 31 01:02:44 PM PDT 24
Finished Mar 31 01:02:45 PM PDT 24
Peak memory 195196 kb
Host smart-40bc6ff9-4166-430c-9f61-52ee8bcbc187
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968561154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2968561154
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.2321936801
Short name T228
Test name
Test status
Simulation time 161398866 ps
CPU time 2.23 seconds
Started Mar 31 01:02:45 PM PDT 24
Finished Mar 31 01:02:48 PM PDT 24
Peak memory 199652 kb
Host smart-2d03a081-332d-4945-88f1-9d875481d40f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2321936801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.2321936801
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.272128305
Short name T84
Test name
Test status
Simulation time 1784992439 ps
CPU time 24.44 seconds
Started Mar 31 01:02:45 PM PDT 24
Finished Mar 31 01:03:10 PM PDT 24
Peak memory 199628 kb
Host smart-ac3fae0c-0732-45ed-a869-0cbfd1eadc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272128305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.272128305
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3411509348
Short name T115
Test name
Test status
Simulation time 6732589364 ps
CPU time 92.84 seconds
Started Mar 31 01:02:44 PM PDT 24
Finished Mar 31 01:04:17 PM PDT 24
Peak memory 199720 kb
Host smart-28b9dc5b-711f-4b4a-a1ab-1682bc64e048
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3411509348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3411509348
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1892572067
Short name T424
Test name
Test status
Simulation time 3402501094 ps
CPU time 188.21 seconds
Started Mar 31 01:02:45 PM PDT 24
Finished Mar 31 01:05:53 PM PDT 24
Peak memory 199756 kb
Host smart-4c9f4ec0-8b7e-485e-b581-06eae51eec01
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892572067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1892572067
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3415595592
Short name T404
Test name
Test status
Simulation time 1045395517 ps
CPU time 15.59 seconds
Started Mar 31 01:02:43 PM PDT 24
Finished Mar 31 01:02:59 PM PDT 24
Peak memory 199632 kb
Host smart-7bbd81f5-8c8b-43eb-ace6-467aac3d3ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415595592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3415595592
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2723289270
Short name T509
Test name
Test status
Simulation time 488423620 ps
CPU time 7.32 seconds
Started Mar 31 01:02:39 PM PDT 24
Finished Mar 31 01:02:47 PM PDT 24
Peak memory 199612 kb
Host smart-bb24add2-d1cc-43fd-be50-929e3ef421ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723289270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2723289270
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.152670859
Short name T514
Test name
Test status
Simulation time 38798403213 ps
CPU time 577.29 seconds
Started Mar 31 01:02:46 PM PDT 24
Finished Mar 31 01:12:24 PM PDT 24
Peak memory 232356 kb
Host smart-17de97f5-1432-4a2f-8a83-98e52f1cbbe7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152670859 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.152670859
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.1750268068
Short name T531
Test name
Test status
Simulation time 76683868 ps
CPU time 1.37 seconds
Started Mar 31 01:02:45 PM PDT 24
Finished Mar 31 01:02:46 PM PDT 24
Peak memory 199624 kb
Host smart-65c8edb6-5dcf-4549-9010-934415e39a1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750268068 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.1750268068
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.557909010
Short name T122
Test name
Test status
Simulation time 32203140508 ps
CPU time 459.14 seconds
Started Mar 31 01:02:45 PM PDT 24
Finished Mar 31 01:10:24 PM PDT 24
Peak memory 199660 kb
Host smart-40b480cb-43fe-48c1-b15d-d498008cdbdd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557909010 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.557909010
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.1073460444
Short name T372
Test name
Test status
Simulation time 8351824582 ps
CPU time 86.39 seconds
Started Mar 31 01:02:45 PM PDT 24
Finished Mar 31 01:04:11 PM PDT 24
Peak memory 199696 kb
Host smart-367fbb9d-415d-4f7e-9b8b-7af11efa0515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073460444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.1073460444
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.4028838667
Short name T138
Test name
Test status
Simulation time 54723398 ps
CPU time 0.6 seconds
Started Mar 31 01:00:42 PM PDT 24
Finished Mar 31 01:00:43 PM PDT 24
Peak memory 195212 kb
Host smart-3e5d7a0b-066e-461f-9027-6c629be8e856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028838667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.4028838667
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.2169637598
Short name T560
Test name
Test status
Simulation time 5333082901 ps
CPU time 32.53 seconds
Started Mar 31 01:00:42 PM PDT 24
Finished Mar 31 01:01:15 PM PDT 24
Peak memory 232364 kb
Host smart-1c0bec8c-1c89-41a5-8242-d43423110119
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2169637598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2169637598
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3741959249
Short name T348
Test name
Test status
Simulation time 103294342 ps
CPU time 2.07 seconds
Started Mar 31 01:00:42 PM PDT 24
Finished Mar 31 01:00:45 PM PDT 24
Peak memory 199548 kb
Host smart-8b7ba26c-35fa-4f07-9c2a-f5cc59599fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741959249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3741959249
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2943743222
Short name T429
Test name
Test status
Simulation time 2121014498 ps
CPU time 132.26 seconds
Started Mar 31 01:00:42 PM PDT 24
Finished Mar 31 01:02:55 PM PDT 24
Peak memory 199656 kb
Host smart-8167190e-1672-467f-9df8-a61c9a4b11b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2943743222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2943743222
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.3377001368
Short name T49
Test name
Test status
Simulation time 10291426363 ps
CPU time 62.71 seconds
Started Mar 31 01:00:41 PM PDT 24
Finished Mar 31 01:01:44 PM PDT 24
Peak memory 199716 kb
Host smart-847af3b4-8b8b-4436-bbfa-8c3198ae6e4b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377001368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3377001368
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3449388646
Short name T482
Test name
Test status
Simulation time 5425713344 ps
CPU time 48.8 seconds
Started Mar 31 01:00:42 PM PDT 24
Finished Mar 31 01:01:31 PM PDT 24
Peak memory 199648 kb
Host smart-22e330ff-8474-4ba0-95e4-53f56e012262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449388646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3449388646
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3734126838
Short name T34
Test name
Test status
Simulation time 95591519 ps
CPU time 1.03 seconds
Started Mar 31 01:00:41 PM PDT 24
Finished Mar 31 01:00:43 PM PDT 24
Peak memory 219148 kb
Host smart-331f4411-b104-4233-b1aa-f89799789144
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734126838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3734126838
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.2489152665
Short name T466
Test name
Test status
Simulation time 601745011 ps
CPU time 5.07 seconds
Started Mar 31 01:00:41 PM PDT 24
Finished Mar 31 01:00:46 PM PDT 24
Peak memory 199628 kb
Host smart-a61265b3-691d-44e8-8182-77f43c6b242e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489152665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2489152665
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.1144681203
Short name T505
Test name
Test status
Simulation time 63211107 ps
CPU time 1.21 seconds
Started Mar 31 01:00:42 PM PDT 24
Finished Mar 31 01:00:43 PM PDT 24
Peak memory 199396 kb
Host smart-d2b6076d-f81d-4ffc-bc18-06760f7d94f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144681203 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.1144681203
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.1672566474
Short name T477
Test name
Test status
Simulation time 40128857935 ps
CPU time 433.88 seconds
Started Mar 31 01:00:39 PM PDT 24
Finished Mar 31 01:07:54 PM PDT 24
Peak memory 199620 kb
Host smart-e2707459-dc97-4ba8-8225-92ece0d6fbf6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672566474 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.1672566474
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2818689988
Short name T289
Test name
Test status
Simulation time 4867378491 ps
CPU time 33.14 seconds
Started Mar 31 01:00:43 PM PDT 24
Finished Mar 31 01:01:16 PM PDT 24
Peak memory 199700 kb
Host smart-13181c9d-cc8f-4e85-bb1d-00761a675601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818689988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2818689988
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2686970199
Short name T485
Test name
Test status
Simulation time 10931380 ps
CPU time 0.56 seconds
Started Mar 31 01:02:53 PM PDT 24
Finished Mar 31 01:02:53 PM PDT 24
Peak memory 193988 kb
Host smart-e51177f7-0798-403f-84a7-c5a8a2facf0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686970199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2686970199
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1030653871
Short name T169
Test name
Test status
Simulation time 4713273610 ps
CPU time 47.35 seconds
Started Mar 31 01:02:45 PM PDT 24
Finished Mar 31 01:03:33 PM PDT 24
Peak memory 232468 kb
Host smart-ddf201c6-5449-4a89-a579-9eb191a3cc44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1030653871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1030653871
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3751720776
Short name T299
Test name
Test status
Simulation time 202625864 ps
CPU time 3.92 seconds
Started Mar 31 01:02:50 PM PDT 24
Finished Mar 31 01:02:54 PM PDT 24
Peak memory 199572 kb
Host smart-65c8b948-94bc-4e17-8c63-c41ac48a4b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751720776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3751720776
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.2520889519
Short name T45
Test name
Test status
Simulation time 556658298 ps
CPU time 14.78 seconds
Started Mar 31 01:02:46 PM PDT 24
Finished Mar 31 01:03:00 PM PDT 24
Peak memory 199692 kb
Host smart-8f378c4e-7959-454e-bebc-e1b82ff56d36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2520889519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2520889519
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.1858798861
Short name T17
Test name
Test status
Simulation time 2281160798 ps
CPU time 32.17 seconds
Started Mar 31 01:02:52 PM PDT 24
Finished Mar 31 01:03:25 PM PDT 24
Peak memory 199712 kb
Host smart-897d9348-4969-4485-8834-2dfc8ce5ac8e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858798861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.1858798861
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.813360802
Short name T351
Test name
Test status
Simulation time 19080206497 ps
CPU time 97.65 seconds
Started Mar 31 01:02:45 PM PDT 24
Finished Mar 31 01:04:23 PM PDT 24
Peak memory 199696 kb
Host smart-aa60bd3e-8dcf-430f-86e5-0c2be5a7559a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813360802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.813360802
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1033585687
Short name T38
Test name
Test status
Simulation time 3248510713 ps
CPU time 4.45 seconds
Started Mar 31 01:02:44 PM PDT 24
Finished Mar 31 01:02:49 PM PDT 24
Peak memory 199720 kb
Host smart-49b54b13-bdba-42c5-a7dd-0c0297553a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033585687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1033585687
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.3129220085
Short name T168
Test name
Test status
Simulation time 63275285261 ps
CPU time 1806.6 seconds
Started Mar 31 01:02:52 PM PDT 24
Finished Mar 31 01:32:59 PM PDT 24
Peak memory 207908 kb
Host smart-85f84842-fe9f-455d-9d33-a039c8741c4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129220085 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3129220085
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.4293296950
Short name T76
Test name
Test status
Simulation time 41762159 ps
CPU time 1.06 seconds
Started Mar 31 01:02:53 PM PDT 24
Finished Mar 31 01:02:54 PM PDT 24
Peak memory 197960 kb
Host smart-f8fce9b0-9e3c-4a72-bd3a-10432bbcf424
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293296950 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.4293296950
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.3523034474
Short name T473
Test name
Test status
Simulation time 58274853829 ps
CPU time 476.06 seconds
Started Mar 31 01:02:51 PM PDT 24
Finished Mar 31 01:10:47 PM PDT 24
Peak memory 199516 kb
Host smart-b7644272-82de-4522-9f99-ffa0528671bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523034474 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.3523034474
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.3751415766
Short name T119
Test name
Test status
Simulation time 7769162375 ps
CPU time 38.92 seconds
Started Mar 31 01:02:52 PM PDT 24
Finished Mar 31 01:03:31 PM PDT 24
Peak memory 199748 kb
Host smart-3cc62606-7cff-44e5-a893-726af0bf59bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751415766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.3751415766
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1676686931
Short name T238
Test name
Test status
Simulation time 26192667 ps
CPU time 0.58 seconds
Started Mar 31 01:02:59 PM PDT 24
Finished Mar 31 01:02:59 PM PDT 24
Peak memory 194156 kb
Host smart-31bebc5f-be01-4d7b-80c4-6a39396b2dde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676686931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1676686931
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2509465878
Short name T568
Test name
Test status
Simulation time 1952220589 ps
CPU time 15.55 seconds
Started Mar 31 01:02:53 PM PDT 24
Finished Mar 31 01:03:08 PM PDT 24
Peak memory 207828 kb
Host smart-f3603797-a5ee-4f11-9512-d4002ec72d43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2509465878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2509465878
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1200253122
Short name T287
Test name
Test status
Simulation time 1356006285 ps
CPU time 58.41 seconds
Started Mar 31 01:02:54 PM PDT 24
Finished Mar 31 01:03:52 PM PDT 24
Peak memory 199584 kb
Host smart-73ee4a37-fa32-40f1-9d72-ca84c59a7b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200253122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1200253122
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2165127257
Short name T26
Test name
Test status
Simulation time 8750955646 ps
CPU time 105.36 seconds
Started Mar 31 01:02:51 PM PDT 24
Finished Mar 31 01:04:37 PM PDT 24
Peak memory 199724 kb
Host smart-e0e193e5-d08a-436e-ba2f-cde5913d83b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2165127257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2165127257
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3749955762
Short name T536
Test name
Test status
Simulation time 12683163900 ps
CPU time 157.14 seconds
Started Mar 31 01:02:51 PM PDT 24
Finished Mar 31 01:05:28 PM PDT 24
Peak memory 199720 kb
Host smart-c982e213-54b6-47d7-8581-9cc27879efa1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749955762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3749955762
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_smoke.1649716346
Short name T209
Test name
Test status
Simulation time 352960170 ps
CPU time 5.69 seconds
Started Mar 31 01:02:50 PM PDT 24
Finished Mar 31 01:02:56 PM PDT 24
Peak memory 199644 kb
Host smart-fcc31c02-e5e4-479d-9fe9-47661c48fee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649716346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1649716346
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.1660851623
Short name T166
Test name
Test status
Simulation time 58575825 ps
CPU time 1.21 seconds
Started Mar 31 01:02:59 PM PDT 24
Finished Mar 31 01:03:01 PM PDT 24
Peak memory 198620 kb
Host smart-f7721d95-c768-4631-8b1f-a52098bd3de6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660851623 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.1660851623
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.1494418807
Short name T143
Test name
Test status
Simulation time 30502693099 ps
CPU time 569.77 seconds
Started Mar 31 01:02:59 PM PDT 24
Finished Mar 31 01:12:29 PM PDT 24
Peak memory 199536 kb
Host smart-4f5b4dd8-a58c-406e-86c2-7115f54ec657
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494418807 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.1494418807
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3330191816
Short name T578
Test name
Test status
Simulation time 6774893261 ps
CPU time 64.66 seconds
Started Mar 31 01:03:04 PM PDT 24
Finished Mar 31 01:04:08 PM PDT 24
Peak memory 199644 kb
Host smart-58ddc45b-56a9-4713-be7e-ff9ac9519252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330191816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3330191816
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3202413302
Short name T204
Test name
Test status
Simulation time 18904529 ps
CPU time 0.59 seconds
Started Mar 31 01:03:00 PM PDT 24
Finished Mar 31 01:03:01 PM PDT 24
Peak memory 195200 kb
Host smart-eaf25b90-568b-4002-99bf-279850e25825
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202413302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3202413302
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2213003773
Short name T400
Test name
Test status
Simulation time 1624464385 ps
CPU time 27.99 seconds
Started Mar 31 01:03:00 PM PDT 24
Finished Mar 31 01:03:28 PM PDT 24
Peak memory 218068 kb
Host smart-5ce7cfdd-96eb-47d5-8d94-1c157dfe27b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2213003773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2213003773
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.3773062331
Short name T334
Test name
Test status
Simulation time 2796967320 ps
CPU time 25.47 seconds
Started Mar 31 01:02:59 PM PDT 24
Finished Mar 31 01:03:24 PM PDT 24
Peak memory 199668 kb
Host smart-4eb9ed3b-8f01-4377-87c4-657c5a8b334a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773062331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3773062331
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.378353702
Short name T296
Test name
Test status
Simulation time 429489335 ps
CPU time 26.23 seconds
Started Mar 31 01:02:59 PM PDT 24
Finished Mar 31 01:03:25 PM PDT 24
Peak memory 199624 kb
Host smart-4ef37e77-b10a-4664-8c7d-c1b2a47bd565
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=378353702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.378353702
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.1872404363
Short name T437
Test name
Test status
Simulation time 2038123767 ps
CPU time 26.71 seconds
Started Mar 31 01:03:00 PM PDT 24
Finished Mar 31 01:03:27 PM PDT 24
Peak memory 199668 kb
Host smart-364b0705-cc7f-40ec-9505-56015021157a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872404363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.1872404363
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3315487322
Short name T150
Test name
Test status
Simulation time 345405722 ps
CPU time 9.86 seconds
Started Mar 31 01:03:01 PM PDT 24
Finished Mar 31 01:03:11 PM PDT 24
Peak memory 199636 kb
Host smart-ad99204d-7f8b-4100-ad6f-02753ee942dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315487322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3315487322
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3338684444
Short name T244
Test name
Test status
Simulation time 175510667 ps
CPU time 2.79 seconds
Started Mar 31 01:02:58 PM PDT 24
Finished Mar 31 01:03:01 PM PDT 24
Peak memory 199656 kb
Host smart-48ed90d6-c25d-4ebb-9b53-454a921e67eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338684444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3338684444
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.1936072074
Short name T569
Test name
Test status
Simulation time 128809366322 ps
CPU time 1561.36 seconds
Started Mar 31 01:03:00 PM PDT 24
Finished Mar 31 01:29:02 PM PDT 24
Peak memory 199736 kb
Host smart-4feb72ac-d7ca-43eb-9ffc-6f903ea95f54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936072074 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1936072074
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.3626724077
Short name T62
Test name
Test status
Simulation time 30584568 ps
CPU time 1.32 seconds
Started Mar 31 01:02:58 PM PDT 24
Finished Mar 31 01:02:59 PM PDT 24
Peak memory 199632 kb
Host smart-9a86f6b3-7f42-4090-9c35-b96c67fad4db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626724077 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.3626724077
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.1955679315
Short name T215
Test name
Test status
Simulation time 170044712388 ps
CPU time 482.27 seconds
Started Mar 31 01:02:59 PM PDT 24
Finished Mar 31 01:11:01 PM PDT 24
Peak memory 199664 kb
Host smart-16316f89-fa33-469e-a40e-29ef4e5ab70a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955679315 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.1955679315
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3537241446
Short name T565
Test name
Test status
Simulation time 1261964125 ps
CPU time 13.74 seconds
Started Mar 31 01:03:04 PM PDT 24
Finished Mar 31 01:03:18 PM PDT 24
Peak memory 199660 kb
Host smart-fb39aaa4-0caf-4333-bec6-54745058d8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537241446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3537241446
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1831282663
Short name T440
Test name
Test status
Simulation time 47898357 ps
CPU time 0.6 seconds
Started Mar 31 01:03:14 PM PDT 24
Finished Mar 31 01:03:14 PM PDT 24
Peak memory 195288 kb
Host smart-304dfe80-2ffa-4377-b8c6-b1b4490cc690
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831282663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1831282663
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.2979396222
Short name T450
Test name
Test status
Simulation time 901954420 ps
CPU time 16.19 seconds
Started Mar 31 01:03:05 PM PDT 24
Finished Mar 31 01:03:22 PM PDT 24
Peak memory 215360 kb
Host smart-067ee4a2-6d4e-4ebd-a117-aecd715f936e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2979396222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2979396222
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.562101346
Short name T402
Test name
Test status
Simulation time 1001530428 ps
CPU time 10.25 seconds
Started Mar 31 01:03:07 PM PDT 24
Finished Mar 31 01:03:17 PM PDT 24
Peak memory 199620 kb
Host smart-df3a5a51-ec19-40e8-b70c-695117d45640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562101346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.562101346
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.3218145029
Short name T59
Test name
Test status
Simulation time 5678468163 ps
CPU time 78.43 seconds
Started Mar 31 01:03:08 PM PDT 24
Finished Mar 31 01:04:26 PM PDT 24
Peak memory 199620 kb
Host smart-18474fd4-17ba-4884-8e00-05d4ea0286b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3218145029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.3218145029
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.3763018196
Short name T30
Test name
Test status
Simulation time 3792030012 ps
CPU time 198.53 seconds
Started Mar 31 01:03:05 PM PDT 24
Finished Mar 31 01:06:23 PM PDT 24
Peak memory 199696 kb
Host smart-ed76c078-5fe3-4365-ad05-e74d15fec728
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763018196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3763018196
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.383681134
Short name T233
Test name
Test status
Simulation time 19293135654 ps
CPU time 129.8 seconds
Started Mar 31 01:03:06 PM PDT 24
Finished Mar 31 01:05:16 PM PDT 24
Peak memory 199644 kb
Host smart-4de7acdf-c58e-4ac6-874c-eac5d30a1f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383681134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.383681134
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2232190217
Short name T276
Test name
Test status
Simulation time 1608476147 ps
CPU time 4.67 seconds
Started Mar 31 01:03:06 PM PDT 24
Finished Mar 31 01:03:10 PM PDT 24
Peak memory 199592 kb
Host smart-ae9f5005-b1cc-4c26-bd83-e47ebc491739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232190217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2232190217
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1484049726
Short name T145
Test name
Test status
Simulation time 24020172852 ps
CPU time 70.93 seconds
Started Mar 31 01:03:07 PM PDT 24
Finished Mar 31 01:04:18 PM PDT 24
Peak memory 199680 kb
Host smart-0ea19740-8c50-4bd3-a580-a01db6131c59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484049726 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1484049726
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.525609877
Short name T218
Test name
Test status
Simulation time 218528697 ps
CPU time 1.28 seconds
Started Mar 31 01:03:05 PM PDT 24
Finished Mar 31 01:03:06 PM PDT 24
Peak memory 199164 kb
Host smart-482c1e9d-f959-499e-9fbd-5a7e4c8a2429
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525609877 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_hmac_vectors.525609877
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.4174513975
Short name T207
Test name
Test status
Simulation time 75125599671 ps
CPU time 535.57 seconds
Started Mar 31 01:03:06 PM PDT 24
Finished Mar 31 01:12:01 PM PDT 24
Peak memory 199568 kb
Host smart-dda533cb-b535-4082-8a99-0618bf941a1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174513975 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.4174513975
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.3860488489
Short name T581
Test name
Test status
Simulation time 39842246509 ps
CPU time 79.69 seconds
Started Mar 31 01:03:06 PM PDT 24
Finished Mar 31 01:04:26 PM PDT 24
Peak memory 199708 kb
Host smart-e1b14a68-3785-4f54-818a-e58029dc9db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860488489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3860488489
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1087364776
Short name T319
Test name
Test status
Simulation time 24781036 ps
CPU time 0.58 seconds
Started Mar 31 01:03:11 PM PDT 24
Finished Mar 31 01:03:12 PM PDT 24
Peak memory 195124 kb
Host smart-d84c9e9d-0890-43bc-8990-d97ae5ceefad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087364776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1087364776
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3744736520
Short name T58
Test name
Test status
Simulation time 83251342 ps
CPU time 1.84 seconds
Started Mar 31 01:03:05 PM PDT 24
Finished Mar 31 01:03:07 PM PDT 24
Peak memory 199568 kb
Host smart-ebb55085-6a4e-48c8-8b4b-ee6c9377b931
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3744736520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3744736520
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.599576003
Short name T497
Test name
Test status
Simulation time 628660596 ps
CPU time 31.37 seconds
Started Mar 31 01:03:12 PM PDT 24
Finished Mar 31 01:03:43 PM PDT 24
Peak memory 199688 kb
Host smart-8b96ae4b-3660-4e8b-9bb5-b3bfb9d63c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599576003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.599576003
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1466062605
Short name T164
Test name
Test status
Simulation time 583743727 ps
CPU time 18.7 seconds
Started Mar 31 01:03:07 PM PDT 24
Finished Mar 31 01:03:26 PM PDT 24
Peak memory 199664 kb
Host smart-27bf16f2-57cd-4627-bae3-0d148fc005fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1466062605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1466062605
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1801545437
Short name T234
Test name
Test status
Simulation time 137795330 ps
CPU time 1.97 seconds
Started Mar 31 01:03:12 PM PDT 24
Finished Mar 31 01:03:14 PM PDT 24
Peak memory 199524 kb
Host smart-c6206f43-2b73-48aa-83af-599e337ec15d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801545437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1801545437
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1852157802
Short name T247
Test name
Test status
Simulation time 10990202271 ps
CPU time 34.51 seconds
Started Mar 31 01:03:05 PM PDT 24
Finished Mar 31 01:03:40 PM PDT 24
Peak memory 199692 kb
Host smart-e59361bd-e079-41fc-8a95-7f15a7f8c455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852157802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1852157802
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2190798889
Short name T354
Test name
Test status
Simulation time 1176864181 ps
CPU time 4.5 seconds
Started Mar 31 01:03:06 PM PDT 24
Finished Mar 31 01:03:10 PM PDT 24
Peak memory 199632 kb
Host smart-4c3b9c6d-b425-4bf7-a589-5aa6ac9830ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190798889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2190798889
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2635710595
Short name T82
Test name
Test status
Simulation time 57556133024 ps
CPU time 777.25 seconds
Started Mar 31 01:03:11 PM PDT 24
Finished Mar 31 01:16:09 PM PDT 24
Peak memory 199764 kb
Host smart-5e2ceae3-1234-40cf-81ee-f7c34c8a661a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635710595 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2635710595
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.2580521311
Short name T392
Test name
Test status
Simulation time 169791400 ps
CPU time 1.06 seconds
Started Mar 31 01:03:10 PM PDT 24
Finished Mar 31 01:03:11 PM PDT 24
Peak memory 199044 kb
Host smart-05269130-2656-4418-a4d9-4dce2e02d663
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580521311 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.2580521311
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.4204898983
Short name T377
Test name
Test status
Simulation time 63755698486 ps
CPU time 469.55 seconds
Started Mar 31 01:03:13 PM PDT 24
Finished Mar 31 01:11:02 PM PDT 24
Peak memory 199632 kb
Host smart-cf0a058e-742f-4538-841b-b8e65c332655
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204898983 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.4204898983
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.3255661312
Short name T431
Test name
Test status
Simulation time 7772060498 ps
CPU time 94.63 seconds
Started Mar 31 01:03:14 PM PDT 24
Finished Mar 31 01:04:49 PM PDT 24
Peak memory 199660 kb
Host smart-dd27ab9b-1492-44e8-aba4-6457050d2df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255661312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.3255661312
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.953568280
Short name T283
Test name
Test status
Simulation time 13065600 ps
CPU time 0.57 seconds
Started Mar 31 01:03:17 PM PDT 24
Finished Mar 31 01:03:18 PM PDT 24
Peak memory 195228 kb
Host smart-6b7ceac7-b234-40bd-8ba5-68af426dd086
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953568280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.953568280
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.760408961
Short name T57
Test name
Test status
Simulation time 9519164086 ps
CPU time 38.18 seconds
Started Mar 31 01:03:14 PM PDT 24
Finished Mar 31 01:03:52 PM PDT 24
Peak memory 225008 kb
Host smart-9ce46028-dd84-4bc7-8bbf-c0fe2fb13320
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=760408961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.760408961
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3035144221
Short name T148
Test name
Test status
Simulation time 1000412687 ps
CPU time 16.14 seconds
Started Mar 31 01:03:12 PM PDT 24
Finished Mar 31 01:03:28 PM PDT 24
Peak memory 199712 kb
Host smart-137a769c-01fa-42ab-ab84-0d44fb4775d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035144221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3035144221
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3490115109
Short name T570
Test name
Test status
Simulation time 5993436881 ps
CPU time 88.2 seconds
Started Mar 31 01:03:13 PM PDT 24
Finished Mar 31 01:04:42 PM PDT 24
Peak memory 199680 kb
Host smart-acd061f7-bbfe-4925-9c4f-e12272daa7b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3490115109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3490115109
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1330218684
Short name T481
Test name
Test status
Simulation time 4581545176 ps
CPU time 131.81 seconds
Started Mar 31 01:03:12 PM PDT 24
Finished Mar 31 01:05:24 PM PDT 24
Peak memory 199600 kb
Host smart-c5e7516c-9555-4046-931d-f68dffe3404a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330218684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1330218684
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3472063683
Short name T4
Test name
Test status
Simulation time 22440058053 ps
CPU time 77.75 seconds
Started Mar 31 01:03:12 PM PDT 24
Finished Mar 31 01:04:29 PM PDT 24
Peak memory 199632 kb
Host smart-6c374874-31cf-4b1c-a09d-32f46b607594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472063683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3472063683
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1721944459
Short name T328
Test name
Test status
Simulation time 83189912 ps
CPU time 1.42 seconds
Started Mar 31 01:03:15 PM PDT 24
Finished Mar 31 01:03:16 PM PDT 24
Peak memory 199616 kb
Host smart-afec3142-4acc-4bef-83af-39691eeb9078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721944459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1721944459
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.1856162881
Short name T14
Test name
Test status
Simulation time 179819115677 ps
CPU time 877.22 seconds
Started Mar 31 01:03:17 PM PDT 24
Finished Mar 31 01:17:55 PM PDT 24
Peak memory 247908 kb
Host smart-ae40f08a-dada-4f41-bfa6-3fbee7cb2536
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856162881 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1856162881
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.323813772
Short name T559
Test name
Test status
Simulation time 225318175 ps
CPU time 1.29 seconds
Started Mar 31 01:03:20 PM PDT 24
Finished Mar 31 01:03:22 PM PDT 24
Peak memory 199544 kb
Host smart-1e626821-01e7-434e-bc00-7b5ecea2c3b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323813772 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_hmac_vectors.323813772
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.1167782578
Short name T390
Test name
Test status
Simulation time 516599500444 ps
CPU time 482.08 seconds
Started Mar 31 01:03:18 PM PDT 24
Finished Mar 31 01:11:20 PM PDT 24
Peak memory 199672 kb
Host smart-f0996e20-9c8b-4bfb-947a-c3069ae89efc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167782578 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.1167782578
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1317161545
Short name T350
Test name
Test status
Simulation time 6810670158 ps
CPU time 93.97 seconds
Started Mar 31 01:03:18 PM PDT 24
Finished Mar 31 01:04:52 PM PDT 24
Peak memory 199680 kb
Host smart-776817fa-3bfa-468f-8348-005a6d5bdf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317161545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1317161545
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.342621122
Short name T129
Test name
Test status
Simulation time 16417627 ps
CPU time 0.58 seconds
Started Mar 31 01:03:27 PM PDT 24
Finished Mar 31 01:03:28 PM PDT 24
Peak memory 195204 kb
Host smart-9ffaa8bc-739d-419d-afa1-504d69c81611
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342621122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.342621122
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.4019000588
Short name T447
Test name
Test status
Simulation time 3282007179 ps
CPU time 65.18 seconds
Started Mar 31 01:03:18 PM PDT 24
Finished Mar 31 01:04:24 PM PDT 24
Peak memory 230304 kb
Host smart-c2d28512-2078-4c8f-9f3c-646e0f2d75d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4019000588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.4019000588
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2632419850
Short name T114
Test name
Test status
Simulation time 393517417 ps
CPU time 2.14 seconds
Started Mar 31 01:03:18 PM PDT 24
Finished Mar 31 01:03:20 PM PDT 24
Peak memory 199444 kb
Host smart-3b13fcdc-cb0e-4e07-8d6b-1e998d79e923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632419850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2632419850
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3779113835
Short name T593
Test name
Test status
Simulation time 1231299192 ps
CPU time 63.47 seconds
Started Mar 31 01:03:19 PM PDT 24
Finished Mar 31 01:04:22 PM PDT 24
Peak memory 199688 kb
Host smart-59ebe9c9-1e21-4fd5-94ca-53cd43a039b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3779113835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3779113835
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.46466762
Short name T250
Test name
Test status
Simulation time 5679333124 ps
CPU time 70.8 seconds
Started Mar 31 01:03:20 PM PDT 24
Finished Mar 31 01:04:31 PM PDT 24
Peak memory 199708 kb
Host smart-51dcb17a-25e3-4612-a752-0674cacbe4b5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46466762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.46466762
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.4054353074
Short name T415
Test name
Test status
Simulation time 4604336637 ps
CPU time 29.61 seconds
Started Mar 31 01:03:19 PM PDT 24
Finished Mar 31 01:03:49 PM PDT 24
Peak memory 199700 kb
Host smart-c0d31568-b002-4f75-b543-a59adb9e217d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054353074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.4054353074
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3935918513
Short name T595
Test name
Test status
Simulation time 659753746 ps
CPU time 4.56 seconds
Started Mar 31 01:03:19 PM PDT 24
Finished Mar 31 01:03:24 PM PDT 24
Peak memory 199544 kb
Host smart-dd104800-08f6-497e-9aa7-39293569f824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935918513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3935918513
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3657461499
Short name T46
Test name
Test status
Simulation time 97752810215 ps
CPU time 1207.82 seconds
Started Mar 31 01:03:18 PM PDT 24
Finished Mar 31 01:23:26 PM PDT 24
Peak memory 216080 kb
Host smart-5aab8592-47b7-4194-9048-038ce7b13922
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657461499 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3657461499
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.759187077
Short name T421
Test name
Test status
Simulation time 86308611 ps
CPU time 1.13 seconds
Started Mar 31 01:03:19 PM PDT 24
Finished Mar 31 01:03:21 PM PDT 24
Peak memory 199272 kb
Host smart-ebc99b77-c608-4688-b5bb-09b565627f54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759187077 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_test_hmac_vectors.759187077
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.2542087804
Short name T413
Test name
Test status
Simulation time 532497301190 ps
CPU time 529.1 seconds
Started Mar 31 01:03:19 PM PDT 24
Finished Mar 31 01:12:08 PM PDT 24
Peak memory 199668 kb
Host smart-da683a78-879d-406d-8a01-5589a80ebe07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542087804 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.2542087804
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1045566838
Short name T592
Test name
Test status
Simulation time 252655374 ps
CPU time 5.54 seconds
Started Mar 31 01:03:17 PM PDT 24
Finished Mar 31 01:03:23 PM PDT 24
Peak memory 199612 kb
Host smart-acd6589b-9e71-4a6a-9fb1-afc73ed7e0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045566838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1045566838
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.4185111652
Short name T558
Test name
Test status
Simulation time 20400700 ps
CPU time 0.6 seconds
Started Mar 31 01:03:30 PM PDT 24
Finished Mar 31 01:03:31 PM PDT 24
Peak memory 195216 kb
Host smart-75ab8244-5d6c-4895-8b37-c7c8e2a9d38d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185111652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.4185111652
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.181358838
Short name T21
Test name
Test status
Simulation time 2109762522 ps
CPU time 20.22 seconds
Started Mar 31 01:03:25 PM PDT 24
Finished Mar 31 01:03:45 PM PDT 24
Peak memory 207836 kb
Host smart-5ce7e918-bf8f-43ac-89db-7fa0ef3d3d86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=181358838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.181358838
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2147395948
Short name T530
Test name
Test status
Simulation time 4314299480 ps
CPU time 24.59 seconds
Started Mar 31 01:03:24 PM PDT 24
Finished Mar 31 01:03:48 PM PDT 24
Peak memory 199700 kb
Host smart-835fec91-7ea4-46c6-bd8c-a9c2493cab28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147395948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2147395948
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1019645984
Short name T110
Test name
Test status
Simulation time 3020378810 ps
CPU time 148.39 seconds
Started Mar 31 01:03:30 PM PDT 24
Finished Mar 31 01:05:59 PM PDT 24
Peak memory 199636 kb
Host smart-587ca8bd-5e7e-402e-8725-3d50277934f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1019645984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1019645984
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1311615516
Short name T191
Test name
Test status
Simulation time 178556385 ps
CPU time 10.11 seconds
Started Mar 31 01:03:26 PM PDT 24
Finished Mar 31 01:03:36 PM PDT 24
Peak memory 199644 kb
Host smart-8cff4f2b-5afe-4fb6-8daa-bd872650cfaa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311615516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1311615516
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.2864230384
Short name T391
Test name
Test status
Simulation time 870837262 ps
CPU time 52.96 seconds
Started Mar 31 01:03:25 PM PDT 24
Finished Mar 31 01:04:19 PM PDT 24
Peak memory 199664 kb
Host smart-e9bcfd01-732b-40ea-a398-feca1d215dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864230384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2864230384
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1951309913
Short name T212
Test name
Test status
Simulation time 1202957978 ps
CPU time 3.55 seconds
Started Mar 31 01:03:26 PM PDT 24
Finished Mar 31 01:03:30 PM PDT 24
Peak memory 199620 kb
Host smart-494bd319-3583-46e7-8625-36c972f62c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951309913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1951309913
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.1761136255
Short name T81
Test name
Test status
Simulation time 108369054103 ps
CPU time 779.53 seconds
Started Mar 31 01:03:30 PM PDT 24
Finished Mar 31 01:16:30 PM PDT 24
Peak memory 207856 kb
Host smart-418e55c3-7f59-48de-b61a-1e2f6d50ec1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761136255 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.1761136255
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.3003799016
Short name T393
Test name
Test status
Simulation time 32996951 ps
CPU time 1.26 seconds
Started Mar 31 01:03:30 PM PDT 24
Finished Mar 31 01:03:32 PM PDT 24
Peak memory 199400 kb
Host smart-802b270c-24f6-41b1-8692-937dfa424007
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003799016 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.3003799016
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.3175927718
Short name T369
Test name
Test status
Simulation time 40398078376 ps
CPU time 509.25 seconds
Started Mar 31 01:03:25 PM PDT 24
Finished Mar 31 01:11:55 PM PDT 24
Peak memory 199700 kb
Host smart-432d012c-4817-4d46-9eba-d3bb10ffabc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175927718 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.3175927718
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3904625788
Short name T448
Test name
Test status
Simulation time 22590768035 ps
CPU time 78.99 seconds
Started Mar 31 01:03:24 PM PDT 24
Finished Mar 31 01:04:43 PM PDT 24
Peak memory 199644 kb
Host smart-6254952d-bdad-418b-ac5e-d5c5baa6f73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904625788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3904625788
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1189723763
Short name T379
Test name
Test status
Simulation time 15204030 ps
CPU time 0.58 seconds
Started Mar 31 01:03:32 PM PDT 24
Finished Mar 31 01:03:33 PM PDT 24
Peak memory 195124 kb
Host smart-5249d34b-4fcc-4467-a231-908b6316ee6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189723763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1189723763
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.3912188372
Short name T326
Test name
Test status
Simulation time 1494348600 ps
CPU time 35.94 seconds
Started Mar 31 01:03:28 PM PDT 24
Finished Mar 31 01:04:04 PM PDT 24
Peak memory 232372 kb
Host smart-30aa5950-81cd-4906-8717-26ef2399614e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3912188372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3912188372
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.2574536799
Short name T418
Test name
Test status
Simulation time 2396533611 ps
CPU time 26.55 seconds
Started Mar 31 01:03:32 PM PDT 24
Finished Mar 31 01:03:59 PM PDT 24
Peak memory 199720 kb
Host smart-2ab435ca-a37a-431b-98db-7dce8a2cb1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574536799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2574536799
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.1941474689
Short name T420
Test name
Test status
Simulation time 10302410238 ps
CPU time 152.19 seconds
Started Mar 31 01:03:30 PM PDT 24
Finished Mar 31 01:06:02 PM PDT 24
Peak memory 199728 kb
Host smart-a416d53a-65e6-4da8-a52d-33a23bc39172
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1941474689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1941474689
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.2429941084
Short name T28
Test name
Test status
Simulation time 4112377073 ps
CPU time 99.27 seconds
Started Mar 31 01:03:31 PM PDT 24
Finished Mar 31 01:05:11 PM PDT 24
Peak memory 199704 kb
Host smart-41e81ff4-23da-4abc-9446-bae37314dde8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429941084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.2429941084
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1646702795
Short name T263
Test name
Test status
Simulation time 31375029365 ps
CPU time 39.4 seconds
Started Mar 31 01:03:25 PM PDT 24
Finished Mar 31 01:04:04 PM PDT 24
Peak memory 199672 kb
Host smart-7be4659e-67eb-4b1d-b2ba-7809820fa4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646702795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1646702795
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3987463847
Short name T452
Test name
Test status
Simulation time 301992252 ps
CPU time 4.74 seconds
Started Mar 31 01:03:24 PM PDT 24
Finished Mar 31 01:03:29 PM PDT 24
Peak memory 199656 kb
Host smart-221c2761-b60b-4e5d-9ff4-db98f0041f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987463847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3987463847
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2072089603
Short name T301
Test name
Test status
Simulation time 17208779339 ps
CPU time 238.99 seconds
Started Mar 31 01:03:36 PM PDT 24
Finished Mar 31 01:07:35 PM PDT 24
Peak memory 224188 kb
Host smart-4f9dd5df-e639-4d32-bd53-3d427a53180c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072089603 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2072089603
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.1554140972
Short name T163
Test name
Test status
Simulation time 110883316 ps
CPU time 1.26 seconds
Started Mar 31 01:03:33 PM PDT 24
Finished Mar 31 01:03:34 PM PDT 24
Peak memory 199672 kb
Host smart-72f1de54-e833-4a6d-952c-3f4c95e395f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554140972 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.1554140972
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.726772559
Short name T488
Test name
Test status
Simulation time 117544904436 ps
CPU time 544.91 seconds
Started Mar 31 01:03:32 PM PDT 24
Finished Mar 31 01:12:37 PM PDT 24
Peak memory 199680 kb
Host smart-da55be66-b8f0-4c60-be18-0433fad19269
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726772559 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.726772559
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1719614195
Short name T527
Test name
Test status
Simulation time 25648565226 ps
CPU time 78.71 seconds
Started Mar 31 01:03:34 PM PDT 24
Finished Mar 31 01:04:53 PM PDT 24
Peak memory 199748 kb
Host smart-a5e59366-94f9-401f-8d02-305285cdc51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719614195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1719614195
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3325398006
Short name T580
Test name
Test status
Simulation time 11416299 ps
CPU time 0.58 seconds
Started Mar 31 01:03:41 PM PDT 24
Finished Mar 31 01:03:42 PM PDT 24
Peak memory 195080 kb
Host smart-28f4fd90-05c1-4531-b007-8f7ccd4d22e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325398006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3325398006
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2841323877
Short name T407
Test name
Test status
Simulation time 1534864227 ps
CPU time 16.92 seconds
Started Mar 31 01:03:32 PM PDT 24
Finished Mar 31 01:03:49 PM PDT 24
Peak memory 199528 kb
Host smart-fc8cb28e-0e74-4565-a9da-ed252b997272
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2841323877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2841323877
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3229188213
Short name T219
Test name
Test status
Simulation time 825578633 ps
CPU time 17.21 seconds
Started Mar 31 01:03:32 PM PDT 24
Finished Mar 31 01:03:50 PM PDT 24
Peak memory 199508 kb
Host smart-d8159581-ff45-4e81-b299-a0610aba5f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229188213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3229188213
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3459982760
Short name T265
Test name
Test status
Simulation time 945231714 ps
CPU time 14.31 seconds
Started Mar 31 01:03:34 PM PDT 24
Finished Mar 31 01:03:49 PM PDT 24
Peak memory 199652 kb
Host smart-7df37b65-88da-459b-80f8-5882b1e079a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3459982760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3459982760
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.948845213
Short name T543
Test name
Test status
Simulation time 10791462151 ps
CPU time 108.83 seconds
Started Mar 31 01:03:29 PM PDT 24
Finished Mar 31 01:05:18 PM PDT 24
Peak memory 199748 kb
Host smart-e569c70e-ff9a-4a95-9bde-00f00f89eb51
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948845213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.948845213
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.3274729560
Short name T149
Test name
Test status
Simulation time 22753681050 ps
CPU time 79.41 seconds
Started Mar 31 01:03:31 PM PDT 24
Finished Mar 31 01:04:50 PM PDT 24
Peak memory 199696 kb
Host smart-7289b2fc-e0ea-4ae8-9de6-67998a4fc001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274729560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3274729560
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.9450229
Short name T451
Test name
Test status
Simulation time 158186321 ps
CPU time 4.99 seconds
Started Mar 31 01:03:33 PM PDT 24
Finished Mar 31 01:03:38 PM PDT 24
Peak memory 199496 kb
Host smart-f8ca899d-bbaa-40b9-bef6-f95cf0bd172f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9450229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.9450229
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.3813387184
Short name T516
Test name
Test status
Simulation time 154370626133 ps
CPU time 2082.44 seconds
Started Mar 31 01:03:39 PM PDT 24
Finished Mar 31 01:38:22 PM PDT 24
Peak memory 237612 kb
Host smart-1acef65d-1e07-4048-b33e-7a121c23f8f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813387184 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.3813387184
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.2469664110
Short name T499
Test name
Test status
Simulation time 56943502 ps
CPU time 1.26 seconds
Started Mar 31 01:03:30 PM PDT 24
Finished Mar 31 01:03:32 PM PDT 24
Peak memory 199464 kb
Host smart-4ac20d8c-21a4-4ed5-8cd9-b90bd34274d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469664110 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.2469664110
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.833496760
Short name T435
Test name
Test status
Simulation time 48147178273 ps
CPU time 449.82 seconds
Started Mar 31 01:03:30 PM PDT 24
Finished Mar 31 01:11:00 PM PDT 24
Peak memory 199592 kb
Host smart-d6fffcd6-cc24-45f8-a7f9-8c2c926895d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833496760 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.833496760
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1461163170
Short name T304
Test name
Test status
Simulation time 1080957290 ps
CPU time 50.46 seconds
Started Mar 31 01:03:32 PM PDT 24
Finished Mar 31 01:04:22 PM PDT 24
Peak memory 199712 kb
Host smart-70abe5a4-2ac9-4105-b225-abd3b089230c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461163170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1461163170
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.2766409935
Short name T190
Test name
Test status
Simulation time 106103653 ps
CPU time 0.58 seconds
Started Mar 31 01:00:52 PM PDT 24
Finished Mar 31 01:00:53 PM PDT 24
Peak memory 195148 kb
Host smart-d5bf6ad6-bcd5-43e3-8246-be73a3c7e4d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766409935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.2766409935
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.261718339
Short name T192
Test name
Test status
Simulation time 18153288437 ps
CPU time 41.21 seconds
Started Mar 31 01:00:43 PM PDT 24
Finished Mar 31 01:01:24 PM PDT 24
Peak memory 232488 kb
Host smart-71d62de0-44f1-459d-b0cc-bf9f180825c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=261718339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.261718339
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3702132691
Short name T467
Test name
Test status
Simulation time 300443637 ps
CPU time 5.35 seconds
Started Mar 31 01:00:41 PM PDT 24
Finished Mar 31 01:00:47 PM PDT 24
Peak memory 199616 kb
Host smart-9c4dc6ac-b046-4bb5-be3c-b48276209c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702132691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3702132691
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.906583723
Short name T444
Test name
Test status
Simulation time 4824201874 ps
CPU time 69.53 seconds
Started Mar 31 01:00:41 PM PDT 24
Finished Mar 31 01:01:51 PM PDT 24
Peak memory 199776 kb
Host smart-ada45501-3758-47cc-9b41-c749fb394c96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=906583723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.906583723
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.147053497
Short name T15
Test name
Test status
Simulation time 2901951897 ps
CPU time 81.62 seconds
Started Mar 31 01:00:43 PM PDT 24
Finished Mar 31 01:02:05 PM PDT 24
Peak memory 199672 kb
Host smart-47bd44fc-c491-4d6a-96f6-cc31345ecbec
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147053497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.147053497
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.896472013
Short name T268
Test name
Test status
Simulation time 6901509868 ps
CPU time 139.83 seconds
Started Mar 31 01:00:42 PM PDT 24
Finished Mar 31 01:03:02 PM PDT 24
Peak memory 199748 kb
Host smart-2ecb5d1e-a8fe-457b-af64-f74e11a418d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896472013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.896472013
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.4196126410
Short name T472
Test name
Test status
Simulation time 216015566 ps
CPU time 6.8 seconds
Started Mar 31 01:00:41 PM PDT 24
Finished Mar 31 01:00:48 PM PDT 24
Peak memory 199572 kb
Host smart-670f1f5f-ae7b-4d41-8315-8a9dc9aa7e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196126410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.4196126410
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1283230494
Short name T258
Test name
Test status
Simulation time 4425363500 ps
CPU time 79.82 seconds
Started Mar 31 01:00:47 PM PDT 24
Finished Mar 31 01:02:08 PM PDT 24
Peak memory 199704 kb
Host smart-f97834a3-f68a-4643-a8a0-033a11c9cb75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283230494 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1283230494
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.1481899577
Short name T118
Test name
Test status
Simulation time 84312734 ps
CPU time 0.97 seconds
Started Mar 31 01:00:50 PM PDT 24
Finished Mar 31 01:00:52 PM PDT 24
Peak memory 198468 kb
Host smart-543fc341-752d-4b24-a73d-faca32db4bfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481899577 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.1481899577
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.1924233238
Short name T479
Test name
Test status
Simulation time 26439909669 ps
CPU time 388.59 seconds
Started Mar 31 01:00:39 PM PDT 24
Finished Mar 31 01:07:08 PM PDT 24
Peak memory 199496 kb
Host smart-7808b910-b8d9-42a9-969c-21696138b671
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924233238 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.1924233238
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.788055087
Short name T8
Test name
Test status
Simulation time 3900673453 ps
CPU time 73.09 seconds
Started Mar 31 01:00:40 PM PDT 24
Finished Mar 31 01:01:53 PM PDT 24
Peak memory 199716 kb
Host smart-0bbd8c32-d051-44e8-bb8e-22851e1af4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788055087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.788055087
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.3847755071
Short name T353
Test name
Test status
Simulation time 19083404 ps
CPU time 0.56 seconds
Started Mar 31 01:00:47 PM PDT 24
Finished Mar 31 01:00:48 PM PDT 24
Peak memory 195076 kb
Host smart-de3b69f1-58bb-446e-b4f0-279221f5f4ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847755071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.3847755071
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3699435381
Short name T363
Test name
Test status
Simulation time 542381425 ps
CPU time 5.64 seconds
Started Mar 31 01:00:47 PM PDT 24
Finished Mar 31 01:00:52 PM PDT 24
Peak memory 207828 kb
Host smart-60865e5c-db8b-40a4-b240-6d130363df25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3699435381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3699435381
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.691306925
Short name T313
Test name
Test status
Simulation time 3488504928 ps
CPU time 42.46 seconds
Started Mar 31 01:00:53 PM PDT 24
Finished Mar 31 01:01:36 PM PDT 24
Peak memory 199664 kb
Host smart-83ddd0f3-a43b-4a7b-9044-e53cafa44556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691306925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.691306925
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.829184865
Short name T542
Test name
Test status
Simulation time 2375264721 ps
CPU time 40.08 seconds
Started Mar 31 01:00:52 PM PDT 24
Finished Mar 31 01:01:33 PM PDT 24
Peak memory 199708 kb
Host smart-9dcdb5ff-22be-4a85-87c3-c3e89f80ba2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=829184865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.829184865
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3993070669
Short name T293
Test name
Test status
Simulation time 1534773443 ps
CPU time 90.24 seconds
Started Mar 31 01:00:51 PM PDT 24
Finished Mar 31 01:02:23 PM PDT 24
Peak memory 199508 kb
Host smart-c321b66f-2f17-4faf-a6c2-74a4559454fa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993070669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3993070669
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3402941010
Short name T442
Test name
Test status
Simulation time 415938756 ps
CPU time 19.21 seconds
Started Mar 31 01:00:47 PM PDT 24
Finished Mar 31 01:01:06 PM PDT 24
Peak memory 199648 kb
Host smart-f57a4f0a-8850-4257-a8a6-9f73471c0fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402941010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3402941010
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2292353191
Short name T144
Test name
Test status
Simulation time 889335678 ps
CPU time 6.83 seconds
Started Mar 31 01:00:50 PM PDT 24
Finished Mar 31 01:00:57 PM PDT 24
Peak memory 199640 kb
Host smart-ac30be03-8d74-414c-b1df-9831422346ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292353191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2292353191
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.1993415737
Short name T504
Test name
Test status
Simulation time 69097982648 ps
CPU time 905.81 seconds
Started Mar 31 01:00:53 PM PDT 24
Finished Mar 31 01:16:00 PM PDT 24
Peak memory 226048 kb
Host smart-0d1e43dc-4496-4544-bd5c-7b750ff753e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993415737 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1993415737
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.1761819702
Short name T553
Test name
Test status
Simulation time 78372774 ps
CPU time 1.03 seconds
Started Mar 31 01:00:49 PM PDT 24
Finished Mar 31 01:00:50 PM PDT 24
Peak memory 198932 kb
Host smart-94d7eaf6-6605-49eb-9325-fbd40f972cfd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761819702 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.1761819702
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.3082104534
Short name T487
Test name
Test status
Simulation time 37530112950 ps
CPU time 513.76 seconds
Started Mar 31 01:00:51 PM PDT 24
Finished Mar 31 01:09:25 PM PDT 24
Peak memory 199572 kb
Host smart-204d5bb1-01f3-4fc0-8e3c-30c538bbac75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082104534 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.3082104534
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.3251593673
Short name T278
Test name
Test status
Simulation time 976272499 ps
CPU time 3.49 seconds
Started Mar 31 01:00:49 PM PDT 24
Finished Mar 31 01:00:52 PM PDT 24
Peak memory 199548 kb
Host smart-ff1ff5cd-ffa1-4c68-bcae-58bcae2b6e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251593673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3251593673
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/64.hmac_stress_all_with_rand_reset.2364632700
Short name T10
Test name
Test status
Simulation time 56643520667 ps
CPU time 1087.82 seconds
Started Mar 31 01:03:47 PM PDT 24
Finished Mar 31 01:21:56 PM PDT 24
Peak memory 216088 kb
Host smart-05fa93bd-b980-409e-9efe-022fd271133b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2364632700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.hmac_stress_all_with_rand_reset.2364632700
Directory /workspace/64.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2293065032
Short name T384
Test name
Test status
Simulation time 63488673 ps
CPU time 0.63 seconds
Started Mar 31 01:00:48 PM PDT 24
Finished Mar 31 01:00:49 PM PDT 24
Peak memory 195252 kb
Host smart-ed4848a6-9f21-43a1-8c22-c00df6f4e5e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293065032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2293065032
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.365253838
Short name T535
Test name
Test status
Simulation time 1611884600 ps
CPU time 63.38 seconds
Started Mar 31 01:00:51 PM PDT 24
Finished Mar 31 01:01:54 PM PDT 24
Peak memory 229376 kb
Host smart-b1fbbdad-bc18-4b83-b6f7-036b18fcd59a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=365253838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.365253838
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1583644931
Short name T383
Test name
Test status
Simulation time 8268964149 ps
CPU time 45.08 seconds
Started Mar 31 01:00:48 PM PDT 24
Finished Mar 31 01:01:33 PM PDT 24
Peak memory 199612 kb
Host smart-d5afb217-90be-4aa6-8661-ad68cb70fe30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583644931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1583644931
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2884863251
Short name T217
Test name
Test status
Simulation time 789557553 ps
CPU time 12.21 seconds
Started Mar 31 01:00:46 PM PDT 24
Finished Mar 31 01:00:58 PM PDT 24
Peak memory 199620 kb
Host smart-0fabad01-2ddd-4f2c-969b-ce0cfe4fbc1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2884863251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2884863251
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.850811769
Short name T230
Test name
Test status
Simulation time 6999172626 ps
CPU time 25.33 seconds
Started Mar 31 01:00:50 PM PDT 24
Finished Mar 31 01:01:16 PM PDT 24
Peak memory 199632 kb
Host smart-88d4835c-cb87-4582-960f-211daec08af3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850811769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.850811769
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3911634187
Short name T339
Test name
Test status
Simulation time 830014708 ps
CPU time 45.52 seconds
Started Mar 31 01:00:49 PM PDT 24
Finished Mar 31 01:01:34 PM PDT 24
Peak memory 199648 kb
Host smart-c374c815-ef56-4c51-abe5-1d3c4b77df3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911634187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3911634187
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2480024210
Short name T427
Test name
Test status
Simulation time 415425691 ps
CPU time 2.72 seconds
Started Mar 31 01:00:49 PM PDT 24
Finished Mar 31 01:00:52 PM PDT 24
Peak memory 199620 kb
Host smart-8b342379-68bd-4a10-8036-e85f542f5cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480024210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2480024210
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.3090611415
Short name T423
Test name
Test status
Simulation time 215137362015 ps
CPU time 684.25 seconds
Started Mar 31 01:00:53 PM PDT 24
Finished Mar 31 01:12:18 PM PDT 24
Peak memory 199648 kb
Host smart-b595e023-ad2e-448b-a4e9-ae5dbe640442
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090611415 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.3090611415
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.1964105362
Short name T71
Test name
Test status
Simulation time 19203094767 ps
CPU time 512.42 seconds
Started Mar 31 01:00:52 PM PDT 24
Finished Mar 31 01:09:25 PM PDT 24
Peak memory 216168 kb
Host smart-3faebb2b-a675-4ac9-9650-ca2b1e168273
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1964105362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.1964105362
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.617120936
Short name T211
Test name
Test status
Simulation time 81082911 ps
CPU time 1.04 seconds
Started Mar 31 01:00:48 PM PDT 24
Finished Mar 31 01:00:49 PM PDT 24
Peak memory 198980 kb
Host smart-4ca91872-ab33-4e25-9e2f-6e39a5dde189
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617120936 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.hmac_test_hmac_vectors.617120936
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.1593668468
Short name T152
Test name
Test status
Simulation time 143184290992 ps
CPU time 468.27 seconds
Started Mar 31 01:00:49 PM PDT 24
Finished Mar 31 01:08:38 PM PDT 24
Peak memory 199556 kb
Host smart-17ab28fb-ebb8-4ac5-8f27-4b33d95d54df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593668468 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.1593668468
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.3225717728
Short name T414
Test name
Test status
Simulation time 1244081989 ps
CPU time 59.19 seconds
Started Mar 31 01:00:51 PM PDT 24
Finished Mar 31 01:01:50 PM PDT 24
Peak memory 199596 kb
Host smart-029c256c-36fe-49e3-b68e-2646ee3cda86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225717728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3225717728
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/78.hmac_stress_all_with_rand_reset.846663334
Short name T12
Test name
Test status
Simulation time 28429955005 ps
CPU time 1438.15 seconds
Started Mar 31 01:03:59 PM PDT 24
Finished Mar 31 01:27:58 PM PDT 24
Peak memory 216092 kb
Host smart-5d22c95c-f254-4d56-bb78-450abaed92c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=846663334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.hmac_stress_all_with_rand_reset.846663334
Directory /workspace/78.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.517965461
Short name T197
Test name
Test status
Simulation time 69703181 ps
CPU time 0.58 seconds
Started Mar 31 01:00:57 PM PDT 24
Finished Mar 31 01:00:57 PM PDT 24
Peak memory 195140 kb
Host smart-b997cafe-0afe-4ddd-a6b9-d1bbbb315b4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517965461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.517965461
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.798940200
Short name T373
Test name
Test status
Simulation time 6679566533 ps
CPU time 59.61 seconds
Started Mar 31 01:00:53 PM PDT 24
Finished Mar 31 01:01:53 PM PDT 24
Peak memory 222288 kb
Host smart-7d0355e5-a19c-4f2c-b3c1-52f934d140e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=798940200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.798940200
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2738510197
Short name T375
Test name
Test status
Simulation time 1240117954 ps
CPU time 19.47 seconds
Started Mar 31 01:00:48 PM PDT 24
Finished Mar 31 01:01:08 PM PDT 24
Peak memory 199644 kb
Host smart-6e10a7c9-0945-45de-bc6d-052c39c4a0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738510197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2738510197
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.4272403654
Short name T259
Test name
Test status
Simulation time 983540517 ps
CPU time 57.43 seconds
Started Mar 31 01:00:47 PM PDT 24
Finished Mar 31 01:01:45 PM PDT 24
Peak memory 199488 kb
Host smart-71ddee23-9add-4d95-aa15-c252f25e556f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4272403654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.4272403654
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.4235186534
Short name T544
Test name
Test status
Simulation time 2867750591 ps
CPU time 150.47 seconds
Started Mar 31 01:00:49 PM PDT 24
Finished Mar 31 01:03:20 PM PDT 24
Peak memory 199716 kb
Host smart-f1a2adb6-5411-46b1-b536-010a26b0791d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235186534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.4235186534
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1052093669
Short name T417
Test name
Test status
Simulation time 3820783357 ps
CPU time 57.86 seconds
Started Mar 31 01:00:56 PM PDT 24
Finished Mar 31 01:01:54 PM PDT 24
Peak memory 199680 kb
Host smart-43546feb-7c43-478a-bec0-d14437dae4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052093669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1052093669
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.723102453
Short name T188
Test name
Test status
Simulation time 89431748 ps
CPU time 1.13 seconds
Started Mar 31 01:00:51 PM PDT 24
Finished Mar 31 01:00:54 PM PDT 24
Peak memory 199580 kb
Host smart-d2803f66-04e3-483b-9ccc-b221e1bee74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723102453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.723102453
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.1760859685
Short name T484
Test name
Test status
Simulation time 12699904069 ps
CPU time 150.95 seconds
Started Mar 31 01:00:50 PM PDT 24
Finished Mar 31 01:03:22 PM PDT 24
Peak memory 199416 kb
Host smart-db81837c-7b44-4529-9371-b8ebd20002da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760859685 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1760859685
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.1320756080
Short name T522
Test name
Test status
Simulation time 112199317 ps
CPU time 1.36 seconds
Started Mar 31 01:00:53 PM PDT 24
Finished Mar 31 01:00:54 PM PDT 24
Peak memory 199608 kb
Host smart-5b41a678-c323-48c1-92ba-1da798b18459
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320756080 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.1320756080
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.1187250227
Short name T439
Test name
Test status
Simulation time 107363669977 ps
CPU time 444.7 seconds
Started Mar 31 01:00:53 PM PDT 24
Finished Mar 31 01:08:18 PM PDT 24
Peak memory 199660 kb
Host smart-04c850e6-bd23-4b66-857e-d92180ece929
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187250227 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.1187250227
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.3416907614
Short name T44
Test name
Test status
Simulation time 8535201202 ps
CPU time 30.69 seconds
Started Mar 31 01:00:47 PM PDT 24
Finished Mar 31 01:01:17 PM PDT 24
Peak memory 199744 kb
Host smart-80f7d7d2-f77b-4de9-b5f4-204367197fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416907614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3416907614
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/87.hmac_stress_all_with_rand_reset.426591956
Short name T72
Test name
Test status
Simulation time 100181108742 ps
CPU time 778.94 seconds
Started Mar 31 01:03:58 PM PDT 24
Finished Mar 31 01:16:57 PM PDT 24
Peak memory 215828 kb
Host smart-2e0fde2a-607f-4ed6-86fe-d1b0daa09758
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=426591956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.hmac_stress_all_with_rand_reset.426591956
Directory /workspace/87.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_alert_test.4034214818
Short name T513
Test name
Test status
Simulation time 22709975 ps
CPU time 0.62 seconds
Started Mar 31 01:00:55 PM PDT 24
Finished Mar 31 01:00:56 PM PDT 24
Peak memory 195244 kb
Host smart-85861197-3891-4ab8-8a44-bc8398d78caf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034214818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.4034214818
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1371927528
Short name T341
Test name
Test status
Simulation time 1309543844 ps
CPU time 24.56 seconds
Started Mar 31 01:00:55 PM PDT 24
Finished Mar 31 01:01:20 PM PDT 24
Peak memory 217012 kb
Host smart-d9bd803f-79e8-42d0-b178-efbb2bc5e2ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1371927528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1371927528
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.1993432338
Short name T498
Test name
Test status
Simulation time 1487760196 ps
CPU time 11.59 seconds
Started Mar 31 01:00:52 PM PDT 24
Finished Mar 31 01:01:04 PM PDT 24
Peak memory 199628 kb
Host smart-0baa963b-c8b3-45d2-8d00-85d32a2dbd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993432338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.1993432338
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3664591595
Short name T352
Test name
Test status
Simulation time 1772964983 ps
CPU time 23.93 seconds
Started Mar 31 01:00:51 PM PDT 24
Finished Mar 31 01:01:16 PM PDT 24
Peak memory 199500 kb
Host smart-57d48357-af54-4017-a6f6-b784fc03c6cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3664591595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3664591595
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.2700869513
Short name T32
Test name
Test status
Simulation time 12342272302 ps
CPU time 154.88 seconds
Started Mar 31 01:00:54 PM PDT 24
Finished Mar 31 01:03:29 PM PDT 24
Peak memory 199744 kb
Host smart-f95c8acc-ced4-4ea7-870b-3340a5323c89
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700869513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2700869513
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.811544266
Short name T286
Test name
Test status
Simulation time 1991856857 ps
CPU time 39.15 seconds
Started Mar 31 01:00:55 PM PDT 24
Finished Mar 31 01:01:35 PM PDT 24
Peak memory 199640 kb
Host smart-1d937e03-13f7-49ec-b9fe-2511e5acabb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811544266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.811544266
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.422119762
Short name T577
Test name
Test status
Simulation time 1265846629 ps
CPU time 4.17 seconds
Started Mar 31 01:00:57 PM PDT 24
Finished Mar 31 01:01:01 PM PDT 24
Peak memory 199636 kb
Host smart-1a97d1b6-4eb6-456a-9715-4a67942775b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422119762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.422119762
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.959287894
Short name T206
Test name
Test status
Simulation time 59520755823 ps
CPU time 576.68 seconds
Started Mar 31 01:00:56 PM PDT 24
Finished Mar 31 01:10:33 PM PDT 24
Peak memory 232392 kb
Host smart-ef3a9637-17a9-4d69-9551-f31d54524c1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959287894 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.959287894
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.4181016393
Short name T196
Test name
Test status
Simulation time 73714203 ps
CPU time 1.42 seconds
Started Mar 31 01:00:53 PM PDT 24
Finished Mar 31 01:00:54 PM PDT 24
Peak memory 199624 kb
Host smart-e3eff0bd-d7fe-4eeb-a77d-a180d52f649f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181016393 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.4181016393
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.2629693368
Short name T303
Test name
Test status
Simulation time 130813738382 ps
CPU time 567.92 seconds
Started Mar 31 01:00:53 PM PDT 24
Finished Mar 31 01:10:21 PM PDT 24
Peak memory 199612 kb
Host smart-cf9bead6-602e-4cc8-ba89-8bc270481820
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629693368 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.2629693368
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3036149193
Short name T27
Test name
Test status
Simulation time 3239258476 ps
CPU time 47.65 seconds
Started Mar 31 01:00:57 PM PDT 24
Finished Mar 31 01:01:45 PM PDT 24
Peak memory 199676 kb
Host smart-7178384d-f895-440a-a1dc-bdf82d2ea81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036149193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3036149193
Directory /workspace/9.hmac_wipe_secret/latest
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