Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15302206	1			T1	14931		T2	2467		T3	72175
all_values[1]	15302206	1			T1	14931		T2	2467		T3	72175
all_values[2]	15302206	1			T1	14931		T2	2467		T3	72175

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100128

1

T1

229

T2

322

T6

576

auto[1]

45806490

1

T1

44564

T2

7079

T3

216525

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43465472

1

T1

37865

T2

7388

T3

207650

auto[1]

2441146

1

T1

6928

T2

13

T3

8875

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	35793	1			T2	320		T6	563		T13	83
all_values[0]	auto[0]	auto[1]	479	1			T2	2		T6	4		T13	5
all_values[0]	auto[1]	auto[0]	15216195	1			T1	14921		T2	2134		T3	71981
all_values[0]	auto[1]	auto[1]	49739	1			T1	10		T2	11		T3	194
all_values[1]	auto[0]	auto[0]	27996	1			T13	5		T39	24		T19	8
all_values[1]	auto[0]	auto[1]	169	1			T51	5		T16	3		T17	6
all_values[1]	auto[1]	auto[0]	15273641	1			T1	14931		T2	2467		T3	72175
all_values[1]	auto[1]	auto[1]	400	1			T6	3		T13	9		T26	1
all_values[2]	auto[0]	auto[0]	26028	1			T1	229		T6	9		T13	4
all_values[2]	auto[0]	auto[1]	9663	1			T13	716		T51	3		T16	1
all_values[2]	auto[1]	auto[0]	12885819	1			T1	7784		T2	2467		T3	63494
all_values[2]	auto[1]	auto[1]	2380696	1			T1	6918		T3	8681		T4	9616