Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7430704

1

T1

552

T2

1932

T3

37275

auto[1]

2542225

1

T1

3931

T2

507

T5

117

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2518904

1

T1

2863

T2

983

T5

120

auto[1]

7454025

1

T1

1620

T2

1456

T3

37275

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6784759

1

T1

3506

T2

2000

T3

37275

auto[1]

3188170

1

T1

977

T2

439

T5

98

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6782483	1			T1	3603		T2	2113		T3	35081
fifo_depth[1]	461043	1			T1	231		T2	146		T3	1396
fifo_depth[2]	365409	1			T1	208		T2	96		T3	561
fifo_depth[3]	286341	1			T1	155		T2	56		T3	173
fifo_depth[4]	239822	1			T1	113		T2	17		T3	49
fifo_depth[5]	208260	1			T1	74		T2	9		T3	12
fifo_depth[6]	196247	1			T1	46		T2	1		T3	2
fifo_depth[7]	171343	1			T1	36		T2	1		T3	1
fifo_depth[8]	153808	1			T1	12		T6	4847		T13	2464
fifo_depth[9]	105963	1			T1	5		T6	3685		T13	1944
fifo_depth[10]	80811	1			T6	2433		T13	1852		T18	29
fifo_depth[11]	51283	1			T6	1447		T13	1702		T18	14
fifo_depth[12]	52404	1			T6	807		T13	2232		T18	3
fifo_depth[13]	28641	1			T6	399		T13	1615		T18	1
fifo_depth[14]	36091	1			T6	318		T13	2097		T18	1
fifo_depth[15]	25320	1			T6	223		T13	1686		T18	1
fifo_depth[16]	93248	1			T6	3142		T13	8282		T44	3

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3326246

1

T1

880

T2

326

T3

2194

auto[1]

6646683

1

T1

3603

T2

2113

T3

35081

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9837129

1

T1

4483

T2

2439

T3

37275

auto[1]

135800

1

T6

4238

T13

6432

T19

5

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

218732

1

T2

93

T6

2905

T13

4975

auto[0]

auto[0]

auto[0]

auto[1]

243052

1

T1

638

T2

32

T6

4771

auto[0]

auto[0]

auto[1]

auto[0]

1049002

1

T2

99

T3

2194

T4

2324

auto[0]

auto[0]

auto[1]

auto[1]

237655

1

T1

174

T2

39

T6

1352

auto[0]

auto[1]

auto[0]

auto[0]

406776

1

T1

11

T5

5

T6

13421

auto[0]

auto[1]

auto[0]

auto[1]

375453

1

T5

3

T6

13486

T13

12548

auto[0]

auto[1]

auto[1]

auto[0]

394488

1

T2

63

T5

2

T6

13610

auto[0]

auto[1]

auto[1]

auto[1]

401088

1

T1

57

T5

6

T6

8429

auto[1]

auto[0]

auto[0]

auto[0]

243203

1

T1

7

T2

649

T5

35

auto[1]

auto[0]

auto[0]

auto[1]

237400

1

T1

1598

T2

209

T5

37

auto[1]

auto[0]

auto[1]

auto[0]

4308858

1

T1

458

T2

652

T3

35081

auto[1]

auto[0]

auto[1]

auto[1]

246857

1

T1

631

T2

227

T5

28

auto[1]

auto[1]

auto[0]

auto[0]

401820

1

T1

76

T5

24

T6

3725

auto[1]

auto[1]

auto[0]

auto[1]

392468

1

T1

533

T5

16

T6

5747

auto[1]

auto[1]

auto[1]

auto[0]

407825

1

T2

376

T5

15

T6

6968

auto[1]

auto[1]

auto[1]

auto[1]

408252

1

T1

300

T5

27

T6

4211

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

449028

1

T1

7

T2

742

T5

35

auto[0]

auto[0]

auto[0]

auto[1]

462753

1

T1

2236

T2

241

T5

37

auto[0]

auto[0]

auto[1]

auto[0]

5345619

1

T1

458

T2

751

T3

37275

auto[0]

auto[0]

auto[1]

auto[1]

460023

1

T1

805

T2

266

T5

28

auto[0]

auto[1]

auto[0]

auto[0]

791023

1

T1

87

T5

29

T6

15437

auto[0]

auto[1]

auto[0]

auto[1]

749631

1

T1

533

T5

19

T6

17980

auto[0]

auto[1]

auto[1]

auto[0]

786320

1

T2

439

T5

17

T6

20023

auto[0]

auto[1]

auto[1]

auto[1]

792732

1

T1

357

T5

33

T6

12563

auto[1]

auto[0]

auto[0]

auto[0]

12907

1

T6

247

T13

160

T19

1

auto[1]

auto[0]

auto[0]

auto[1]

17699

1

T6

348

T13

828

T26

501

auto[1]

auto[0]

auto[1]

auto[0]

12241

1

T6

49

T13

1295

T20

1

auto[1]

auto[0]

auto[1]

auto[1]

24489

1

T13

271

T26

245

T21

1

auto[1]

auto[1]

auto[0]

auto[0]

17573

1

T6

1709

T13

498

T26

61

auto[1]

auto[1]

auto[0]

auto[1]

18290

1

T6

1253

T13

1783

T19

3

auto[1]

auto[1]

auto[1]

auto[0]

15993

1

T6

555

T13

559

T20

1

auto[1]

auto[1]

auto[1]

auto[1]

16608

1

T6

77

T13

1038

T19

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	256110	1			T1	7		T2	649		T5	35
fifo_depth[0]	auto[0]	auto[0]	auto[1]	255099	1			T1	1598		T2	209		T5	37
fifo_depth[0]	auto[0]	auto[1]	auto[0]	4321099	1			T1	458		T2	652		T3	35081
fifo_depth[0]	auto[0]	auto[1]	auto[1]	271346	1			T1	631		T2	227		T5	28
fifo_depth[0]	auto[1]	auto[0]	auto[0]	419393	1			T1	76		T5	24		T6	5434
fifo_depth[0]	auto[1]	auto[0]	auto[1]	410758	1			T1	533		T5	16		T6	7000
fifo_depth[0]	auto[1]	auto[1]	auto[0]	423818	1			T2	376		T5	15		T6	7523
fifo_depth[0]	auto[1]	auto[1]	auto[1]	424860	1			T1	300		T5	27		T6	4288
fifo_depth[1]	auto[0]	auto[0]	auto[0]	17798	1			T2	36		T6	176		T13	137
fifo_depth[1]	auto[0]	auto[0]	auto[1]	17816	1			T1	133		T2	19		T6	198
fifo_depth[1]	auto[0]	auto[1]	auto[0]	243013	1			T2	44		T3	1396		T4	1434
fifo_depth[1]	auto[0]	auto[1]	auto[1]	18417	1			T1	74		T2	17		T6	138
fifo_depth[1]	auto[1]	auto[0]	auto[0]	41705	1			T1	5		T5	3		T6	820
fifo_depth[1]	auto[1]	auto[0]	auto[1]	39741	1			T5	3		T6	1168		T13	399
fifo_depth[1]	auto[1]	auto[1]	auto[0]	41701	1			T2	30		T6	1466		T13	281
fifo_depth[1]	auto[1]	auto[1]	auto[1]	40852	1			T1	19		T5	4		T6	833
fifo_depth[2]	auto[0]	auto[0]	auto[0]	14758	1			T2	31		T6	171		T13	137
fifo_depth[2]	auto[0]	auto[0]	auto[1]	15244	1			T1	134		T2	9		T6	228
fifo_depth[2]	auto[0]	auto[1]	auto[0]	177847	1			T2	30		T3	561		T4	537
fifo_depth[2]	auto[0]	auto[1]	auto[1]	14714	1			T1	45		T2	9		T6	152
fifo_depth[2]	auto[1]	auto[0]	auto[0]	36410	1			T1	4		T5	2		T6	758
fifo_depth[2]	auto[1]	auto[0]	auto[1]	34484	1			T6	1187		T13	400		T27	9
fifo_depth[2]	auto[1]	auto[1]	auto[0]	36071	1			T2	17		T5	1		T6	1411
fifo_depth[2]	auto[1]	auto[1]	auto[1]	35881	1			T1	25		T5	2		T6	849
fifo_depth[3]	auto[0]	auto[0]	auto[0]	10886	1			T2	15		T6	149		T13	101
fifo_depth[3]	auto[0]	auto[0]	auto[1]	11790	1			T1	110		T2	3		T6	218
fifo_depth[3]	auto[0]	auto[1]	auto[0]	130995	1			T2	22		T3	173		T4	248
fifo_depth[3]	auto[0]	auto[1]	auto[1]	11416	1			T1	34		T2	6		T6	141
fifo_depth[3]	auto[1]	auto[0]	auto[0]	31349	1			T1	1		T6	830		T13	500
fifo_depth[3]	auto[1]	auto[0]	auto[1]	29148	1			T6	1171		T13	456		T18	25
fifo_depth[3]	auto[1]	auto[1]	auto[0]	30704	1			T2	10		T5	1		T6	1480
fifo_depth[3]	auto[1]	auto[1]	auto[1]	30053	1			T1	10		T6	832		T13	496
fifo_depth[4]	auto[0]	auto[0]	auto[0]	10088	1			T2	8		T6	157		T13	58
fifo_depth[4]	auto[0]	auto[0]	auto[1]	11266	1			T1	94		T6	270		T13	18
fifo_depth[4]	auto[0]	auto[1]	auto[0]	94414	1			T2	2		T3	49		T4	68
fifo_depth[4]	auto[0]	auto[1]	auto[1]	10311	1			T1	16		T2	4		T6	150
fifo_depth[4]	auto[1]	auto[0]	auto[0]	30312	1			T1	1		T6	818		T13	511
fifo_depth[4]	auto[1]	auto[0]	auto[1]	26851	1			T6	1164		T13	434		T18	20
fifo_depth[4]	auto[1]	auto[1]	auto[0]	28372	1			T2	3		T6	1461		T13	326
fifo_depth[4]	auto[1]	auto[1]	auto[1]	28208	1			T1	2		T6	851		T13	618
fifo_depth[5]	auto[0]	auto[0]	auto[0]	8363	1			T2	2		T6	156		T13	22
fifo_depth[5]	auto[0]	auto[0]	auto[1]	9569	1			T1	68		T2	1		T6	273
fifo_depth[5]	auto[0]	auto[1]	auto[0]	76568	1			T2	1		T3	12		T4	32
fifo_depth[5]	auto[0]	auto[1]	auto[1]	8996	1			T1	5		T2	3		T6	159
fifo_depth[5]	auto[1]	auto[0]	auto[0]	27965	1			T6	775		T13	496		T27	1
fifo_depth[5]	auto[1]	auto[0]	auto[1]	24564	1			T6	1176		T13	417		T18	24
fifo_depth[5]	auto[1]	auto[1]	auto[0]	26193	1			T2	2		T6	1383		T13	315
fifo_depth[5]	auto[1]	auto[1]	auto[1]	26042	1			T1	1		T6	826		T13	530
fifo_depth[6]	auto[0]	auto[0]	auto[0]	8376	1			T6	175		T13	45		T18	39
fifo_depth[6]	auto[0]	auto[0]	auto[1]	9731	1			T1	46		T6	245		T13	96
fifo_depth[6]	auto[0]	auto[1]	auto[0]	66194	1			T3	2		T4	5		T6	2076
fifo_depth[6]	auto[0]	auto[1]	auto[1]	8953	1			T6	135		T13	125		T14	27
fifo_depth[6]	auto[1]	auto[0]	auto[0]	27683	1			T6	797		T13	484		T18	29
fifo_depth[6]	auto[1]	auto[0]	auto[1]	24274	1			T6	1169		T13	456		T18	27
fifo_depth[6]	auto[1]	auto[1]	auto[0]	25644	1			T2	1		T6	1416		T13	309
fifo_depth[6]	auto[1]	auto[1]	auto[1]	25392	1			T6	759		T13	531		T44	448
fifo_depth[7]	auto[0]	auto[0]	auto[0]	7460	1			T2	1		T6	155		T13	54
fifo_depth[7]	auto[0]	auto[0]	auto[1]	8810	1			T1	36		T6	234		T13	73
fifo_depth[7]	auto[0]	auto[1]	auto[0]	52366	1			T3	1		T6	1763		T13	42
fifo_depth[7]	auto[0]	auto[1]	auto[1]	8064	1			T6	143		T13	43		T14	27
fifo_depth[7]	auto[1]	auto[0]	auto[0]	25044	1			T6	719		T13	456		T18	28
fifo_depth[7]	auto[1]	auto[0]	auto[1]	22359	1			T6	1083		T13	442		T18	15
fifo_depth[7]	auto[1]	auto[1]	auto[0]	23657	1			T6	1242		T13	323		T18	28
fifo_depth[7]	auto[1]	auto[1]	auto[1]	23583	1			T6	772		T13	499		T44	363
fifo_depth[8]	auto[0]	auto[0]	auto[0]	7372	1			T6	143		T13	169		T18	4
fifo_depth[8]	auto[0]	auto[0]	auto[1]	9260	1			T1	12		T6	195		T13	256
fifo_depth[8]	auto[0]	auto[1]	auto[0]	39889	1			T6	1272		T13	81		T14	33
fifo_depth[8]	auto[0]	auto[1]	auto[1]	9087	1			T6	119		T13	294		T14	22
fifo_depth[8]	auto[1]	auto[0]	auto[0]	23058	1			T6	547		T13	441		T18	32
fifo_depth[8]	auto[1]	auto[0]	auto[1]	20268	1			T6	833		T13	346		T18	4
fifo_depth[8]	auto[1]	auto[1]	auto[0]	22545	1			T6	1102		T13	337		T18	17
fifo_depth[8]	auto[1]	auto[1]	auto[1]	22329	1			T6	636		T13	540		T44	340
fifo_depth[9]	auto[0]	auto[0]	auto[0]	5105	1			T6	93		T13	172		T18	1
fifo_depth[9]	auto[0]	auto[0]	auto[1]	6311	1			T1	5		T6	167		T13	250
fifo_depth[9]	auto[0]	auto[1]	auto[0]	26722	1			T6	883		T13	34		T14	38
fifo_depth[9]	auto[0]	auto[1]	auto[1]	5385	1			T6	95		T13	113		T14	15
fifo_depth[9]	auto[1]	auto[0]	auto[0]	16806	1			T6	495		T13	317		T18	25
fifo_depth[9]	auto[1]	auto[0]	auto[1]	14096	1			T6	657		T13	343		T18	1
fifo_depth[9]	auto[1]	auto[1]	auto[0]	16163	1			T6	797		T13	307		T18	25
fifo_depth[9]	auto[1]	auto[1]	auto[1]	15375	1			T6	498		T13	408		T44	236
fifo_depth[10]	auto[0]	auto[0]	auto[0]	4951	1			T6	67		T13	153		T14	10
fifo_depth[10]	auto[0]	auto[0]	auto[1]	6163	1			T6	123		T13	259		T26	1
fifo_depth[10]	auto[0]	auto[1]	auto[0]	18124	1			T6	594		T13	50		T14	18
fifo_depth[10]	auto[0]	auto[1]	auto[1]	4632	1			T6	70		T13	259		T14	8
fifo_depth[10]	auto[1]	auto[0]	auto[0]	12598	1			T6	335		T13	227		T18	15
fifo_depth[10]	auto[1]	auto[0]	auto[1]	10837	1			T6	434		T13	259		T18	1
fifo_depth[10]	auto[1]	auto[1]	auto[0]	12034	1			T6	523		T13	251		T18	13
fifo_depth[10]	auto[1]	auto[1]	auto[1]	11472	1			T6	287		T13	394		T44	153
fifo_depth[11]	auto[0]	auto[0]	auto[0]	3114	1			T6	35		T13	217		T14	6
fifo_depth[11]	auto[0]	auto[0]	auto[1]	4359	1			T6	85		T13	308		T26	4
fifo_depth[11]	auto[0]	auto[1]	auto[0]	11085	1			T6	346		T13	83		T14	8
fifo_depth[11]	auto[0]	auto[1]	auto[1]	3063	1			T6	29		T13	157		T14	9
fifo_depth[11]	auto[1]	auto[0]	auto[0]	7639	1			T6	195		T13	197		T18	13
fifo_depth[11]	auto[1]	auto[0]	auto[1]	6722	1			T6	260		T13	248		T44	24
fifo_depth[11]	auto[1]	auto[1]	auto[0]	7922	1			T6	315		T13	240		T18	1
fifo_depth[11]	auto[1]	auto[1]	auto[1]	7379	1			T6	182		T13	252		T44	81
fifo_depth[12]	auto[0]	auto[0]	auto[0]	4580	1			T6	14		T13	288		T14	3
fifo_depth[12]	auto[0]	auto[0]	auto[1]	5968	1			T6	74		T13	288		T26	13
fifo_depth[12]	auto[0]	auto[1]	auto[0]	8649	1			T6	195		T13	27		T14	5
fifo_depth[12]	auto[0]	auto[1]	auto[1]	4385	1			T6	13		T13	405		T14	4
fifo_depth[12]	auto[1]	auto[0]	auto[0]	7395	1			T6	116		T13	272		T18	2
fifo_depth[12]	auto[1]	auto[0]	auto[1]	6366	1			T6	124		T13	384		T44	23
fifo_depth[12]	auto[1]	auto[1]	auto[0]	7050	1			T6	157		T13	145		T18	1
fifo_depth[12]	auto[1]	auto[1]	auto[1]	8011	1			T6	114		T13	423		T44	51
fifo_depth[13]	auto[0]	auto[0]	auto[0]	2470	1			T6	8		T13	281		T26	18
fifo_depth[13]	auto[0]	auto[0]	auto[1]	3663	1			T6	28		T13	303		T26	6
fifo_depth[13]	auto[0]	auto[1]	auto[0]	4294	1			T6	95		T13	83		T14	8
fifo_depth[13]	auto[0]	auto[1]	auto[1]	2422	1			T6	4		T13	218		T14	5
fifo_depth[13]	auto[1]	auto[0]	auto[0]	4070	1			T6	86		T13	144		T18	1
fifo_depth[13]	auto[1]	auto[0]	auto[1]	3675	1			T6	54		T13	209		T44	5
fifo_depth[13]	auto[1]	auto[1]	auto[0]	3933	1			T6	68		T13	158		T44	15
fifo_depth[13]	auto[1]	auto[1]	auto[1]	4114	1			T6	56		T13	219		T44	19
fifo_depth[14]	auto[0]	auto[0]	auto[0]	4463	1			T6	3		T13	250		T14	1
fifo_depth[14]	auto[0]	auto[0]	auto[1]	4983	1			T6	80		T13	346		T26	9
fifo_depth[14]	auto[0]	auto[1]	auto[0]	5251	1			T6	62		T13	106		T26	34
fifo_depth[14]	auto[0]	auto[1]	auto[1]	3120	1			T6	3		T13	305		T26	109
fifo_depth[14]	auto[1]	auto[0]	auto[0]	5114	1			T6	38		T13	183		T44	3
fifo_depth[14]	auto[1]	auto[0]	auto[1]	4215	1			T6	45		T13	337		T44	3
fifo_depth[14]	auto[1]	auto[1]	auto[0]	4365	1			T6	35		T13	129		T18	1
fifo_depth[14]	auto[1]	auto[1]	auto[1]	4580	1			T6	52		T13	441		T44	11
fifo_depth[15]	auto[0]	auto[0]	auto[0]	2654	1			T6	1		T13	278		T14	1
fifo_depth[15]	auto[0]	auto[0]	auto[1]	3796	1			T6	71		T13	363		T26	5
fifo_depth[15]	auto[0]	auto[1]	auto[0]	3164	1			T6	27		T13	135		T26	2
fifo_depth[15]	auto[0]	auto[1]	auto[1]	2214	1			T13	207		T26	9		T120	35
fifo_depth[15]	auto[1]	auto[0]	auto[0]	3234	1			T6	55		T13	98		T44	1
fifo_depth[15]	auto[1]	auto[0]	auto[1]	3143	1			T6	39		T13	187		T26	43
fifo_depth[15]	auto[1]	auto[1]	auto[0]	3385	1			T6	6		T13	169		T18	1
fifo_depth[15]	auto[1]	auto[1]	auto[1]	3730	1			T6	24		T13	249		T44	10
fifo_depth[16]	auto[0]	auto[0]	auto[0]	7837	1			T6	4		T13	218		T26	77
fifo_depth[16]	auto[0]	auto[0]	auto[1]	13872	1			T6	173		T13	540		T26	108
fifo_depth[16]	auto[0]	auto[1]	auto[0]	9118	1			T6	158		T13	126		T26	3
fifo_depth[16]	auto[0]	auto[1]	auto[1]	8685	1			T6	1		T13	322		T26	78
fifo_depth[16]	auto[1]	auto[0]	auto[0]	16352	1			T6	2379		T13	3033		T44	1
fifo_depth[16]	auto[1]	auto[0]	auto[1]	11869	1			T6	176		T13	868		T26	54
fifo_depth[16]	auto[1]	auto[1]	auto[0]	14394	1			T6	2		T13	967		T44	1
fifo_depth[16]	auto[1]	auto[1]	auto[1]	11121	1			T6	249		T13	2208		T44	1