Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	15302206	1			T1	14931		T2	2467		T3	72175
all_pins[1]	15302206	1			T1	14931		T2	2467		T3	72175
all_pins[2]	15302206	1			T1	14931		T2	2467		T3	72175

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	43474684	1			T1	37865		T2	7390		T3	207650
values[0x1]	2431934	1			T1	6928		T2	11		T3	8875
transitions[0x0=>0x1]	2431776	1			T1	6928		T2	11		T3	8875
transitions[0x1=>0x0]	2431797	1			T1	6928		T2	11		T3	8875

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	15251398	1			T1	14921		T2	2456		T3	71981
all_pins[0]	values[0x1]	50808	1			T1	10		T2	11		T3	194
all_pins[0]	transitions[0x0=>0x1]	50743	1			T1	10		T2	11		T3	194
all_pins[0]	transitions[0x1=>0x0]	2380652	1			T1	6918		T3	8681		T4	9616
all_pins[1]	values[0x0]	15301776	1			T1	14931		T2	2467		T3	72175
all_pins[1]	values[0x1]	430	1			T6	3		T13	13		T26	1
all_pins[1]	transitions[0x0=>0x1]	376	1			T6	3		T13	13		T26	1
all_pins[1]	transitions[0x1=>0x0]	50754	1			T1	10		T2	11		T3	194
all_pins[2]	values[0x0]	12921510	1			T1	8013		T2	2467		T3	63494
all_pins[2]	values[0x1]	2380696	1			T1	6918		T3	8681		T4	9616
all_pins[2]	transitions[0x0=>0x1]	2380657	1			T1	6918		T3	8681		T4	9616
all_pins[2]	transitions[0x1=>0x0]	391	1			T6	3		T13	13		T26	1