Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 848 1 T13 4 T51 18 T16 17
all_values[1] 848 1 T13 4 T51 18 T16 17
all_values[2] 848 1 T13 4 T51 18 T16 17


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1294 1 T13 9 T51 27 T16 26
auto[1] 1250 1 T13 3 T51 27 T16 25


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 913 1 T13 7 T51 9 T16 21
auto[1] 1631 1 T13 5 T51 45 T16 30


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1472 1 T13 9 T51 26 T16 29
auto[1] 1072 1 T13 3 T51 28 T16 22


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 136 1 T17 7 T112 5 T30 5
all_values[0] auto[0] auto[0] auto[1] 81 1 T13 1 T51 4 T16 1
all_values[0] auto[0] auto[1] auto[0] 161 1 T16 3 T17 5 T112 2
all_values[0] auto[0] auto[1] auto[1] 93 1 T13 1 T51 2 T16 2
all_values[0] auto[1] auto[0] auto[1] 198 1 T13 2 T51 5 T16 6
all_values[0] auto[1] auto[1] auto[1] 179 1 T51 7 T16 5 T17 4
all_values[1] auto[0] auto[0] auto[0] 152 1 T13 4 T51 3 T16 3
all_values[1] auto[0] auto[0] auto[1] 103 1 T51 3 T16 2 T17 3
all_values[1] auto[0] auto[1] auto[0] 141 1 T51 1 T16 5 T17 4
all_values[1] auto[0] auto[1] auto[1] 102 1 T51 2 T16 2 T17 5
all_values[1] auto[1] auto[0] auto[1] 182 1 T51 5 T16 3 T17 6
all_values[1] auto[1] auto[1] auto[1] 168 1 T51 4 T16 2 T17 6
all_values[2] auto[0] auto[0] auto[0] 170 1 T13 2 T51 3 T16 8
all_values[2] auto[0] auto[0] auto[1] 98 1 T51 1 T16 1 T17 1
all_values[2] auto[0] auto[1] auto[0] 153 1 T13 1 T51 2 T16 2
all_values[2] auto[0] auto[1] auto[1] 82 1 T51 5 T112 3 T30 1
all_values[2] auto[1] auto[0] auto[1] 174 1 T51 3 T16 2 T17 4
all_values[2] auto[1] auto[1] auto[1] 171 1 T13 1 T51 4 T16 4


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%