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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.58 92.46 85.39 100.00 73.68 85.93 99.49 69.08


Total test records in report: 731
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T537 /workspace/coverage/default/9.hmac_wipe_secret.3130735206 Apr 02 12:44:36 PM PDT 24 Apr 02 12:45:02 PM PDT 24 1188641441 ps
T538 /workspace/coverage/default/30.hmac_burst_wr.955466945 Apr 02 12:45:17 PM PDT 24 Apr 02 12:45:22 PM PDT 24 1084038899 ps
T539 /workspace/coverage/default/0.hmac_error.2273387541 Apr 02 12:44:06 PM PDT 24 Apr 02 12:47:45 PM PDT 24 92624693484 ps
T540 /workspace/coverage/default/35.hmac_long_msg.1802504250 Apr 02 12:45:33 PM PDT 24 Apr 02 12:45:56 PM PDT 24 1058271493 ps
T541 /workspace/coverage/default/41.hmac_test_sha_vectors.2373435395 Apr 02 12:45:52 PM PDT 24 Apr 02 12:53:26 PM PDT 24 15975004422 ps
T542 /workspace/coverage/default/17.hmac_stress_all.2168721021 Apr 02 12:44:53 PM PDT 24 Apr 02 12:58:46 PM PDT 24 84747061712 ps
T543 /workspace/coverage/default/21.hmac_test_hmac_vectors.1434220222 Apr 02 12:44:53 PM PDT 24 Apr 02 12:44:56 PM PDT 24 328780872 ps
T544 /workspace/coverage/default/40.hmac_test_hmac_vectors.2942057954 Apr 02 12:45:46 PM PDT 24 Apr 02 12:45:47 PM PDT 24 245954359 ps
T545 /workspace/coverage/default/33.hmac_wipe_secret.1286078311 Apr 02 12:45:29 PM PDT 24 Apr 02 12:46:12 PM PDT 24 13289429068 ps
T546 /workspace/coverage/default/35.hmac_error.1059353383 Apr 02 12:45:31 PM PDT 24 Apr 02 12:48:21 PM PDT 24 11046008975 ps
T547 /workspace/coverage/default/6.hmac_stress_all.2556300065 Apr 02 12:44:36 PM PDT 24 Apr 02 01:19:35 PM PDT 24 632020632218 ps
T548 /workspace/coverage/default/37.hmac_test_hmac_vectors.1663306177 Apr 02 12:45:38 PM PDT 24 Apr 02 12:45:40 PM PDT 24 207161168 ps
T549 /workspace/coverage/default/14.hmac_alert_test.2066498493 Apr 02 12:44:49 PM PDT 24 Apr 02 12:44:49 PM PDT 24 47785828 ps
T550 /workspace/coverage/default/49.hmac_datapath_stress.335416530 Apr 02 12:46:15 PM PDT 24 Apr 02 12:47:06 PM PDT 24 823072344 ps
T551 /workspace/coverage/default/5.hmac_burst_wr.1705529835 Apr 02 12:44:27 PM PDT 24 Apr 02 12:45:24 PM PDT 24 2212914702 ps
T552 /workspace/coverage/default/41.hmac_error.3084826196 Apr 02 12:45:50 PM PDT 24 Apr 02 12:46:46 PM PDT 24 3996041237 ps
T553 /workspace/coverage/default/29.hmac_long_msg.266070757 Apr 02 12:45:14 PM PDT 24 Apr 02 12:45:29 PM PDT 24 1041899490 ps
T554 /workspace/coverage/default/46.hmac_test_hmac_vectors.3898755607 Apr 02 12:46:03 PM PDT 24 Apr 02 12:46:04 PM PDT 24 31244991 ps
T555 /workspace/coverage/default/6.hmac_smoke.1499285848 Apr 02 12:44:26 PM PDT 24 Apr 02 12:44:29 PM PDT 24 1054418892 ps
T556 /workspace/coverage/default/20.hmac_error.1181449763 Apr 02 12:44:51 PM PDT 24 Apr 02 12:46:38 PM PDT 24 1935841961 ps
T557 /workspace/coverage/default/100.hmac_stress_all_with_rand_reset.663367240 Apr 02 12:46:27 PM PDT 24 Apr 02 01:07:42 PM PDT 24 44822697352 ps
T558 /workspace/coverage/default/22.hmac_error.3874218251 Apr 02 12:44:59 PM PDT 24 Apr 02 12:47:29 PM PDT 24 8361193319 ps
T559 /workspace/coverage/default/45.hmac_smoke.64922975 Apr 02 12:46:00 PM PDT 24 Apr 02 12:46:03 PM PDT 24 206467325 ps
T560 /workspace/coverage/default/4.hmac_burst_wr.3670254674 Apr 02 12:44:17 PM PDT 24 Apr 02 12:44:24 PM PDT 24 402253789 ps
T561 /workspace/coverage/default/36.hmac_wipe_secret.188608152 Apr 02 12:45:35 PM PDT 24 Apr 02 12:45:58 PM PDT 24 1098396565 ps
T562 /workspace/coverage/default/40.hmac_smoke.3200126679 Apr 02 12:45:45 PM PDT 24 Apr 02 12:45:48 PM PDT 24 517331243 ps
T563 /workspace/coverage/default/29.hmac_datapath_stress.3405521561 Apr 02 12:45:12 PM PDT 24 Apr 02 12:46:22 PM PDT 24 4795380071 ps
T37 /workspace/coverage/default/4.hmac_sec_cm.3885176619 Apr 02 12:44:26 PM PDT 24 Apr 02 12:44:28 PM PDT 24 62721416 ps
T564 /workspace/coverage/default/47.hmac_burst_wr.2516357491 Apr 02 12:46:11 PM PDT 24 Apr 02 12:46:58 PM PDT 24 5739428605 ps
T565 /workspace/coverage/default/25.hmac_error.2559525550 Apr 02 12:45:01 PM PDT 24 Apr 02 12:46:42 PM PDT 24 7570014626 ps
T47 /workspace/coverage/default/36.hmac_error.3723970203 Apr 02 12:45:36 PM PDT 24 Apr 02 12:49:58 PM PDT 24 171294911736 ps
T566 /workspace/coverage/default/4.hmac_stress_all.387836849 Apr 02 12:44:23 PM PDT 24 Apr 02 12:45:19 PM PDT 24 6296335861 ps
T567 /workspace/coverage/default/39.hmac_datapath_stress.2334883195 Apr 02 12:45:48 PM PDT 24 Apr 02 12:48:39 PM PDT 24 10747021770 ps
T568 /workspace/coverage/default/48.hmac_smoke.1495239351 Apr 02 12:46:12 PM PDT 24 Apr 02 12:46:18 PM PDT 24 1298867225 ps
T569 /workspace/coverage/default/8.hmac_datapath_stress.391402480 Apr 02 12:44:34 PM PDT 24 Apr 02 12:46:09 PM PDT 24 3112284069 ps
T570 /workspace/coverage/default/20.hmac_alert_test.2185236785 Apr 02 12:44:57 PM PDT 24 Apr 02 12:44:57 PM PDT 24 26708425 ps
T571 /workspace/coverage/default/46.hmac_burst_wr.34539621 Apr 02 12:46:07 PM PDT 24 Apr 02 12:46:27 PM PDT 24 5162663697 ps
T572 /workspace/coverage/default/3.hmac_alert_test.1167055502 Apr 02 12:44:14 PM PDT 24 Apr 02 12:44:15 PM PDT 24 15230402 ps
T573 /workspace/coverage/default/11.hmac_datapath_stress.1393415415 Apr 02 12:44:42 PM PDT 24 Apr 02 12:45:14 PM PDT 24 828695255 ps
T574 /workspace/coverage/default/19.hmac_wipe_secret.150718349 Apr 02 12:45:07 PM PDT 24 Apr 02 12:45:36 PM PDT 24 1528008599 ps
T575 /workspace/coverage/default/5.hmac_long_msg.1576933414 Apr 02 12:44:31 PM PDT 24 Apr 02 12:44:34 PM PDT 24 210944563 ps
T576 /workspace/coverage/default/45.hmac_error.1840439171 Apr 02 12:46:02 PM PDT 24 Apr 02 12:46:10 PM PDT 24 1670163835 ps
T577 /workspace/coverage/default/38.hmac_long_msg.2930716948 Apr 02 12:45:42 PM PDT 24 Apr 02 12:47:46 PM PDT 24 8431077201 ps
T578 /workspace/coverage/default/36.hmac_back_pressure.2056520331 Apr 02 12:45:36 PM PDT 24 Apr 02 12:46:20 PM PDT 24 1069941590 ps
T579 /workspace/coverage/default/42.hmac_test_sha_vectors.3441891338 Apr 02 12:46:01 PM PDT 24 Apr 02 12:53:40 PM PDT 24 131241317968 ps
T580 /workspace/coverage/default/17.hmac_datapath_stress.323768019 Apr 02 12:44:54 PM PDT 24 Apr 02 12:45:40 PM PDT 24 6960460352 ps
T581 /workspace/coverage/default/25.hmac_wipe_secret.1892126478 Apr 02 12:45:03 PM PDT 24 Apr 02 12:45:58 PM PDT 24 16403609125 ps
T582 /workspace/coverage/default/0.hmac_alert_test.4043296688 Apr 02 12:44:08 PM PDT 24 Apr 02 12:44:08 PM PDT 24 20826657 ps
T583 /workspace/coverage/default/24.hmac_datapath_stress.1411910839 Apr 02 12:44:59 PM PDT 24 Apr 02 12:45:57 PM PDT 24 1008227834 ps
T584 /workspace/coverage/default/9.hmac_datapath_stress.1635003909 Apr 02 12:44:40 PM PDT 24 Apr 02 12:45:20 PM PDT 24 1409560794 ps
T585 /workspace/coverage/default/25.hmac_back_pressure.3164285112 Apr 02 12:45:01 PM PDT 24 Apr 02 12:45:48 PM PDT 24 5270665058 ps
T38 /workspace/coverage/default/1.hmac_sec_cm.1786181006 Apr 02 12:44:10 PM PDT 24 Apr 02 12:44:12 PM PDT 24 83686213 ps
T586 /workspace/coverage/default/18.hmac_wipe_secret.4169781092 Apr 02 12:44:52 PM PDT 24 Apr 02 12:45:52 PM PDT 24 17586677961 ps
T587 /workspace/coverage/default/20.hmac_smoke.2305793467 Apr 02 12:44:54 PM PDT 24 Apr 02 12:44:58 PM PDT 24 208357711 ps
T588 /workspace/coverage/default/22.hmac_test_hmac_vectors.2802138279 Apr 02 12:44:58 PM PDT 24 Apr 02 12:44:59 PM PDT 24 52298135 ps
T589 /workspace/coverage/default/17.hmac_test_sha_vectors.2222542591 Apr 02 12:44:54 PM PDT 24 Apr 02 12:53:55 PM PDT 24 58074269218 ps
T590 /workspace/coverage/default/38.hmac_back_pressure.1831119512 Apr 02 12:45:40 PM PDT 24 Apr 02 12:45:46 PM PDT 24 262146960 ps
T591 /workspace/coverage/default/11.hmac_test_sha_vectors.3737671067 Apr 02 12:44:43 PM PDT 24 Apr 02 12:53:14 PM PDT 24 256053325588 ps
T592 /workspace/coverage/default/15.hmac_alert_test.785220953 Apr 02 12:44:52 PM PDT 24 Apr 02 12:44:52 PM PDT 24 29569534 ps
T48 /workspace/coverage/default/26.hmac_error.3543793937 Apr 02 12:45:06 PM PDT 24 Apr 02 12:47:47 PM PDT 24 8497869199 ps
T593 /workspace/coverage/default/15.hmac_burst_wr.1453550941 Apr 02 12:44:49 PM PDT 24 Apr 02 12:44:51 PM PDT 24 112127304 ps
T594 /workspace/coverage/default/9.hmac_test_sha_vectors.3583417020 Apr 02 12:44:38 PM PDT 24 Apr 02 12:53:36 PM PDT 24 43707865229 ps
T595 /workspace/coverage/default/31.hmac_test_hmac_vectors.3739669128 Apr 02 12:45:23 PM PDT 24 Apr 02 12:45:26 PM PDT 24 56918534 ps
T596 /workspace/coverage/default/12.hmac_long_msg.4228135210 Apr 02 12:44:40 PM PDT 24 Apr 02 12:45:25 PM PDT 24 11188064595 ps
T597 /workspace/coverage/default/36.hmac_smoke.995091094 Apr 02 12:45:36 PM PDT 24 Apr 02 12:45:45 PM PDT 24 853873248 ps
T598 /workspace/coverage/default/15.hmac_long_msg.3896452066 Apr 02 12:44:53 PM PDT 24 Apr 02 12:45:21 PM PDT 24 1344203663 ps
T599 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3747197930 Apr 02 12:23:59 PM PDT 24 Apr 02 12:24:03 PM PDT 24 71875633 ps
T600 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1315922594 Apr 02 12:23:17 PM PDT 24 Apr 02 12:23:18 PM PDT 24 16389081 ps
T65 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.308548560 Apr 02 12:22:05 PM PDT 24 Apr 02 12:22:06 PM PDT 24 36732026 ps
T61 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2254407466 Apr 02 12:22:11 PM PDT 24 Apr 02 12:22:15 PM PDT 24 259374687 ps
T601 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1297739600 Apr 02 12:23:08 PM PDT 24 Apr 02 12:23:08 PM PDT 24 12489302 ps
T66 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1440001637 Apr 02 12:21:57 PM PDT 24 Apr 02 12:21:58 PM PDT 24 66603372 ps
T84 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.359907072 Apr 02 12:23:43 PM PDT 24 Apr 02 12:23:44 PM PDT 24 95910198 ps
T62 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2706957767 Apr 02 12:22:52 PM PDT 24 Apr 02 12:22:54 PM PDT 24 998460481 ps
T85 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2588493285 Apr 02 12:24:06 PM PDT 24 Apr 02 12:34:45 PM PDT 24 132370695828 ps
T602 /workspace/coverage/cover_reg_top/24.hmac_intr_test.331611682 Apr 02 12:23:13 PM PDT 24 Apr 02 12:23:13 PM PDT 24 39536840 ps
T603 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1877422627 Apr 02 12:22:49 PM PDT 24 Apr 02 12:22:51 PM PDT 24 45530541 ps
T604 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1213454381 Apr 02 12:23:34 PM PDT 24 Apr 02 12:23:35 PM PDT 24 25643670 ps
T605 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3104822716 Apr 02 12:22:43 PM PDT 24 Apr 02 12:22:54 PM PDT 24 3182022492 ps
T606 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3686070885 Apr 02 12:22:53 PM PDT 24 Apr 02 12:22:56 PM PDT 24 560376906 ps
T607 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3233232105 Apr 02 12:22:33 PM PDT 24 Apr 02 12:22:36 PM PDT 24 470001670 ps
T608 /workspace/coverage/cover_reg_top/18.hmac_intr_test.3381381477 Apr 02 12:22:52 PM PDT 24 Apr 02 12:22:53 PM PDT 24 12127421 ps
T609 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2309033179 Apr 02 12:24:07 PM PDT 24 Apr 02 12:24:09 PM PDT 24 12935819 ps
T86 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1510961187 Apr 02 12:22:47 PM PDT 24 Apr 02 12:22:50 PM PDT 24 749608075 ps
T87 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3222352820 Apr 02 12:22:57 PM PDT 24 Apr 02 12:22:58 PM PDT 24 55786360 ps
T610 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.4179417208 Apr 02 12:24:05 PM PDT 24 Apr 02 12:24:07 PM PDT 24 767150002 ps
T88 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.772723233 Apr 02 12:22:33 PM PDT 24 Apr 02 12:22:39 PM PDT 24 385404471 ps
T611 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2689825238 Apr 02 12:23:12 PM PDT 24 Apr 02 12:23:14 PM PDT 24 95295971 ps
T612 /workspace/coverage/cover_reg_top/43.hmac_intr_test.180020772 Apr 02 12:23:08 PM PDT 24 Apr 02 12:23:09 PM PDT 24 14512238 ps
T613 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1817463038 Apr 02 12:22:49 PM PDT 24 Apr 02 12:22:52 PM PDT 24 71328342 ps
T614 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3096530488 Apr 02 12:22:43 PM PDT 24 Apr 02 12:22:45 PM PDT 24 22992964 ps
T615 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.360018590 Apr 02 12:22:09 PM PDT 24 Apr 02 12:22:10 PM PDT 24 71024917 ps
T99 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2314607812 Apr 02 12:22:56 PM PDT 24 Apr 02 12:22:57 PM PDT 24 113540592 ps
T616 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3670363749 Apr 02 12:22:58 PM PDT 24 Apr 02 12:22:59 PM PDT 24 215517075 ps
T617 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3436021514 Apr 02 12:21:39 PM PDT 24 Apr 02 12:21:45 PM PDT 24 751277473 ps
T100 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.94699580 Apr 02 12:22:39 PM PDT 24 Apr 02 12:22:45 PM PDT 24 441304417 ps
T618 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.461858652 Apr 02 12:22:40 PM PDT 24 Apr 02 12:22:42 PM PDT 24 101468387 ps
T619 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1345633369 Apr 02 12:22:27 PM PDT 24 Apr 02 12:22:29 PM PDT 24 164092547 ps
T620 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3268511050 Apr 02 12:23:13 PM PDT 24 Apr 02 12:23:13 PM PDT 24 23151151 ps
T101 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2420125576 Apr 02 12:21:22 PM PDT 24 Apr 02 12:21:23 PM PDT 24 22250212 ps
T621 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1716471354 Apr 02 12:20:58 PM PDT 24 Apr 02 12:21:00 PM PDT 24 234496341 ps
T622 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1908164520 Apr 02 12:22:33 PM PDT 24 Apr 02 12:22:35 PM PDT 24 41594838 ps
T63 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1009536147 Apr 02 12:21:43 PM PDT 24 Apr 02 12:21:46 PM PDT 24 356050540 ps
T623 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2242905212 Apr 02 12:22:46 PM PDT 24 Apr 02 12:22:47 PM PDT 24 107947542 ps
T624 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3741523868 Apr 02 12:24:07 PM PDT 24 Apr 02 12:24:08 PM PDT 24 103526336 ps
T625 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2519739997 Apr 02 12:22:36 PM PDT 24 Apr 02 12:22:38 PM PDT 24 393789770 ps
T113 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1986231390 Apr 02 12:22:43 PM PDT 24 Apr 02 12:22:46 PM PDT 24 84232822 ps
T626 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1011934663 Apr 02 12:23:02 PM PDT 24 Apr 02 12:23:03 PM PDT 24 53965851 ps
T627 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3178156778 Apr 02 12:21:50 PM PDT 24 Apr 02 12:21:51 PM PDT 24 38271346 ps
T628 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2929853265 Apr 02 12:22:29 PM PDT 24 Apr 02 12:22:31 PM PDT 24 61323145 ps
T629 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2654176411 Apr 02 12:22:19 PM PDT 24 Apr 02 12:22:20 PM PDT 24 200249484 ps
T630 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.619516386 Apr 02 12:22:17 PM PDT 24 Apr 02 12:31:19 PM PDT 24 56148231658 ps
T631 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1856379811 Apr 02 12:22:54 PM PDT 24 Apr 02 12:22:59 PM PDT 24 111877914 ps
T632 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1962655481 Apr 02 12:22:33 PM PDT 24 Apr 02 12:22:34 PM PDT 24 82945102 ps
T633 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.4271592890 Apr 02 12:22:02 PM PDT 24 Apr 02 12:22:03 PM PDT 24 36264262 ps
T102 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3477982006 Apr 02 12:23:08 PM PDT 24 Apr 02 12:23:09 PM PDT 24 72304257 ps
T634 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2132251675 Apr 02 12:21:24 PM PDT 24 Apr 02 12:21:24 PM PDT 24 44135136 ps
T635 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.418958464 Apr 02 12:22:48 PM PDT 24 Apr 02 12:22:50 PM PDT 24 91840578 ps
T636 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1669226732 Apr 02 12:23:04 PM PDT 24 Apr 02 12:23:06 PM PDT 24 84195402 ps
T103 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2713934238 Apr 02 12:22:24 PM PDT 24 Apr 02 12:22:25 PM PDT 24 14785660 ps
T637 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3992460130 Apr 02 12:21:55 PM PDT 24 Apr 02 12:21:56 PM PDT 24 21423581 ps
T638 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1134741636 Apr 02 12:22:38 PM PDT 24 Apr 02 12:22:41 PM PDT 24 78738311 ps
T104 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3333765241 Apr 02 12:22:51 PM PDT 24 Apr 02 12:22:52 PM PDT 24 17495755 ps
T105 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1589476054 Apr 02 12:22:39 PM PDT 24 Apr 02 12:22:40 PM PDT 24 18939914 ps
T106 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1978583818 Apr 02 12:22:51 PM PDT 24 Apr 02 12:22:57 PM PDT 24 989657501 ps
T114 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1615142148 Apr 02 12:23:40 PM PDT 24 Apr 02 12:23:45 PM PDT 24 865031721 ps
T639 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3563166415 Apr 02 12:24:06 PM PDT 24 Apr 02 12:24:07 PM PDT 24 38710159 ps
T116 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3800084614 Apr 02 12:22:00 PM PDT 24 Apr 02 12:22:04 PM PDT 24 183577116 ps
T640 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2363442274 Apr 02 12:22:36 PM PDT 24 Apr 02 12:22:39 PM PDT 24 1501668051 ps
T641 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.321362461 Apr 02 12:21:55 PM PDT 24 Apr 02 12:21:58 PM PDT 24 44624867 ps
T642 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1421029288 Apr 02 12:21:58 PM PDT 24 Apr 02 12:22:00 PM PDT 24 26021556 ps
T643 /workspace/coverage/cover_reg_top/26.hmac_intr_test.336460090 Apr 02 12:24:18 PM PDT 24 Apr 02 12:24:19 PM PDT 24 54191174 ps
T644 /workspace/coverage/cover_reg_top/49.hmac_intr_test.1183461501 Apr 02 12:23:17 PM PDT 24 Apr 02 12:23:18 PM PDT 24 11375098 ps
T645 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2764934715 Apr 02 12:23:42 PM PDT 24 Apr 02 12:23:43 PM PDT 24 25829816 ps
T646 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.673754579 Apr 02 12:24:09 PM PDT 24 Apr 02 12:24:12 PM PDT 24 138691791 ps
T647 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3833807065 Apr 02 12:21:34 PM PDT 24 Apr 02 12:21:42 PM PDT 24 606269382 ps
T107 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2922443178 Apr 02 12:21:46 PM PDT 24 Apr 02 12:21:47 PM PDT 24 42875558 ps
T648 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3505678981 Apr 02 12:22:44 PM PDT 24 Apr 02 12:22:47 PM PDT 24 2564193184 ps
T649 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1988117481 Apr 02 12:23:44 PM PDT 24 Apr 02 12:23:46 PM PDT 24 400762636 ps
T650 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3092737459 Apr 02 12:24:15 PM PDT 24 Apr 02 12:24:15 PM PDT 24 41974081 ps
T651 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3648974205 Apr 02 12:23:36 PM PDT 24 Apr 02 12:23:39 PM PDT 24 146599136 ps
T652 /workspace/coverage/cover_reg_top/17.hmac_intr_test.3355159797 Apr 02 12:24:06 PM PDT 24 Apr 02 12:24:07 PM PDT 24 14709446 ps
T653 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1021624901 Apr 02 12:22:23 PM PDT 24 Apr 02 12:22:24 PM PDT 24 81724088 ps
T654 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3303286440 Apr 02 12:22:34 PM PDT 24 Apr 02 12:22:38 PM PDT 24 2271414319 ps
T117 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2794544222 Apr 02 12:23:59 PM PDT 24 Apr 02 12:24:03 PM PDT 24 468062132 ps
T655 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1382139540 Apr 02 12:24:06 PM PDT 24 Apr 02 12:24:07 PM PDT 24 32089396 ps
T656 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2475440332 Apr 02 12:22:55 PM PDT 24 Apr 02 12:22:56 PM PDT 24 39754551 ps
T657 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2972139078 Apr 02 12:22:53 PM PDT 24 Apr 02 12:22:55 PM PDT 24 25170680 ps
T64 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2291025291 Apr 02 12:22:44 PM PDT 24 Apr 02 12:22:48 PM PDT 24 126962222 ps
T658 /workspace/coverage/cover_reg_top/47.hmac_intr_test.2919952984 Apr 02 12:23:08 PM PDT 24 Apr 02 12:23:09 PM PDT 24 26776331 ps
T659 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1582485392 Apr 02 12:21:44 PM PDT 24 Apr 02 12:21:46 PM PDT 24 588320900 ps
T660 /workspace/coverage/cover_reg_top/40.hmac_intr_test.473592636 Apr 02 12:24:10 PM PDT 24 Apr 02 12:24:11 PM PDT 24 24805429 ps
T661 /workspace/coverage/cover_reg_top/37.hmac_intr_test.689714165 Apr 02 12:23:13 PM PDT 24 Apr 02 12:23:14 PM PDT 24 14726706 ps
T662 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1003773598 Apr 02 12:23:43 PM PDT 24 Apr 02 12:23:45 PM PDT 24 486096095 ps
T108 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3343096527 Apr 02 12:23:36 PM PDT 24 Apr 02 12:23:37 PM PDT 24 95346176 ps
T663 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.166542215 Apr 02 12:22:34 PM PDT 24 Apr 02 12:22:36 PM PDT 24 46361539 ps
T664 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.4184061918 Apr 02 12:24:00 PM PDT 24 Apr 02 12:24:04 PM PDT 24 257437073 ps
T665 /workspace/coverage/cover_reg_top/20.hmac_intr_test.307786340 Apr 02 12:24:07 PM PDT 24 Apr 02 12:24:08 PM PDT 24 26649894 ps
T666 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1916608401 Apr 02 12:23:44 PM PDT 24 Apr 02 12:23:47 PM PDT 24 150961639 ps
T115 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3206631530 Apr 02 12:23:48 PM PDT 24 Apr 02 12:23:52 PM PDT 24 765922478 ps
T667 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3490324571 Apr 02 12:23:08 PM PDT 24 Apr 02 12:23:08 PM PDT 24 91274064 ps
T668 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1603907451 Apr 02 12:22:30 PM PDT 24 Apr 02 12:22:32 PM PDT 24 231389882 ps
T669 /workspace/coverage/cover_reg_top/6.hmac_intr_test.4085568062 Apr 02 12:22:38 PM PDT 24 Apr 02 12:22:39 PM PDT 24 37721791 ps
T109 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1860943005 Apr 02 12:22:24 PM PDT 24 Apr 02 12:22:25 PM PDT 24 83006555 ps
T670 /workspace/coverage/cover_reg_top/21.hmac_intr_test.661878020 Apr 02 12:24:21 PM PDT 24 Apr 02 12:24:21 PM PDT 24 16782009 ps
T671 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2367353834 Apr 02 12:21:44 PM PDT 24 Apr 02 12:21:45 PM PDT 24 68890246 ps
T672 /workspace/coverage/cover_reg_top/29.hmac_intr_test.1338631795 Apr 02 12:23:08 PM PDT 24 Apr 02 12:23:09 PM PDT 24 50268947 ps
T673 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1662268142 Apr 02 12:23:04 PM PDT 24 Apr 02 12:23:07 PM PDT 24 163360041 ps
T674 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3216669902 Apr 02 12:22:23 PM PDT 24 Apr 02 12:22:26 PM PDT 24 90265723 ps
T675 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2683980171 Apr 02 12:21:17 PM PDT 24 Apr 02 12:21:29 PM PDT 24 11764304456 ps
T676 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.405051451 Apr 02 12:22:37 PM PDT 24 Apr 02 12:22:41 PM PDT 24 261078941 ps
T677 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1537214252 Apr 02 12:23:05 PM PDT 24 Apr 02 12:23:05 PM PDT 24 55832516 ps
T118 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1639225750 Apr 02 12:21:37 PM PDT 24 Apr 02 12:21:39 PM PDT 24 105222682 ps
T678 /workspace/coverage/cover_reg_top/22.hmac_intr_test.348729119 Apr 02 12:23:06 PM PDT 24 Apr 02 12:23:07 PM PDT 24 17581423 ps
T679 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3311493423 Apr 02 12:22:45 PM PDT 24 Apr 02 12:22:46 PM PDT 24 36879771 ps
T680 /workspace/coverage/cover_reg_top/1.hmac_intr_test.452220984 Apr 02 12:24:02 PM PDT 24 Apr 02 12:24:03 PM PDT 24 27505990 ps
T681 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2553584407 Apr 02 12:24:06 PM PDT 24 Apr 02 12:24:09 PM PDT 24 236606727 ps
T682 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3268152340 Apr 02 12:22:57 PM PDT 24 Apr 02 12:22:59 PM PDT 24 149201839 ps
T683 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3100751483 Apr 02 12:23:17 PM PDT 24 Apr 02 12:23:18 PM PDT 24 14093066 ps
T684 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2407434462 Apr 02 12:22:50 PM PDT 24 Apr 02 12:22:54 PM PDT 24 784970551 ps
T110 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.565616593 Apr 02 12:21:27 PM PDT 24 Apr 02 12:21:28 PM PDT 24 120355581 ps
T685 /workspace/coverage/cover_reg_top/9.hmac_intr_test.24670850 Apr 02 12:23:17 PM PDT 24 Apr 02 12:23:19 PM PDT 24 43387916 ps
T686 /workspace/coverage/cover_reg_top/14.hmac_intr_test.3086885360 Apr 02 12:22:36 PM PDT 24 Apr 02 12:22:37 PM PDT 24 25108557 ps
T111 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1609779827 Apr 02 12:22:14 PM PDT 24 Apr 02 12:22:16 PM PDT 24 23917966 ps
T687 /workspace/coverage/cover_reg_top/11.hmac_intr_test.2159306493 Apr 02 12:23:28 PM PDT 24 Apr 02 12:23:30 PM PDT 24 49150063 ps
T688 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2196110311 Apr 02 12:23:13 PM PDT 24 Apr 02 12:23:15 PM PDT 24 49794831 ps
T689 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.382861812 Apr 02 12:22:00 PM PDT 24 Apr 02 12:22:04 PM PDT 24 706278926 ps
T690 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3807020982 Apr 02 12:21:55 PM PDT 24 Apr 02 12:21:56 PM PDT 24 18223574 ps
T691 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2378506559 Apr 02 12:23:43 PM PDT 24 Apr 02 12:23:44 PM PDT 24 23538438 ps
T692 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.232399536 Apr 02 12:22:02 PM PDT 24 Apr 02 12:22:51 PM PDT 24 2876030665 ps
T693 /workspace/coverage/cover_reg_top/10.hmac_intr_test.2694829909 Apr 02 12:23:17 PM PDT 24 Apr 02 12:23:19 PM PDT 24 15277408 ps
T694 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1476111617 Apr 02 12:22:35 PM PDT 24 Apr 02 12:22:37 PM PDT 24 499280257 ps
T695 /workspace/coverage/cover_reg_top/3.hmac_intr_test.1702981132 Apr 02 12:22:24 PM PDT 24 Apr 02 12:22:25 PM PDT 24 22803413 ps
T696 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3447073865 Apr 02 12:22:49 PM PDT 24 Apr 02 12:22:52 PM PDT 24 407305026 ps
T697 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2944733050 Apr 02 12:22:23 PM PDT 24 Apr 02 12:22:24 PM PDT 24 17927457 ps
T698 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1237386814 Apr 02 12:23:12 PM PDT 24 Apr 02 12:23:15 PM PDT 24 108719982 ps
T119 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2340852710 Apr 02 12:22:30 PM PDT 24 Apr 02 12:22:32 PM PDT 24 89457793 ps
T699 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.4101478590 Apr 02 12:23:00 PM PDT 24 Apr 02 12:23:01 PM PDT 24 155228096 ps
T700 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3043364205 Apr 02 12:21:18 PM PDT 24 Apr 02 12:21:19 PM PDT 24 44636170 ps
T701 /workspace/coverage/cover_reg_top/48.hmac_intr_test.4185358112 Apr 02 12:23:08 PM PDT 24 Apr 02 12:23:09 PM PDT 24 117582916 ps
T702 /workspace/coverage/cover_reg_top/28.hmac_intr_test.3667317939 Apr 02 12:22:57 PM PDT 24 Apr 02 12:22:58 PM PDT 24 16471325 ps
T703 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1874203442 Apr 02 12:21:57 PM PDT 24 Apr 02 12:35:13 PM PDT 24 83220744612 ps
T704 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3804836965 Apr 02 12:22:39 PM PDT 24 Apr 02 12:22:41 PM PDT 24 784376196 ps
T705 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1332034160 Apr 02 12:20:57 PM PDT 24 Apr 02 12:21:00 PM PDT 24 190509498 ps
T706 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.25317487 Apr 02 12:23:34 PM PDT 24 Apr 02 12:23:36 PM PDT 24 31955158 ps
T707 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1504773432 Apr 02 12:22:29 PM PDT 24 Apr 02 12:22:30 PM PDT 24 21113742 ps
T708 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3728011022 Apr 02 12:22:43 PM PDT 24 Apr 02 12:22:46 PM PDT 24 188015426 ps
T709 /workspace/coverage/cover_reg_top/7.hmac_intr_test.3771328200 Apr 02 12:21:55 PM PDT 24 Apr 02 12:21:56 PM PDT 24 32589171 ps
T710 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.996086617 Apr 02 12:23:49 PM PDT 24 Apr 02 12:23:51 PM PDT 24 31125846 ps
T711 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.4262534022 Apr 02 12:21:34 PM PDT 24 Apr 02 12:21:35 PM PDT 24 148603643 ps
T67 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2068299545 Apr 02 12:22:36 PM PDT 24 Apr 02 12:22:40 PM PDT 24 3127575446 ps
T712 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3699044750 Apr 02 12:23:08 PM PDT 24 Apr 02 12:23:09 PM PDT 24 15900700 ps
T713 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2707175140 Apr 02 12:22:15 PM PDT 24 Apr 02 12:22:17 PM PDT 24 237492471 ps
T714 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1293007350 Apr 02 12:23:34 PM PDT 24 Apr 02 12:23:35 PM PDT 24 244594856 ps
T715 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1172887886 Apr 02 12:23:08 PM PDT 24 Apr 02 12:23:09 PM PDT 24 59428694 ps
T716 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1357035871 Apr 02 12:22:40 PM PDT 24 Apr 02 12:22:43 PM PDT 24 796320141 ps
T717 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.499270271 Apr 02 12:24:21 PM PDT 24 Apr 02 12:24:23 PM PDT 24 202312512 ps
T718 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2680327611 Apr 02 12:22:35 PM PDT 24 Apr 02 12:22:36 PM PDT 24 42376054 ps
T719 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3198407041 Apr 02 12:23:09 PM PDT 24 Apr 02 12:23:11 PM PDT 24 146000020 ps
T720 /workspace/coverage/cover_reg_top/0.hmac_intr_test.3935544033 Apr 02 12:22:33 PM PDT 24 Apr 02 12:22:34 PM PDT 24 19732807 ps
T721 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2740908436 Apr 02 12:23:43 PM PDT 24 Apr 02 12:23:44 PM PDT 24 14634668 ps
T722 /workspace/coverage/cover_reg_top/35.hmac_intr_test.835603298 Apr 02 12:23:08 PM PDT 24 Apr 02 12:23:09 PM PDT 24 10868396 ps
T723 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.4224123049 Apr 02 12:23:05 PM PDT 24 Apr 02 12:23:07 PM PDT 24 79182412 ps
T724 /workspace/coverage/cover_reg_top/38.hmac_intr_test.1312420177 Apr 02 12:23:00 PM PDT 24 Apr 02 12:23:01 PM PDT 24 15197620 ps
T725 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3225445322 Apr 02 12:22:36 PM PDT 24 Apr 02 12:22:38 PM PDT 24 34026199 ps
T726 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2643895235 Apr 02 12:24:10 PM PDT 24 Apr 02 12:24:12 PM PDT 24 154836080 ps
T727 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2174433025 Apr 02 12:21:38 PM PDT 24 Apr 02 12:21:39 PM PDT 24 38174832 ps
T728 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1552527833 Apr 02 12:23:29 PM PDT 24 Apr 02 12:23:31 PM PDT 24 30395715 ps
T729 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.704082143 Apr 02 12:22:17 PM PDT 24 Apr 02 12:22:21 PM PDT 24 116712665 ps
T730 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.765174236 Apr 02 12:20:50 PM PDT 24 Apr 02 12:20:52 PM PDT 24 49954223 ps
T731 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3644262171 Apr 02 12:22:42 PM PDT 24 Apr 02 12:22:45 PM PDT 24 824281608 ps

Test location /workspace/coverage/default/15.hmac_stress_all.3084882809
Short name T13
Test name
Test status
Simulation time 29187922404 ps
CPU time 407.71 seconds
Started Apr 02 12:44:50 PM PDT 24
Finished Apr 02 12:51:38 PM PDT 24
Peak memory 199752 kb
Host smart-2a055c3e-5c38-46a6-b336-4b334118560c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084882809 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3084882809
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/116.hmac_stress_all_with_rand_reset.3908863901
Short name T10
Test name
Test status
Simulation time 162879539461 ps
CPU time 1856.33 seconds
Started Apr 02 12:46:35 PM PDT 24
Finished Apr 02 01:17:33 PM PDT 24
Peak memory 248944 kb
Host smart-2f0862eb-cd64-4e18-9ca2-b9d68f5dcdaa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3908863901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.hmac_stress_all_with_rand_reset.3908863901
Directory /workspace/116.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.92676126
Short name T25
Test name
Test status
Simulation time 59995381 ps
CPU time 0.86 seconds
Started Apr 02 12:44:16 PM PDT 24
Finished Apr 02 12:44:17 PM PDT 24
Peak memory 218172 kb
Host smart-8c867126-0706-4408-9292-ccc9f7167826
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92676126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.92676126
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/40.hmac_stress_all.3601768855
Short name T16
Test name
Test status
Simulation time 84980297808 ps
CPU time 1078.05 seconds
Started Apr 02 12:45:46 PM PDT 24
Finished Apr 02 01:03:44 PM PDT 24
Peak memory 240576 kb
Host smart-b162fb92-f1fc-4a94-bd47-439a820b2002
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601768855 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3601768855
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2254407466
Short name T61
Test name
Test status
Simulation time 259374687 ps
CPU time 3.91 seconds
Started Apr 02 12:22:11 PM PDT 24
Finished Apr 02 12:22:15 PM PDT 24
Peak memory 199092 kb
Host smart-757a9de9-094b-4fdf-b13f-e029eaa38c0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254407466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2254407466
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.2220361980
Short name T8
Test name
Test status
Simulation time 193142873388 ps
CPU time 3620.52 seconds
Started Apr 02 12:44:25 PM PDT 24
Finished Apr 02 01:44:46 PM PDT 24
Peak memory 248880 kb
Host smart-a01f2411-4643-447b-981c-8bb5ec4e4ad9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2220361980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.2220361980
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2413871816
Short name T54
Test name
Test status
Simulation time 1801817621 ps
CPU time 35.02 seconds
Started Apr 02 12:44:40 PM PDT 24
Finished Apr 02 12:45:16 PM PDT 24
Peak memory 232428 kb
Host smart-771261df-47a4-497f-bc20-4290fd09bfc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2413871816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2413871816
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2314607812
Short name T99
Test name
Test status
Simulation time 113540592 ps
CPU time 0.88 seconds
Started Apr 02 12:22:56 PM PDT 24
Finished Apr 02 12:22:57 PM PDT 24
Peak memory 197784 kb
Host smart-eaeea0be-2eea-4ed6-9575-26b3ba82ccc3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314607812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2314607812
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/default/1.hmac_alert_test.264542288
Short name T22
Test name
Test status
Simulation time 15252535 ps
CPU time 0.58 seconds
Started Apr 02 12:44:17 PM PDT 24
Finished Apr 02 12:44:17 PM PDT 24
Peak memory 194696 kb
Host smart-d66ea372-0bad-4640-8cdb-77611985fb50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264542288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.264542288
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2794544222
Short name T117
Test name
Test status
Simulation time 468062132 ps
CPU time 3.58 seconds
Started Apr 02 12:23:59 PM PDT 24
Finished Apr 02 12:24:03 PM PDT 24
Peak memory 198992 kb
Host smart-e47964f5-e44a-40ec-9354-6399f5bd6c8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794544222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2794544222
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2068299545
Short name T67
Test name
Test status
Simulation time 3127575446 ps
CPU time 4.04 seconds
Started Apr 02 12:22:36 PM PDT 24
Finished Apr 02 12:22:40 PM PDT 24
Peak memory 199040 kb
Host smart-b9f0e75e-32bb-465f-a52c-d01e52f87e84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068299545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2068299545
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3388789252
Short name T6
Test name
Test status
Simulation time 49657930275 ps
CPU time 1383.36 seconds
Started Apr 02 12:44:51 PM PDT 24
Finished Apr 02 01:07:55 PM PDT 24
Peak memory 199748 kb
Host smart-4410072c-91c2-4b5f-8fce-03ac5dabb855
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388789252 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3388789252
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2291025291
Short name T64
Test name
Test status
Simulation time 126962222 ps
CPU time 3.88 seconds
Started Apr 02 12:22:44 PM PDT 24
Finished Apr 02 12:22:48 PM PDT 24
Peak memory 199024 kb
Host smart-9afbecb2-4603-4152-88bd-9f9794395805
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291025291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2291025291
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1982262257
Short name T49
Test name
Test status
Simulation time 354412132234 ps
CPU time 1121.81 seconds
Started Apr 02 12:45:28 PM PDT 24
Finished Apr 02 01:04:10 PM PDT 24
Peak memory 199672 kb
Host smart-a7cce13d-14bc-4123-9403-45423d4bfdc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982262257 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1982262257
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.772723233
Short name T88
Test name
Test status
Simulation time 385404471 ps
CPU time 5.76 seconds
Started Apr 02 12:22:33 PM PDT 24
Finished Apr 02 12:22:39 PM PDT 24
Peak memory 196656 kb
Host smart-13a76c6a-792d-4f66-93ac-b4f7663dd4b6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772723233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.772723233
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1978583818
Short name T106
Test name
Test status
Simulation time 989657501 ps
CPU time 4.98 seconds
Started Apr 02 12:22:51 PM PDT 24
Finished Apr 02 12:22:57 PM PDT 24
Peak memory 198908 kb
Host smart-9a58eea8-ac1a-417a-a0d0-7107b408b49d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978583818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1978583818
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1504773432
Short name T707
Test name
Test status
Simulation time 21113742 ps
CPU time 0.82 seconds
Started Apr 02 12:22:29 PM PDT 24
Finished Apr 02 12:22:30 PM PDT 24
Peak memory 195944 kb
Host smart-2462a1d7-8522-4e70-8a5a-6c1c3b5361c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504773432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1504773432
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1603907451
Short name T668
Test name
Test status
Simulation time 231389882 ps
CPU time 1.85 seconds
Started Apr 02 12:22:30 PM PDT 24
Finished Apr 02 12:22:32 PM PDT 24
Peak memory 199028 kb
Host smart-6ccb75f5-c8ae-4b5e-927c-8b6894f8de79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603907451 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1603907451
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2929853265
Short name T628
Test name
Test status
Simulation time 61323145 ps
CPU time 0.97 seconds
Started Apr 02 12:22:29 PM PDT 24
Finished Apr 02 12:22:31 PM PDT 24
Peak memory 198608 kb
Host smart-e94302a9-0a2a-4650-b062-d9ab39a0d7f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929853265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2929853265
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.3935544033
Short name T720
Test name
Test status
Simulation time 19732807 ps
CPU time 0.62 seconds
Started Apr 02 12:22:33 PM PDT 24
Finished Apr 02 12:22:34 PM PDT 24
Peak memory 192404 kb
Host smart-94eb88fd-732b-4224-9d9a-a77714ecd693
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935544033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3935544033
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.765174236
Short name T730
Test name
Test status
Simulation time 49954223 ps
CPU time 2.26 seconds
Started Apr 02 12:20:50 PM PDT 24
Finished Apr 02 12:20:52 PM PDT 24
Peak memory 199012 kb
Host smart-03685106-d729-4e17-b813-805767ea00c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765174236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_
outstanding.765174236
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1716471354
Short name T621
Test name
Test status
Simulation time 234496341 ps
CPU time 1.63 seconds
Started Apr 02 12:20:58 PM PDT 24
Finished Apr 02 12:21:00 PM PDT 24
Peak memory 199048 kb
Host smart-7fbc5466-2b10-4312-b9c0-7657078b208f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716471354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1716471354
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2340852710
Short name T119
Test name
Test status
Simulation time 89457793 ps
CPU time 2.78 seconds
Started Apr 02 12:22:30 PM PDT 24
Finished Apr 02 12:22:32 PM PDT 24
Peak memory 198808 kb
Host smart-1083341b-c935-4bfd-80ad-0827f3acf749
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340852710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2340852710
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3644262171
Short name T731
Test name
Test status
Simulation time 824281608 ps
CPU time 3.41 seconds
Started Apr 02 12:22:42 PM PDT 24
Finished Apr 02 12:22:45 PM PDT 24
Peak memory 197748 kb
Host smart-3bd6ab2f-51b9-4310-8ee0-07ea53faa659
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644262171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3644262171
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1856379811
Short name T631
Test name
Test status
Simulation time 111877914 ps
CPU time 5.04 seconds
Started Apr 02 12:22:54 PM PDT 24
Finished Apr 02 12:22:59 PM PDT 24
Peak memory 197496 kb
Host smart-6116ec70-6927-48ea-96d9-b8b352f99ef7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856379811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1856379811
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2707175140
Short name T713
Test name
Test status
Simulation time 237492471 ps
CPU time 1.8 seconds
Started Apr 02 12:22:15 PM PDT 24
Finished Apr 02 12:22:17 PM PDT 24
Peak memory 198816 kb
Host smart-1b5c53ee-50da-4a99-a431-622656f9f098
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707175140 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2707175140
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1609779827
Short name T111
Test name
Test status
Simulation time 23917966 ps
CPU time 0.85 seconds
Started Apr 02 12:22:14 PM PDT 24
Finished Apr 02 12:22:16 PM PDT 24
Peak memory 196960 kb
Host smart-5b6563de-fb47-48c2-a9d4-00d0eb068d76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609779827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1609779827
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.452220984
Short name T680
Test name
Test status
Simulation time 27505990 ps
CPU time 0.62 seconds
Started Apr 02 12:24:02 PM PDT 24
Finished Apr 02 12:24:03 PM PDT 24
Peak memory 193640 kb
Host smart-c753b8d7-b925-47fa-90f3-d2605dcfbfb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452220984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.452220984
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.4101478590
Short name T699
Test name
Test status
Simulation time 155228096 ps
CPU time 1.08 seconds
Started Apr 02 12:23:00 PM PDT 24
Finished Apr 02 12:23:01 PM PDT 24
Peak memory 198940 kb
Host smart-dbce120c-62ed-4573-a7e5-d70c10010e90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101478590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.4101478590
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3233232105
Short name T607
Test name
Test status
Simulation time 470001670 ps
CPU time 2.37 seconds
Started Apr 02 12:22:33 PM PDT 24
Finished Apr 02 12:22:36 PM PDT 24
Peak memory 197412 kb
Host smart-e5f31a21-bd59-4d68-bdad-2a449ac90f27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233232105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3233232105
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1332034160
Short name T705
Test name
Test status
Simulation time 190509498 ps
CPU time 3.22 seconds
Started Apr 02 12:20:57 PM PDT 24
Finished Apr 02 12:21:00 PM PDT 24
Peak memory 199128 kb
Host smart-3c0d7a56-b92c-4b75-ae8f-77dcf21b653b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332034160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1332034160
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.360018590
Short name T615
Test name
Test status
Simulation time 71024917 ps
CPU time 1.12 seconds
Started Apr 02 12:22:09 PM PDT 24
Finished Apr 02 12:22:10 PM PDT 24
Peak memory 198992 kb
Host smart-695d0f23-472b-423b-a261-e3069fbaebbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360018590 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.360018590
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.308548560
Short name T65
Test name
Test status
Simulation time 36732026 ps
CPU time 0.95 seconds
Started Apr 02 12:22:05 PM PDT 24
Finished Apr 02 12:22:06 PM PDT 24
Peak memory 198372 kb
Host smart-e9287706-56b8-4cbc-acf6-fef8798566c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308548560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.308548560
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.2694829909
Short name T693
Test name
Test status
Simulation time 15277408 ps
CPU time 0.64 seconds
Started Apr 02 12:23:17 PM PDT 24
Finished Apr 02 12:23:19 PM PDT 24
Peak memory 192580 kb
Host smart-db0657fb-cf83-4f83-bc36-6c37aebaf808
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694829909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2694829909
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1213454381
Short name T604
Test name
Test status
Simulation time 25643670 ps
CPU time 0.99 seconds
Started Apr 02 12:23:34 PM PDT 24
Finished Apr 02 12:23:35 PM PDT 24
Peak memory 198716 kb
Host smart-5a194250-f2a9-498f-93cd-2f60e72e2991
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213454381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1213454381
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.25317487
Short name T706
Test name
Test status
Simulation time 31955158 ps
CPU time 1.47 seconds
Started Apr 02 12:23:34 PM PDT 24
Finished Apr 02 12:23:36 PM PDT 24
Peak memory 199096 kb
Host smart-f2d7be6b-9e51-463e-9327-81d9b37fc143
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25317487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.25317487
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1988117481
Short name T649
Test name
Test status
Simulation time 400762636 ps
CPU time 2.19 seconds
Started Apr 02 12:23:44 PM PDT 24
Finished Apr 02 12:23:46 PM PDT 24
Peak memory 199056 kb
Host smart-a2fc02d6-9819-4e48-906f-af6eb6fc32b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988117481 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1988117481
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.359907072
Short name T84
Test name
Test status
Simulation time 95910198 ps
CPU time 0.82 seconds
Started Apr 02 12:23:43 PM PDT 24
Finished Apr 02 12:23:44 PM PDT 24
Peak memory 197888 kb
Host smart-44d17d93-f5e6-4bba-b6a9-b6f4bb62427f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359907072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.359907072
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2159306493
Short name T687
Test name
Test status
Simulation time 49150063 ps
CPU time 0.7 seconds
Started Apr 02 12:23:28 PM PDT 24
Finished Apr 02 12:23:30 PM PDT 24
Peak memory 193208 kb
Host smart-57cdd48f-60d3-4a13-98e2-d43f5aafd7ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159306493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2159306493
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1021624901
Short name T653
Test name
Test status
Simulation time 81724088 ps
CPU time 1.1 seconds
Started Apr 02 12:22:23 PM PDT 24
Finished Apr 02 12:22:24 PM PDT 24
Peak memory 198632 kb
Host smart-59890f26-9911-4eda-b72e-eb7fd06f3ecd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021624901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.1021624901
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1552527833
Short name T728
Test name
Test status
Simulation time 30395715 ps
CPU time 1.59 seconds
Started Apr 02 12:23:29 PM PDT 24
Finished Apr 02 12:23:31 PM PDT 24
Peak memory 198152 kb
Host smart-4366e49b-21b7-4889-a7a9-786fb8385661
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552527833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1552527833
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1615142148
Short name T114
Test name
Test status
Simulation time 865031721 ps
CPU time 4.26 seconds
Started Apr 02 12:23:40 PM PDT 24
Finished Apr 02 12:23:45 PM PDT 24
Peak memory 198336 kb
Host smart-0afc8eb5-d1f6-49ea-8ca7-4d8999d75cbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615142148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1615142148
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1345633369
Short name T619
Test name
Test status
Simulation time 164092547 ps
CPU time 2.22 seconds
Started Apr 02 12:22:27 PM PDT 24
Finished Apr 02 12:22:29 PM PDT 24
Peak memory 199028 kb
Host smart-62a3fb5a-2a45-4524-b77b-b6688b468907
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345633369 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1345633369
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2378506559
Short name T691
Test name
Test status
Simulation time 23538438 ps
CPU time 0.8 seconds
Started Apr 02 12:23:43 PM PDT 24
Finished Apr 02 12:23:44 PM PDT 24
Peak memory 198128 kb
Host smart-954b9419-bc51-419d-aec1-e1185f9374dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378506559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2378506559
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2944733050
Short name T697
Test name
Test status
Simulation time 17927457 ps
CPU time 0.61 seconds
Started Apr 02 12:22:23 PM PDT 24
Finished Apr 02 12:22:24 PM PDT 24
Peak memory 193824 kb
Host smart-a0ffb07f-b30b-46d8-96cc-ef1527f8ba45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944733050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2944733050
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.4179417208
Short name T610
Test name
Test status
Simulation time 767150002 ps
CPU time 2.13 seconds
Started Apr 02 12:24:05 PM PDT 24
Finished Apr 02 12:24:07 PM PDT 24
Peak memory 198920 kb
Host smart-c9227df1-67f5-4fe2-8701-3f16b4008d9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179417208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.4179417208
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2643895235
Short name T726
Test name
Test status
Simulation time 154836080 ps
CPU time 1.72 seconds
Started Apr 02 12:24:10 PM PDT 24
Finished Apr 02 12:24:12 PM PDT 24
Peak memory 199072 kb
Host smart-e90c1473-a6ff-4f24-94eb-eb64025ceded
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643895235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2643895235
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1916608401
Short name T666
Test name
Test status
Simulation time 150961639 ps
CPU time 2.82 seconds
Started Apr 02 12:23:44 PM PDT 24
Finished Apr 02 12:23:47 PM PDT 24
Peak memory 198984 kb
Host smart-1741a948-1b36-4428-9377-f0b78abf0a0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916608401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1916608401
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1908164520
Short name T622
Test name
Test status
Simulation time 41594838 ps
CPU time 2.62 seconds
Started Apr 02 12:22:33 PM PDT 24
Finished Apr 02 12:22:35 PM PDT 24
Peak memory 199088 kb
Host smart-78417954-4004-4f32-9160-d3aece059e19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908164520 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1908164520
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1860943005
Short name T109
Test name
Test status
Simulation time 83006555 ps
CPU time 0.75 seconds
Started Apr 02 12:22:24 PM PDT 24
Finished Apr 02 12:22:25 PM PDT 24
Peak memory 196940 kb
Host smart-021ca6dd-7ec2-42dd-9087-90261c74f320
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860943005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1860943005
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2740908436
Short name T721
Test name
Test status
Simulation time 14634668 ps
CPU time 0.6 seconds
Started Apr 02 12:23:43 PM PDT 24
Finished Apr 02 12:23:44 PM PDT 24
Peak memory 193712 kb
Host smart-5d2290ae-dbe2-4a03-8bc4-21d0122d2b6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740908436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2740908436
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.166542215
Short name T663
Test name
Test status
Simulation time 46361539 ps
CPU time 2.13 seconds
Started Apr 02 12:22:34 PM PDT 24
Finished Apr 02 12:22:36 PM PDT 24
Peak memory 198916 kb
Host smart-dc6c6bea-9a2c-4a0b-8fa7-5fc2bef2b6be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166542215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr
_outstanding.166542215
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3747197930
Short name T599
Test name
Test status
Simulation time 71875633 ps
CPU time 3.53 seconds
Started Apr 02 12:23:59 PM PDT 24
Finished Apr 02 12:24:03 PM PDT 24
Peak memory 199104 kb
Host smart-e1c70d7a-4276-4ef9-a2e8-fec7a1a38401
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747197930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3747197930
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3216669902
Short name T674
Test name
Test status
Simulation time 90265723 ps
CPU time 2.81 seconds
Started Apr 02 12:22:23 PM PDT 24
Finished Apr 02 12:22:26 PM PDT 24
Peak memory 199168 kb
Host smart-843988d0-2a56-4701-9ab9-d9bd7e40fbc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216669902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3216669902
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1476111617
Short name T694
Test name
Test status
Simulation time 499280257 ps
CPU time 2.3 seconds
Started Apr 02 12:22:35 PM PDT 24
Finished Apr 02 12:22:37 PM PDT 24
Peak memory 199172 kb
Host smart-05745917-9c8d-434d-9eb9-68a6ce93e25f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476111617 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1476111617
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1962655481
Short name T632
Test name
Test status
Simulation time 82945102 ps
CPU time 0.83 seconds
Started Apr 02 12:22:33 PM PDT 24
Finished Apr 02 12:22:34 PM PDT 24
Peak memory 198260 kb
Host smart-2967741f-c2c2-4edd-bf35-6121cfa9943d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962655481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.1962655481
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.3086885360
Short name T686
Test name
Test status
Simulation time 25108557 ps
CPU time 0.63 seconds
Started Apr 02 12:22:36 PM PDT 24
Finished Apr 02 12:22:37 PM PDT 24
Peak memory 193892 kb
Host smart-2f098495-5b25-4914-bb75-479ec4da95e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086885360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.3086885360
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2363442274
Short name T640
Test name
Test status
Simulation time 1501668051 ps
CPU time 2.6 seconds
Started Apr 02 12:22:36 PM PDT 24
Finished Apr 02 12:22:39 PM PDT 24
Peak memory 198572 kb
Host smart-448210b9-5907-4ddf-a9aa-f6d93eb244fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363442274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2363442274
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3225445322
Short name T725
Test name
Test status
Simulation time 34026199 ps
CPU time 1.77 seconds
Started Apr 02 12:22:36 PM PDT 24
Finished Apr 02 12:22:38 PM PDT 24
Peak memory 199076 kb
Host smart-d711f7af-6caf-402b-aa1a-47aacf6969ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225445322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3225445322
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.418958464
Short name T635
Test name
Test status
Simulation time 91840578 ps
CPU time 1.33 seconds
Started Apr 02 12:22:48 PM PDT 24
Finished Apr 02 12:22:50 PM PDT 24
Peak memory 199152 kb
Host smart-3db028d1-e143-44f0-91f3-5eac3a3077f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418958464 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.418958464
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1589476054
Short name T105
Test name
Test status
Simulation time 18939914 ps
CPU time 0.92 seconds
Started Apr 02 12:22:39 PM PDT 24
Finished Apr 02 12:22:40 PM PDT 24
Peak memory 198580 kb
Host smart-2465dd96-9926-4973-809e-4ea863c5d090
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589476054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1589476054
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1172887886
Short name T715
Test name
Test status
Simulation time 59428694 ps
CPU time 0.62 seconds
Started Apr 02 12:23:08 PM PDT 24
Finished Apr 02 12:23:09 PM PDT 24
Peak memory 193576 kb
Host smart-43e331f3-9c4c-4510-9628-d5998748adad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172887886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1172887886
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3804836965
Short name T704
Test name
Test status
Simulation time 784376196 ps
CPU time 1.14 seconds
Started Apr 02 12:22:39 PM PDT 24
Finished Apr 02 12:22:41 PM PDT 24
Peak memory 198588 kb
Host smart-6fb29992-00a1-4a6a-b79d-1425ccf54202
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804836965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3804836965
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2519739997
Short name T625
Test name
Test status
Simulation time 393789770 ps
CPU time 1.8 seconds
Started Apr 02 12:22:36 PM PDT 24
Finished Apr 02 12:22:38 PM PDT 24
Peak memory 199048 kb
Host smart-8a2cc6c1-898b-4a85-b107-640e5f48bc63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519739997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.2519739997
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.405051451
Short name T676
Test name
Test status
Simulation time 261078941 ps
CPU time 3.77 seconds
Started Apr 02 12:22:37 PM PDT 24
Finished Apr 02 12:22:41 PM PDT 24
Peak memory 198976 kb
Host smart-b8500c5c-f3fe-4922-bbc3-57e92512382a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405051451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.405051451
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1817463038
Short name T613
Test name
Test status
Simulation time 71328342 ps
CPU time 1.71 seconds
Started Apr 02 12:22:49 PM PDT 24
Finished Apr 02 12:22:52 PM PDT 24
Peak memory 199040 kb
Host smart-5f1f9ac2-9c7e-4e70-a6d8-5a676bfee5ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817463038 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.1817463038
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2242905212
Short name T623
Test name
Test status
Simulation time 107947542 ps
CPU time 0.93 seconds
Started Apr 02 12:22:46 PM PDT 24
Finished Apr 02 12:22:47 PM PDT 24
Peak memory 198192 kb
Host smart-8ba0118e-f1e4-4fa6-8a02-d2e72e8e09fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242905212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2242905212
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3311493423
Short name T679
Test name
Test status
Simulation time 36879771 ps
CPU time 0.58 seconds
Started Apr 02 12:22:45 PM PDT 24
Finished Apr 02 12:22:46 PM PDT 24
Peak memory 193592 kb
Host smart-50210655-4dcd-4fc0-a1fa-3a1ffa95f8fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311493423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3311493423
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1877422627
Short name T603
Test name
Test status
Simulation time 45530541 ps
CPU time 1.11 seconds
Started Apr 02 12:22:49 PM PDT 24
Finished Apr 02 12:22:51 PM PDT 24
Peak memory 198668 kb
Host smart-9c7e675f-23ed-4cbf-a151-9fdac06d9c55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877422627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1877422627
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3447073865
Short name T696
Test name
Test status
Simulation time 407305026 ps
CPU time 1.93 seconds
Started Apr 02 12:22:49 PM PDT 24
Finished Apr 02 12:22:52 PM PDT 24
Peak memory 199156 kb
Host smart-4ed4461a-d79b-44c3-95c1-31a085e5ad01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447073865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3447073865
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1986231390
Short name T113
Test name
Test status
Simulation time 84232822 ps
CPU time 1.95 seconds
Started Apr 02 12:22:43 PM PDT 24
Finished Apr 02 12:22:46 PM PDT 24
Peak memory 199012 kb
Host smart-dd2e49b8-d949-4f8c-9c48-1f9547e234b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986231390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1986231390
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3198407041
Short name T719
Test name
Test status
Simulation time 146000020 ps
CPU time 2.43 seconds
Started Apr 02 12:23:09 PM PDT 24
Finished Apr 02 12:23:11 PM PDT 24
Peak memory 199068 kb
Host smart-58da314d-3c63-4a5b-87ba-f0b4c1209c4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198407041 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.3198407041
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3333765241
Short name T104
Test name
Test status
Simulation time 17495755 ps
CPU time 0.89 seconds
Started Apr 02 12:22:51 PM PDT 24
Finished Apr 02 12:22:52 PM PDT 24
Peak memory 198028 kb
Host smart-421bcddc-5297-4355-a00d-33f3323e8c02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333765241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3333765241
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.3355159797
Short name T652
Test name
Test status
Simulation time 14709446 ps
CPU time 0.64 seconds
Started Apr 02 12:24:06 PM PDT 24
Finished Apr 02 12:24:07 PM PDT 24
Peak memory 191992 kb
Host smart-c505e9e0-a19d-427d-bdf0-c2374bbf41f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355159797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3355159797
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1003773598
Short name T662
Test name
Test status
Simulation time 486096095 ps
CPU time 2.28 seconds
Started Apr 02 12:23:43 PM PDT 24
Finished Apr 02 12:23:45 PM PDT 24
Peak memory 198948 kb
Host smart-b2eb8e4f-e613-4764-8dd8-ffb6327527bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003773598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.1003773598
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.673754579
Short name T646
Test name
Test status
Simulation time 138691791 ps
CPU time 3.14 seconds
Started Apr 02 12:24:09 PM PDT 24
Finished Apr 02 12:24:12 PM PDT 24
Peak memory 199048 kb
Host smart-13ddb983-df6d-405c-a6d4-cfe1c6724107
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673754579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.673754579
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2706957767
Short name T62
Test name
Test status
Simulation time 998460481 ps
CPU time 1.76 seconds
Started Apr 02 12:22:52 PM PDT 24
Finished Apr 02 12:22:54 PM PDT 24
Peak memory 199116 kb
Host smart-e884ab4a-1706-4833-b3cb-ece21256cada
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706957767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2706957767
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2588493285
Short name T85
Test name
Test status
Simulation time 132370695828 ps
CPU time 638.56 seconds
Started Apr 02 12:24:06 PM PDT 24
Finished Apr 02 12:34:45 PM PDT 24
Peak memory 213872 kb
Host smart-615e32b3-7721-4fc2-90e8-80438ee1513a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588493285 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2588493285
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3477982006
Short name T102
Test name
Test status
Simulation time 72304257 ps
CPU time 0.7 seconds
Started Apr 02 12:23:08 PM PDT 24
Finished Apr 02 12:23:09 PM PDT 24
Peak memory 196516 kb
Host smart-0dfe83f8-cf78-407c-89bc-dc8da0b149ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477982006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3477982006
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3381381477
Short name T608
Test name
Test status
Simulation time 12127421 ps
CPU time 0.63 seconds
Started Apr 02 12:22:52 PM PDT 24
Finished Apr 02 12:22:53 PM PDT 24
Peak memory 193968 kb
Host smart-3af19589-23d5-4447-b1ea-c499424e5e67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381381477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3381381477
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.499270271
Short name T717
Test name
Test status
Simulation time 202312512 ps
CPU time 1.82 seconds
Started Apr 02 12:24:21 PM PDT 24
Finished Apr 02 12:24:23 PM PDT 24
Peak memory 198976 kb
Host smart-01c6030c-b622-4c2e-b6f0-98e9560a3226
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499270271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.499270271
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.996086617
Short name T710
Test name
Test status
Simulation time 31125846 ps
CPU time 1.57 seconds
Started Apr 02 12:23:49 PM PDT 24
Finished Apr 02 12:23:51 PM PDT 24
Peak memory 199084 kb
Host smart-9ec3bc6e-2583-4000-b47b-f4b5e3cca701
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996086617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.996086617
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3206631530
Short name T115
Test name
Test status
Simulation time 765922478 ps
CPU time 4.05 seconds
Started Apr 02 12:23:48 PM PDT 24
Finished Apr 02 12:23:52 PM PDT 24
Peak memory 199032 kb
Host smart-a4d58eee-0140-41a0-af40-5d6999e52b2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206631530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3206631530
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2196110311
Short name T688
Test name
Test status
Simulation time 49794831 ps
CPU time 1.21 seconds
Started Apr 02 12:23:13 PM PDT 24
Finished Apr 02 12:23:15 PM PDT 24
Peak memory 199124 kb
Host smart-dd9d0eee-8342-449e-875a-f476f182e2cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196110311 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.2196110311
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3741523868
Short name T624
Test name
Test status
Simulation time 103526336 ps
CPU time 0.91 seconds
Started Apr 02 12:24:07 PM PDT 24
Finished Apr 02 12:24:08 PM PDT 24
Peak memory 197828 kb
Host smart-6f42e970-fcd0-42dc-8268-29fa6c188a22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741523868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3741523868
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2309033179
Short name T609
Test name
Test status
Simulation time 12935819 ps
CPU time 0.58 seconds
Started Apr 02 12:24:07 PM PDT 24
Finished Apr 02 12:24:09 PM PDT 24
Peak memory 193452 kb
Host smart-676a0f26-6faa-4780-9bea-ce05215c450e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309033179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2309033179
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2553584407
Short name T681
Test name
Test status
Simulation time 236606727 ps
CPU time 2.48 seconds
Started Apr 02 12:24:06 PM PDT 24
Finished Apr 02 12:24:09 PM PDT 24
Peak memory 196856 kb
Host smart-11dacd45-f9c1-49ea-aca6-d49bd90ee0a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553584407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.2553584407
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2972139078
Short name T657
Test name
Test status
Simulation time 25170680 ps
CPU time 1.52 seconds
Started Apr 02 12:22:53 PM PDT 24
Finished Apr 02 12:22:55 PM PDT 24
Peak memory 199164 kb
Host smart-e1f55ad6-d0d4-4c56-af1e-994b2909e703
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972139078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2972139078
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2407434462
Short name T684
Test name
Test status
Simulation time 784970551 ps
CPU time 3.16 seconds
Started Apr 02 12:22:50 PM PDT 24
Finished Apr 02 12:22:54 PM PDT 24
Peak memory 199396 kb
Host smart-79b5793c-8b01-4bf8-8dab-b9ef0adb7667
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407434462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2407434462
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3505678981
Short name T648
Test name
Test status
Simulation time 2564193184 ps
CPU time 3.13 seconds
Started Apr 02 12:22:44 PM PDT 24
Finished Apr 02 12:22:47 PM PDT 24
Peak memory 199012 kb
Host smart-f465a93b-492f-4a33-9b51-936dea6b284c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505678981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3505678981
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3104822716
Short name T605
Test name
Test status
Simulation time 3182022492 ps
CPU time 10.3 seconds
Started Apr 02 12:22:43 PM PDT 24
Finished Apr 02 12:22:54 PM PDT 24
Peak memory 198956 kb
Host smart-551fac8b-e463-4f9c-8d15-f7adcc7507bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104822716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3104822716
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2680327611
Short name T718
Test name
Test status
Simulation time 42376054 ps
CPU time 0.78 seconds
Started Apr 02 12:22:35 PM PDT 24
Finished Apr 02 12:22:36 PM PDT 24
Peak memory 196220 kb
Host smart-ac800305-9c11-43d5-be14-eb37d500c323
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680327611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2680327611
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3728011022
Short name T708
Test name
Test status
Simulation time 188015426 ps
CPU time 2.28 seconds
Started Apr 02 12:22:43 PM PDT 24
Finished Apr 02 12:22:46 PM PDT 24
Peak memory 199072 kb
Host smart-af6906f7-9a0d-47e7-8add-6add1cda16ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728011022 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3728011022
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3096530488
Short name T614
Test name
Test status
Simulation time 22992964 ps
CPU time 0.8 seconds
Started Apr 02 12:22:43 PM PDT 24
Finished Apr 02 12:22:45 PM PDT 24
Peak memory 198220 kb
Host smart-6832e12e-f84a-4293-99af-200ccaa0040d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096530488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.3096530488
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2654176411
Short name T629
Test name
Test status
Simulation time 200249484 ps
CPU time 0.57 seconds
Started Apr 02 12:22:19 PM PDT 24
Finished Apr 02 12:22:20 PM PDT 24
Peak memory 192872 kb
Host smart-af4f1e92-c8ef-40ff-99c2-dbb5d728c083
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654176411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2654176411
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3686070885
Short name T606
Test name
Test status
Simulation time 560376906 ps
CPU time 2.34 seconds
Started Apr 02 12:22:53 PM PDT 24
Finished Apr 02 12:22:56 PM PDT 24
Peak memory 198720 kb
Host smart-7723ec1b-5b8b-42ec-84b1-78f999ae041f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686070885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3686070885
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3303286440
Short name T654
Test name
Test status
Simulation time 2271414319 ps
CPU time 3.87 seconds
Started Apr 02 12:22:34 PM PDT 24
Finished Apr 02 12:22:38 PM PDT 24
Peak memory 199060 kb
Host smart-678e9be4-0060-4d44-8077-a602c4b86b99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303286440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3303286440
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.704082143
Short name T729
Test name
Test status
Simulation time 116712665 ps
CPU time 2.73 seconds
Started Apr 02 12:22:17 PM PDT 24
Finished Apr 02 12:22:21 PM PDT 24
Peak memory 198204 kb
Host smart-9fea91e7-044c-4f7f-9409-48c5666edd0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704082143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.704082143
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.307786340
Short name T665
Test name
Test status
Simulation time 26649894 ps
CPU time 0.58 seconds
Started Apr 02 12:24:07 PM PDT 24
Finished Apr 02 12:24:08 PM PDT 24
Peak memory 193672 kb
Host smart-bc6051d7-59bd-4059-b76a-377ce92efe98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307786340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.307786340
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.661878020
Short name T670
Test name
Test status
Simulation time 16782009 ps
CPU time 0.57 seconds
Started Apr 02 12:24:21 PM PDT 24
Finished Apr 02 12:24:21 PM PDT 24
Peak memory 193860 kb
Host smart-93febe4b-d849-47f9-8c25-5cd208f3321c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661878020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.661878020
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.348729119
Short name T678
Test name
Test status
Simulation time 17581423 ps
CPU time 0.58 seconds
Started Apr 02 12:23:06 PM PDT 24
Finished Apr 02 12:23:07 PM PDT 24
Peak memory 193684 kb
Host smart-0cc87154-ab3f-4234-acb9-9c4eb2a4cd4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348729119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.348729119
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2764934715
Short name T645
Test name
Test status
Simulation time 25829816 ps
CPU time 0.62 seconds
Started Apr 02 12:23:42 PM PDT 24
Finished Apr 02 12:23:43 PM PDT 24
Peak memory 192924 kb
Host smart-46de484a-3a8c-4951-9ac2-fe7687235122
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764934715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2764934715
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.331611682
Short name T602
Test name
Test status
Simulation time 39536840 ps
CPU time 0.55 seconds
Started Apr 02 12:23:13 PM PDT 24
Finished Apr 02 12:23:13 PM PDT 24
Peak memory 193652 kb
Host smart-4b20ca7e-c14c-4844-9ddb-b91457a5a30d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331611682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.331611682
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3092737459
Short name T650
Test name
Test status
Simulation time 41974081 ps
CPU time 0.55 seconds
Started Apr 02 12:24:15 PM PDT 24
Finished Apr 02 12:24:15 PM PDT 24
Peak memory 193656 kb
Host smart-57841835-d03f-4b16-9418-87d356e25fb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092737459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3092737459
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.336460090
Short name T643
Test name
Test status
Simulation time 54191174 ps
CPU time 0.58 seconds
Started Apr 02 12:24:18 PM PDT 24
Finished Apr 02 12:24:19 PM PDT 24
Peak memory 193660 kb
Host smart-290832c6-d6f5-481c-bb2e-bef641fc4b3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336460090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.336460090
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1382139540
Short name T655
Test name
Test status
Simulation time 32089396 ps
CPU time 0.67 seconds
Started Apr 02 12:24:06 PM PDT 24
Finished Apr 02 12:24:07 PM PDT 24
Peak memory 191788 kb
Host smart-97f44ec0-67a3-4b01-b252-8b7f21059207
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382139540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1382139540
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.3667317939
Short name T702
Test name
Test status
Simulation time 16471325 ps
CPU time 0.58 seconds
Started Apr 02 12:22:57 PM PDT 24
Finished Apr 02 12:22:58 PM PDT 24
Peak memory 193580 kb
Host smart-38fd68df-452c-4697-b370-e7e7fd99ccac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667317939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3667317939
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1338631795
Short name T672
Test name
Test status
Simulation time 50268947 ps
CPU time 0.56 seconds
Started Apr 02 12:23:08 PM PDT 24
Finished Apr 02 12:23:09 PM PDT 24
Peak memory 193840 kb
Host smart-2a6f5a54-89b0-433f-9650-4c4f0be6d281
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338631795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1338631795
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.94699580
Short name T100
Test name
Test status
Simulation time 441304417 ps
CPU time 5.43 seconds
Started Apr 02 12:22:39 PM PDT 24
Finished Apr 02 12:22:45 PM PDT 24
Peak memory 198840 kb
Host smart-d929e2b3-382e-4bd7-b791-25dd6727b167
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94699580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.94699580
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2683980171
Short name T675
Test name
Test status
Simulation time 11764304456 ps
CPU time 10.8 seconds
Started Apr 02 12:21:17 PM PDT 24
Finished Apr 02 12:21:29 PM PDT 24
Peak memory 198304 kb
Host smart-cf90890b-8726-4323-8778-c882fda554a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683980171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2683980171
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3043364205
Short name T700
Test name
Test status
Simulation time 44636170 ps
CPU time 1.05 seconds
Started Apr 02 12:21:18 PM PDT 24
Finished Apr 02 12:21:19 PM PDT 24
Peak memory 198088 kb
Host smart-5aeed2bc-c867-42dd-a684-1a46e6a1038a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043364205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3043364205
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1510961187
Short name T86
Test name
Test status
Simulation time 749608075 ps
CPU time 2.22 seconds
Started Apr 02 12:22:47 PM PDT 24
Finished Apr 02 12:22:50 PM PDT 24
Peak memory 198364 kb
Host smart-f6f8e641-087c-4676-b82e-e4c88858e865
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510961187 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1510961187
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2713934238
Short name T103
Test name
Test status
Simulation time 14785660 ps
CPU time 0.66 seconds
Started Apr 02 12:22:24 PM PDT 24
Finished Apr 02 12:22:25 PM PDT 24
Peak memory 196060 kb
Host smart-9926933c-62b8-4a15-bb59-0aca213056cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713934238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2713934238
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.1702981132
Short name T695
Test name
Test status
Simulation time 22803413 ps
CPU time 0.6 seconds
Started Apr 02 12:22:24 PM PDT 24
Finished Apr 02 12:22:25 PM PDT 24
Peak memory 192956 kb
Host smart-46d94da5-b432-498a-910b-30ff65e660ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702981132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.1702981132
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.461858652
Short name T618
Test name
Test status
Simulation time 101468387 ps
CPU time 1.74 seconds
Started Apr 02 12:22:40 PM PDT 24
Finished Apr 02 12:22:42 PM PDT 24
Peak memory 198544 kb
Host smart-e8382549-f3e6-473e-a5a8-0d40f9491bb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461858652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.461858652
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1134741636
Short name T638
Test name
Test status
Simulation time 78738311 ps
CPU time 2.24 seconds
Started Apr 02 12:22:38 PM PDT 24
Finished Apr 02 12:22:41 PM PDT 24
Peak memory 197848 kb
Host smart-5533f026-b44a-4431-87b6-c4c6c76f091d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134741636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1134741636
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1315922594
Short name T600
Test name
Test status
Simulation time 16389081 ps
CPU time 0.6 seconds
Started Apr 02 12:23:17 PM PDT 24
Finished Apr 02 12:23:18 PM PDT 24
Peak memory 193876 kb
Host smart-a4c59c96-6680-4b02-8f52-93212876ee25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315922594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1315922594
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3699044750
Short name T712
Test name
Test status
Simulation time 15900700 ps
CPU time 0.6 seconds
Started Apr 02 12:23:08 PM PDT 24
Finished Apr 02 12:23:09 PM PDT 24
Peak memory 193636 kb
Host smart-d8079712-d228-4ac1-be66-826ade9fda4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699044750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3699044750
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3222352820
Short name T87
Test name
Test status
Simulation time 55786360 ps
CPU time 0.6 seconds
Started Apr 02 12:22:57 PM PDT 24
Finished Apr 02 12:22:58 PM PDT 24
Peak memory 193732 kb
Host smart-3e3991db-0bee-44ca-9e88-d81c4a647e0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222352820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3222352820
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3100751483
Short name T683
Test name
Test status
Simulation time 14093066 ps
CPU time 0.57 seconds
Started Apr 02 12:23:17 PM PDT 24
Finished Apr 02 12:23:18 PM PDT 24
Peak memory 193608 kb
Host smart-f91fb626-fb32-4819-8370-859b84246866
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100751483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3100751483
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3490324571
Short name T667
Test name
Test status
Simulation time 91274064 ps
CPU time 0.59 seconds
Started Apr 02 12:23:08 PM PDT 24
Finished Apr 02 12:23:08 PM PDT 24
Peak memory 193576 kb
Host smart-26d6ddf0-60e3-4705-89b6-d87f424ad503
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490324571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3490324571
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.835603298
Short name T722
Test name
Test status
Simulation time 10868396 ps
CPU time 0.58 seconds
Started Apr 02 12:23:08 PM PDT 24
Finished Apr 02 12:23:09 PM PDT 24
Peak memory 193696 kb
Host smart-c02bd663-b18e-4d7c-b47b-f26ce55c14ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835603298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.835603298
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2475440332
Short name T656
Test name
Test status
Simulation time 39754551 ps
CPU time 0.62 seconds
Started Apr 02 12:22:55 PM PDT 24
Finished Apr 02 12:22:56 PM PDT 24
Peak memory 193744 kb
Host smart-201e1051-336d-4238-a02f-de660b4e4707
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475440332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2475440332
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.689714165
Short name T661
Test name
Test status
Simulation time 14726706 ps
CPU time 0.63 seconds
Started Apr 02 12:23:13 PM PDT 24
Finished Apr 02 12:23:14 PM PDT 24
Peak memory 193588 kb
Host smart-d4d36048-b6dc-4a0a-8ba2-faa1858271cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689714165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.689714165
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.1312420177
Short name T724
Test name
Test status
Simulation time 15197620 ps
CPU time 0.6 seconds
Started Apr 02 12:23:00 PM PDT 24
Finished Apr 02 12:23:01 PM PDT 24
Peak memory 193604 kb
Host smart-41ee441f-3c13-4d8b-b4b5-c8bdc24e9889
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312420177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1312420177
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1011934663
Short name T626
Test name
Test status
Simulation time 53965851 ps
CPU time 0.67 seconds
Started Apr 02 12:23:02 PM PDT 24
Finished Apr 02 12:23:03 PM PDT 24
Peak memory 193008 kb
Host smart-e819ee10-b7cb-4a6d-9998-d8ec4a0dc6a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011934663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1011934663
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3833807065
Short name T647
Test name
Test status
Simulation time 606269382 ps
CPU time 8.3 seconds
Started Apr 02 12:21:34 PM PDT 24
Finished Apr 02 12:21:42 PM PDT 24
Peak memory 198580 kb
Host smart-016b4585-209a-4c85-a457-2fceabb80f53
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833807065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3833807065
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3436021514
Short name T617
Test name
Test status
Simulation time 751277473 ps
CPU time 5.59 seconds
Started Apr 02 12:21:39 PM PDT 24
Finished Apr 02 12:21:45 PM PDT 24
Peak memory 197716 kb
Host smart-abb06161-1ead-4ac2-8b6e-60db862636fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436021514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3436021514
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2420125576
Short name T101
Test name
Test status
Simulation time 22250212 ps
CPU time 1.03 seconds
Started Apr 02 12:21:22 PM PDT 24
Finished Apr 02 12:21:23 PM PDT 24
Peak memory 197984 kb
Host smart-1bae0ffa-0ce8-43dd-9c14-fc8a763c9b01
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420125576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2420125576
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.4224123049
Short name T723
Test name
Test status
Simulation time 79182412 ps
CPU time 1.72 seconds
Started Apr 02 12:23:05 PM PDT 24
Finished Apr 02 12:23:07 PM PDT 24
Peak memory 199076 kb
Host smart-c4863635-0ee1-4d39-abfe-1b7a6dc35838
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224123049 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.4224123049
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.565616593
Short name T110
Test name
Test status
Simulation time 120355581 ps
CPU time 0.95 seconds
Started Apr 02 12:21:27 PM PDT 24
Finished Apr 02 12:21:28 PM PDT 24
Peak memory 198264 kb
Host smart-ee92900b-88d1-4bbe-abe4-3641dadc8e98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565616593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.565616593
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2132251675
Short name T634
Test name
Test status
Simulation time 44135136 ps
CPU time 0.62 seconds
Started Apr 02 12:21:24 PM PDT 24
Finished Apr 02 12:21:24 PM PDT 24
Peak memory 194016 kb
Host smart-b880ce2d-ffea-427f-abf3-76e7d6b099a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132251675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2132251675
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1669226732
Short name T636
Test name
Test status
Simulation time 84195402 ps
CPU time 2 seconds
Started Apr 02 12:23:04 PM PDT 24
Finished Apr 02 12:23:06 PM PDT 24
Peak memory 199020 kb
Host smart-d7c160c9-5072-455d-9b75-51f914bf5e52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669226732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1669226732
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3268152340
Short name T682
Test name
Test status
Simulation time 149201839 ps
CPU time 1.2 seconds
Started Apr 02 12:22:57 PM PDT 24
Finished Apr 02 12:22:59 PM PDT 24
Peak memory 198364 kb
Host smart-0db41512-3e0f-4961-8766-30cab21b90ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268152340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3268152340
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1357035871
Short name T716
Test name
Test status
Simulation time 796320141 ps
CPU time 2.74 seconds
Started Apr 02 12:22:40 PM PDT 24
Finished Apr 02 12:22:43 PM PDT 24
Peak memory 198956 kb
Host smart-086ea496-bb8a-4397-8f14-56947a074f02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357035871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1357035871
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.473592636
Short name T660
Test name
Test status
Simulation time 24805429 ps
CPU time 0.59 seconds
Started Apr 02 12:24:10 PM PDT 24
Finished Apr 02 12:24:11 PM PDT 24
Peak memory 193592 kb
Host smart-e25ae31e-0b3d-45cf-a5f0-556c64d318be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473592636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.473592636
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1537214252
Short name T677
Test name
Test status
Simulation time 55832516 ps
CPU time 0.6 seconds
Started Apr 02 12:23:05 PM PDT 24
Finished Apr 02 12:23:05 PM PDT 24
Peak memory 193712 kb
Host smart-859584f7-efae-4d55-86c8-5e841af589f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537214252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1537214252
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3563166415
Short name T639
Test name
Test status
Simulation time 38710159 ps
CPU time 0.66 seconds
Started Apr 02 12:24:06 PM PDT 24
Finished Apr 02 12:24:07 PM PDT 24
Peak memory 191760 kb
Host smart-ccbabbbf-80d1-4dfe-9a7b-8e2ca84c52f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563166415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3563166415
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.180020772
Short name T612
Test name
Test status
Simulation time 14512238 ps
CPU time 0.57 seconds
Started Apr 02 12:23:08 PM PDT 24
Finished Apr 02 12:23:09 PM PDT 24
Peak memory 193572 kb
Host smart-45753e14-ce2f-415f-88b5-79c2e23355b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180020772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.180020772
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3670363749
Short name T616
Test name
Test status
Simulation time 215517075 ps
CPU time 0.61 seconds
Started Apr 02 12:22:58 PM PDT 24
Finished Apr 02 12:22:59 PM PDT 24
Peak memory 193740 kb
Host smart-7bbacaa8-581e-4297-b073-0c7544c01ede
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670363749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3670363749
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1297739600
Short name T601
Test name
Test status
Simulation time 12489302 ps
CPU time 0.59 seconds
Started Apr 02 12:23:08 PM PDT 24
Finished Apr 02 12:23:08 PM PDT 24
Peak memory 193476 kb
Host smart-210c3065-860d-4418-84ec-073edf349954
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297739600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1297739600
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3268511050
Short name T620
Test name
Test status
Simulation time 23151151 ps
CPU time 0.58 seconds
Started Apr 02 12:23:13 PM PDT 24
Finished Apr 02 12:23:13 PM PDT 24
Peak memory 193848 kb
Host smart-b230bc0a-8479-4fce-873e-5ad9ad3626de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268511050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3268511050
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.2919952984
Short name T658
Test name
Test status
Simulation time 26776331 ps
CPU time 0.59 seconds
Started Apr 02 12:23:08 PM PDT 24
Finished Apr 02 12:23:09 PM PDT 24
Peak memory 193896 kb
Host smart-6dda0b14-55bd-4561-8284-a45beedf495c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919952984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2919952984
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.4185358112
Short name T701
Test name
Test status
Simulation time 117582916 ps
CPU time 0.56 seconds
Started Apr 02 12:23:08 PM PDT 24
Finished Apr 02 12:23:09 PM PDT 24
Peak memory 193628 kb
Host smart-091f9c62-f2a4-4df3-b3d4-1ae26f8d50da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185358112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.4185358112
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1183461501
Short name T644
Test name
Test status
Simulation time 11375098 ps
CPU time 0.57 seconds
Started Apr 02 12:23:17 PM PDT 24
Finished Apr 02 12:23:18 PM PDT 24
Peak memory 193608 kb
Host smart-d9347172-2cf5-4dd8-bed8-e4fb14186058
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183461501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1183461501
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.619516386
Short name T630
Test name
Test status
Simulation time 56148231658 ps
CPU time 541.71 seconds
Started Apr 02 12:22:17 PM PDT 24
Finished Apr 02 12:31:19 PM PDT 24
Peak memory 215636 kb
Host smart-659fdf0d-b0d8-440b-a92d-6ef1e62bd3bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619516386 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.619516386
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.4262534022
Short name T711
Test name
Test status
Simulation time 148603643 ps
CPU time 0.67 seconds
Started Apr 02 12:21:34 PM PDT 24
Finished Apr 02 12:21:35 PM PDT 24
Peak memory 196132 kb
Host smart-464992a3-a819-4949-b745-0c2dbcdf0436
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262534022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.4262534022
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2174433025
Short name T727
Test name
Test status
Simulation time 38174832 ps
CPU time 0.58 seconds
Started Apr 02 12:21:38 PM PDT 24
Finished Apr 02 12:21:39 PM PDT 24
Peak memory 193740 kb
Host smart-4f6cb6ce-a144-4cc7-a7be-0ca53910ec5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174433025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2174433025
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2689825238
Short name T611
Test name
Test status
Simulation time 95295971 ps
CPU time 1.25 seconds
Started Apr 02 12:23:12 PM PDT 24
Finished Apr 02 12:23:14 PM PDT 24
Peak memory 196064 kb
Host smart-a01cfd61-c252-41d1-9d62-4ff8978b5705
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689825238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.2689825238
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1662268142
Short name T673
Test name
Test status
Simulation time 163360041 ps
CPU time 2.94 seconds
Started Apr 02 12:23:04 PM PDT 24
Finished Apr 02 12:23:07 PM PDT 24
Peak memory 199080 kb
Host smart-bfaf3822-79d3-4d8b-b070-0ea0352fa758
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662268142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1662268142
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1639225750
Short name T118
Test name
Test status
Simulation time 105222682 ps
CPU time 1.98 seconds
Started Apr 02 12:21:37 PM PDT 24
Finished Apr 02 12:21:39 PM PDT 24
Peak memory 199084 kb
Host smart-dca2ee6b-3a43-46a2-acca-137e5c0ec6af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639225750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1639225750
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1874203442
Short name T703
Test name
Test status
Simulation time 83220744612 ps
CPU time 795.62 seconds
Started Apr 02 12:21:57 PM PDT 24
Finished Apr 02 12:35:13 PM PDT 24
Peak memory 215496 kb
Host smart-aeaaf975-7315-492c-8862-2da35701e11b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874203442 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1874203442
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2922443178
Short name T107
Test name
Test status
Simulation time 42875558 ps
CPU time 0.82 seconds
Started Apr 02 12:21:46 PM PDT 24
Finished Apr 02 12:21:47 PM PDT 24
Peak memory 198748 kb
Host smart-dcb20dd9-e6aa-400a-8b4b-2e1ccdd3c33d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922443178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2922443178
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.4085568062
Short name T669
Test name
Test status
Simulation time 37721791 ps
CPU time 0.6 seconds
Started Apr 02 12:22:38 PM PDT 24
Finished Apr 02 12:22:39 PM PDT 24
Peak memory 193748 kb
Host smart-3b83174b-315e-4fac-beda-1571453dd5de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085568062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.4085568062
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1582485392
Short name T659
Test name
Test status
Simulation time 588320900 ps
CPU time 1.99 seconds
Started Apr 02 12:21:44 PM PDT 24
Finished Apr 02 12:21:46 PM PDT 24
Peak memory 198988 kb
Host smart-f013a00b-e277-4f33-a90b-6a1b98815571
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582485392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1582485392
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2367353834
Short name T671
Test name
Test status
Simulation time 68890246 ps
CPU time 1.47 seconds
Started Apr 02 12:21:44 PM PDT 24
Finished Apr 02 12:21:45 PM PDT 24
Peak memory 199176 kb
Host smart-83adfb5f-3f8e-44fa-bf2a-a4676d4a6c9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367353834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2367353834
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1009536147
Short name T63
Test name
Test status
Simulation time 356050540 ps
CPU time 2.84 seconds
Started Apr 02 12:21:43 PM PDT 24
Finished Apr 02 12:21:46 PM PDT 24
Peak memory 198972 kb
Host smart-9457970f-027b-4bf8-95d8-eb07db1c9ce8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009536147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1009536147
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3648974205
Short name T651
Test name
Test status
Simulation time 146599136 ps
CPU time 2.27 seconds
Started Apr 02 12:23:36 PM PDT 24
Finished Apr 02 12:23:39 PM PDT 24
Peak memory 199176 kb
Host smart-7141bd25-4900-4a06-a6dc-b9e91ea3302c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648974205 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.3648974205
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3343096527
Short name T108
Test name
Test status
Simulation time 95346176 ps
CPU time 0.87 seconds
Started Apr 02 12:23:36 PM PDT 24
Finished Apr 02 12:23:37 PM PDT 24
Peak memory 198828 kb
Host smart-bdcf8136-56ac-4c8c-9844-43fc6093b78b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343096527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3343096527
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.3771328200
Short name T709
Test name
Test status
Simulation time 32589171 ps
CPU time 0.62 seconds
Started Apr 02 12:21:55 PM PDT 24
Finished Apr 02 12:21:56 PM PDT 24
Peak memory 193816 kb
Host smart-0030a6c8-5a27-486f-828b-06c301beac9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771328200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3771328200
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3178156778
Short name T627
Test name
Test status
Simulation time 38271346 ps
CPU time 1.06 seconds
Started Apr 02 12:21:50 PM PDT 24
Finished Apr 02 12:21:51 PM PDT 24
Peak memory 198684 kb
Host smart-6c00e93a-b60a-4ecc-97c8-24da2a86a4e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178156778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3178156778
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.4184061918
Short name T664
Test name
Test status
Simulation time 257437073 ps
CPU time 3.5 seconds
Started Apr 02 12:24:00 PM PDT 24
Finished Apr 02 12:24:04 PM PDT 24
Peak memory 199088 kb
Host smart-7671c99f-a499-49fd-a163-64f24aaf5cb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184061918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.4184061918
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.232399536
Short name T692
Test name
Test status
Simulation time 2876030665 ps
CPU time 48.65 seconds
Started Apr 02 12:22:02 PM PDT 24
Finished Apr 02 12:22:51 PM PDT 24
Peak memory 214872 kb
Host smart-f029f146-d5b0-4a76-bb2b-588ade6df8bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232399536 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.232399536
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3807020982
Short name T690
Test name
Test status
Simulation time 18223574 ps
CPU time 1 seconds
Started Apr 02 12:21:55 PM PDT 24
Finished Apr 02 12:21:56 PM PDT 24
Peak memory 198300 kb
Host smart-11e9683b-95a9-4533-8f58-4e8984ee8bbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807020982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3807020982
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3992460130
Short name T637
Test name
Test status
Simulation time 21423581 ps
CPU time 0.62 seconds
Started Apr 02 12:21:55 PM PDT 24
Finished Apr 02 12:21:56 PM PDT 24
Peak memory 193736 kb
Host smart-1aea8b6c-f262-44fe-a8ef-c22a4cf4d2b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992460130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3992460130
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1293007350
Short name T714
Test name
Test status
Simulation time 244594856 ps
CPU time 1.11 seconds
Started Apr 02 12:23:34 PM PDT 24
Finished Apr 02 12:23:35 PM PDT 24
Peak memory 197032 kb
Host smart-440d1ba1-f012-4e6b-87eb-4a146b8d0ac5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293007350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1293007350
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.321362461
Short name T641
Test name
Test status
Simulation time 44624867 ps
CPU time 2.35 seconds
Started Apr 02 12:21:55 PM PDT 24
Finished Apr 02 12:21:58 PM PDT 24
Peak memory 199040 kb
Host smart-f67c18b3-3551-40e8-9d79-bbf3e70c249b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321362461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.321362461
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3800084614
Short name T116
Test name
Test status
Simulation time 183577116 ps
CPU time 3.29 seconds
Started Apr 02 12:22:00 PM PDT 24
Finished Apr 02 12:22:04 PM PDT 24
Peak memory 198984 kb
Host smart-af342259-cf49-4203-a7d3-33d0f531e7d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800084614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3800084614
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.4271592890
Short name T633
Test name
Test status
Simulation time 36264262 ps
CPU time 1.17 seconds
Started Apr 02 12:22:02 PM PDT 24
Finished Apr 02 12:22:03 PM PDT 24
Peak memory 199084 kb
Host smart-43e0ae4f-ea4f-4124-80a8-867200022e66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271592890 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.4271592890
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1440001637
Short name T66
Test name
Test status
Simulation time 66603372 ps
CPU time 0.74 seconds
Started Apr 02 12:21:57 PM PDT 24
Finished Apr 02 12:21:58 PM PDT 24
Peak memory 196668 kb
Host smart-a0769edd-09f3-47e7-a033-cb816f479d85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440001637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1440001637
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.24670850
Short name T685
Test name
Test status
Simulation time 43387916 ps
CPU time 0.61 seconds
Started Apr 02 12:23:17 PM PDT 24
Finished Apr 02 12:23:19 PM PDT 24
Peak memory 192460 kb
Host smart-07961f85-3158-444c-aa36-29973581d8fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24670850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.24670850
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1237386814
Short name T698
Test name
Test status
Simulation time 108719982 ps
CPU time 1.91 seconds
Started Apr 02 12:23:12 PM PDT 24
Finished Apr 02 12:23:15 PM PDT 24
Peak memory 197864 kb
Host smart-a4e6f95f-9391-4b36-a560-dab87a3a21c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237386814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.1237386814
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1421029288
Short name T642
Test name
Test status
Simulation time 26021556 ps
CPU time 1.42 seconds
Started Apr 02 12:21:58 PM PDT 24
Finished Apr 02 12:22:00 PM PDT 24
Peak memory 199124 kb
Host smart-52d52f9f-d013-4e77-8fcc-ea2997e984b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421029288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1421029288
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.382861812
Short name T689
Test name
Test status
Simulation time 706278926 ps
CPU time 3.22 seconds
Started Apr 02 12:22:00 PM PDT 24
Finished Apr 02 12:22:04 PM PDT 24
Peak memory 198976 kb
Host smart-d0fb394c-b256-4015-96a3-4d8320e9b177
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382861812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.382861812
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.4043296688
Short name T582
Test name
Test status
Simulation time 20826657 ps
CPU time 0.64 seconds
Started Apr 02 12:44:08 PM PDT 24
Finished Apr 02 12:44:08 PM PDT 24
Peak memory 195168 kb
Host smart-3ecb9b61-a247-41bf-a49b-4dfabb7ab4a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043296688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.4043296688
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2845344775
Short name T271
Test name
Test status
Simulation time 166186057 ps
CPU time 5.89 seconds
Started Apr 02 12:44:12 PM PDT 24
Finished Apr 02 12:44:18 PM PDT 24
Peak memory 200680 kb
Host smart-7f091a24-73be-410b-802a-870f29f72f41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2845344775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2845344775
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.2292974425
Short name T265
Test name
Test status
Simulation time 1351051628 ps
CPU time 11.22 seconds
Started Apr 02 12:44:10 PM PDT 24
Finished Apr 02 12:44:21 PM PDT 24
Peak memory 199664 kb
Host smart-4a857128-909c-4e7b-acf1-8d0d212442e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292974425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2292974425
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.2396024749
Short name T166
Test name
Test status
Simulation time 3289288980 ps
CPU time 49.96 seconds
Started Apr 02 12:44:10 PM PDT 24
Finished Apr 02 12:45:00 PM PDT 24
Peak memory 199704 kb
Host smart-6d143f2e-58a3-46aa-95a0-261155470d39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2396024749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2396024749
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2273387541
Short name T539
Test name
Test status
Simulation time 92624693484 ps
CPU time 217.76 seconds
Started Apr 02 12:44:06 PM PDT 24
Finished Apr 02 12:47:45 PM PDT 24
Peak memory 199700 kb
Host smart-ad2ae2ff-610c-40e6-b503-e98bb488db8b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273387541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2273387541
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.4175573599
Short name T270
Test name
Test status
Simulation time 1975405298 ps
CPU time 115.05 seconds
Started Apr 02 12:44:06 PM PDT 24
Finished Apr 02 12:46:02 PM PDT 24
Peak memory 199636 kb
Host smart-7689625f-ab3e-4b9b-8496-23f82d5481c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175573599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.4175573599
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1635680063
Short name T35
Test name
Test status
Simulation time 161309845 ps
CPU time 0.85 seconds
Started Apr 02 12:44:08 PM PDT 24
Finished Apr 02 12:44:09 PM PDT 24
Peak memory 218136 kb
Host smart-20fee44c-72a6-409a-b37b-b71777208e7d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635680063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1635680063
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.1352309292
Short name T211
Test name
Test status
Simulation time 196215509 ps
CPU time 1.59 seconds
Started Apr 02 12:44:08 PM PDT 24
Finished Apr 02 12:44:10 PM PDT 24
Peak memory 199612 kb
Host smart-e260a498-cf87-4881-aaee-81907ef1bad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352309292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1352309292
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2188338716
Short name T184
Test name
Test status
Simulation time 292187919474 ps
CPU time 533.47 seconds
Started Apr 02 12:44:10 PM PDT 24
Finished Apr 02 12:53:04 PM PDT 24
Peak memory 199668 kb
Host smart-d6b4a096-f0d6-4c16-82dd-c0cab5cdc43d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188338716 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2188338716
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.3741845560
Short name T200
Test name
Test status
Simulation time 200122649 ps
CPU time 1.02 seconds
Started Apr 02 12:44:13 PM PDT 24
Finished Apr 02 12:44:14 PM PDT 24
Peak memory 199260 kb
Host smart-3231587b-28d1-42d7-914c-44bbf1910b80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741845560 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.3741845560
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.1746823488
Short name T364
Test name
Test status
Simulation time 6797716091 ps
CPU time 370.04 seconds
Started Apr 02 12:44:08 PM PDT 24
Finished Apr 02 12:50:19 PM PDT 24
Peak memory 199652 kb
Host smart-12c255fb-1823-4a15-95c5-b1eee34f08e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746823488 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.1746823488
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3469689465
Short name T146
Test name
Test status
Simulation time 3372107951 ps
CPU time 72.2 seconds
Started Apr 02 12:44:08 PM PDT 24
Finished Apr 02 12:45:21 PM PDT 24
Peak memory 199716 kb
Host smart-c3f37ad9-0932-4c4e-b394-4a17f3075888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469689465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3469689465
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3386667957
Short name T386
Test name
Test status
Simulation time 4892865267 ps
CPU time 52.16 seconds
Started Apr 02 12:44:11 PM PDT 24
Finished Apr 02 12:45:03 PM PDT 24
Peak memory 218156 kb
Host smart-f6efea52-a750-4f71-94a0-ac8d70ecc46c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3386667957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3386667957
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2525588696
Short name T375
Test name
Test status
Simulation time 2920038388 ps
CPU time 10.11 seconds
Started Apr 02 12:44:10 PM PDT 24
Finished Apr 02 12:44:21 PM PDT 24
Peak memory 199696 kb
Host smart-ad8e7ea3-24a0-4109-97ed-fcfb3b525805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525588696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2525588696
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3873942081
Short name T121
Test name
Test status
Simulation time 4311890085 ps
CPU time 56.81 seconds
Started Apr 02 12:44:18 PM PDT 24
Finished Apr 02 12:45:15 PM PDT 24
Peak memory 199704 kb
Host smart-88654fc1-031b-4611-bcb7-22c062a81c2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3873942081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3873942081
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.2482498297
Short name T241
Test name
Test status
Simulation time 11592676107 ps
CPU time 156.71 seconds
Started Apr 02 12:44:10 PM PDT 24
Finished Apr 02 12:46:48 PM PDT 24
Peak memory 199644 kb
Host smart-7e6565a6-87ca-4017-8e2f-b16212e9398f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482498297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2482498297
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2430266291
Short name T394
Test name
Test status
Simulation time 31933628198 ps
CPU time 93.52 seconds
Started Apr 02 12:44:07 PM PDT 24
Finished Apr 02 12:45:41 PM PDT 24
Peak memory 199664 kb
Host smart-87d808bd-5138-4e14-9ea3-9668f40c657f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430266291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2430266291
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1786181006
Short name T38
Test name
Test status
Simulation time 83686213 ps
CPU time 0.96 seconds
Started Apr 02 12:44:10 PM PDT 24
Finished Apr 02 12:44:12 PM PDT 24
Peak memory 219208 kb
Host smart-d607607d-b38b-4db1-bba5-8b881058ed85
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786181006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1786181006
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.2596746837
Short name T331
Test name
Test status
Simulation time 154157365 ps
CPU time 2.62 seconds
Started Apr 02 12:44:12 PM PDT 24
Finished Apr 02 12:44:15 PM PDT 24
Peak memory 199648 kb
Host smart-b4901263-03e2-4242-a2b5-5a570f4e6817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596746837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2596746837
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3123585529
Short name T176
Test name
Test status
Simulation time 200300614211 ps
CPU time 1270.9 seconds
Started Apr 02 12:44:10 PM PDT 24
Finished Apr 02 01:05:22 PM PDT 24
Peak memory 199732 kb
Host smart-ce76e744-c5a5-45d4-8772-a42205527c87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123585529 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3123585529
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.2835511219
Short name T336
Test name
Test status
Simulation time 56047236 ps
CPU time 1.3 seconds
Started Apr 02 12:44:11 PM PDT 24
Finished Apr 02 12:44:13 PM PDT 24
Peak memory 199616 kb
Host smart-71b5cf26-96a8-4a75-abcf-ca08ac0665c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835511219 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.2835511219
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.2516058096
Short name T187
Test name
Test status
Simulation time 24223720111 ps
CPU time 421.6 seconds
Started Apr 02 12:44:10 PM PDT 24
Finished Apr 02 12:51:12 PM PDT 24
Peak memory 199624 kb
Host smart-bdffd62f-de2e-4754-9378-a73dd0078b02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516058096 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.2516058096
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1370548748
Short name T413
Test name
Test status
Simulation time 1876716123 ps
CPU time 85.37 seconds
Started Apr 02 12:44:10 PM PDT 24
Finished Apr 02 12:45:36 PM PDT 24
Peak memory 199664 kb
Host smart-59cb1e7b-829b-4147-8dad-b1f653d83051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370548748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1370548748
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3100490015
Short name T290
Test name
Test status
Simulation time 12467024 ps
CPU time 0.59 seconds
Started Apr 02 12:44:39 PM PDT 24
Finished Apr 02 12:44:40 PM PDT 24
Peak memory 195164 kb
Host smart-a94865b6-23cc-4cbf-9db2-46a4b463f55f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100490015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3100490015
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3004089159
Short name T244
Test name
Test status
Simulation time 7019162029 ps
CPU time 16.35 seconds
Started Apr 02 12:44:42 PM PDT 24
Finished Apr 02 12:44:58 PM PDT 24
Peak memory 220124 kb
Host smart-f74a76e7-f017-40df-a9a0-21d13d494d50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3004089159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3004089159
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.1133547579
Short name T39
Test name
Test status
Simulation time 6744424116 ps
CPU time 24.55 seconds
Started Apr 02 12:44:42 PM PDT 24
Finished Apr 02 12:45:07 PM PDT 24
Peak memory 199660 kb
Host smart-6500451c-dbdb-485b-b446-7174efa1986b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133547579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1133547579
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.2382708596
Short name T388
Test name
Test status
Simulation time 7687077434 ps
CPU time 106.56 seconds
Started Apr 02 12:44:36 PM PDT 24
Finished Apr 02 12:46:23 PM PDT 24
Peak memory 199568 kb
Host smart-3b77c585-a2cd-42ab-bb26-9096173c3d0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2382708596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2382708596
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.2577614645
Short name T233
Test name
Test status
Simulation time 6346422043 ps
CPU time 42.32 seconds
Started Apr 02 12:44:39 PM PDT 24
Finished Apr 02 12:45:21 PM PDT 24
Peak memory 199716 kb
Host smart-ab42028b-5f6f-45ba-95b3-b1437a6cf9d8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577614645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2577614645
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.2125724901
Short name T72
Test name
Test status
Simulation time 7378278406 ps
CPU time 137.43 seconds
Started Apr 02 12:44:37 PM PDT 24
Finished Apr 02 12:46:55 PM PDT 24
Peak memory 199680 kb
Host smart-021d1a07-4553-4224-96fc-f607cf9f446e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125724901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2125724901
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.377441110
Short name T488
Test name
Test status
Simulation time 511212917 ps
CPU time 3.51 seconds
Started Apr 02 12:44:38 PM PDT 24
Finished Apr 02 12:44:42 PM PDT 24
Peak memory 199628 kb
Host smart-3c6f4641-370b-4f11-bc40-b9b556f86b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377441110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.377441110
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.2288912877
Short name T312
Test name
Test status
Simulation time 117981715778 ps
CPU time 2310.18 seconds
Started Apr 02 12:44:41 PM PDT 24
Finished Apr 02 01:23:12 PM PDT 24
Peak memory 216100 kb
Host smart-050c99e3-d1e7-4255-8ebe-62402b92ad36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288912877 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.2288912877
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.1023135791
Short name T178
Test name
Test status
Simulation time 31437647 ps
CPU time 1.24 seconds
Started Apr 02 12:44:40 PM PDT 24
Finished Apr 02 12:44:41 PM PDT 24
Peak memory 199628 kb
Host smart-841cdc52-50b8-42d2-b315-dd7e2078f382
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023135791 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.1023135791
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.1385786432
Short name T451
Test name
Test status
Simulation time 68208387564 ps
CPU time 474.38 seconds
Started Apr 02 12:44:38 PM PDT 24
Finished Apr 02 12:52:33 PM PDT 24
Peak memory 199584 kb
Host smart-05fa1850-42fe-4231-b3dd-912183ba421a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385786432 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.1385786432
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.1155011889
Short name T189
Test name
Test status
Simulation time 2010459208 ps
CPU time 25.68 seconds
Started Apr 02 12:44:37 PM PDT 24
Finished Apr 02 12:45:03 PM PDT 24
Peak memory 199668 kb
Host smart-8a781ff3-e46b-450f-92c7-051c9759cdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155011889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1155011889
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/100.hmac_stress_all_with_rand_reset.663367240
Short name T557
Test name
Test status
Simulation time 44822697352 ps
CPU time 1273.66 seconds
Started Apr 02 12:46:27 PM PDT 24
Finished Apr 02 01:07:42 PM PDT 24
Peak memory 240440 kb
Host smart-4da16679-ff84-4a5b-ba8c-e632ddeb54dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=663367240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.hmac_stress_all_with_rand_reset.663367240
Directory /workspace/100.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.737280680
Short name T167
Test name
Test status
Simulation time 35801911 ps
CPU time 0.57 seconds
Started Apr 02 12:44:44 PM PDT 24
Finished Apr 02 12:44:44 PM PDT 24
Peak memory 195160 kb
Host smart-6c868918-b06f-470f-b0b9-c26981780f69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737280680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.737280680
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.2367073621
Short name T472
Test name
Test status
Simulation time 17674520785 ps
CPU time 31.94 seconds
Started Apr 02 12:44:42 PM PDT 24
Finished Apr 02 12:45:14 PM PDT 24
Peak memory 199548 kb
Host smart-08629039-4543-4d72-b523-dde24e356ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367073621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.2367073621
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1393415415
Short name T573
Test name
Test status
Simulation time 828695255 ps
CPU time 32.43 seconds
Started Apr 02 12:44:42 PM PDT 24
Finished Apr 02 12:45:14 PM PDT 24
Peak memory 199704 kb
Host smart-b47aefb6-7cd1-4bf7-8335-87e80a049741
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1393415415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1393415415
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2258908188
Short name T525
Test name
Test status
Simulation time 13938723826 ps
CPU time 176.06 seconds
Started Apr 02 12:44:42 PM PDT 24
Finished Apr 02 12:47:38 PM PDT 24
Peak memory 199656 kb
Host smart-17e06496-142b-4884-ad0c-62cc055ce22e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258908188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2258908188
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1023877697
Short name T407
Test name
Test status
Simulation time 899413309 ps
CPU time 50.47 seconds
Started Apr 02 12:44:43 PM PDT 24
Finished Apr 02 12:45:34 PM PDT 24
Peak memory 199620 kb
Host smart-e768b00f-a32e-4faf-b447-e6e587b777d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023877697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1023877697
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.478653753
Short name T123
Test name
Test status
Simulation time 473692814 ps
CPU time 5.83 seconds
Started Apr 02 12:44:45 PM PDT 24
Finished Apr 02 12:44:51 PM PDT 24
Peak memory 199688 kb
Host smart-93399f21-f155-49ce-96ca-d4965a9aaa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478653753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.478653753
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.1309998019
Short name T112
Test name
Test status
Simulation time 37307083910 ps
CPU time 975.78 seconds
Started Apr 02 12:44:41 PM PDT 24
Finished Apr 02 01:00:57 PM PDT 24
Peak memory 215536 kb
Host smart-65d040cb-c4d5-454b-81b1-0cb4391dfab3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309998019 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1309998019
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.2437111219
Short name T226
Test name
Test status
Simulation time 43522249 ps
CPU time 1.19 seconds
Started Apr 02 12:44:43 PM PDT 24
Finished Apr 02 12:44:45 PM PDT 24
Peak memory 198960 kb
Host smart-69522454-8272-4956-8909-ae484dd29a59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437111219 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.2437111219
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.3737671067
Short name T591
Test name
Test status
Simulation time 256053325588 ps
CPU time 510.54 seconds
Started Apr 02 12:44:43 PM PDT 24
Finished Apr 02 12:53:14 PM PDT 24
Peak memory 199600 kb
Host smart-f912846c-4c62-4530-a441-f9791876c121
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737671067 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.3737671067
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.415894929
Short name T418
Test name
Test status
Simulation time 383118281 ps
CPU time 15.24 seconds
Started Apr 02 12:44:41 PM PDT 24
Finished Apr 02 12:44:56 PM PDT 24
Peak memory 199632 kb
Host smart-ae0cbfcf-fda9-47b8-bbb2-c757e4787269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415894929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.415894929
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1080629320
Short name T332
Test name
Test status
Simulation time 15079903 ps
CPU time 0.59 seconds
Started Apr 02 12:44:48 PM PDT 24
Finished Apr 02 12:44:49 PM PDT 24
Peak memory 194144 kb
Host smart-1d712178-f9c6-4ead-a2e4-068a7abff709
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080629320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1080629320
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3353326473
Short name T387
Test name
Test status
Simulation time 2344514852 ps
CPU time 25.94 seconds
Started Apr 02 12:44:40 PM PDT 24
Finished Apr 02 12:45:06 PM PDT 24
Peak memory 232464 kb
Host smart-2bc0105c-4e21-497a-93be-54e04b2a2e54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3353326473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3353326473
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.4164697545
Short name T483
Test name
Test status
Simulation time 154999296 ps
CPU time 8.34 seconds
Started Apr 02 12:44:40 PM PDT 24
Finished Apr 02 12:44:49 PM PDT 24
Peak memory 199660 kb
Host smart-96e70f28-962e-4d15-8166-07d8c1a7b6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164697545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.4164697545
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.1966631702
Short name T163
Test name
Test status
Simulation time 3518402340 ps
CPU time 65.3 seconds
Started Apr 02 12:44:45 PM PDT 24
Finished Apr 02 12:45:50 PM PDT 24
Peak memory 199568 kb
Host smart-5dc72846-bd73-4e71-871a-486c85a15c8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1966631702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1966631702
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.3476304733
Short name T526
Test name
Test status
Simulation time 13780548777 ps
CPU time 205.99 seconds
Started Apr 02 12:44:40 PM PDT 24
Finished Apr 02 12:48:06 PM PDT 24
Peak memory 199660 kb
Host smart-00ee3f65-1d2c-438e-9a7e-662811963b35
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476304733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3476304733
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.4228135210
Short name T596
Test name
Test status
Simulation time 11188064595 ps
CPU time 44.45 seconds
Started Apr 02 12:44:40 PM PDT 24
Finished Apr 02 12:45:25 PM PDT 24
Peak memory 199736 kb
Host smart-343ce81f-eed4-4904-a01f-ba125b76022e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228135210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.4228135210
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.4097787887
Short name T513
Test name
Test status
Simulation time 187712323 ps
CPU time 3.01 seconds
Started Apr 02 12:44:44 PM PDT 24
Finished Apr 02 12:44:47 PM PDT 24
Peak memory 199620 kb
Host smart-366c4933-9843-4fdb-97f9-417fa31ac56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097787887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.4097787887
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.2650389694
Short name T520
Test name
Test status
Simulation time 84538669143 ps
CPU time 1425.71 seconds
Started Apr 02 12:44:46 PM PDT 24
Finished Apr 02 01:08:32 PM PDT 24
Peak memory 247976 kb
Host smart-27758cd0-0420-48ec-be3d-ce8a8d41b40c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650389694 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2650389694
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.1630674055
Short name T496
Test name
Test status
Simulation time 57604239 ps
CPU time 1.07 seconds
Started Apr 02 12:44:44 PM PDT 24
Finished Apr 02 12:44:45 PM PDT 24
Peak memory 198992 kb
Host smart-cbc4355b-d72d-4385-a7b9-daec8230ec8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630674055 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.1630674055
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.3326289499
Short name T324
Test name
Test status
Simulation time 8508050404 ps
CPU time 472.48 seconds
Started Apr 02 12:44:45 PM PDT 24
Finished Apr 02 12:52:38 PM PDT 24
Peak memory 199656 kb
Host smart-2ddf465d-db50-48f3-a78e-09a076c57196
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326289499 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.3326289499
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3389921607
Short name T266
Test name
Test status
Simulation time 304804574 ps
CPU time 9.06 seconds
Started Apr 02 12:44:45 PM PDT 24
Finished Apr 02 12:44:54 PM PDT 24
Peak memory 199664 kb
Host smart-11f2911f-f05c-46cd-a775-c5cf4ebefa61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389921607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3389921607
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2608775115
Short name T531
Test name
Test status
Simulation time 13286255 ps
CPU time 0.59 seconds
Started Apr 02 12:44:48 PM PDT 24
Finished Apr 02 12:44:49 PM PDT 24
Peak memory 195196 kb
Host smart-af1a2f2d-66a3-48bb-b945-8ec3ed87b9ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608775115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2608775115
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3245958489
Short name T21
Test name
Test status
Simulation time 1948429636 ps
CPU time 37.24 seconds
Started Apr 02 12:44:47 PM PDT 24
Finished Apr 02 12:45:24 PM PDT 24
Peak memory 216052 kb
Host smart-6e807c40-3830-4d12-85b2-25acfaea563a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3245958489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3245958489
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.507611827
Short name T26
Test name
Test status
Simulation time 502251751 ps
CPU time 24.84 seconds
Started Apr 02 12:44:47 PM PDT 24
Finished Apr 02 12:45:12 PM PDT 24
Peak memory 199676 kb
Host smart-fefaad9c-1006-4fbc-8a80-7b08fb7a1f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507611827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.507611827
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1506880408
Short name T154
Test name
Test status
Simulation time 963261143 ps
CPU time 29.02 seconds
Started Apr 02 12:44:45 PM PDT 24
Finished Apr 02 12:45:14 PM PDT 24
Peak memory 199700 kb
Host smart-732ecd15-faba-4eea-8b5b-79a817a0c350
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1506880408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1506880408
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.3339079156
Short name T517
Test name
Test status
Simulation time 3556979598 ps
CPU time 46.25 seconds
Started Apr 02 12:44:48 PM PDT 24
Finished Apr 02 12:45:35 PM PDT 24
Peak memory 199672 kb
Host smart-a5cc3cda-ee64-4e23-b5b8-ab7d38cf594b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339079156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3339079156
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2235221501
Short name T73
Test name
Test status
Simulation time 735129267 ps
CPU time 20.36 seconds
Started Apr 02 12:44:48 PM PDT 24
Finished Apr 02 12:45:09 PM PDT 24
Peak memory 199648 kb
Host smart-e1ff24cd-3c9c-495b-b1db-b3eeb7cb5e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235221501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2235221501
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2196938189
Short name T409
Test name
Test status
Simulation time 1818487174 ps
CPU time 4.21 seconds
Started Apr 02 12:44:44 PM PDT 24
Finished Apr 02 12:44:49 PM PDT 24
Peak memory 199636 kb
Host smart-4273d94b-115d-4921-82ca-e70065e3f55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196938189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2196938189
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.86948075
Short name T82
Test name
Test status
Simulation time 377164637284 ps
CPU time 1345.84 seconds
Started Apr 02 12:44:48 PM PDT 24
Finished Apr 02 01:07:14 PM PDT 24
Peak memory 216092 kb
Host smart-acc28ab6-2b88-422a-ab82-32a30f04d403
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86948075 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.86948075
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.424940711
Short name T341
Test name
Test status
Simulation time 32711501 ps
CPU time 1.22 seconds
Started Apr 02 12:44:47 PM PDT 24
Finished Apr 02 12:44:48 PM PDT 24
Peak memory 199608 kb
Host smart-18aad4ca-36d4-4f7c-af2b-45eb8345b3c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424940711 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_hmac_vectors.424940711
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.3369458399
Short name T209
Test name
Test status
Simulation time 35643060306 ps
CPU time 491.09 seconds
Started Apr 02 12:44:48 PM PDT 24
Finished Apr 02 12:52:59 PM PDT 24
Peak memory 199528 kb
Host smart-d3bee421-6aa3-4119-83bd-27072f9fa893
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369458399 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.3369458399
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3032095421
Short name T261
Test name
Test status
Simulation time 2366640480 ps
CPU time 32.88 seconds
Started Apr 02 12:44:48 PM PDT 24
Finished Apr 02 12:45:21 PM PDT 24
Peak memory 199580 kb
Host smart-e0070561-9f23-4f41-9877-046806922aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032095421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3032095421
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2066498493
Short name T549
Test name
Test status
Simulation time 47785828 ps
CPU time 0.56 seconds
Started Apr 02 12:44:49 PM PDT 24
Finished Apr 02 12:44:49 PM PDT 24
Peak memory 195168 kb
Host smart-4e785584-4804-4e79-830f-fbc81ba8cc8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066498493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2066498493
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2782791164
Short name T478
Test name
Test status
Simulation time 249992064 ps
CPU time 1.72 seconds
Started Apr 02 12:44:45 PM PDT 24
Finished Apr 02 12:44:47 PM PDT 24
Peak memory 199432 kb
Host smart-6fd52124-f842-4b80-b46a-8314993396e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2782791164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2782791164
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.686738604
Short name T120
Test name
Test status
Simulation time 4300891240 ps
CPU time 56.02 seconds
Started Apr 02 12:44:46 PM PDT 24
Finished Apr 02 12:45:42 PM PDT 24
Peak memory 199704 kb
Host smart-e3a578e3-e044-43df-a136-2ebf49b46e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686738604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.686738604
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.1493489594
Short name T384
Test name
Test status
Simulation time 3661424465 ps
CPU time 104.42 seconds
Started Apr 02 12:44:45 PM PDT 24
Finished Apr 02 12:46:29 PM PDT 24
Peak memory 199716 kb
Host smart-4de0d205-6ab3-4fac-8f62-ba8116b49597
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1493489594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1493489594
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.4023793693
Short name T33
Test name
Test status
Simulation time 5617962462 ps
CPU time 49.03 seconds
Started Apr 02 12:44:48 PM PDT 24
Finished Apr 02 12:45:37 PM PDT 24
Peak memory 199736 kb
Host smart-2158039c-5b09-4a26-8ef9-a07f954b8ac8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023793693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.4023793693
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.861534342
Short name T251
Test name
Test status
Simulation time 5581615191 ps
CPU time 100.2 seconds
Started Apr 02 12:44:46 PM PDT 24
Finished Apr 02 12:46:26 PM PDT 24
Peak memory 199740 kb
Host smart-78a3a9f9-1177-40f2-9df4-17de3361b86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861534342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.861534342
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.2494578556
Short name T134
Test name
Test status
Simulation time 443193488 ps
CPU time 3.02 seconds
Started Apr 02 12:44:46 PM PDT 24
Finished Apr 02 12:44:49 PM PDT 24
Peak memory 199616 kb
Host smart-a4897e3f-7933-4477-a207-ac7a98f84f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494578556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2494578556
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2797988226
Short name T81
Test name
Test status
Simulation time 969332527045 ps
CPU time 1620.96 seconds
Started Apr 02 12:44:49 PM PDT 24
Finished Apr 02 01:11:51 PM PDT 24
Peak memory 216088 kb
Host smart-9dfe4cda-feb0-40f0-9c79-f47d021efe2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797988226 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2797988226
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.1950760239
Short name T519
Test name
Test status
Simulation time 120893562 ps
CPU time 1.24 seconds
Started Apr 02 12:44:50 PM PDT 24
Finished Apr 02 12:44:51 PM PDT 24
Peak memory 199604 kb
Host smart-f663f105-9234-405d-9ced-566dda70bb11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950760239 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.1950760239
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.2086932752
Short name T533
Test name
Test status
Simulation time 26339516842 ps
CPU time 446.32 seconds
Started Apr 02 12:44:53 PM PDT 24
Finished Apr 02 12:52:20 PM PDT 24
Peak memory 199500 kb
Host smart-db6d779f-eb3a-4673-96bf-85ac795df624
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086932752 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.2086932752
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2821433069
Short name T193
Test name
Test status
Simulation time 1712195902 ps
CPU time 7.7 seconds
Started Apr 02 12:44:51 PM PDT 24
Finished Apr 02 12:44:59 PM PDT 24
Peak memory 199584 kb
Host smart-f74742dd-b64b-4d2a-a422-519b657aa3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821433069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2821433069
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.785220953
Short name T592
Test name
Test status
Simulation time 29569534 ps
CPU time 0.56 seconds
Started Apr 02 12:44:52 PM PDT 24
Finished Apr 02 12:44:52 PM PDT 24
Peak memory 194140 kb
Host smart-379bcc20-68eb-43be-aa01-57569549c568
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785220953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.785220953
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1345015830
Short name T429
Test name
Test status
Simulation time 336208795 ps
CPU time 6 seconds
Started Apr 02 12:44:51 PM PDT 24
Finished Apr 02 12:44:57 PM PDT 24
Peak memory 207828 kb
Host smart-83e4614b-bfb6-45b2-9896-9491f3026266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1345015830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1345015830
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1453550941
Short name T593
Test name
Test status
Simulation time 112127304 ps
CPU time 1.49 seconds
Started Apr 02 12:44:49 PM PDT 24
Finished Apr 02 12:44:51 PM PDT 24
Peak memory 199692 kb
Host smart-ad17678a-0b13-439b-8e88-7e9281b6de19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453550941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1453550941
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.359310808
Short name T60
Test name
Test status
Simulation time 1976033761 ps
CPU time 115.9 seconds
Started Apr 02 12:45:11 PM PDT 24
Finished Apr 02 12:47:07 PM PDT 24
Peak memory 199648 kb
Host smart-12c3d9aa-147d-4a18-bede-3fae6e4f4902
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=359310808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.359310808
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2412585683
Short name T46
Test name
Test status
Simulation time 7322960783 ps
CPU time 49.62 seconds
Started Apr 02 12:44:51 PM PDT 24
Finished Apr 02 12:45:41 PM PDT 24
Peak memory 199760 kb
Host smart-3a56a794-b3cb-4996-a8d1-848306ed84d2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412585683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2412585683
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3896452066
Short name T598
Test name
Test status
Simulation time 1344203663 ps
CPU time 27.41 seconds
Started Apr 02 12:44:53 PM PDT 24
Finished Apr 02 12:45:21 PM PDT 24
Peak memory 199632 kb
Host smart-3571f53d-4d73-403d-af90-e64ace552185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896452066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3896452066
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2110546855
Short name T248
Test name
Test status
Simulation time 82462203 ps
CPU time 1.52 seconds
Started Apr 02 12:44:54 PM PDT 24
Finished Apr 02 12:44:56 PM PDT 24
Peak memory 199508 kb
Host smart-158ae8d2-b6dc-454e-a97a-0b436f49c257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110546855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2110546855
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.4186862172
Short name T453
Test name
Test status
Simulation time 42744704 ps
CPU time 0.96 seconds
Started Apr 02 12:45:10 PM PDT 24
Finished Apr 02 12:45:12 PM PDT 24
Peak memory 198524 kb
Host smart-47868d2a-4c25-4d56-b104-2efe25023fa9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186862172 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.4186862172
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.3308105591
Short name T482
Test name
Test status
Simulation time 212687297731 ps
CPU time 455.76 seconds
Started Apr 02 12:45:11 PM PDT 24
Finished Apr 02 12:52:47 PM PDT 24
Peak memory 199636 kb
Host smart-de0d4fe2-e899-4951-97d5-90d6c16eafde
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308105591 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.3308105591
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.856172516
Short name T507
Test name
Test status
Simulation time 6081767893 ps
CPU time 81.12 seconds
Started Apr 02 12:45:11 PM PDT 24
Finished Apr 02 12:46:33 PM PDT 24
Peak memory 199708 kb
Host smart-32fea297-078c-4577-bc47-36c405c1fc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856172516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.856172516
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3111240589
Short name T406
Test name
Test status
Simulation time 13256259 ps
CPU time 0.58 seconds
Started Apr 02 12:44:57 PM PDT 24
Finished Apr 02 12:44:58 PM PDT 24
Peak memory 195252 kb
Host smart-a3391a53-ef60-45f2-a777-ed5e20cdd8ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111240589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3111240589
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.992811110
Short name T521
Test name
Test status
Simulation time 614830616 ps
CPU time 20.4 seconds
Started Apr 02 12:44:46 PM PDT 24
Finished Apr 02 12:45:06 PM PDT 24
Peak memory 207828 kb
Host smart-efa38019-b75a-47a6-9d9f-c3a5c54a213b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=992811110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.992811110
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1212605540
Short name T443
Test name
Test status
Simulation time 7256438533 ps
CPU time 39 seconds
Started Apr 02 12:44:47 PM PDT 24
Finished Apr 02 12:45:26 PM PDT 24
Peak memory 199724 kb
Host smart-1d6fbd64-17b9-4332-97f6-c70a0e5c333d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212605540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1212605540
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3022017961
Short name T321
Test name
Test status
Simulation time 1492098295 ps
CPU time 90.26 seconds
Started Apr 02 12:44:47 PM PDT 24
Finished Apr 02 12:46:18 PM PDT 24
Peak memory 199668 kb
Host smart-6db01bf8-b155-4889-bf76-aa5d4edbae30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3022017961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3022017961
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.4068204499
Short name T303
Test name
Test status
Simulation time 6174872731 ps
CPU time 31.07 seconds
Started Apr 02 12:44:48 PM PDT 24
Finished Apr 02 12:45:20 PM PDT 24
Peak memory 199700 kb
Host smart-7b366437-4c0d-481d-a511-a925af677743
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068204499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.4068204499
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2069351014
Short name T197
Test name
Test status
Simulation time 35106784911 ps
CPU time 137.44 seconds
Started Apr 02 12:44:49 PM PDT 24
Finished Apr 02 12:47:06 PM PDT 24
Peak memory 199592 kb
Host smart-c5e44e42-29f3-47d0-8837-5b3d2679308c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069351014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2069351014
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.131379629
Short name T530
Test name
Test status
Simulation time 992515847 ps
CPU time 6.47 seconds
Started Apr 02 12:44:51 PM PDT 24
Finished Apr 02 12:44:58 PM PDT 24
Peak memory 199644 kb
Host smart-449bf1f3-0607-4b82-99fe-ed3e42cdc55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131379629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.131379629
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.2247271423
Short name T408
Test name
Test status
Simulation time 115162277 ps
CPU time 1.12 seconds
Started Apr 02 12:45:01 PM PDT 24
Finished Apr 02 12:45:02 PM PDT 24
Peak memory 199604 kb
Host smart-513b5223-c9c9-45d4-be4c-53f48a9b6f87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247271423 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.2247271423
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.2049032117
Short name T219
Test name
Test status
Simulation time 37029858261 ps
CPU time 460.17 seconds
Started Apr 02 12:45:06 PM PDT 24
Finished Apr 02 12:52:47 PM PDT 24
Peak memory 199632 kb
Host smart-af8248d4-3edd-4133-9389-3928a16dc53a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049032117 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.2049032117
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2515589714
Short name T182
Test name
Test status
Simulation time 18792046276 ps
CPU time 75.93 seconds
Started Apr 02 12:44:54 PM PDT 24
Finished Apr 02 12:46:11 PM PDT 24
Peak memory 199716 kb
Host smart-cab6e953-9257-4b49-8d1d-6213a212d6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515589714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2515589714
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/161.hmac_stress_all_with_rand_reset.1905022179
Short name T7
Test name
Test status
Simulation time 70341758842 ps
CPU time 432.12 seconds
Started Apr 02 12:46:49 PM PDT 24
Finished Apr 02 12:54:01 PM PDT 24
Peak memory 215928 kb
Host smart-75bd4264-6086-48ba-a694-2cf5587cf15b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1905022179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.hmac_stress_all_with_rand_reset.1905022179
Directory /workspace/161.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.945154975
Short name T337
Test name
Test status
Simulation time 34603456 ps
CPU time 0.57 seconds
Started Apr 02 12:44:53 PM PDT 24
Finished Apr 02 12:44:54 PM PDT 24
Peak memory 195172 kb
Host smart-300dce4b-ccc2-4b09-9fe7-326283762cb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945154975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.945154975
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3660841064
Short name T20
Test name
Test status
Simulation time 289282757 ps
CPU time 15.51 seconds
Started Apr 02 12:44:51 PM PDT 24
Finished Apr 02 12:45:06 PM PDT 24
Peak memory 232112 kb
Host smart-dd8331d4-365b-4c44-9a6d-9f351cfa888f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3660841064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3660841064
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.874896607
Short name T441
Test name
Test status
Simulation time 930998360 ps
CPU time 20.35 seconds
Started Apr 02 12:44:52 PM PDT 24
Finished Apr 02 12:45:12 PM PDT 24
Peak memory 199700 kb
Host smart-5efa750a-6552-434b-ab6d-35ad2c8436b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874896607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.874896607
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.323768019
Short name T580
Test name
Test status
Simulation time 6960460352 ps
CPU time 44.81 seconds
Started Apr 02 12:44:54 PM PDT 24
Finished Apr 02 12:45:40 PM PDT 24
Peak memory 199732 kb
Host smart-054d5d3e-ee44-4e1e-af11-5fde3559c6ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=323768019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.323768019
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.2814573565
Short name T315
Test name
Test status
Simulation time 14930976505 ps
CPU time 145.32 seconds
Started Apr 02 12:44:48 PM PDT 24
Finished Apr 02 12:47:14 PM PDT 24
Peak memory 199708 kb
Host smart-ab7d2964-4159-4185-969e-4739c90cf7ad
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814573565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2814573565
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3045980385
Short name T484
Test name
Test status
Simulation time 344287645 ps
CPU time 7.44 seconds
Started Apr 02 12:44:51 PM PDT 24
Finished Apr 02 12:44:58 PM PDT 24
Peak memory 199644 kb
Host smart-44850483-386a-4dcf-84bb-7f1d1b6cfd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045980385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3045980385
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2901734335
Short name T298
Test name
Test status
Simulation time 408414802 ps
CPU time 2.72 seconds
Started Apr 02 12:45:11 PM PDT 24
Finished Apr 02 12:45:14 PM PDT 24
Peak memory 199624 kb
Host smart-72abdae1-0d0e-4fa1-a72e-6d7ab59125e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901734335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2901734335
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2168721021
Short name T542
Test name
Test status
Simulation time 84747061712 ps
CPU time 831.81 seconds
Started Apr 02 12:44:53 PM PDT 24
Finished Apr 02 12:58:46 PM PDT 24
Peak memory 242512 kb
Host smart-5ca19db2-c44f-4714-bc55-09f8fa2662f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168721021 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2168721021
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.684224638
Short name T506
Test name
Test status
Simulation time 217571246 ps
CPU time 1.27 seconds
Started Apr 02 12:44:54 PM PDT 24
Finished Apr 02 12:44:56 PM PDT 24
Peak memory 199232 kb
Host smart-c84b6749-0411-4591-97da-121f7030486b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684224638 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.hmac_test_hmac_vectors.684224638
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.2222542591
Short name T589
Test name
Test status
Simulation time 58074269218 ps
CPU time 540.42 seconds
Started Apr 02 12:44:54 PM PDT 24
Finished Apr 02 12:53:55 PM PDT 24
Peak memory 199580 kb
Host smart-68cad766-753e-4a63-829a-1c16b7f013c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222542591 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.2222542591
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.2012332808
Short name T461
Test name
Test status
Simulation time 473617943 ps
CPU time 13.27 seconds
Started Apr 02 12:44:52 PM PDT 24
Finished Apr 02 12:45:05 PM PDT 24
Peak memory 199672 kb
Host smart-f8701433-c76a-4d25-baae-250eb4d2b27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012332808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.2012332808
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/178.hmac_stress_all_with_rand_reset.1689673358
Short name T68
Test name
Test status
Simulation time 15733929458 ps
CPU time 324.85 seconds
Started Apr 02 12:46:50 PM PDT 24
Finished Apr 02 12:52:16 PM PDT 24
Peak memory 227472 kb
Host smart-533879f5-08af-4de5-8cc6-f9b6059ee15a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1689673358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.hmac_stress_all_with_rand_reset.1689673358
Directory /workspace/178.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2453038883
Short name T357
Test name
Test status
Simulation time 30786508 ps
CPU time 0.55 seconds
Started Apr 02 12:44:53 PM PDT 24
Finished Apr 02 12:44:55 PM PDT 24
Peak memory 195244 kb
Host smart-f1a86d9b-da22-47ce-99b0-ff740eb4b451
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453038883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2453038883
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.146134983
Short name T74
Test name
Test status
Simulation time 862818093 ps
CPU time 33.74 seconds
Started Apr 02 12:45:02 PM PDT 24
Finished Apr 02 12:45:36 PM PDT 24
Peak memory 227264 kb
Host smart-a0c60ce7-0319-4f1b-b745-e3d3012f12a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=146134983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.146134983
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.101322789
Short name T411
Test name
Test status
Simulation time 1921960503 ps
CPU time 36.15 seconds
Started Apr 02 12:44:51 PM PDT 24
Finished Apr 02 12:45:27 PM PDT 24
Peak memory 199652 kb
Host smart-0e43b0f0-0572-4b81-b01e-05352c3aad71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101322789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.101322789
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3748050726
Short name T435
Test name
Test status
Simulation time 6121284730 ps
CPU time 89.92 seconds
Started Apr 02 12:44:52 PM PDT 24
Finished Apr 02 12:46:22 PM PDT 24
Peak memory 199724 kb
Host smart-787d4a15-339f-4e95-ad02-4c3b4278542f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3748050726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3748050726
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.528731647
Short name T58
Test name
Test status
Simulation time 11694215225 ps
CPU time 59.31 seconds
Started Apr 02 12:44:57 PM PDT 24
Finished Apr 02 12:45:56 PM PDT 24
Peak memory 199540 kb
Host smart-17dd226e-2e0f-4077-b5a0-5aef767a1600
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528731647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.528731647
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.4238114962
Short name T293
Test name
Test status
Simulation time 11649581294 ps
CPU time 70.22 seconds
Started Apr 02 12:44:50 PM PDT 24
Finished Apr 02 12:46:00 PM PDT 24
Peak memory 199740 kb
Host smart-0e8aeb1f-4698-4864-9409-493e9a4fb4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238114962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.4238114962
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2284852106
Short name T404
Test name
Test status
Simulation time 435795189 ps
CPU time 3.46 seconds
Started Apr 02 12:44:54 PM PDT 24
Finished Apr 02 12:44:58 PM PDT 24
Peak memory 199636 kb
Host smart-f7582e7d-afb1-4b3a-9dab-cf07e6d6d47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284852106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2284852106
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.2616023637
Short name T80
Test name
Test status
Simulation time 633092274922 ps
CPU time 1156.83 seconds
Started Apr 02 12:44:56 PM PDT 24
Finished Apr 02 01:04:13 PM PDT 24
Peak memory 215108 kb
Host smart-80023176-6a71-43f5-8f7a-e8bc2365e5dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616023637 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2616023637
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.3370993151
Short name T96
Test name
Test status
Simulation time 438322772 ps
CPU time 1.2 seconds
Started Apr 02 12:44:53 PM PDT 24
Finished Apr 02 12:44:55 PM PDT 24
Peak memory 199576 kb
Host smart-f5c8f1d8-6555-4e59-a801-8e004aef6ef6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370993151 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.3370993151
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.3626644324
Short name T438
Test name
Test status
Simulation time 156054732370 ps
CPU time 470.82 seconds
Started Apr 02 12:44:59 PM PDT 24
Finished Apr 02 12:52:50 PM PDT 24
Peak memory 199648 kb
Host smart-6d4fb8d1-b922-48b5-ba50-71b0bb468259
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626644324 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.3626644324
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.4169781092
Short name T586
Test name
Test status
Simulation time 17586677961 ps
CPU time 59.13 seconds
Started Apr 02 12:44:52 PM PDT 24
Finished Apr 02 12:45:52 PM PDT 24
Peak memory 199668 kb
Host smart-75338e95-1f38-47aa-abbd-53b701ca6113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169781092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.4169781092
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/182.hmac_stress_all_with_rand_reset.1314118656
Short name T9
Test name
Test status
Simulation time 122218335994 ps
CPU time 564.14 seconds
Started Apr 02 12:46:53 PM PDT 24
Finished Apr 02 12:56:18 PM PDT 24
Peak memory 245860 kb
Host smart-eb92a479-3252-4c35-a38b-be9b5ec289df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1314118656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.hmac_stress_all_with_rand_reset.1314118656
Directory /workspace/182.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.241644696
Short name T432
Test name
Test status
Simulation time 14236675 ps
CPU time 0.59 seconds
Started Apr 02 12:44:53 PM PDT 24
Finished Apr 02 12:44:54 PM PDT 24
Peak memory 195188 kb
Host smart-377840d4-cb9b-470e-8ae6-e276116dfe70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241644696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.241644696
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.1323656995
Short name T423
Test name
Test status
Simulation time 1484162317 ps
CPU time 50.17 seconds
Started Apr 02 12:44:53 PM PDT 24
Finished Apr 02 12:45:44 PM PDT 24
Peak memory 215640 kb
Host smart-6ed07c5f-81bc-4707-970c-3506b9874540
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1323656995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.1323656995
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2820174669
Short name T213
Test name
Test status
Simulation time 4807708556 ps
CPU time 77.45 seconds
Started Apr 02 12:44:51 PM PDT 24
Finished Apr 02 12:46:09 PM PDT 24
Peak memory 199684 kb
Host smart-91917ee8-993b-43fa-b13a-ca59522ad97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820174669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2820174669
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1313531374
Short name T90
Test name
Test status
Simulation time 1064026928 ps
CPU time 59 seconds
Started Apr 02 12:44:52 PM PDT 24
Finished Apr 02 12:45:51 PM PDT 24
Peak memory 199668 kb
Host smart-ab5270e3-3899-42d5-8a73-9b2273ae7861
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1313531374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1313531374
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2764269345
Short name T159
Test name
Test status
Simulation time 8457576326 ps
CPU time 38.46 seconds
Started Apr 02 12:44:58 PM PDT 24
Finished Apr 02 12:45:37 PM PDT 24
Peak memory 199724 kb
Host smart-2df0fafa-97b9-4933-8a7c-8bb728b41c88
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764269345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2764269345
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.2559443332
Short name T346
Test name
Test status
Simulation time 3070568943 ps
CPU time 48.05 seconds
Started Apr 02 12:44:54 PM PDT 24
Finished Apr 02 12:45:43 PM PDT 24
Peak memory 199668 kb
Host smart-7c829ec8-a952-49cf-9964-e8a0854f2b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559443332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2559443332
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.810030383
Short name T425
Test name
Test status
Simulation time 517328552 ps
CPU time 6.45 seconds
Started Apr 02 12:44:54 PM PDT 24
Finished Apr 02 12:45:01 PM PDT 24
Peak memory 199660 kb
Host smart-ee6f6d3c-a05a-4f2c-afd8-a8c28826d450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810030383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.810030383
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.81853122
Short name T91
Test name
Test status
Simulation time 263818002 ps
CPU time 2.41 seconds
Started Apr 02 12:45:03 PM PDT 24
Finished Apr 02 12:45:06 PM PDT 24
Peak memory 199528 kb
Host smart-18c35f34-bbe4-4944-b81d-f8d874dbd33d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81853122 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.81853122
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.3557415569
Short name T308
Test name
Test status
Simulation time 31802122 ps
CPU time 1.25 seconds
Started Apr 02 12:45:01 PM PDT 24
Finished Apr 02 12:45:02 PM PDT 24
Peak memory 199136 kb
Host smart-74b208fe-4b0d-41bf-850f-e7a6215081d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557415569 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.3557415569
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.3577404501
Short name T3
Test name
Test status
Simulation time 53637630235 ps
CPU time 525.05 seconds
Started Apr 02 12:45:03 PM PDT 24
Finished Apr 02 12:53:49 PM PDT 24
Peak memory 199644 kb
Host smart-ae6542b6-b1fb-45d5-b03a-13b72f490f09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577404501 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.3577404501
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.150718349
Short name T574
Test name
Test status
Simulation time 1528008599 ps
CPU time 28.39 seconds
Started Apr 02 12:45:07 PM PDT 24
Finished Apr 02 12:45:36 PM PDT 24
Peak memory 199624 kb
Host smart-31e1024f-97f6-421c-a17d-028cbe19d299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150718349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.150718349
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/193.hmac_stress_all_with_rand_reset.3565992501
Short name T70
Test name
Test status
Simulation time 2487964409 ps
CPU time 131.63 seconds
Started Apr 02 12:47:00 PM PDT 24
Finished Apr 02 12:49:12 PM PDT 24
Peak memory 216112 kb
Host smart-7d67b9b8-afa7-4e31-9bb0-eb4c2759dcc5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3565992501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.hmac_stress_all_with_rand_reset.3565992501
Directory /workspace/193.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/196.hmac_stress_all_with_rand_reset.4167259551
Short name T12
Test name
Test status
Simulation time 97466239539 ps
CPU time 843.3 seconds
Started Apr 02 12:46:59 PM PDT 24
Finished Apr 02 01:01:03 PM PDT 24
Peak memory 216184 kb
Host smart-25826ace-0195-4519-a739-fecd682e6557
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4167259551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.hmac_stress_all_with_rand_reset.4167259551
Directory /workspace/196.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2579227409
Short name T157
Test name
Test status
Simulation time 10955412 ps
CPU time 0.61 seconds
Started Apr 02 12:44:10 PM PDT 24
Finished Apr 02 12:44:10 PM PDT 24
Peak memory 194140 kb
Host smart-daf85047-d9f4-49d1-87d8-88a25840b7a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579227409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2579227409
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.115332744
Short name T198
Test name
Test status
Simulation time 5254602687 ps
CPU time 36.29 seconds
Started Apr 02 12:44:09 PM PDT 24
Finished Apr 02 12:44:45 PM PDT 24
Peak memory 216000 kb
Host smart-96457f1b-f4aa-4720-b223-aad79e69566d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=115332744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.115332744
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3183165924
Short name T278
Test name
Test status
Simulation time 7936694134 ps
CPU time 20.47 seconds
Started Apr 02 12:44:11 PM PDT 24
Finished Apr 02 12:44:32 PM PDT 24
Peak memory 199708 kb
Host smart-40f7f172-e2c2-4d2a-bed5-6d2833ff7421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183165924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3183165924
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.97487823
Short name T450
Test name
Test status
Simulation time 773212908 ps
CPU time 42.14 seconds
Started Apr 02 12:44:15 PM PDT 24
Finished Apr 02 12:44:57 PM PDT 24
Peak memory 199832 kb
Host smart-40c6e3a7-f8ca-4bfc-979d-38c56f3c412b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=97487823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.97487823
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.237828387
Short name T29
Test name
Test status
Simulation time 6053860370 ps
CPU time 71.08 seconds
Started Apr 02 12:44:11 PM PDT 24
Finished Apr 02 12:45:22 PM PDT 24
Peak memory 199644 kb
Host smart-0c2a408b-0c45-4c5c-9316-a3b9222cddad
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237828387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.237828387
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.233561816
Short name T285
Test name
Test status
Simulation time 4358763266 ps
CPU time 79.2 seconds
Started Apr 02 12:44:14 PM PDT 24
Finished Apr 02 12:45:33 PM PDT 24
Peak memory 199888 kb
Host smart-fdc6f2b3-760e-4efd-a66e-001458d5b213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233561816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.233561816
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3566670760
Short name T36
Test name
Test status
Simulation time 161153165 ps
CPU time 1.01 seconds
Started Apr 02 12:44:18 PM PDT 24
Finished Apr 02 12:44:19 PM PDT 24
Peak memory 219128 kb
Host smart-f9c5aa11-056a-4880-a5a1-0c9cc84f84eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566670760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3566670760
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.450347516
Short name T371
Test name
Test status
Simulation time 194160432 ps
CPU time 5.86 seconds
Started Apr 02 12:44:18 PM PDT 24
Finished Apr 02 12:44:24 PM PDT 24
Peak memory 199464 kb
Host smart-a8b88998-2651-4768-b27d-779799f35c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450347516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.450347516
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.944759293
Short name T30
Test name
Test status
Simulation time 24268282063 ps
CPU time 1253.67 seconds
Started Apr 02 12:44:14 PM PDT 24
Finished Apr 02 01:05:08 PM PDT 24
Peak memory 199888 kb
Host smart-40493a80-d94b-4ef5-9c85-6d2905e262fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944759293 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.944759293
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.2461374411
Short name T227
Test name
Test status
Simulation time 220318172 ps
CPU time 1.1 seconds
Started Apr 02 12:44:13 PM PDT 24
Finished Apr 02 12:44:15 PM PDT 24
Peak memory 199380 kb
Host smart-338f8dea-694c-4e62-b6c4-fddd78b05578
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461374411 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.2461374411
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.1344978788
Short name T382
Test name
Test status
Simulation time 33496386454 ps
CPU time 425.42 seconds
Started Apr 02 12:44:18 PM PDT 24
Finished Apr 02 12:51:24 PM PDT 24
Peak memory 199572 kb
Host smart-420711e4-4c07-4bb0-bbc0-84a070fdbe7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344978788 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.1344978788
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.34186672
Short name T383
Test name
Test status
Simulation time 3731045667 ps
CPU time 40.08 seconds
Started Apr 02 12:44:19 PM PDT 24
Finished Apr 02 12:44:59 PM PDT 24
Peak memory 199560 kb
Host smart-f47d3b99-4cc9-4db6-8607-b04f28a95e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34186672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.34186672
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2185236785
Short name T570
Test name
Test status
Simulation time 26708425 ps
CPU time 0.57 seconds
Started Apr 02 12:44:57 PM PDT 24
Finished Apr 02 12:44:57 PM PDT 24
Peak memory 194132 kb
Host smart-c3c71cc5-c5a0-48a7-aa26-a560bd1c107b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185236785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2185236785
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1149659964
Short name T465
Test name
Test status
Simulation time 593359205 ps
CPU time 25.76 seconds
Started Apr 02 12:44:55 PM PDT 24
Finished Apr 02 12:45:21 PM PDT 24
Peak memory 219012 kb
Host smart-02272a6c-d13d-4a2f-9ffc-1f41e099f635
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1149659964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1149659964
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.620834787
Short name T437
Test name
Test status
Simulation time 4518674665 ps
CPU time 34.43 seconds
Started Apr 02 12:44:54 PM PDT 24
Finished Apr 02 12:45:29 PM PDT 24
Peak memory 199688 kb
Host smart-e9b9bb6c-a9d8-484c-a07e-3f046bf7772b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620834787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.620834787
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3868062499
Short name T183
Test name
Test status
Simulation time 174260124 ps
CPU time 1.85 seconds
Started Apr 02 12:44:57 PM PDT 24
Finished Apr 02 12:45:00 PM PDT 24
Peak memory 199624 kb
Host smart-8689ed9a-617c-4646-8e71-2dad55c9f667
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3868062499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3868062499
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1181449763
Short name T556
Test name
Test status
Simulation time 1935841961 ps
CPU time 106.54 seconds
Started Apr 02 12:44:51 PM PDT 24
Finished Apr 02 12:46:38 PM PDT 24
Peak memory 199616 kb
Host smart-ea1f82d3-d4da-4b8b-9e17-3ba8fd4ed0ed
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181449763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1181449763
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2783855155
Short name T2
Test name
Test status
Simulation time 1896622124 ps
CPU time 18.76 seconds
Started Apr 02 12:44:52 PM PDT 24
Finished Apr 02 12:45:11 PM PDT 24
Peak memory 199528 kb
Host smart-b95d7e0e-e4d0-4c97-964b-0f6251d6d61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783855155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2783855155
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.2305793467
Short name T587
Test name
Test status
Simulation time 208357711 ps
CPU time 3.57 seconds
Started Apr 02 12:44:54 PM PDT 24
Finished Apr 02 12:44:58 PM PDT 24
Peak memory 199624 kb
Host smart-77568e6d-4cae-4c2a-8988-bd4a4c323811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305793467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2305793467
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2958303824
Short name T217
Test name
Test status
Simulation time 11750395045 ps
CPU time 281.05 seconds
Started Apr 02 12:44:54 PM PDT 24
Finished Apr 02 12:49:36 PM PDT 24
Peak memory 240700 kb
Host smart-6a336229-2bcf-488d-b2c1-8c665b768fe2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958303824 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2958303824
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.1174496514
Short name T487
Test name
Test status
Simulation time 31922174 ps
CPU time 1.1 seconds
Started Apr 02 12:44:54 PM PDT 24
Finished Apr 02 12:44:56 PM PDT 24
Peak memory 199132 kb
Host smart-1f1ee14b-494e-47de-b317-9c3495c18ff9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174496514 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.1174496514
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.3953751149
Short name T534
Test name
Test status
Simulation time 44569503078 ps
CPU time 567.56 seconds
Started Apr 02 12:44:54 PM PDT 24
Finished Apr 02 12:54:22 PM PDT 24
Peak memory 199676 kb
Host smart-dda41e82-bf4b-41b8-8a4b-4241fc469d7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953751149 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.3953751149
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.278329617
Short name T144
Test name
Test status
Simulation time 11861671368 ps
CPU time 42.12 seconds
Started Apr 02 12:44:59 PM PDT 24
Finished Apr 02 12:45:41 PM PDT 24
Peak memory 199700 kb
Host smart-60c99f73-d98c-4e12-afde-6d7bdeae741e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278329617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.278329617
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.240853333
Short name T243
Test name
Test status
Simulation time 17123805 ps
CPU time 0.57 seconds
Started Apr 02 12:45:11 PM PDT 24
Finished Apr 02 12:45:12 PM PDT 24
Peak memory 195144 kb
Host smart-b9f91590-3e1c-4971-893e-6a9291050722
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240853333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.240853333
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.751616337
Short name T230
Test name
Test status
Simulation time 965359449 ps
CPU time 36.68 seconds
Started Apr 02 12:44:59 PM PDT 24
Finished Apr 02 12:45:36 PM PDT 24
Peak memory 230896 kb
Host smart-27a2fc02-977c-49d2-a283-6d970c869872
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=751616337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.751616337
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.62196186
Short name T325
Test name
Test status
Simulation time 449823719 ps
CPU time 9.8 seconds
Started Apr 02 12:44:54 PM PDT 24
Finished Apr 02 12:45:05 PM PDT 24
Peak memory 199600 kb
Host smart-0f8fcf22-05bd-4631-bf9d-8f7a1070bb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62196186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.62196186
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.4090384977
Short name T245
Test name
Test status
Simulation time 726603694 ps
CPU time 46.19 seconds
Started Apr 02 12:45:00 PM PDT 24
Finished Apr 02 12:45:47 PM PDT 24
Peak memory 199628 kb
Host smart-ca26b815-b124-4fdd-b5b1-decbacc327a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4090384977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.4090384977
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.332870268
Short name T335
Test name
Test status
Simulation time 3359627202 ps
CPU time 185.92 seconds
Started Apr 02 12:45:11 PM PDT 24
Finished Apr 02 12:48:18 PM PDT 24
Peak memory 199608 kb
Host smart-cf434a17-e11f-4788-9b9e-c6441f3550be
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332870268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.332870268
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1340658463
Short name T433
Test name
Test status
Simulation time 792285441 ps
CPU time 13.31 seconds
Started Apr 02 12:44:57 PM PDT 24
Finished Apr 02 12:45:10 PM PDT 24
Peak memory 199492 kb
Host smart-d115e93b-72d7-4455-9815-99b35e79e44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340658463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1340658463
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3830398232
Short name T173
Test name
Test status
Simulation time 462244651 ps
CPU time 4.91 seconds
Started Apr 02 12:44:56 PM PDT 24
Finished Apr 02 12:45:01 PM PDT 24
Peak memory 199648 kb
Host smart-1f658d17-fd19-411b-91fe-ce514054d5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830398232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3830398232
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2844700212
Short name T511
Test name
Test status
Simulation time 29636169711 ps
CPU time 581.06 seconds
Started Apr 02 12:45:01 PM PDT 24
Finished Apr 02 12:54:43 PM PDT 24
Peak memory 207864 kb
Host smart-19d11457-691a-4be6-98b9-30df077cdc82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844700212 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2844700212
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.1434220222
Short name T543
Test name
Test status
Simulation time 328780872 ps
CPU time 1.38 seconds
Started Apr 02 12:44:53 PM PDT 24
Finished Apr 02 12:44:56 PM PDT 24
Peak memory 199600 kb
Host smart-aece5ae1-190b-497a-ae11-6b9ca48e5009
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434220222 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.1434220222
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.2091357130
Short name T313
Test name
Test status
Simulation time 40912354477 ps
CPU time 439.31 seconds
Started Apr 02 12:45:00 PM PDT 24
Finished Apr 02 12:52:19 PM PDT 24
Peak memory 199648 kb
Host smart-e3f76f0d-ffa9-43c4-bb0a-495e2419fb37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091357130 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.2091357130
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2237099797
Short name T156
Test name
Test status
Simulation time 823673626 ps
CPU time 44.37 seconds
Started Apr 02 12:44:52 PM PDT 24
Finished Apr 02 12:45:37 PM PDT 24
Peak memory 199624 kb
Host smart-50364a2f-db30-414e-9e43-05c39fe1f1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237099797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2237099797
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1219795229
Short name T283
Test name
Test status
Simulation time 47832127 ps
CPU time 0.57 seconds
Started Apr 02 12:44:58 PM PDT 24
Finished Apr 02 12:44:58 PM PDT 24
Peak memory 194880 kb
Host smart-c71edf64-b6ed-47a4-b305-8b975ab93c8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219795229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1219795229
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2206035919
Short name T322
Test name
Test status
Simulation time 324738240 ps
CPU time 11.22 seconds
Started Apr 02 12:44:59 PM PDT 24
Finished Apr 02 12:45:10 PM PDT 24
Peak memory 215148 kb
Host smart-6fafdd0d-cc53-46cf-9389-8e75241a53f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2206035919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2206035919
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1693687362
Short name T339
Test name
Test status
Simulation time 2561734522 ps
CPU time 11.24 seconds
Started Apr 02 12:44:59 PM PDT 24
Finished Apr 02 12:45:10 PM PDT 24
Peak memory 199680 kb
Host smart-da86d62a-0820-4656-ba64-a1b5632bac53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693687362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1693687362
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3898910100
Short name T415
Test name
Test status
Simulation time 249897892 ps
CPU time 12.94 seconds
Started Apr 02 12:44:57 PM PDT 24
Finished Apr 02 12:45:10 PM PDT 24
Peak memory 199624 kb
Host smart-afc7226d-64ac-48d2-ad67-9590ec37cf82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3898910100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3898910100
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.3874218251
Short name T558
Test name
Test status
Simulation time 8361193319 ps
CPU time 150.46 seconds
Started Apr 02 12:44:59 PM PDT 24
Finished Apr 02 12:47:29 PM PDT 24
Peak memory 199736 kb
Host smart-f0ac959d-2ed9-4d7e-b28a-830bca3a3ebe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874218251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3874218251
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2322195448
Short name T138
Test name
Test status
Simulation time 10846107947 ps
CPU time 57.47 seconds
Started Apr 02 12:45:02 PM PDT 24
Finished Apr 02 12:46:00 PM PDT 24
Peak memory 199680 kb
Host smart-87b92861-41de-4c2e-8de9-64c36278f346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322195448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2322195448
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1458935169
Short name T139
Test name
Test status
Simulation time 736686660 ps
CPU time 1.71 seconds
Started Apr 02 12:44:50 PM PDT 24
Finished Apr 02 12:44:52 PM PDT 24
Peak memory 199684 kb
Host smart-fc903817-d3eb-4823-831d-7d4c990a75c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458935169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1458935169
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.3107021597
Short name T470
Test name
Test status
Simulation time 194071845427 ps
CPU time 2221.45 seconds
Started Apr 02 12:44:56 PM PDT 24
Finished Apr 02 01:21:58 PM PDT 24
Peak memory 240684 kb
Host smart-104cc6bc-0092-43fe-b0b9-1d904df6425f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107021597 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3107021597
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.2802138279
Short name T588
Test name
Test status
Simulation time 52298135 ps
CPU time 1.03 seconds
Started Apr 02 12:44:58 PM PDT 24
Finished Apr 02 12:44:59 PM PDT 24
Peak memory 198936 kb
Host smart-86484362-4c37-43dd-9fa4-7e2e5478e009
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802138279 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.2802138279
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.2612664899
Short name T252
Test name
Test status
Simulation time 29374080043 ps
CPU time 444.23 seconds
Started Apr 02 12:44:58 PM PDT 24
Finished Apr 02 12:52:22 PM PDT 24
Peak memory 199644 kb
Host smart-dda78f9b-3cf1-43ba-a075-4a89b8713dca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612664899 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.2612664899
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2925332853
Short name T391
Test name
Test status
Simulation time 6264637808 ps
CPU time 76.25 seconds
Started Apr 02 12:44:55 PM PDT 24
Finished Apr 02 12:46:12 PM PDT 24
Peak memory 199724 kb
Host smart-d6a88d33-9a35-438b-88b1-ea81089253ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925332853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2925332853
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.3018371417
Short name T272
Test name
Test status
Simulation time 51972062 ps
CPU time 0.63 seconds
Started Apr 02 12:44:56 PM PDT 24
Finished Apr 02 12:44:57 PM PDT 24
Peak memory 195216 kb
Host smart-93dba802-ae5d-49d5-a83d-9b83e254ebbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018371417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3018371417
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.4198637800
Short name T53
Test name
Test status
Simulation time 1140447008 ps
CPU time 39.82 seconds
Started Apr 02 12:44:57 PM PDT 24
Finished Apr 02 12:45:38 PM PDT 24
Peak memory 218072 kb
Host smart-c6ee6e6d-8c96-4cd0-90a8-3581c6dca9e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4198637800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.4198637800
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.2501520720
Short name T284
Test name
Test status
Simulation time 7504939440 ps
CPU time 31.42 seconds
Started Apr 02 12:44:58 PM PDT 24
Finished Apr 02 12:45:30 PM PDT 24
Peak memory 199684 kb
Host smart-d5287974-383e-4ace-a845-547ff0ffaffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501520720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2501520720
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1579890658
Short name T491
Test name
Test status
Simulation time 1411792294 ps
CPU time 21.67 seconds
Started Apr 02 12:45:00 PM PDT 24
Finished Apr 02 12:45:21 PM PDT 24
Peak memory 199680 kb
Host smart-9210346f-6e86-45b0-99ce-8c10bb4fa50e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1579890658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1579890658
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2428889556
Short name T489
Test name
Test status
Simulation time 7374894711 ps
CPU time 79.23 seconds
Started Apr 02 12:44:56 PM PDT 24
Finished Apr 02 12:46:16 PM PDT 24
Peak memory 199736 kb
Host smart-9fb1098b-fd33-4715-9d0a-7a5cab3b7aa6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428889556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2428889556
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3341045397
Short name T291
Test name
Test status
Simulation time 7246330566 ps
CPU time 115.47 seconds
Started Apr 02 12:44:57 PM PDT 24
Finished Apr 02 12:46:53 PM PDT 24
Peak memory 199732 kb
Host smart-ba8c5aae-c6fc-4d39-8c01-312d84d30b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341045397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3341045397
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.185430756
Short name T535
Test name
Test status
Simulation time 346471561 ps
CPU time 5.25 seconds
Started Apr 02 12:44:56 PM PDT 24
Finished Apr 02 12:45:02 PM PDT 24
Peak memory 199612 kb
Host smart-c7f0312d-d3a3-4ec0-a553-cbfe831d7733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185430756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.185430756
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3744068044
Short name T269
Test name
Test status
Simulation time 14580787767 ps
CPU time 809.87 seconds
Started Apr 02 12:44:58 PM PDT 24
Finished Apr 02 12:58:28 PM PDT 24
Peak memory 224240 kb
Host smart-d3ccba90-3024-450d-8734-4318509b2d36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744068044 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3744068044
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.707648430
Short name T202
Test name
Test status
Simulation time 37907656 ps
CPU time 1.01 seconds
Started Apr 02 12:44:58 PM PDT 24
Finished Apr 02 12:45:00 PM PDT 24
Peak memory 198304 kb
Host smart-2f81da2b-5397-4b1d-bdd1-7885b85e7c4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707648430 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_hmac_vectors.707648430
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.1278622359
Short name T348
Test name
Test status
Simulation time 28542493497 ps
CPU time 420.17 seconds
Started Apr 02 12:44:59 PM PDT 24
Finished Apr 02 12:51:59 PM PDT 24
Peak memory 199532 kb
Host smart-87753b51-35e4-4b26-9a85-ffd9aa85245e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278622359 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.1278622359
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.895607934
Short name T79
Test name
Test status
Simulation time 29487470440 ps
CPU time 50.58 seconds
Started Apr 02 12:44:56 PM PDT 24
Finished Apr 02 12:45:47 PM PDT 24
Peak memory 199692 kb
Host smart-ca4c6c2c-3720-4c18-b3f5-7d9524c3aa02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895607934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.895607934
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.1552931150
Short name T204
Test name
Test status
Simulation time 46293571 ps
CPU time 0.58 seconds
Started Apr 02 12:45:01 PM PDT 24
Finished Apr 02 12:45:01 PM PDT 24
Peak memory 195204 kb
Host smart-ea73e437-d569-47e5-a187-4a7068d420ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552931150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.1552931150
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2277728907
Short name T370
Test name
Test status
Simulation time 5014476646 ps
CPU time 28.99 seconds
Started Apr 02 12:45:00 PM PDT 24
Finished Apr 02 12:45:29 PM PDT 24
Peak memory 207924 kb
Host smart-1d0d2f8c-f81b-44e6-870c-82224b14bbb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2277728907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2277728907
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.4210593773
Short name T310
Test name
Test status
Simulation time 446541931 ps
CPU time 4.8 seconds
Started Apr 02 12:45:01 PM PDT 24
Finished Apr 02 12:45:06 PM PDT 24
Peak memory 199532 kb
Host smart-d647260c-5367-4cb1-bc50-1e42165c10cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210593773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.4210593773
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1411910839
Short name T583
Test name
Test status
Simulation time 1008227834 ps
CPU time 58 seconds
Started Apr 02 12:44:59 PM PDT 24
Finished Apr 02 12:45:57 PM PDT 24
Peak memory 199628 kb
Host smart-4b9b9745-42fa-4013-a83d-1e49acd091e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1411910839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1411910839
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.546087953
Short name T42
Test name
Test status
Simulation time 4723917478 ps
CPU time 81.21 seconds
Started Apr 02 12:45:02 PM PDT 24
Finished Apr 02 12:46:24 PM PDT 24
Peak memory 199728 kb
Host smart-21a74f1a-2125-40be-bd43-e6bd8c75c151
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546087953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.546087953
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.3221578823
Short name T398
Test name
Test status
Simulation time 10657914036 ps
CPU time 104.59 seconds
Started Apr 02 12:44:56 PM PDT 24
Finished Apr 02 12:46:40 PM PDT 24
Peak memory 199632 kb
Host smart-35775c54-6624-4a0d-82a2-9ae72c999ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221578823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3221578823
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1417069815
Short name T5
Test name
Test status
Simulation time 1695281106 ps
CPU time 5.56 seconds
Started Apr 02 12:44:56 PM PDT 24
Finished Apr 02 12:45:02 PM PDT 24
Peak memory 199632 kb
Host smart-f5e0a255-4f1b-40dd-8fde-3d658b40fc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417069815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1417069815
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3313396652
Short name T528
Test name
Test status
Simulation time 151795669736 ps
CPU time 2129.75 seconds
Started Apr 02 12:45:04 PM PDT 24
Finished Apr 02 01:20:35 PM PDT 24
Peak memory 242720 kb
Host smart-e54cec7f-3c10-458a-a008-69ee89b8409d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313396652 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3313396652
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.2178823102
Short name T143
Test name
Test status
Simulation time 280476549 ps
CPU time 1.43 seconds
Started Apr 02 12:45:02 PM PDT 24
Finished Apr 02 12:45:04 PM PDT 24
Peak memory 199576 kb
Host smart-cc85cff7-1732-4b5c-b79d-8f456cc4a882
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178823102 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.2178823102
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.2558599018
Short name T207
Test name
Test status
Simulation time 28544727906 ps
CPU time 509.16 seconds
Started Apr 02 12:45:05 PM PDT 24
Finished Apr 02 12:53:34 PM PDT 24
Peak memory 199588 kb
Host smart-e3e251b9-8b52-4121-bee4-d63cb5251625
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558599018 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.2558599018
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.4017290489
Short name T502
Test name
Test status
Simulation time 416070172 ps
CPU time 17.82 seconds
Started Apr 02 12:45:03 PM PDT 24
Finished Apr 02 12:45:21 PM PDT 24
Peak memory 199576 kb
Host smart-59d0fd7d-0671-4dde-913a-a3b7e57be198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017290489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.4017290489
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3085522757
Short name T267
Test name
Test status
Simulation time 125913377 ps
CPU time 0.61 seconds
Started Apr 02 12:45:02 PM PDT 24
Finished Apr 02 12:45:03 PM PDT 24
Peak memory 195184 kb
Host smart-bf852331-243f-4ad9-80d6-dcdc588276cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085522757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3085522757
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3164285112
Short name T585
Test name
Test status
Simulation time 5270665058 ps
CPU time 46.12 seconds
Started Apr 02 12:45:01 PM PDT 24
Finished Apr 02 12:45:48 PM PDT 24
Peak memory 207800 kb
Host smart-21224e18-7f8f-4eed-9ebd-9637fdf0d376
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3164285112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3164285112
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2713202485
Short name T174
Test name
Test status
Simulation time 2945899470 ps
CPU time 45.39 seconds
Started Apr 02 12:45:06 PM PDT 24
Finished Apr 02 12:45:51 PM PDT 24
Peak memory 199608 kb
Host smart-a20985fc-9100-4553-b56d-32cc191c490f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713202485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2713202485
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1971905672
Short name T447
Test name
Test status
Simulation time 2185376982 ps
CPU time 33 seconds
Started Apr 02 12:45:00 PM PDT 24
Finished Apr 02 12:45:33 PM PDT 24
Peak memory 199708 kb
Host smart-6aae6977-b7b6-4b30-b2c8-f02b56976d39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1971905672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1971905672
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2559525550
Short name T565
Test name
Test status
Simulation time 7570014626 ps
CPU time 100.08 seconds
Started Apr 02 12:45:01 PM PDT 24
Finished Apr 02 12:46:42 PM PDT 24
Peak memory 199720 kb
Host smart-d1213cee-7c1d-4839-80d0-a307cc69532c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559525550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2559525550
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.711985495
Short name T323
Test name
Test status
Simulation time 7072490745 ps
CPU time 70.87 seconds
Started Apr 02 12:45:02 PM PDT 24
Finished Apr 02 12:46:13 PM PDT 24
Peak memory 199724 kb
Host smart-da299ab0-4368-452a-81d6-08b20756c72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711985495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.711985495
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.404634954
Short name T205
Test name
Test status
Simulation time 734616659 ps
CPU time 6.15 seconds
Started Apr 02 12:45:03 PM PDT 24
Finished Apr 02 12:45:09 PM PDT 24
Peak memory 199644 kb
Host smart-0dad1d23-a927-45fb-b87a-250636562d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404634954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.404634954
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2698968477
Short name T247
Test name
Test status
Simulation time 160923229186 ps
CPU time 1456.57 seconds
Started Apr 02 12:45:01 PM PDT 24
Finished Apr 02 01:09:19 PM PDT 24
Peak memory 199736 kb
Host smart-3f7d1e88-dcd1-4b48-90bf-218306cacf3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698968477 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2698968477
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.2686684674
Short name T57
Test name
Test status
Simulation time 148282811 ps
CPU time 1.18 seconds
Started Apr 02 12:45:06 PM PDT 24
Finished Apr 02 12:45:08 PM PDT 24
Peak memory 199360 kb
Host smart-e8e827d7-7701-4a89-9e3c-5ef9c46f0dbd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686684674 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.2686684674
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.2721486646
Short name T177
Test name
Test status
Simulation time 178309438160 ps
CPU time 521.81 seconds
Started Apr 02 12:45:02 PM PDT 24
Finished Apr 02 12:53:44 PM PDT 24
Peak memory 199664 kb
Host smart-205dafea-ce91-4827-8fe3-16515b1c3c26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721486646 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.2721486646
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1892126478
Short name T581
Test name
Test status
Simulation time 16403609125 ps
CPU time 54.63 seconds
Started Apr 02 12:45:03 PM PDT 24
Finished Apr 02 12:45:58 PM PDT 24
Peak memory 199716 kb
Host smart-ce6bc052-66a5-45db-b20f-b20e423d7fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892126478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1892126478
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.569715835
Short name T410
Test name
Test status
Simulation time 39613874 ps
CPU time 0.56 seconds
Started Apr 02 12:45:04 PM PDT 24
Finished Apr 02 12:45:06 PM PDT 24
Peak memory 195276 kb
Host smart-81980a2f-44da-4f50-94f2-71a0f362700f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569715835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.569715835
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3132448472
Short name T250
Test name
Test status
Simulation time 320295033 ps
CPU time 12.28 seconds
Started Apr 02 12:45:31 PM PDT 24
Finished Apr 02 12:45:44 PM PDT 24
Peak memory 207828 kb
Host smart-d0672f51-284f-4d20-a06a-10fb8b06ca85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3132448472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3132448472
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2197685745
Short name T275
Test name
Test status
Simulation time 606434895 ps
CPU time 2.68 seconds
Started Apr 02 12:45:06 PM PDT 24
Finished Apr 02 12:45:09 PM PDT 24
Peak memory 199604 kb
Host smart-1f0e03b0-32a3-42a7-8629-25ab4ffa122b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197685745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2197685745
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.4028016295
Short name T304
Test name
Test status
Simulation time 253186288 ps
CPU time 10.22 seconds
Started Apr 02 12:45:06 PM PDT 24
Finished Apr 02 12:45:16 PM PDT 24
Peak memory 199644 kb
Host smart-5cb314ee-20a5-4075-a17c-c8e834b13886
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4028016295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.4028016295
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3543793937
Short name T48
Test name
Test status
Simulation time 8497869199 ps
CPU time 160.44 seconds
Started Apr 02 12:45:06 PM PDT 24
Finished Apr 02 12:47:47 PM PDT 24
Peak memory 199720 kb
Host smart-31ad1380-64e0-48d9-9c18-678954bfcdff
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543793937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3543793937
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3447563243
Short name T41
Test name
Test status
Simulation time 2651370753 ps
CPU time 54.32 seconds
Started Apr 02 12:45:04 PM PDT 24
Finished Apr 02 12:45:59 PM PDT 24
Peak memory 199628 kb
Host smart-bb211862-b1e7-4d9f-81b6-49d487fafb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447563243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3447563243
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3595343390
Short name T420
Test name
Test status
Simulation time 421646517 ps
CPU time 2.71 seconds
Started Apr 02 12:45:04 PM PDT 24
Finished Apr 02 12:45:07 PM PDT 24
Peak memory 199624 kb
Host smart-76b68424-8e7d-4add-8249-afd694ef1590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595343390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3595343390
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.1031487351
Short name T479
Test name
Test status
Simulation time 35936245096 ps
CPU time 509.08 seconds
Started Apr 02 12:45:09 PM PDT 24
Finished Apr 02 12:53:39 PM PDT 24
Peak memory 199732 kb
Host smart-c6a85512-56cf-4f82-acc2-583ba1aabe79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031487351 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1031487351
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.3878384095
Short name T253
Test name
Test status
Simulation time 84794911 ps
CPU time 1.04 seconds
Started Apr 02 12:45:09 PM PDT 24
Finished Apr 02 12:45:10 PM PDT 24
Peak memory 199068 kb
Host smart-993442f4-feb6-4e59-ad02-c974c3ca2ea6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878384095 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.3878384095
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.2237461664
Short name T296
Test name
Test status
Simulation time 57144646153 ps
CPU time 519.14 seconds
Started Apr 02 12:45:05 PM PDT 24
Finished Apr 02 12:53:44 PM PDT 24
Peak memory 199636 kb
Host smart-f188b2fd-e635-4301-a0e8-05f035a65a81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237461664 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.2237461664
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.1052236196
Short name T299
Test name
Test status
Simulation time 1456675047 ps
CPU time 60.84 seconds
Started Apr 02 12:45:03 PM PDT 24
Finished Apr 02 12:46:05 PM PDT 24
Peak memory 199668 kb
Host smart-ff30cf6f-6648-4b99-8783-f1525991c3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052236196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1052236196
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.172366281
Short name T462
Test name
Test status
Simulation time 40352605 ps
CPU time 0.58 seconds
Started Apr 02 12:45:10 PM PDT 24
Finished Apr 02 12:45:11 PM PDT 24
Peak memory 195220 kb
Host smart-b76aeed7-5c11-4faf-a964-12bad75fa12f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172366281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.172366281
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3354035951
Short name T56
Test name
Test status
Simulation time 2733683865 ps
CPU time 56.42 seconds
Started Apr 02 12:45:09 PM PDT 24
Finished Apr 02 12:46:06 PM PDT 24
Peak memory 225356 kb
Host smart-befea98d-dcaf-4b65-8650-6f172dd77fbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3354035951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3354035951
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.499967728
Short name T180
Test name
Test status
Simulation time 1993104506 ps
CPU time 39.32 seconds
Started Apr 02 12:45:05 PM PDT 24
Finished Apr 02 12:45:45 PM PDT 24
Peak memory 199648 kb
Host smart-41d85f8d-7acf-439c-af89-e2b83bb4d214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499967728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.499967728
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.2314205715
Short name T307
Test name
Test status
Simulation time 1713848591 ps
CPU time 100.88 seconds
Started Apr 02 12:45:02 PM PDT 24
Finished Apr 02 12:46:43 PM PDT 24
Peak memory 199588 kb
Host smart-501e7f24-fb89-4195-9f89-874765f4a666
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2314205715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.2314205715
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3770537014
Short name T254
Test name
Test status
Simulation time 7106020609 ps
CPU time 98.65 seconds
Started Apr 02 12:45:06 PM PDT 24
Finished Apr 02 12:46:45 PM PDT 24
Peak memory 199744 kb
Host smart-50ba8d32-2efb-4f78-87af-519c0dfae0ee
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770537014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3770537014
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2782164240
Short name T463
Test name
Test status
Simulation time 19370723311 ps
CPU time 79.78 seconds
Started Apr 02 12:45:09 PM PDT 24
Finished Apr 02 12:46:29 PM PDT 24
Peak memory 199736 kb
Host smart-c70f1ab4-cd8d-4088-880f-94c51b0c551d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782164240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2782164240
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2425543274
Short name T402
Test name
Test status
Simulation time 694664971 ps
CPU time 3.22 seconds
Started Apr 02 12:45:05 PM PDT 24
Finished Apr 02 12:45:08 PM PDT 24
Peak memory 199556 kb
Host smart-cc7eab9b-aa89-4a67-bf88-9dadb1cb39af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425543274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2425543274
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2809252027
Short name T500
Test name
Test status
Simulation time 31247108784 ps
CPU time 1660.83 seconds
Started Apr 02 12:45:07 PM PDT 24
Finished Apr 02 01:12:48 PM PDT 24
Peak memory 199728 kb
Host smart-aded5ecf-36e5-479a-9346-45df41ee1473
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809252027 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2809252027
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.4219241484
Short name T43
Test name
Test status
Simulation time 72614457 ps
CPU time 1.25 seconds
Started Apr 02 12:45:10 PM PDT 24
Finished Apr 02 12:45:11 PM PDT 24
Peak memory 199428 kb
Host smart-8bddd3c0-7ecd-4af5-a12e-755bf41f31b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219241484 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.4219241484
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.3790742664
Short name T524
Test name
Test status
Simulation time 55688278155 ps
CPU time 520.03 seconds
Started Apr 02 12:45:10 PM PDT 24
Finished Apr 02 12:53:50 PM PDT 24
Peak memory 199668 kb
Host smart-d06f5221-fce4-42c3-a32b-abc5b386a28e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790742664 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.3790742664
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.537549954
Short name T393
Test name
Test status
Simulation time 10982316515 ps
CPU time 40 seconds
Started Apr 02 12:45:04 PM PDT 24
Finished Apr 02 12:45:44 PM PDT 24
Peak memory 199728 kb
Host smart-38f58617-1b1f-4bfa-8c45-32374ed345c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537549954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.537549954
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2655541607
Short name T355
Test name
Test status
Simulation time 109319233 ps
CPU time 0.58 seconds
Started Apr 02 12:45:14 PM PDT 24
Finished Apr 02 12:45:15 PM PDT 24
Peak memory 195224 kb
Host smart-a2306643-6c61-4c39-985e-39dd04364f32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655541607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2655541607
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3819141796
Short name T168
Test name
Test status
Simulation time 1225755189 ps
CPU time 10 seconds
Started Apr 02 12:45:06 PM PDT 24
Finished Apr 02 12:45:17 PM PDT 24
Peak memory 207684 kb
Host smart-169921de-70db-4b0b-9c8b-5eb34b0370c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3819141796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3819141796
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.4137433256
Short name T508
Test name
Test status
Simulation time 2262362049 ps
CPU time 11.73 seconds
Started Apr 02 12:45:11 PM PDT 24
Finished Apr 02 12:45:23 PM PDT 24
Peak memory 199664 kb
Host smart-a331d9e6-b434-443d-a8f6-80e21a6a55ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137433256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.4137433256
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3216992733
Short name T152
Test name
Test status
Simulation time 3958762988 ps
CPU time 114.43 seconds
Started Apr 02 12:45:10 PM PDT 24
Finished Apr 02 12:47:05 PM PDT 24
Peak memory 199744 kb
Host smart-6c3f8fa8-6e3a-4aeb-a576-72fa4dd48c41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3216992733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3216992733
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.2274728322
Short name T359
Test name
Test status
Simulation time 9231275463 ps
CPU time 128.79 seconds
Started Apr 02 12:45:13 PM PDT 24
Finished Apr 02 12:47:22 PM PDT 24
Peak memory 199712 kb
Host smart-af918618-ce75-4b48-9160-e3aa0d407aa9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274728322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.2274728322
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.3514273583
Short name T186
Test name
Test status
Simulation time 5980515944 ps
CPU time 123.57 seconds
Started Apr 02 12:45:10 PM PDT 24
Finished Apr 02 12:47:14 PM PDT 24
Peak memory 199644 kb
Host smart-27e385c2-e33f-40a3-adcc-a1c7a90f8401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514273583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3514273583
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.759938563
Short name T229
Test name
Test status
Simulation time 214866262 ps
CPU time 6.6 seconds
Started Apr 02 12:45:09 PM PDT 24
Finished Apr 02 12:45:16 PM PDT 24
Peak memory 199684 kb
Host smart-3de4fac4-4cfe-4e91-93be-86a45435bd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759938563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.759938563
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3162068726
Short name T446
Test name
Test status
Simulation time 55379023405 ps
CPU time 1171.3 seconds
Started Apr 02 12:45:16 PM PDT 24
Finished Apr 02 01:04:48 PM PDT 24
Peak memory 224240 kb
Host smart-716afbac-055b-45d2-9c26-f80cf1861ab0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162068726 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3162068726
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.1481775120
Short name T362
Test name
Test status
Simulation time 107706599 ps
CPU time 1.32 seconds
Started Apr 02 12:45:17 PM PDT 24
Finished Apr 02 12:45:18 PM PDT 24
Peak memory 199368 kb
Host smart-0f800bf1-2ace-4179-b372-0e66761abc13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481775120 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.1481775120
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.1294014955
Short name T455
Test name
Test status
Simulation time 15846019924 ps
CPU time 421.8 seconds
Started Apr 02 12:45:12 PM PDT 24
Finished Apr 02 12:52:14 PM PDT 24
Peak memory 199660 kb
Host smart-219463fa-cf86-4959-9b7f-38a8942e7cea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294014955 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.1294014955
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3713349543
Short name T171
Test name
Test status
Simulation time 1177704995 ps
CPU time 25.84 seconds
Started Apr 02 12:45:13 PM PDT 24
Finished Apr 02 12:45:39 PM PDT 24
Peak memory 199648 kb
Host smart-e7e481bd-0471-44e4-9caa-6aa17cfbb99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713349543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3713349543
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.3057068270
Short name T145
Test name
Test status
Simulation time 12845066 ps
CPU time 0.6 seconds
Started Apr 02 12:45:15 PM PDT 24
Finished Apr 02 12:45:16 PM PDT 24
Peak memory 194180 kb
Host smart-45cdb3f4-5c9a-4a40-a8b4-dc506f8f4dd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057068270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3057068270
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.782861226
Short name T395
Test name
Test status
Simulation time 1596988420 ps
CPU time 68.17 seconds
Started Apr 02 12:45:16 PM PDT 24
Finished Apr 02 12:46:24 PM PDT 24
Peak memory 232372 kb
Host smart-9e5b6ba1-6715-4495-bb62-ca96282c235f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=782861226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.782861226
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.3196491342
Short name T149
Test name
Test status
Simulation time 1668219357 ps
CPU time 32.58 seconds
Started Apr 02 12:45:18 PM PDT 24
Finished Apr 02 12:45:50 PM PDT 24
Peak memory 199560 kb
Host smart-a1251d5b-3866-4555-9766-a13a521a64ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196491342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3196491342
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3405521561
Short name T563
Test name
Test status
Simulation time 4795380071 ps
CPU time 70.16 seconds
Started Apr 02 12:45:12 PM PDT 24
Finished Apr 02 12:46:22 PM PDT 24
Peak memory 199760 kb
Host smart-802f0a8e-0be5-4eb3-941f-97e413c43e34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3405521561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3405521561
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.47705631
Short name T476
Test name
Test status
Simulation time 9780885895 ps
CPU time 181.94 seconds
Started Apr 02 12:45:20 PM PDT 24
Finished Apr 02 12:48:22 PM PDT 24
Peak memory 199728 kb
Host smart-e38895ba-a07e-430f-9fc7-773e1622e67e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47705631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.47705631
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.266070757
Short name T553
Test name
Test status
Simulation time 1041899490 ps
CPU time 15.53 seconds
Started Apr 02 12:45:14 PM PDT 24
Finished Apr 02 12:45:29 PM PDT 24
Peak memory 199668 kb
Host smart-af5a6667-8d20-4f4a-97c8-32b366f3f791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266070757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.266070757
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.4012302561
Short name T459
Test name
Test status
Simulation time 1054273330 ps
CPU time 6.3 seconds
Started Apr 02 12:45:11 PM PDT 24
Finished Apr 02 12:45:17 PM PDT 24
Peak memory 199676 kb
Host smart-498e6587-1bdd-4e09-8676-0efe6fef6d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012302561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.4012302561
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.963065368
Short name T466
Test name
Test status
Simulation time 24916302470 ps
CPU time 485.43 seconds
Started Apr 02 12:45:16 PM PDT 24
Finished Apr 02 12:53:22 PM PDT 24
Peak memory 229888 kb
Host smart-f772640d-257c-4fd8-a34e-32755410fdfd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963065368 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.963065368
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.332130378
Short name T234
Test name
Test status
Simulation time 59453252 ps
CPU time 1.27 seconds
Started Apr 02 12:45:18 PM PDT 24
Finished Apr 02 12:45:20 PM PDT 24
Peak memory 199596 kb
Host smart-c1515469-feb1-450e-b050-1119567e213b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332130378 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_hmac_vectors.332130378
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.2745191981
Short name T94
Test name
Test status
Simulation time 7535118869 ps
CPU time 441.96 seconds
Started Apr 02 12:45:18 PM PDT 24
Finished Apr 02 12:52:40 PM PDT 24
Peak memory 199648 kb
Host smart-806c8931-f081-4ed5-9566-0aea2927eac7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745191981 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.2745191981
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.510592849
Short name T240
Test name
Test status
Simulation time 3686657856 ps
CPU time 25.78 seconds
Started Apr 02 12:45:20 PM PDT 24
Finished Apr 02 12:45:46 PM PDT 24
Peak memory 199684 kb
Host smart-b5bf6ada-3952-47ff-9757-97f6d4922180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510592849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.510592849
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.1167055502
Short name T572
Test name
Test status
Simulation time 15230402 ps
CPU time 0.61 seconds
Started Apr 02 12:44:14 PM PDT 24
Finished Apr 02 12:44:15 PM PDT 24
Peak memory 195132 kb
Host smart-ef9f8246-282c-4e7a-ba99-0da64f048f24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167055502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1167055502
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3010791321
Short name T444
Test name
Test status
Simulation time 4338062374 ps
CPU time 36.65 seconds
Started Apr 02 12:44:10 PM PDT 24
Finished Apr 02 12:44:48 PM PDT 24
Peak memory 229416 kb
Host smart-b07838da-d4a0-490a-8418-50c6de2f1f72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3010791321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3010791321
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1823821026
Short name T330
Test name
Test status
Simulation time 5743423976 ps
CPU time 29.74 seconds
Started Apr 02 12:44:11 PM PDT 24
Finished Apr 02 12:44:41 PM PDT 24
Peak memory 199736 kb
Host smart-6ef6c007-b599-48b9-9c9f-fbf1a4b8644b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823821026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1823821026
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.865035670
Short name T263
Test name
Test status
Simulation time 5911481650 ps
CPU time 89.94 seconds
Started Apr 02 12:44:18 PM PDT 24
Finished Apr 02 12:45:48 PM PDT 24
Peak memory 199708 kb
Host smart-765d5a38-4030-484c-b4ce-a2dfc88c1e3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=865035670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.865035670
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2878283986
Short name T311
Test name
Test status
Simulation time 4725673604 ps
CPU time 34.93 seconds
Started Apr 02 12:44:11 PM PDT 24
Finished Apr 02 12:44:46 PM PDT 24
Peak memory 199676 kb
Host smart-dbd3fe03-31ab-432f-966f-e2cad2f9bf76
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878283986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2878283986
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2648468948
Short name T124
Test name
Test status
Simulation time 24560767922 ps
CPU time 88.59 seconds
Started Apr 02 12:44:13 PM PDT 24
Finished Apr 02 12:45:42 PM PDT 24
Peak memory 199740 kb
Host smart-8013a0e4-94ed-40af-822e-48cad67dea98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648468948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2648468948
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_smoke.2563291781
Short name T428
Test name
Test status
Simulation time 87542598 ps
CPU time 2.88 seconds
Started Apr 02 12:44:19 PM PDT 24
Finished Apr 02 12:44:22 PM PDT 24
Peak memory 199464 kb
Host smart-56186cd6-3b57-4e84-8fb9-9df8d32d2ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563291781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.2563291781
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.619174129
Short name T214
Test name
Test status
Simulation time 423498704604 ps
CPU time 2113.33 seconds
Started Apr 02 12:44:12 PM PDT 24
Finished Apr 02 01:19:25 PM PDT 24
Peak memory 240520 kb
Host smart-a67b8ea9-a484-4739-a860-a3189dffd2ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619174129 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.619174129
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.2779465695
Short name T486
Test name
Test status
Simulation time 107358479 ps
CPU time 1.1 seconds
Started Apr 02 12:44:16 PM PDT 24
Finished Apr 02 12:44:18 PM PDT 24
Peak memory 199348 kb
Host smart-ed1b9f50-5296-43ea-b27f-698b7ca486e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779465695 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.2779465695
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.2241578581
Short name T314
Test name
Test status
Simulation time 23908117515 ps
CPU time 433.52 seconds
Started Apr 02 12:44:14 PM PDT 24
Finished Apr 02 12:51:28 PM PDT 24
Peak memory 199644 kb
Host smart-286a8242-bafe-42d7-bfb6-f811b533e51e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241578581 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.2241578581
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.433028712
Short name T292
Test name
Test status
Simulation time 32241488055 ps
CPU time 75.72 seconds
Started Apr 02 12:44:18 PM PDT 24
Finished Apr 02 12:45:34 PM PDT 24
Peak memory 199588 kb
Host smart-2d260410-bc38-4521-a795-a303644a07cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433028712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.433028712
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.755676941
Short name T369
Test name
Test status
Simulation time 40598285 ps
CPU time 0.59 seconds
Started Apr 02 12:45:18 PM PDT 24
Finished Apr 02 12:45:19 PM PDT 24
Peak memory 193964 kb
Host smart-1995df75-e3f0-4f36-913b-032c396b2126
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755676941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.755676941
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2846391845
Short name T50
Test name
Test status
Simulation time 6629025466 ps
CPU time 14.88 seconds
Started Apr 02 12:45:17 PM PDT 24
Finished Apr 02 12:45:32 PM PDT 24
Peak memory 216120 kb
Host smart-472c818b-b80e-4511-80ed-75c77394ccb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2846391845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2846391845
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.955466945
Short name T538
Test name
Test status
Simulation time 1084038899 ps
CPU time 4.87 seconds
Started Apr 02 12:45:17 PM PDT 24
Finished Apr 02 12:45:22 PM PDT 24
Peak memory 199688 kb
Host smart-550f9f96-429f-4a51-b11f-d0a237d3507a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955466945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.955466945
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2662606845
Short name T399
Test name
Test status
Simulation time 3331604032 ps
CPU time 104.26 seconds
Started Apr 02 12:45:20 PM PDT 24
Finished Apr 02 12:47:04 PM PDT 24
Peak memory 199740 kb
Host smart-1814474a-5cde-439e-8c40-7bdc24022583
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2662606845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2662606845
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3779076720
Short name T301
Test name
Test status
Simulation time 1481420868 ps
CPU time 87.96 seconds
Started Apr 02 12:45:20 PM PDT 24
Finished Apr 02 12:46:49 PM PDT 24
Peak memory 199668 kb
Host smart-f8f50daa-2761-4861-8a1e-1495447c259b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779076720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3779076720
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1675889701
Short name T179
Test name
Test status
Simulation time 4283010137 ps
CPU time 84.28 seconds
Started Apr 02 12:45:18 PM PDT 24
Finished Apr 02 12:46:42 PM PDT 24
Peak memory 199632 kb
Host smart-ef7cf7bf-d6b4-429f-a406-354ca00e5a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675889701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1675889701
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3327269951
Short name T212
Test name
Test status
Simulation time 835659871 ps
CPU time 6.31 seconds
Started Apr 02 12:45:16 PM PDT 24
Finished Apr 02 12:45:22 PM PDT 24
Peak memory 199616 kb
Host smart-8ddaaee2-c6fd-4a65-a0d9-36d4a4dc6c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327269951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3327269951
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.3809914735
Short name T228
Test name
Test status
Simulation time 24992900712 ps
CPU time 1052.73 seconds
Started Apr 02 12:45:21 PM PDT 24
Finished Apr 02 01:02:55 PM PDT 24
Peak memory 237932 kb
Host smart-1fbb65ff-f019-4afe-9c1c-fa6b7d8a3ea3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809914735 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.3809914735
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.920940176
Short name T268
Test name
Test status
Simulation time 246846407 ps
CPU time 1.02 seconds
Started Apr 02 12:45:22 PM PDT 24
Finished Apr 02 12:45:24 PM PDT 24
Peak memory 198272 kb
Host smart-f3a78f28-c578-468c-aacf-c74153bd5094
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920940176 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.hmac_test_hmac_vectors.920940176
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.3448429814
Short name T529
Test name
Test status
Simulation time 239981145221 ps
CPU time 461.31 seconds
Started Apr 02 12:45:19 PM PDT 24
Finished Apr 02 12:53:01 PM PDT 24
Peak memory 199656 kb
Host smart-b23afd18-3db7-44aa-84c6-a0622c062466
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448429814 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.3448429814
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.947617396
Short name T503
Test name
Test status
Simulation time 22732310369 ps
CPU time 51.56 seconds
Started Apr 02 12:45:22 PM PDT 24
Finished Apr 02 12:46:14 PM PDT 24
Peak memory 199644 kb
Host smart-c09b6ba7-193c-46da-9c62-a5e2447a2d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947617396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.947617396
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2777945677
Short name T510
Test name
Test status
Simulation time 13145830 ps
CPU time 0.62 seconds
Started Apr 02 12:45:26 PM PDT 24
Finished Apr 02 12:45:27 PM PDT 24
Peak memory 194120 kb
Host smart-bc26f703-964a-4a6b-9dcd-95bf46bc147c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777945677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2777945677
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2798118603
Short name T342
Test name
Test status
Simulation time 1571204513 ps
CPU time 15.94 seconds
Started Apr 02 12:45:23 PM PDT 24
Finished Apr 02 12:45:40 PM PDT 24
Peak memory 213816 kb
Host smart-64691a3e-10af-4056-b645-e0298cbfcb12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2798118603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2798118603
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2402779357
Short name T150
Test name
Test status
Simulation time 2145724842 ps
CPU time 52.07 seconds
Started Apr 02 12:45:19 PM PDT 24
Finished Apr 02 12:46:12 PM PDT 24
Peak memory 199616 kb
Host smart-625cb2ba-5e8e-40cb-a902-bc95ddf78a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402779357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2402779357
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.786732843
Short name T372
Test name
Test status
Simulation time 1483009942 ps
CPU time 85.6 seconds
Started Apr 02 12:45:21 PM PDT 24
Finished Apr 02 12:46:48 PM PDT 24
Peak memory 199640 kb
Host smart-51edd08a-c42b-43c5-9d3b-2bb57bb47ca9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=786732843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.786732843
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.1136829735
Short name T457
Test name
Test status
Simulation time 56405623776 ps
CPU time 196.08 seconds
Started Apr 02 12:45:24 PM PDT 24
Finished Apr 02 12:48:41 PM PDT 24
Peak memory 199740 kb
Host smart-d4843251-3309-479b-9cea-d4965f13a517
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136829735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1136829735
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.942539370
Short name T148
Test name
Test status
Simulation time 23702865103 ps
CPU time 87.38 seconds
Started Apr 02 12:45:18 PM PDT 24
Finished Apr 02 12:46:46 PM PDT 24
Peak memory 199756 kb
Host smart-f1e4fd3a-08d2-46d1-b668-d3fd40d10007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942539370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.942539370
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.4079804965
Short name T92
Test name
Test status
Simulation time 385090943 ps
CPU time 2.49 seconds
Started Apr 02 12:45:19 PM PDT 24
Finished Apr 02 12:45:21 PM PDT 24
Peak memory 199632 kb
Host smart-d5cc72e5-fc52-4f2a-92e2-3fa4fe62202c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079804965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.4079804965
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.1761198866
Short name T34
Test name
Test status
Simulation time 304491298457 ps
CPU time 1048.52 seconds
Started Apr 02 12:45:24 PM PDT 24
Finished Apr 02 01:02:53 PM PDT 24
Peak memory 199748 kb
Host smart-a7a61d84-a2be-4700-9291-e5fe0da9d859
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761198866 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1761198866
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.3739669128
Short name T595
Test name
Test status
Simulation time 56918534 ps
CPU time 1.25 seconds
Started Apr 02 12:45:23 PM PDT 24
Finished Apr 02 12:45:26 PM PDT 24
Peak memory 199324 kb
Host smart-f0c5317e-816f-4046-8fb4-09df882c77f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739669128 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.3739669128
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.2885447957
Short name T216
Test name
Test status
Simulation time 16753441045 ps
CPU time 460.25 seconds
Started Apr 02 12:45:23 PM PDT 24
Finished Apr 02 12:53:04 PM PDT 24
Peak memory 199652 kb
Host smart-4075a5e1-8d9e-4a93-b1d3-d835db3611c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885447957 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.2885447957
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2669530635
Short name T89
Test name
Test status
Simulation time 1217580043 ps
CPU time 46.28 seconds
Started Apr 02 12:45:25 PM PDT 24
Finished Apr 02 12:46:13 PM PDT 24
Peak memory 199584 kb
Host smart-14ae9208-103a-4d21-b40e-941f7f1fbda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669530635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2669530635
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2314535319
Short name T24
Test name
Test status
Simulation time 11919464 ps
CPU time 0.6 seconds
Started Apr 02 12:45:57 PM PDT 24
Finished Apr 02 12:45:58 PM PDT 24
Peak memory 195100 kb
Host smart-c79b941a-f3b3-47cd-98b0-91b64dc67f5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314535319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2314535319
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1296300884
Short name T523
Test name
Test status
Simulation time 4196901240 ps
CPU time 43.94 seconds
Started Apr 02 12:45:24 PM PDT 24
Finished Apr 02 12:46:09 PM PDT 24
Peak memory 216096 kb
Host smart-1b97a457-001d-485e-a1c5-a9b2a65e0be4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1296300884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1296300884
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3128187175
Short name T191
Test name
Test status
Simulation time 2658096079 ps
CPU time 38.72 seconds
Started Apr 02 12:45:24 PM PDT 24
Finished Apr 02 12:46:04 PM PDT 24
Peak memory 199648 kb
Host smart-2db1894d-3021-4057-a9ce-e23fc6bbdcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128187175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3128187175
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2765087879
Short name T328
Test name
Test status
Simulation time 1564504222 ps
CPU time 91.65 seconds
Started Apr 02 12:45:22 PM PDT 24
Finished Apr 02 12:46:54 PM PDT 24
Peak memory 199504 kb
Host smart-700b67cf-efff-45f8-b941-2e67ec191c23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2765087879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2765087879
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.622350324
Short name T366
Test name
Test status
Simulation time 20231905485 ps
CPU time 96.15 seconds
Started Apr 02 12:45:24 PM PDT 24
Finished Apr 02 12:47:01 PM PDT 24
Peak memory 199664 kb
Host smart-a48d4c16-28e9-4bfd-8cdb-a264eb0df630
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622350324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.622350324
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.1965976530
Short name T262
Test name
Test status
Simulation time 2192050524 ps
CPU time 22.95 seconds
Started Apr 02 12:45:25 PM PDT 24
Finished Apr 02 12:45:48 PM PDT 24
Peak memory 199648 kb
Host smart-5f8913c8-192c-49b8-9bc0-5bf4d9ecc790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965976530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1965976530
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1519968277
Short name T378
Test name
Test status
Simulation time 350157972 ps
CPU time 4.75 seconds
Started Apr 02 12:45:23 PM PDT 24
Finished Apr 02 12:45:29 PM PDT 24
Peak memory 199388 kb
Host smart-84dea8a1-8f3c-4b43-8e05-cda6de69fe4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519968277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1519968277
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.1066330798
Short name T351
Test name
Test status
Simulation time 46671249 ps
CPU time 1.04 seconds
Started Apr 02 12:45:23 PM PDT 24
Finished Apr 02 12:45:25 PM PDT 24
Peak memory 198012 kb
Host smart-67e9a0df-14f0-4221-bf74-a55ff2e33807
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066330798 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.1066330798
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.791352015
Short name T349
Test name
Test status
Simulation time 8331119597 ps
CPU time 437.87 seconds
Started Apr 02 12:45:26 PM PDT 24
Finished Apr 02 12:52:45 PM PDT 24
Peak memory 199704 kb
Host smart-4397160d-aab1-4bc4-9d27-0813cdaba94c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791352015 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.791352015
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1265322125
Short name T518
Test name
Test status
Simulation time 23066063074 ps
CPU time 92.22 seconds
Started Apr 02 12:45:25 PM PDT 24
Finished Apr 02 12:46:58 PM PDT 24
Peak memory 199688 kb
Host smart-b8c977e0-c79d-4205-82ef-1ad349cd2a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265322125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1265322125
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.278580435
Short name T294
Test name
Test status
Simulation time 166749876 ps
CPU time 0.56 seconds
Started Apr 02 12:45:32 PM PDT 24
Finished Apr 02 12:45:33 PM PDT 24
Peak memory 194512 kb
Host smart-c68e7b96-a9fe-4009-a02e-5cdf9287a83f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278580435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.278580435
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.2793585314
Short name T185
Test name
Test status
Simulation time 378303930 ps
CPU time 14.28 seconds
Started Apr 02 12:45:28 PM PDT 24
Finished Apr 02 12:45:42 PM PDT 24
Peak memory 207812 kb
Host smart-d1bbc412-00b9-428d-be52-066ef434315a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2793585314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2793585314
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1237737269
Short name T442
Test name
Test status
Simulation time 960414413 ps
CPU time 15.1 seconds
Started Apr 02 12:45:29 PM PDT 24
Finished Apr 02 12:45:44 PM PDT 24
Peak memory 199604 kb
Host smart-bd1ce4d9-91e2-424b-a78c-9a0481245321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237737269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1237737269
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.476205639
Short name T222
Test name
Test status
Simulation time 1906847988 ps
CPU time 114.12 seconds
Started Apr 02 12:45:28 PM PDT 24
Finished Apr 02 12:47:22 PM PDT 24
Peak memory 199636 kb
Host smart-1981eb1f-0983-40f6-976d-2f7911a4577f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=476205639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.476205639
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.863508689
Short name T300
Test name
Test status
Simulation time 3535244743 ps
CPU time 188.01 seconds
Started Apr 02 12:45:30 PM PDT 24
Finished Apr 02 12:48:38 PM PDT 24
Peak memory 199696 kb
Host smart-0ae97e45-ab0b-4279-930c-a7d1c27cf543
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863508689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.863508689
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3334621295
Short name T203
Test name
Test status
Simulation time 2918918245 ps
CPU time 45.95 seconds
Started Apr 02 12:45:28 PM PDT 24
Finished Apr 02 12:46:14 PM PDT 24
Peak memory 199704 kb
Host smart-9e8e137f-f6b1-4453-9ce6-17068bf0845d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334621295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3334621295
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.2895573727
Short name T259
Test name
Test status
Simulation time 80974069 ps
CPU time 1.73 seconds
Started Apr 02 12:45:27 PM PDT 24
Finished Apr 02 12:45:29 PM PDT 24
Peak memory 199600 kb
Host smart-b0196d9a-0901-4976-a594-597080bb1c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895573727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2895573727
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.627410620
Short name T309
Test name
Test status
Simulation time 398784541659 ps
CPU time 1476.34 seconds
Started Apr 02 12:45:37 PM PDT 24
Finished Apr 02 01:10:15 PM PDT 24
Peak memory 199728 kb
Host smart-dac0d63b-da6b-4b24-870d-fb0249d8cde1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627410620 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.627410620
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.534496644
Short name T274
Test name
Test status
Simulation time 155821138 ps
CPU time 1 seconds
Started Apr 02 12:45:28 PM PDT 24
Finished Apr 02 12:45:29 PM PDT 24
Peak memory 197944 kb
Host smart-6d942b3f-59bf-4769-9c59-d4ca672538a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534496644 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.hmac_test_hmac_vectors.534496644
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.3733746930
Short name T190
Test name
Test status
Simulation time 251621572669 ps
CPU time 445.01 seconds
Started Apr 02 12:45:28 PM PDT 24
Finished Apr 02 12:52:53 PM PDT 24
Peak memory 199580 kb
Host smart-41bc74ed-c1be-44eb-aa15-8b105fd04a4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733746930 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.3733746930
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.1286078311
Short name T545
Test name
Test status
Simulation time 13289429068 ps
CPU time 42.35 seconds
Started Apr 02 12:45:29 PM PDT 24
Finished Apr 02 12:46:12 PM PDT 24
Peak memory 199684 kb
Host smart-6528aaa8-5a1d-4088-b64c-8a5f0706a431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286078311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1286078311
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3350124341
Short name T170
Test name
Test status
Simulation time 14677779 ps
CPU time 0.63 seconds
Started Apr 02 12:45:42 PM PDT 24
Finished Apr 02 12:45:43 PM PDT 24
Peak memory 194140 kb
Host smart-ca8e4159-471d-4126-aa3a-1739dc3570ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350124341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3350124341
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3093033739
Short name T19
Test name
Test status
Simulation time 1292360414 ps
CPU time 48.51 seconds
Started Apr 02 12:45:37 PM PDT 24
Finished Apr 02 12:46:27 PM PDT 24
Peak memory 207824 kb
Host smart-a2a5109a-1fa5-46ea-87fc-0df00459cf83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3093033739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3093033739
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2652642826
Short name T493
Test name
Test status
Simulation time 1256638132 ps
CPU time 63.45 seconds
Started Apr 02 12:45:31 PM PDT 24
Finished Apr 02 12:46:35 PM PDT 24
Peak memory 199544 kb
Host smart-0e5dfc9e-36d9-41f4-8733-9417f85c16ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652642826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2652642826
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.1566530990
Short name T141
Test name
Test status
Simulation time 361455274 ps
CPU time 18.82 seconds
Started Apr 02 12:45:31 PM PDT 24
Finished Apr 02 12:45:50 PM PDT 24
Peak memory 199528 kb
Host smart-fb7d8d4d-4f74-4331-8e36-c7df93154b02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1566530990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1566530990
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.2238176322
Short name T15
Test name
Test status
Simulation time 8506028823 ps
CPU time 134.56 seconds
Started Apr 02 12:45:32 PM PDT 24
Finished Apr 02 12:47:47 PM PDT 24
Peak memory 199712 kb
Host smart-2b683208-1f33-419b-b08f-868e8d2d783f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238176322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2238176322
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3663583234
Short name T417
Test name
Test status
Simulation time 6367444921 ps
CPU time 96.54 seconds
Started Apr 02 12:45:30 PM PDT 24
Finished Apr 02 12:47:07 PM PDT 24
Peak memory 199776 kb
Host smart-7869b6fe-df41-4ac7-b247-6d26c8cc9b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663583234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3663583234
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.614757754
Short name T473
Test name
Test status
Simulation time 76069165 ps
CPU time 0.72 seconds
Started Apr 02 12:45:30 PM PDT 24
Finished Apr 02 12:45:31 PM PDT 24
Peak memory 196824 kb
Host smart-ed8204ef-a069-4c19-a11e-1c55ee5d790a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614757754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.614757754
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.1330239071
Short name T76
Test name
Test status
Simulation time 77852302443 ps
CPU time 1082.46 seconds
Started Apr 02 12:45:39 PM PDT 24
Finished Apr 02 01:03:42 PM PDT 24
Peak memory 215940 kb
Host smart-fba71a95-5698-4981-a0ed-0e13f9c754f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330239071 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1330239071
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.2959346777
Short name T164
Test name
Test status
Simulation time 133386946 ps
CPU time 1.18 seconds
Started Apr 02 12:45:32 PM PDT 24
Finished Apr 02 12:45:34 PM PDT 24
Peak memory 199620 kb
Host smart-0b5264d5-92d7-4969-a099-c5d051c95423
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959346777 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.2959346777
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.2793426510
Short name T169
Test name
Test status
Simulation time 27607405815 ps
CPU time 487.64 seconds
Started Apr 02 12:45:39 PM PDT 24
Finished Apr 02 12:53:47 PM PDT 24
Peak memory 199620 kb
Host smart-18f05455-d6e0-45fd-8689-6f20dc0c6414
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793426510 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.2793426510
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2633019858
Short name T333
Test name
Test status
Simulation time 982041142 ps
CPU time 36.3 seconds
Started Apr 02 12:45:31 PM PDT 24
Finished Apr 02 12:46:08 PM PDT 24
Peak memory 199648 kb
Host smart-a35553f4-546d-4a88-8d12-40b25773f27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633019858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2633019858
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2395167710
Short name T192
Test name
Test status
Simulation time 11592885 ps
CPU time 0.59 seconds
Started Apr 02 12:45:35 PM PDT 24
Finished Apr 02 12:45:36 PM PDT 24
Peak memory 195068 kb
Host smart-095b7d15-c406-45d0-9554-aa1fcb2b3fbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395167710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2395167710
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.4026341891
Short name T512
Test name
Test status
Simulation time 4868107094 ps
CPU time 44.03 seconds
Started Apr 02 12:45:32 PM PDT 24
Finished Apr 02 12:46:16 PM PDT 24
Peak memory 215524 kb
Host smart-9e018de9-49a3-4769-ada9-a21c3fc83f21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4026341891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.4026341891
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.828539420
Short name T316
Test name
Test status
Simulation time 4602413564 ps
CPU time 33.7 seconds
Started Apr 02 12:45:32 PM PDT 24
Finished Apr 02 12:46:06 PM PDT 24
Peak memory 199728 kb
Host smart-1713090c-4e29-4596-b736-e73fc4346c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828539420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.828539420
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3426866390
Short name T98
Test name
Test status
Simulation time 8356907366 ps
CPU time 83.66 seconds
Started Apr 02 12:45:34 PM PDT 24
Finished Apr 02 12:46:58 PM PDT 24
Peak memory 199724 kb
Host smart-36d08f94-49fa-4e32-9627-bbde3c270f1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3426866390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3426866390
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.1059353383
Short name T546
Test name
Test status
Simulation time 11046008975 ps
CPU time 170.38 seconds
Started Apr 02 12:45:31 PM PDT 24
Finished Apr 02 12:48:21 PM PDT 24
Peak memory 199760 kb
Host smart-25ad353c-1950-4551-955d-8d01adf7de38
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059353383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1059353383
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1802504250
Short name T540
Test name
Test status
Simulation time 1058271493 ps
CPU time 21.25 seconds
Started Apr 02 12:45:33 PM PDT 24
Finished Apr 02 12:45:56 PM PDT 24
Peak memory 199644 kb
Host smart-a978dff4-cbc6-4c9a-befc-cb268ecf2f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802504250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1802504250
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2870856963
Short name T365
Test name
Test status
Simulation time 249955734 ps
CPU time 3.97 seconds
Started Apr 02 12:45:47 PM PDT 24
Finished Apr 02 12:45:51 PM PDT 24
Peak memory 199704 kb
Host smart-b1505b29-681d-4e63-b546-815bf086ff84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870856963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2870856963
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3908806303
Short name T414
Test name
Test status
Simulation time 124498256582 ps
CPU time 524.36 seconds
Started Apr 02 12:45:31 PM PDT 24
Finished Apr 02 12:54:15 PM PDT 24
Peak memory 199864 kb
Host smart-ba36b867-8cf2-493a-883e-07d4f577d873
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908806303 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3908806303
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.4075949738
Short name T129
Test name
Test status
Simulation time 28407764 ps
CPU time 1.1 seconds
Started Apr 02 12:45:32 PM PDT 24
Finished Apr 02 12:45:34 PM PDT 24
Peak memory 199516 kb
Host smart-d7c8f2ec-c495-4890-9ea7-33472d35c34a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075949738 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.4075949738
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.3609514452
Short name T97
Test name
Test status
Simulation time 56699962360 ps
CPU time 507.55 seconds
Started Apr 02 12:45:35 PM PDT 24
Finished Apr 02 12:54:05 PM PDT 24
Peak memory 199692 kb
Host smart-43e4fbbc-fc5c-4795-acbd-620be76473d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609514452 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.3609514452
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.1288531625
Short name T318
Test name
Test status
Simulation time 1197679300 ps
CPU time 23.9 seconds
Started Apr 02 12:45:33 PM PDT 24
Finished Apr 02 12:45:57 PM PDT 24
Peak memory 199644 kb
Host smart-614f695f-f6ac-4557-bcf5-aa39951d2850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288531625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.1288531625
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2634050094
Short name T77
Test name
Test status
Simulation time 14823895 ps
CPU time 0.55 seconds
Started Apr 02 12:45:37 PM PDT 24
Finished Apr 02 12:45:39 PM PDT 24
Peak memory 194160 kb
Host smart-ed190c67-678e-4eca-b6ba-886c43cb77c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634050094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2634050094
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.2056520331
Short name T578
Test name
Test status
Simulation time 1069941590 ps
CPU time 42 seconds
Started Apr 02 12:45:36 PM PDT 24
Finished Apr 02 12:46:20 PM PDT 24
Peak memory 224160 kb
Host smart-052ba9c1-3ab3-4fe4-8a62-12dcfa541cc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2056520331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2056520331
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2527092648
Short name T343
Test name
Test status
Simulation time 944538802 ps
CPU time 45.33 seconds
Started Apr 02 12:45:35 PM PDT 24
Finished Apr 02 12:46:21 PM PDT 24
Peak memory 199664 kb
Host smart-a2d296ce-e965-4d48-8b7d-093a8793cdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527092648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2527092648
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3488705115
Short name T498
Test name
Test status
Simulation time 2622184215 ps
CPU time 123.66 seconds
Started Apr 02 12:45:35 PM PDT 24
Finished Apr 02 12:47:39 PM PDT 24
Peak memory 199752 kb
Host smart-bcec166b-b158-42d3-80c6-2825dbe6b35f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3488705115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3488705115
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3723970203
Short name T47
Test name
Test status
Simulation time 171294911736 ps
CPU time 259.7 seconds
Started Apr 02 12:45:36 PM PDT 24
Finished Apr 02 12:49:58 PM PDT 24
Peak memory 199724 kb
Host smart-672be5c3-4a88-49ef-b1c5-2b640ade8ec6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723970203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3723970203
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2673355501
Short name T208
Test name
Test status
Simulation time 3545476602 ps
CPU time 72.07 seconds
Started Apr 02 12:45:41 PM PDT 24
Finished Apr 02 12:46:54 PM PDT 24
Peak memory 199732 kb
Host smart-eb4f112d-dde4-452b-86e9-7e5f40fbd21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673355501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2673355501
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.995091094
Short name T597
Test name
Test status
Simulation time 853873248 ps
CPU time 6.46 seconds
Started Apr 02 12:45:36 PM PDT 24
Finished Apr 02 12:45:45 PM PDT 24
Peak memory 199648 kb
Host smart-a5526b6d-0053-4dc8-9bf5-0cff8a953dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995091094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.995091094
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.2348070941
Short name T380
Test name
Test status
Simulation time 87433968427 ps
CPU time 603.03 seconds
Started Apr 02 12:45:37 PM PDT 24
Finished Apr 02 12:55:41 PM PDT 24
Peak memory 199524 kb
Host smart-7df043d6-118b-4c74-b853-dab35e333e78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348070941 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2348070941
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.883238945
Short name T469
Test name
Test status
Simulation time 30696630 ps
CPU time 1.04 seconds
Started Apr 02 12:45:37 PM PDT 24
Finished Apr 02 12:45:39 PM PDT 24
Peak memory 199404 kb
Host smart-afd0ef2a-121d-4ed0-97de-7f69e4f66f39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883238945 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.hmac_test_hmac_vectors.883238945
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.504500841
Short name T162
Test name
Test status
Simulation time 41847412250 ps
CPU time 554.89 seconds
Started Apr 02 12:45:36 PM PDT 24
Finished Apr 02 12:54:53 PM PDT 24
Peak memory 199588 kb
Host smart-85c6b5ce-2f06-4434-af20-ae3c73adf7f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504500841 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.504500841
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.188608152
Short name T561
Test name
Test status
Simulation time 1098396565 ps
CPU time 23.07 seconds
Started Apr 02 12:45:35 PM PDT 24
Finished Apr 02 12:45:58 PM PDT 24
Peak memory 199616 kb
Host smart-921ce8e7-c0d0-4414-adb4-6e8c55e74075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188608152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.188608152
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.1239650884
Short name T282
Test name
Test status
Simulation time 21993287 ps
CPU time 0.57 seconds
Started Apr 02 12:45:42 PM PDT 24
Finished Apr 02 12:45:43 PM PDT 24
Peak memory 194972 kb
Host smart-334afcaa-c0fd-442b-b4c8-bfde8a5bbb61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239650884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.1239650884
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2500371821
Short name T55
Test name
Test status
Simulation time 1306213728 ps
CPU time 43.51 seconds
Started Apr 02 12:45:36 PM PDT 24
Finished Apr 02 12:46:22 PM PDT 24
Peak memory 216064 kb
Host smart-936a5d27-94a2-4a69-b413-605403b323ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2500371821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2500371821
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3988735499
Short name T246
Test name
Test status
Simulation time 5724478934 ps
CPU time 19.47 seconds
Started Apr 02 12:45:39 PM PDT 24
Finished Apr 02 12:45:59 PM PDT 24
Peak memory 199556 kb
Host smart-e91eecd9-082e-4a4d-a027-9d064ba87a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988735499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3988735499
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.4053332107
Short name T287
Test name
Test status
Simulation time 3538607363 ps
CPU time 31.86 seconds
Started Apr 02 12:45:40 PM PDT 24
Finished Apr 02 12:46:13 PM PDT 24
Peak memory 199692 kb
Host smart-aee6ed68-d322-4cea-9d06-86022ff41316
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4053332107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.4053332107
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3795241077
Short name T379
Test name
Test status
Simulation time 2206477067 ps
CPU time 64.84 seconds
Started Apr 02 12:45:51 PM PDT 24
Finished Apr 02 12:46:56 PM PDT 24
Peak memory 199720 kb
Host smart-028b91a6-fa58-488e-acad-c29b31b628b4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795241077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3795241077
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3413293743
Short name T165
Test name
Test status
Simulation time 4143709105 ps
CPU time 47.26 seconds
Started Apr 02 12:45:35 PM PDT 24
Finished Apr 02 12:46:25 PM PDT 24
Peak memory 199760 kb
Host smart-3377c7c3-cf93-49ac-95a6-0b319d21aac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413293743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3413293743
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.1016264763
Short name T256
Test name
Test status
Simulation time 5250347993 ps
CPU time 6.29 seconds
Started Apr 02 12:45:39 PM PDT 24
Finished Apr 02 12:45:46 PM PDT 24
Peak memory 199676 kb
Host smart-a5f4190c-e3a5-4ccf-919c-1691c3a3c715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016264763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1016264763
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2994932402
Short name T51
Test name
Test status
Simulation time 94572909597 ps
CPU time 667.98 seconds
Started Apr 02 12:45:40 PM PDT 24
Finished Apr 02 12:56:50 PM PDT 24
Peak memory 248136 kb
Host smart-ab835d57-1bf9-4b8c-9629-7b83721d496b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994932402 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2994932402
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.1663306177
Short name T548
Test name
Test status
Simulation time 207161168 ps
CPU time 1.26 seconds
Started Apr 02 12:45:38 PM PDT 24
Finished Apr 02 12:45:40 PM PDT 24
Peak memory 199604 kb
Host smart-68896f4d-ba51-4a69-97cd-e9d63569b1e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663306177 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.1663306177
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.965291944
Short name T419
Test name
Test status
Simulation time 7659277112 ps
CPU time 410.15 seconds
Started Apr 02 12:45:38 PM PDT 24
Finished Apr 02 12:52:28 PM PDT 24
Peak memory 199676 kb
Host smart-41b3ecfa-cb24-4012-b305-58d8f194af1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965291944 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.965291944
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.4202394890
Short name T28
Test name
Test status
Simulation time 6190500957 ps
CPU time 24.94 seconds
Started Apr 02 12:45:41 PM PDT 24
Finished Apr 02 12:46:07 PM PDT 24
Peak memory 199724 kb
Host smart-e9c40267-7030-4517-8258-d699cca1cc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202394890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.4202394890
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.1740778405
Short name T468
Test name
Test status
Simulation time 27820235 ps
CPU time 0.56 seconds
Started Apr 02 12:45:42 PM PDT 24
Finished Apr 02 12:45:43 PM PDT 24
Peak memory 195216 kb
Host smart-174cadca-4ebc-4f32-883c-88e37a23900c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740778405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1740778405
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.1831119512
Short name T590
Test name
Test status
Simulation time 262146960 ps
CPU time 4.78 seconds
Started Apr 02 12:45:40 PM PDT 24
Finished Apr 02 12:45:46 PM PDT 24
Peak memory 199636 kb
Host smart-625eb13a-0ef5-46b5-9b1f-d515543ca2aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1831119512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1831119512
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.4204539107
Short name T522
Test name
Test status
Simulation time 1603027896 ps
CPU time 86.87 seconds
Started Apr 02 12:45:46 PM PDT 24
Finished Apr 02 12:47:13 PM PDT 24
Peak memory 199648 kb
Host smart-837d7ffd-0df9-417e-9cd9-b65260672c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204539107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.4204539107
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2774051263
Short name T158
Test name
Test status
Simulation time 33210230234 ps
CPU time 140.57 seconds
Started Apr 02 12:45:39 PM PDT 24
Finished Apr 02 12:48:01 PM PDT 24
Peak memory 199716 kb
Host smart-beeb0b74-44b5-4f64-8df1-af0137db232b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2774051263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2774051263
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3731984965
Short name T1
Test name
Test status
Simulation time 11794717619 ps
CPU time 82.82 seconds
Started Apr 02 12:45:40 PM PDT 24
Finished Apr 02 12:47:04 PM PDT 24
Peak memory 199672 kb
Host smart-f9031e2c-5241-4670-9085-db29b20fb1cd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731984965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3731984965
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.2930716948
Short name T577
Test name
Test status
Simulation time 8431077201 ps
CPU time 123.49 seconds
Started Apr 02 12:45:42 PM PDT 24
Finished Apr 02 12:47:46 PM PDT 24
Peak memory 199708 kb
Host smart-34d14667-76d5-4365-b1e5-755cd2a07deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930716948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2930716948
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.897666222
Short name T280
Test name
Test status
Simulation time 618274263 ps
CPU time 4.02 seconds
Started Apr 02 12:45:41 PM PDT 24
Finished Apr 02 12:45:46 PM PDT 24
Peak memory 199636 kb
Host smart-a5c27d3c-0a5d-4981-b618-c75d37249a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897666222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.897666222
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.132170134
Short name T295
Test name
Test status
Simulation time 53549099922 ps
CPU time 1507.01 seconds
Started Apr 02 12:46:34 PM PDT 24
Finished Apr 02 01:11:42 PM PDT 24
Peak memory 207944 kb
Host smart-4b30fa81-831a-44d2-ba74-9fa43ff5a889
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132170134 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.132170134
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.2726452592
Short name T199
Test name
Test status
Simulation time 161690842 ps
CPU time 1.01 seconds
Started Apr 02 12:45:42 PM PDT 24
Finished Apr 02 12:45:43 PM PDT 24
Peak memory 199008 kb
Host smart-b337aea8-b139-4729-b543-f82e9f978cdf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726452592 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.2726452592
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.372610426
Short name T122
Test name
Test status
Simulation time 51662738681 ps
CPU time 463.13 seconds
Started Apr 02 12:45:42 PM PDT 24
Finished Apr 02 12:53:25 PM PDT 24
Peak memory 199620 kb
Host smart-56b0d9df-cb0f-4c8c-89c6-3e01465eadc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372610426 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.372610426
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.1193832308
Short name T201
Test name
Test status
Simulation time 4606072459 ps
CPU time 42.17 seconds
Started Apr 02 12:45:39 PM PDT 24
Finished Apr 02 12:46:22 PM PDT 24
Peak memory 199708 kb
Host smart-e47e2d0c-ce40-45ae-b6ef-7520c61b882e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193832308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1193832308
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.948834980
Short name T23
Test name
Test status
Simulation time 15274764 ps
CPU time 0.6 seconds
Started Apr 02 12:45:45 PM PDT 24
Finished Apr 02 12:45:46 PM PDT 24
Peak memory 195068 kb
Host smart-93612eeb-3819-4b9b-8e71-793db43c4f31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948834980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.948834980
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1645708930
Short name T397
Test name
Test status
Simulation time 680605872 ps
CPU time 6.6 seconds
Started Apr 02 12:45:43 PM PDT 24
Finished Apr 02 12:45:50 PM PDT 24
Peak memory 207736 kb
Host smart-62090b49-67d2-4e51-9680-d8a1a2cd834e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1645708930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1645708930
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3761778680
Short name T220
Test name
Test status
Simulation time 1998711245 ps
CPU time 39.72 seconds
Started Apr 02 12:45:44 PM PDT 24
Finished Apr 02 12:46:24 PM PDT 24
Peak memory 199616 kb
Host smart-bb7c8252-248d-4b86-9f9d-8644ed7ed927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761778680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3761778680
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2334883195
Short name T567
Test name
Test status
Simulation time 10747021770 ps
CPU time 170.94 seconds
Started Apr 02 12:45:48 PM PDT 24
Finished Apr 02 12:48:39 PM PDT 24
Peak memory 199712 kb
Host smart-7b4374a6-8318-4234-b56f-9ecb7045d620
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2334883195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2334883195
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.917908391
Short name T344
Test name
Test status
Simulation time 30123257598 ps
CPU time 46.58 seconds
Started Apr 02 12:45:44 PM PDT 24
Finished Apr 02 12:46:31 PM PDT 24
Peak memory 199664 kb
Host smart-ea63d222-0b88-4191-b6f6-2b5e10753b6e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917908391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.917908391
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.2790641428
Short name T480
Test name
Test status
Simulation time 31077034341 ps
CPU time 57.61 seconds
Started Apr 02 12:45:45 PM PDT 24
Finished Apr 02 12:46:43 PM PDT 24
Peak memory 199712 kb
Host smart-1a3dec60-c055-443d-b072-e2257d6b7d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790641428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.2790641428
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3252838434
Short name T405
Test name
Test status
Simulation time 197141040 ps
CPU time 1.78 seconds
Started Apr 02 12:45:44 PM PDT 24
Finished Apr 02 12:45:46 PM PDT 24
Peak memory 199700 kb
Host smart-9ed4ead4-663d-4a0c-b487-f9f5123383a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252838434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3252838434
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.2284319205
Short name T175
Test name
Test status
Simulation time 650799956 ps
CPU time 2.33 seconds
Started Apr 02 12:45:41 PM PDT 24
Finished Apr 02 12:45:44 PM PDT 24
Peak memory 199608 kb
Host smart-44da7d49-916d-4d6f-8311-897defff6be7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284319205 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2284319205
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.3778526376
Short name T374
Test name
Test status
Simulation time 173975918 ps
CPU time 1.02 seconds
Started Apr 02 12:45:43 PM PDT 24
Finished Apr 02 12:45:45 PM PDT 24
Peak memory 198976 kb
Host smart-52ea1c0e-634d-4524-b759-a8ef0a3b3706
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778526376 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.3778526376
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.2980326969
Short name T4
Test name
Test status
Simulation time 151111196398 ps
CPU time 469.91 seconds
Started Apr 02 12:45:44 PM PDT 24
Finished Apr 02 12:53:34 PM PDT 24
Peak memory 199644 kb
Host smart-26b19047-6e9d-4106-90e9-2439fe07f443
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980326969 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.2980326969
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.2213228765
Short name T436
Test name
Test status
Simulation time 29938915686 ps
CPU time 114.7 seconds
Started Apr 02 12:45:48 PM PDT 24
Finished Apr 02 12:47:43 PM PDT 24
Peak memory 199720 kb
Host smart-e4875184-4b16-4992-a6e2-bec99b5eb78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213228765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2213228765
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.1125417439
Short name T352
Test name
Test status
Simulation time 49976362 ps
CPU time 0.57 seconds
Started Apr 02 12:44:26 PM PDT 24
Finished Apr 02 12:44:27 PM PDT 24
Peak memory 194124 kb
Host smart-e5c17a09-5782-4ef2-862a-bbac7557aab0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125417439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1125417439
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.801626776
Short name T495
Test name
Test status
Simulation time 853630868 ps
CPU time 16.64 seconds
Started Apr 02 12:44:14 PM PDT 24
Finished Apr 02 12:44:31 PM PDT 24
Peak memory 207836 kb
Host smart-3c3013e6-af62-4526-ab4a-303d55488584
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=801626776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.801626776
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3670254674
Short name T560
Test name
Test status
Simulation time 402253789 ps
CPU time 6.85 seconds
Started Apr 02 12:44:17 PM PDT 24
Finished Apr 02 12:44:24 PM PDT 24
Peak memory 199612 kb
Host smart-b2d425d6-608f-4d3a-a965-07cfce63e046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670254674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3670254674
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2059484844
Short name T347
Test name
Test status
Simulation time 9722248787 ps
CPU time 150.12 seconds
Started Apr 02 12:44:14 PM PDT 24
Finished Apr 02 12:46:44 PM PDT 24
Peak memory 199728 kb
Host smart-a7b74e65-864f-4a96-acd3-87e45a0d2e04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2059484844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2059484844
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.992196493
Short name T95
Test name
Test status
Simulation time 6847966121 ps
CPU time 53.8 seconds
Started Apr 02 12:44:22 PM PDT 24
Finished Apr 02 12:45:16 PM PDT 24
Peak memory 199748 kb
Host smart-7819ad79-a3a6-4fa3-a6f6-b2618614a5fa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992196493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.992196493
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1974382252
Short name T477
Test name
Test status
Simulation time 1870251198 ps
CPU time 36.4 seconds
Started Apr 02 12:44:18 PM PDT 24
Finished Apr 02 12:44:55 PM PDT 24
Peak memory 199640 kb
Host smart-010e83d3-8ba0-439a-9f54-8d484ff84a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974382252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1974382252
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3885176619
Short name T37
Test name
Test status
Simulation time 62721416 ps
CPU time 0.9 seconds
Started Apr 02 12:44:26 PM PDT 24
Finished Apr 02 12:44:28 PM PDT 24
Peak memory 218164 kb
Host smart-d9340c22-bb7c-455f-a96a-39de1fea8de4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885176619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3885176619
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.2647391655
Short name T147
Test name
Test status
Simulation time 953764744 ps
CPU time 3.77 seconds
Started Apr 02 12:44:15 PM PDT 24
Finished Apr 02 12:44:19 PM PDT 24
Peak memory 199596 kb
Host smart-15e85a28-29df-43c1-a3dd-61524b3cdc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647391655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2647391655
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.387836849
Short name T566
Test name
Test status
Simulation time 6296335861 ps
CPU time 55.74 seconds
Started Apr 02 12:44:23 PM PDT 24
Finished Apr 02 12:45:19 PM PDT 24
Peak memory 207952 kb
Host smart-44c312e7-4d47-419b-88c9-2d263178e0fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387836849 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.387836849
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.3787326204
Short name T237
Test name
Test status
Simulation time 252240281 ps
CPU time 1.08 seconds
Started Apr 02 12:44:24 PM PDT 24
Finished Apr 02 12:44:25 PM PDT 24
Peak memory 199084 kb
Host smart-6546c104-151c-4c26-9d7e-4c3dda73fbc8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787326204 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.3787326204
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.145447733
Short name T454
Test name
Test status
Simulation time 45334387256 ps
CPU time 551.31 seconds
Started Apr 02 12:44:22 PM PDT 24
Finished Apr 02 12:53:34 PM PDT 24
Peak memory 199656 kb
Host smart-bc512896-6311-401c-8588-7d94b8976720
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145447733 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.145447733
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.325344688
Short name T474
Test name
Test status
Simulation time 1885695803 ps
CPU time 27.52 seconds
Started Apr 02 12:44:19 PM PDT 24
Finished Apr 02 12:44:47 PM PDT 24
Peak memory 199664 kb
Host smart-ee5ad3ac-e253-4524-b47e-231ff3d9a1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325344688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.325344688
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2125833027
Short name T231
Test name
Test status
Simulation time 12924568 ps
CPU time 0.56 seconds
Started Apr 02 12:45:48 PM PDT 24
Finished Apr 02 12:45:48 PM PDT 24
Peak memory 193992 kb
Host smart-fb8f7308-059f-4007-9e59-01118b4b9434
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125833027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2125833027
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.3692619094
Short name T350
Test name
Test status
Simulation time 790806687 ps
CPU time 8.04 seconds
Started Apr 02 12:45:48 PM PDT 24
Finished Apr 02 12:45:56 PM PDT 24
Peak memory 207844 kb
Host smart-dc779cbf-f564-4435-b446-e90fbc293ad2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3692619094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3692619094
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3702549330
Short name T224
Test name
Test status
Simulation time 2807515526 ps
CPU time 12.72 seconds
Started Apr 02 12:45:47 PM PDT 24
Finished Apr 02 12:46:00 PM PDT 24
Peak memory 199712 kb
Host smart-e7c5723a-fbef-4882-a820-0bca382079d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702549330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3702549330
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.2317924808
Short name T430
Test name
Test status
Simulation time 3005157167 ps
CPU time 95.32 seconds
Started Apr 02 12:45:46 PM PDT 24
Finished Apr 02 12:47:22 PM PDT 24
Peak memory 199724 kb
Host smart-af31210b-bca6-4559-a749-b80abaabe18c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2317924808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2317924808
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2026457732
Short name T504
Test name
Test status
Simulation time 17314051964 ps
CPU time 78.67 seconds
Started Apr 02 12:45:48 PM PDT 24
Finished Apr 02 12:47:06 PM PDT 24
Peak memory 199740 kb
Host smart-53099d64-c0c3-4cfa-af71-8691e8f0712a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026457732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2026457732
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.4049490484
Short name T536
Test name
Test status
Simulation time 10567145571 ps
CPU time 150.32 seconds
Started Apr 02 12:45:50 PM PDT 24
Finished Apr 02 12:48:20 PM PDT 24
Peak memory 199692 kb
Host smart-ee37a7ee-04e4-4021-a9f3-8ec233dca368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049490484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.4049490484
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.3200126679
Short name T562
Test name
Test status
Simulation time 517331243 ps
CPU time 2.05 seconds
Started Apr 02 12:45:45 PM PDT 24
Finished Apr 02 12:45:48 PM PDT 24
Peak memory 199512 kb
Host smart-c522de44-feda-4faf-aa85-6532f8a1918d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200126679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.3200126679
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.2942057954
Short name T544
Test name
Test status
Simulation time 245954359 ps
CPU time 1.02 seconds
Started Apr 02 12:45:46 PM PDT 24
Finished Apr 02 12:45:47 PM PDT 24
Peak memory 199120 kb
Host smart-d61dff7a-e37a-4bc6-ab11-d0e9232f79e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942057954 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.2942057954
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.419950587
Short name T505
Test name
Test status
Simulation time 61147924205 ps
CPU time 479.23 seconds
Started Apr 02 12:45:50 PM PDT 24
Finished Apr 02 12:53:49 PM PDT 24
Peak memory 199660 kb
Host smart-005d32bd-5f9d-4adb-9354-a37e56a0bec3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419950587 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.419950587
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2469719289
Short name T277
Test name
Test status
Simulation time 4577049025 ps
CPU time 58.66 seconds
Started Apr 02 12:45:47 PM PDT 24
Finished Apr 02 12:46:46 PM PDT 24
Peak memory 199704 kb
Host smart-badb4f65-db68-4012-8fc4-8e63c34216b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469719289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2469719289
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.3157741521
Short name T532
Test name
Test status
Simulation time 13629727 ps
CPU time 0.58 seconds
Started Apr 02 12:45:54 PM PDT 24
Finished Apr 02 12:45:55 PM PDT 24
Peak memory 194120 kb
Host smart-b401f903-155a-40e5-a342-4ac50fa1aada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157741521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3157741521
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2937516526
Short name T257
Test name
Test status
Simulation time 2476552307 ps
CPU time 20.08 seconds
Started Apr 02 12:45:48 PM PDT 24
Finished Apr 02 12:46:08 PM PDT 24
Peak memory 215580 kb
Host smart-cc353151-e366-4024-a0bf-9bd4fcd1414c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2937516526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2937516526
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1433929336
Short name T133
Test name
Test status
Simulation time 12184644823 ps
CPU time 16.49 seconds
Started Apr 02 12:45:48 PM PDT 24
Finished Apr 02 12:46:05 PM PDT 24
Peak memory 199684 kb
Host smart-6e268838-7c74-40e6-b383-93ec1e765626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433929336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1433929336
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.456049893
Short name T320
Test name
Test status
Simulation time 195904825 ps
CPU time 11.91 seconds
Started Apr 02 12:45:47 PM PDT 24
Finished Apr 02 12:45:59 PM PDT 24
Peak memory 199476 kb
Host smart-81b1d70d-06b9-4675-ae6f-409dd87b9cf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=456049893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.456049893
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3084826196
Short name T552
Test name
Test status
Simulation time 3996041237 ps
CPU time 55.56 seconds
Started Apr 02 12:45:50 PM PDT 24
Finished Apr 02 12:46:46 PM PDT 24
Peak memory 199736 kb
Host smart-8cb9420d-8bdc-4560-b1a7-dd7d1d3d4ec1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084826196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3084826196
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3829845827
Short name T279
Test name
Test status
Simulation time 4963087881 ps
CPU time 25.52 seconds
Started Apr 02 12:45:48 PM PDT 24
Finished Apr 02 12:46:14 PM PDT 24
Peak memory 199704 kb
Host smart-1f2a7586-a23b-4e69-a104-be1347e38f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829845827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3829845827
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.2332350787
Short name T389
Test name
Test status
Simulation time 1114850497 ps
CPU time 6.73 seconds
Started Apr 02 12:45:46 PM PDT 24
Finished Apr 02 12:45:53 PM PDT 24
Peak memory 199640 kb
Host smart-7b61b21b-6050-4edb-b469-3906e5dc486e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332350787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.2332350787
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.2745884639
Short name T83
Test name
Test status
Simulation time 504094648557 ps
CPU time 1623.96 seconds
Started Apr 02 12:45:54 PM PDT 24
Finished Apr 02 01:12:59 PM PDT 24
Peak memory 199712 kb
Host smart-8d8aecef-3bcf-4047-9a7e-da04c26cb33b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745884639 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2745884639
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.2064087700
Short name T449
Test name
Test status
Simulation time 269754566 ps
CPU time 1.3 seconds
Started Apr 02 12:45:51 PM PDT 24
Finished Apr 02 12:45:53 PM PDT 24
Peak memory 199556 kb
Host smart-beb4cb8a-b036-47fe-9b9c-5d10ed84d307
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064087700 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.2064087700
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.2373435395
Short name T541
Test name
Test status
Simulation time 15975004422 ps
CPU time 453.45 seconds
Started Apr 02 12:45:52 PM PDT 24
Finished Apr 02 12:53:26 PM PDT 24
Peak memory 199660 kb
Host smart-504151c6-cb3b-49c3-b985-31d5c7cfd42f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373435395 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.2373435395
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.638473160
Short name T416
Test name
Test status
Simulation time 2492714115 ps
CPU time 43.99 seconds
Started Apr 02 12:45:52 PM PDT 24
Finished Apr 02 12:46:36 PM PDT 24
Peak memory 199736 kb
Host smart-632fd61b-8521-4242-a71e-5efb98dc23eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638473160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.638473160
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.4246639009
Short name T142
Test name
Test status
Simulation time 32502444 ps
CPU time 0.58 seconds
Started Apr 02 12:45:55 PM PDT 24
Finished Apr 02 12:45:56 PM PDT 24
Peak memory 194752 kb
Host smart-6a5aaa8d-9618-4136-b5c9-1ba9fe7ae1a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246639009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.4246639009
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1932391709
Short name T492
Test name
Test status
Simulation time 2378486208 ps
CPU time 20.11 seconds
Started Apr 02 12:45:54 PM PDT 24
Finished Apr 02 12:46:14 PM PDT 24
Peak memory 199696 kb
Host smart-6a56f6f0-3b88-4b05-8636-5e2c0365c7e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1932391709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1932391709
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.4284131120
Short name T135
Test name
Test status
Simulation time 18891934043 ps
CPU time 41.49 seconds
Started Apr 02 12:46:01 PM PDT 24
Finished Apr 02 12:46:43 PM PDT 24
Peak memory 199688 kb
Host smart-d6a829b8-6829-47e5-8681-a3e5cf67313c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284131120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.4284131120
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.603149556
Short name T338
Test name
Test status
Simulation time 1017068518 ps
CPU time 55.91 seconds
Started Apr 02 12:45:50 PM PDT 24
Finished Apr 02 12:46:46 PM PDT 24
Peak memory 199668 kb
Host smart-e76895f6-9209-4f11-a1cc-5649553cec52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=603149556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.603149556
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3866429907
Short name T32
Test name
Test status
Simulation time 7906429554 ps
CPU time 140.06 seconds
Started Apr 02 12:45:52 PM PDT 24
Finished Apr 02 12:48:12 PM PDT 24
Peak memory 199552 kb
Host smart-d24907a8-ea08-4fd3-abc3-b221afbe681a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866429907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3866429907
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.404877725
Short name T306
Test name
Test status
Simulation time 19533309755 ps
CPU time 93.7 seconds
Started Apr 02 12:45:54 PM PDT 24
Finished Apr 02 12:47:28 PM PDT 24
Peak memory 199692 kb
Host smart-d6b6780e-5ce3-4d26-b2fc-7a7833e0443d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404877725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.404877725
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.2426785473
Short name T155
Test name
Test status
Simulation time 639470611 ps
CPU time 2.42 seconds
Started Apr 02 12:45:54 PM PDT 24
Finished Apr 02 12:45:57 PM PDT 24
Peak memory 199644 kb
Host smart-d9b0000c-1e6a-4569-98d7-91baa2d0dcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426785473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2426785473
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.1514614425
Short name T71
Test name
Test status
Simulation time 45065451340 ps
CPU time 593.08 seconds
Started Apr 02 12:46:15 PM PDT 24
Finished Apr 02 12:56:09 PM PDT 24
Peak memory 199568 kb
Host smart-e34b37a6-6840-4279-9341-100effaf80f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514614425 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1514614425
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.2180253984
Short name T161
Test name
Test status
Simulation time 213912254 ps
CPU time 1.24 seconds
Started Apr 02 12:45:55 PM PDT 24
Finished Apr 02 12:45:56 PM PDT 24
Peak memory 199644 kb
Host smart-29eb4a9f-6e3d-49b0-8d69-0e400c6c31c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180253984 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.2180253984
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.3441891338
Short name T579
Test name
Test status
Simulation time 131241317968 ps
CPU time 458.81 seconds
Started Apr 02 12:46:01 PM PDT 24
Finished Apr 02 12:53:40 PM PDT 24
Peak memory 199656 kb
Host smart-7e762d58-87b4-4dd7-9d14-2ad183bac07c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441891338 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.3441891338
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.1649660137
Short name T494
Test name
Test status
Simulation time 3282946316 ps
CPU time 47.5 seconds
Started Apr 02 12:45:56 PM PDT 24
Finished Apr 02 12:46:43 PM PDT 24
Peak memory 199724 kb
Host smart-5575d2e9-be4a-4516-bbf5-de5ab7cede44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649660137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1649660137
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2607333539
Short name T136
Test name
Test status
Simulation time 23807068 ps
CPU time 0.58 seconds
Started Apr 02 12:46:01 PM PDT 24
Finished Apr 02 12:46:02 PM PDT 24
Peak memory 195076 kb
Host smart-fe9018ea-fafc-410c-99af-6f2c23086516
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607333539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2607333539
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.991762460
Short name T460
Test name
Test status
Simulation time 5143341897 ps
CPU time 45.84 seconds
Started Apr 02 12:45:54 PM PDT 24
Finished Apr 02 12:46:40 PM PDT 24
Peak memory 245964 kb
Host smart-50c21e01-d0d1-4e9c-ad08-e7106bd8a8de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=991762460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.991762460
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3026084073
Short name T334
Test name
Test status
Simulation time 21804854419 ps
CPU time 88.8 seconds
Started Apr 02 12:45:54 PM PDT 24
Finished Apr 02 12:47:23 PM PDT 24
Peak memory 199712 kb
Host smart-3c27fa89-86ef-41c8-93c3-47cd9a171cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026084073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3026084073
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.1125919144
Short name T188
Test name
Test status
Simulation time 5308430533 ps
CPU time 77.23 seconds
Started Apr 02 12:45:53 PM PDT 24
Finished Apr 02 12:47:10 PM PDT 24
Peak memory 199760 kb
Host smart-c3210d50-f9a9-4463-9f10-8b4469a4fc98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1125919144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.1125919144
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.2247752145
Short name T358
Test name
Test status
Simulation time 10501253072 ps
CPU time 204.19 seconds
Started Apr 02 12:46:01 PM PDT 24
Finished Apr 02 12:49:25 PM PDT 24
Peak memory 199736 kb
Host smart-c2dc044b-c339-4f87-b50a-e5334ffe8697
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247752145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.2247752145
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.2970991680
Short name T361
Test name
Test status
Simulation time 1264016421 ps
CPU time 80.21 seconds
Started Apr 02 12:45:54 PM PDT 24
Finished Apr 02 12:47:14 PM PDT 24
Peak memory 199636 kb
Host smart-561669bf-60e7-401d-bbf8-1d39f7f76884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970991680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2970991680
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.3126760712
Short name T235
Test name
Test status
Simulation time 180714225 ps
CPU time 2.93 seconds
Started Apr 02 12:45:54 PM PDT 24
Finished Apr 02 12:45:57 PM PDT 24
Peak memory 199648 kb
Host smart-412fef42-fa9c-4cf3-913f-8a5f5467ad43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126760712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3126760712
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.4150473361
Short name T368
Test name
Test status
Simulation time 11087288028 ps
CPU time 178.38 seconds
Started Apr 02 12:45:53 PM PDT 24
Finished Apr 02 12:48:52 PM PDT 24
Peak memory 216088 kb
Host smart-8e9ce693-8897-469c-b3c7-db45611fc4a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150473361 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.4150473361
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.2613060600
Short name T373
Test name
Test status
Simulation time 107787494 ps
CPU time 1.14 seconds
Started Apr 02 12:45:57 PM PDT 24
Finished Apr 02 12:45:58 PM PDT 24
Peak memory 199280 kb
Host smart-e59a8d53-c518-4e57-957f-908df9c0face
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613060600 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.2613060600
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.1331755587
Short name T427
Test name
Test status
Simulation time 50100963378 ps
CPU time 461.18 seconds
Started Apr 02 12:45:54 PM PDT 24
Finished Apr 02 12:53:36 PM PDT 24
Peak memory 199668 kb
Host smart-cd66da6b-77b3-4487-9d61-0b23a5097e9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331755587 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.1331755587
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1924102002
Short name T223
Test name
Test status
Simulation time 1208721502 ps
CPU time 35.75 seconds
Started Apr 02 12:45:55 PM PDT 24
Finished Apr 02 12:46:31 PM PDT 24
Peak memory 199676 kb
Host smart-bb6c12db-a918-4f69-a3bb-27861424db5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924102002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1924102002
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1886884141
Short name T516
Test name
Test status
Simulation time 16598863 ps
CPU time 0.61 seconds
Started Apr 02 12:45:58 PM PDT 24
Finished Apr 02 12:45:59 PM PDT 24
Peak memory 195200 kb
Host smart-f0a3bc19-2694-4936-9d93-4a219154b8f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886884141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1886884141
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.1919693326
Short name T353
Test name
Test status
Simulation time 669597038 ps
CPU time 19.45 seconds
Started Apr 02 12:45:55 PM PDT 24
Finished Apr 02 12:46:15 PM PDT 24
Peak memory 225248 kb
Host smart-12ef19c3-585a-41aa-8247-f5bf87c54845
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1919693326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.1919693326
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.708067946
Short name T515
Test name
Test status
Simulation time 8063077372 ps
CPU time 33.93 seconds
Started Apr 02 12:45:58 PM PDT 24
Finished Apr 02 12:46:32 PM PDT 24
Peak memory 199708 kb
Host smart-aa131785-d1b9-4b5c-9541-330a3f9869c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708067946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.708067946
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.755089668
Short name T326
Test name
Test status
Simulation time 24585339457 ps
CPU time 120.72 seconds
Started Apr 02 12:45:58 PM PDT 24
Finished Apr 02 12:47:58 PM PDT 24
Peak memory 199624 kb
Host smart-5bafc452-846a-40df-8c3c-7043ba301eb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=755089668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.755089668
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.153873426
Short name T392
Test name
Test status
Simulation time 4869600976 ps
CPU time 141.91 seconds
Started Apr 02 12:45:56 PM PDT 24
Finished Apr 02 12:48:18 PM PDT 24
Peak memory 199696 kb
Host smart-7584fe57-9892-4ba0-91b4-82a2c96a07c5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153873426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.153873426
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2877048101
Short name T426
Test name
Test status
Simulation time 16416190204 ps
CPU time 79.77 seconds
Started Apr 02 12:45:55 PM PDT 24
Finished Apr 02 12:47:15 PM PDT 24
Peak memory 199688 kb
Host smart-4b196fcf-494f-40fa-b9e3-bc3b04f13d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877048101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2877048101
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.4072363010
Short name T327
Test name
Test status
Simulation time 1298567937 ps
CPU time 3.64 seconds
Started Apr 02 12:45:54 PM PDT 24
Finished Apr 02 12:45:58 PM PDT 24
Peak memory 199648 kb
Host smart-6be97404-927f-4985-be86-4361a774cb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072363010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.4072363010
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3874720358
Short name T172
Test name
Test status
Simulation time 71274182544 ps
CPU time 934.21 seconds
Started Apr 02 12:45:59 PM PDT 24
Finished Apr 02 01:01:34 PM PDT 24
Peak memory 199888 kb
Host smart-1be4a2fc-5475-4929-84f0-976647752337
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874720358 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3874720358
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.1707826731
Short name T194
Test name
Test status
Simulation time 183439242 ps
CPU time 1.07 seconds
Started Apr 02 12:45:58 PM PDT 24
Finished Apr 02 12:45:59 PM PDT 24
Peak memory 198536 kb
Host smart-490ea8df-6095-4cb1-9ef1-6dbc2d3745d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707826731 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.1707826731
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.1751687063
Short name T238
Test name
Test status
Simulation time 17326722735 ps
CPU time 440.19 seconds
Started Apr 02 12:45:57 PM PDT 24
Finished Apr 02 12:53:18 PM PDT 24
Peak memory 199684 kb
Host smart-22ede090-1f91-443a-96e9-0a8f5d0a23e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751687063 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.1751687063
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.3815862315
Short name T273
Test name
Test status
Simulation time 18710398596 ps
CPU time 49.43 seconds
Started Apr 02 12:45:59 PM PDT 24
Finished Apr 02 12:46:49 PM PDT 24
Peak memory 199672 kb
Host smart-5e0047de-6199-4864-92ab-a28edfc3ba9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815862315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.3815862315
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.1997058958
Short name T249
Test name
Test status
Simulation time 24026012 ps
CPU time 0.62 seconds
Started Apr 02 12:46:01 PM PDT 24
Finished Apr 02 12:46:02 PM PDT 24
Peak memory 195092 kb
Host smart-6e2caec9-f9d3-4143-bab4-7aeab39988cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997058958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1997058958
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.705474112
Short name T289
Test name
Test status
Simulation time 697260963 ps
CPU time 29.46 seconds
Started Apr 02 12:46:01 PM PDT 24
Finished Apr 02 12:46:31 PM PDT 24
Peak memory 224236 kb
Host smart-dac93884-48a5-49c5-a361-11f2dcefe043
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=705474112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.705474112
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.974557380
Short name T340
Test name
Test status
Simulation time 2264431371 ps
CPU time 58.25 seconds
Started Apr 02 12:46:04 PM PDT 24
Finished Apr 02 12:47:03 PM PDT 24
Peak memory 199744 kb
Host smart-b0c2499d-aff5-416d-b643-3b7b0ccefa29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974557380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.974557380
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1504219491
Short name T305
Test name
Test status
Simulation time 5658102546 ps
CPU time 82.51 seconds
Started Apr 02 12:45:58 PM PDT 24
Finished Apr 02 12:47:21 PM PDT 24
Peak memory 199716 kb
Host smart-46c458eb-7bcb-4bc2-846b-d2ebdf71c0c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1504219491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1504219491
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1840439171
Short name T576
Test name
Test status
Simulation time 1670163835 ps
CPU time 7.72 seconds
Started Apr 02 12:46:02 PM PDT 24
Finished Apr 02 12:46:10 PM PDT 24
Peak memory 199476 kb
Host smart-6a3fa493-8537-4c98-923c-44ab0373c075
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840439171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1840439171
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.4086448520
Short name T445
Test name
Test status
Simulation time 1067125678 ps
CPU time 20.36 seconds
Started Apr 02 12:45:58 PM PDT 24
Finished Apr 02 12:46:18 PM PDT 24
Peak memory 199648 kb
Host smart-1d10306a-ab90-45ed-a7b1-f61843753902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086448520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.4086448520
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.64922975
Short name T559
Test name
Test status
Simulation time 206467325 ps
CPU time 2.74 seconds
Started Apr 02 12:46:00 PM PDT 24
Finished Apr 02 12:46:03 PM PDT 24
Peak memory 199608 kb
Host smart-3567ed81-4cc7-417f-b2ec-70060fedec7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64922975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.64922975
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.3529036319
Short name T514
Test name
Test status
Simulation time 81936997408 ps
CPU time 1445.56 seconds
Started Apr 02 12:46:01 PM PDT 24
Finished Apr 02 01:10:06 PM PDT 24
Peak memory 232280 kb
Host smart-4191c55a-b5ae-451f-9168-ae9d01e7033d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529036319 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.3529036319
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.2421813936
Short name T206
Test name
Test status
Simulation time 94299826 ps
CPU time 1.03 seconds
Started Apr 02 12:46:02 PM PDT 24
Finished Apr 02 12:46:03 PM PDT 24
Peak memory 199044 kb
Host smart-cbb602a2-12c4-4ad8-9039-b2ed3ac93a37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421813936 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.2421813936
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.2732481480
Short name T151
Test name
Test status
Simulation time 187605722148 ps
CPU time 551.49 seconds
Started Apr 02 12:46:01 PM PDT 24
Finished Apr 02 12:55:13 PM PDT 24
Peak memory 199664 kb
Host smart-116388ee-74a7-4a35-abf4-77a94954832d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732481480 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.2732481480
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.4154267991
Short name T475
Test name
Test status
Simulation time 2229238171 ps
CPU time 69.81 seconds
Started Apr 02 12:46:02 PM PDT 24
Finished Apr 02 12:47:12 PM PDT 24
Peak memory 199696 kb
Host smart-ce524d3f-6b53-4830-95a8-dec010899a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154267991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.4154267991
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.2574598057
Short name T422
Test name
Test status
Simulation time 44893951 ps
CPU time 0.59 seconds
Started Apr 02 12:46:04 PM PDT 24
Finished Apr 02 12:46:05 PM PDT 24
Peak memory 194156 kb
Host smart-b7e7f2dd-1b2e-421e-93c5-0ccc37c2c33a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574598057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2574598057
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3626416554
Short name T381
Test name
Test status
Simulation time 10360443312 ps
CPU time 57.95 seconds
Started Apr 02 12:46:08 PM PDT 24
Finished Apr 02 12:47:06 PM PDT 24
Peak memory 233912 kb
Host smart-477d3c9a-e888-43e7-a876-e2fdabe075a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3626416554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3626416554
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.34539621
Short name T571
Test name
Test status
Simulation time 5162663697 ps
CPU time 19.82 seconds
Started Apr 02 12:46:07 PM PDT 24
Finished Apr 02 12:46:27 PM PDT 24
Peak memory 199700 kb
Host smart-a1e4e6f7-112f-49bb-9177-0547ba194f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34539621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.34539621
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3699550384
Short name T78
Test name
Test status
Simulation time 1058372992 ps
CPU time 58.56 seconds
Started Apr 02 12:46:05 PM PDT 24
Finished Apr 02 12:47:04 PM PDT 24
Peak memory 199656 kb
Host smart-2af73256-2232-4068-95a0-26d7c4d38864
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3699550384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3699550384
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.1278491600
Short name T75
Test name
Test status
Simulation time 3235536267 ps
CPU time 179.48 seconds
Started Apr 02 12:46:05 PM PDT 24
Finished Apr 02 12:49:05 PM PDT 24
Peak memory 199716 kb
Host smart-6822e34c-c802-49c4-911c-2017fe418b04
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278491600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1278491600
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.938527698
Short name T497
Test name
Test status
Simulation time 5993813593 ps
CPU time 80.57 seconds
Started Apr 02 12:46:09 PM PDT 24
Finished Apr 02 12:47:29 PM PDT 24
Peak memory 199724 kb
Host smart-68a1b99f-b31a-43ae-8e23-297a91b01864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938527698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.938527698
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.2991394386
Short name T160
Test name
Test status
Simulation time 17755923 ps
CPU time 0.79 seconds
Started Apr 02 12:46:03 PM PDT 24
Finished Apr 02 12:46:04 PM PDT 24
Peak memory 197424 kb
Host smart-3424f8ab-fc92-4baf-b7c5-cb6eee25a532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991394386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.2991394386
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.275522854
Short name T400
Test name
Test status
Simulation time 333940310690 ps
CPU time 1104.34 seconds
Started Apr 02 12:46:06 PM PDT 24
Finished Apr 02 01:04:30 PM PDT 24
Peak memory 229764 kb
Host smart-7301e154-3c3b-45c2-b285-46696cffde3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275522854 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.275522854
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.3898755607
Short name T554
Test name
Test status
Simulation time 31244991 ps
CPU time 1.01 seconds
Started Apr 02 12:46:03 PM PDT 24
Finished Apr 02 12:46:04 PM PDT 24
Peak memory 197800 kb
Host smart-13cfa405-1e37-4346-a021-4d3cba45937c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898755607 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.3898755607
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.2219946403
Short name T210
Test name
Test status
Simulation time 17234924426 ps
CPU time 447.5 seconds
Started Apr 02 12:46:05 PM PDT 24
Finished Apr 02 12:53:32 PM PDT 24
Peak memory 199676 kb
Host smart-3d8cc621-aa34-4682-af33-184b11075c20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219946403 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.2219946403
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.740665149
Short name T27
Test name
Test status
Simulation time 8969351020 ps
CPU time 37.62 seconds
Started Apr 02 12:46:03 PM PDT 24
Finished Apr 02 12:46:41 PM PDT 24
Peak memory 199708 kb
Host smart-1e0e5b84-2488-4189-9d5c-bc1b0936263d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740665149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.740665149
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3634856781
Short name T125
Test name
Test status
Simulation time 50509705 ps
CPU time 0.57 seconds
Started Apr 02 12:46:12 PM PDT 24
Finished Apr 02 12:46:13 PM PDT 24
Peak memory 194180 kb
Host smart-4347519b-4d4e-4e2d-8221-4e58f45be99d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634856781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3634856781
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2922875493
Short name T218
Test name
Test status
Simulation time 1624404416 ps
CPU time 67.96 seconds
Started Apr 02 12:46:10 PM PDT 24
Finished Apr 02 12:47:18 PM PDT 24
Peak memory 240600 kb
Host smart-aabb3b20-a1f1-4a3f-8940-f42da0e9c78b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2922875493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2922875493
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2516357491
Short name T564
Test name
Test status
Simulation time 5739428605 ps
CPU time 46.48 seconds
Started Apr 02 12:46:11 PM PDT 24
Finished Apr 02 12:46:58 PM PDT 24
Peak memory 199728 kb
Host smart-f5e30d19-4da0-4263-be05-fdd27b18a29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516357491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2516357491
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.324038172
Short name T377
Test name
Test status
Simulation time 3459003657 ps
CPU time 98.42 seconds
Started Apr 02 12:46:10 PM PDT 24
Finished Apr 02 12:47:49 PM PDT 24
Peak memory 199684 kb
Host smart-a16f7d27-483c-4a5e-8647-8abcc2472aca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=324038172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.324038172
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2622438036
Short name T509
Test name
Test status
Simulation time 27658402366 ps
CPU time 98.43 seconds
Started Apr 02 12:46:11 PM PDT 24
Finished Apr 02 12:47:50 PM PDT 24
Peak memory 199692 kb
Host smart-d398b398-7071-41ec-a30d-ac36ede79674
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622438036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2622438036
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3596699202
Short name T255
Test name
Test status
Simulation time 1621806256 ps
CPU time 97.58 seconds
Started Apr 02 12:46:04 PM PDT 24
Finished Apr 02 12:47:42 PM PDT 24
Peak memory 199668 kb
Host smart-f9b3b1ba-799b-494f-8283-b718d9fa2304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596699202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3596699202
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.4051017324
Short name T490
Test name
Test status
Simulation time 162147929 ps
CPU time 2.64 seconds
Started Apr 02 12:46:10 PM PDT 24
Finished Apr 02 12:46:12 PM PDT 24
Peak memory 199624 kb
Host smart-625fcd90-7342-4de5-85c8-32f36d70908d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051017324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.4051017324
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.1539835585
Short name T195
Test name
Test status
Simulation time 273249280808 ps
CPU time 1457.88 seconds
Started Apr 02 12:46:09 PM PDT 24
Finished Apr 02 01:10:27 PM PDT 24
Peak memory 231944 kb
Host smart-e47cfcf5-33c9-41e1-b29e-81e00351cd24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539835585 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.1539835585
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.1271621012
Short name T376
Test name
Test status
Simulation time 158742776 ps
CPU time 0.96 seconds
Started Apr 02 12:46:11 PM PDT 24
Finished Apr 02 12:46:12 PM PDT 24
Peak memory 198896 kb
Host smart-3577c73b-e4f4-4d81-be6c-8747dd9368d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271621012 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.1271621012
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.3590094325
Short name T40
Test name
Test status
Simulation time 44802095859 ps
CPU time 561.92 seconds
Started Apr 02 12:46:10 PM PDT 24
Finished Apr 02 12:55:32 PM PDT 24
Peak memory 199640 kb
Host smart-9a90cd0f-3d80-4551-9e6c-0cfc57dbfbc1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590094325 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.3590094325
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3056120147
Short name T137
Test name
Test status
Simulation time 1951898141 ps
CPU time 42 seconds
Started Apr 02 12:46:08 PM PDT 24
Finished Apr 02 12:46:50 PM PDT 24
Peak memory 199688 kb
Host smart-27905497-17fe-4c8e-9232-eec733f96882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056120147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3056120147
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.453531944
Short name T431
Test name
Test status
Simulation time 11220345 ps
CPU time 0.61 seconds
Started Apr 02 12:46:13 PM PDT 24
Finished Apr 02 12:46:14 PM PDT 24
Peak memory 194084 kb
Host smart-ccb70d66-9762-45d6-9513-e056524f6164
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453531944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.453531944
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2339145052
Short name T464
Test name
Test status
Simulation time 982447002 ps
CPU time 43.29 seconds
Started Apr 02 12:46:11 PM PDT 24
Finished Apr 02 12:46:54 PM PDT 24
Peak memory 228244 kb
Host smart-43f35c85-2b20-4ecb-9438-1760d3e8e303
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2339145052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2339145052
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3412126644
Short name T396
Test name
Test status
Simulation time 785533016 ps
CPU time 6.49 seconds
Started Apr 02 12:46:14 PM PDT 24
Finished Apr 02 12:46:21 PM PDT 24
Peak memory 199616 kb
Host smart-2d469355-8ac0-47d5-8163-17d2809a6f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412126644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3412126644
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.4047841165
Short name T232
Test name
Test status
Simulation time 32726921352 ps
CPU time 102.09 seconds
Started Apr 02 12:46:12 PM PDT 24
Finished Apr 02 12:47:55 PM PDT 24
Peak memory 199728 kb
Host smart-620349c9-daaf-45dc-a3c8-aae66d785bd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4047841165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.4047841165
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.2117805105
Short name T302
Test name
Test status
Simulation time 2743862652 ps
CPU time 35.07 seconds
Started Apr 02 12:46:14 PM PDT 24
Finished Apr 02 12:46:49 PM PDT 24
Peak memory 199560 kb
Host smart-cc006fee-036c-4b28-929a-df3c5810a28e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117805105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.2117805105
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.267709962
Short name T286
Test name
Test status
Simulation time 3829130225 ps
CPU time 38.39 seconds
Started Apr 02 12:46:09 PM PDT 24
Finished Apr 02 12:46:47 PM PDT 24
Peak memory 199736 kb
Host smart-5027497a-f25c-496f-963b-396e99c4ef86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267709962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.267709962
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1495239351
Short name T568
Test name
Test status
Simulation time 1298867225 ps
CPU time 6.18 seconds
Started Apr 02 12:46:12 PM PDT 24
Finished Apr 02 12:46:18 PM PDT 24
Peak memory 199652 kb
Host smart-7840a365-8f69-4af8-a56c-5cd3d8cff1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495239351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1495239351
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.187068522
Short name T424
Test name
Test status
Simulation time 338227910469 ps
CPU time 1599.57 seconds
Started Apr 02 12:46:13 PM PDT 24
Finished Apr 02 01:12:53 PM PDT 24
Peak memory 199756 kb
Host smart-5b1940e1-69ce-4a91-b59f-4d90f18f96cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187068522 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.187068522
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.588039317
Short name T221
Test name
Test status
Simulation time 77359086 ps
CPU time 1.06 seconds
Started Apr 02 12:46:15 PM PDT 24
Finished Apr 02 12:46:17 PM PDT 24
Peak memory 198092 kb
Host smart-7c13d3ef-94c2-4fec-a2b8-a9bfeb5647bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588039317 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_hmac_vectors.588039317
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.1704766687
Short name T153
Test name
Test status
Simulation time 16759321332 ps
CPU time 454.8 seconds
Started Apr 02 12:46:13 PM PDT 24
Finished Apr 02 12:53:48 PM PDT 24
Peak memory 199648 kb
Host smart-d2e93694-6e3d-48ad-9aed-127281b48d90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704766687 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.1704766687
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1112977797
Short name T527
Test name
Test status
Simulation time 10655391616 ps
CPU time 56.74 seconds
Started Apr 02 12:46:13 PM PDT 24
Finished Apr 02 12:47:10 PM PDT 24
Peak memory 199684 kb
Host smart-0f3641e5-d0e1-4a10-8dcf-c6a51e7abc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112977797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1112977797
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2529209523
Short name T467
Test name
Test status
Simulation time 15374689 ps
CPU time 0.59 seconds
Started Apr 02 12:46:18 PM PDT 24
Finished Apr 02 12:46:19 PM PDT 24
Peak memory 195032 kb
Host smart-0d392e06-3d45-459c-92ba-e7782577db43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529209523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2529209523
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1911631936
Short name T434
Test name
Test status
Simulation time 1393314861 ps
CPU time 12.14 seconds
Started Apr 02 12:46:17 PM PDT 24
Finished Apr 02 12:46:29 PM PDT 24
Peak memory 212344 kb
Host smart-bd41ec04-ecb6-4443-8d36-91f81a88c4ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1911631936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1911631936
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1639344039
Short name T131
Test name
Test status
Simulation time 9941448120 ps
CPU time 50.57 seconds
Started Apr 02 12:46:20 PM PDT 24
Finished Apr 02 12:47:11 PM PDT 24
Peak memory 199688 kb
Host smart-2ac6ca77-6335-4bb4-8a14-e0fb15fd848a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639344039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1639344039
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.335416530
Short name T550
Test name
Test status
Simulation time 823072344 ps
CPU time 50.84 seconds
Started Apr 02 12:46:15 PM PDT 24
Finished Apr 02 12:47:06 PM PDT 24
Peak memory 199564 kb
Host smart-884962a5-4d42-4773-a091-f02c3e19c7cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=335416530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.335416530
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.4039806829
Short name T499
Test name
Test status
Simulation time 6679220824 ps
CPU time 89.66 seconds
Started Apr 02 12:46:17 PM PDT 24
Finished Apr 02 12:47:47 PM PDT 24
Peak memory 199740 kb
Host smart-a690e9c8-f289-49dd-a5a4-9506541330bc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039806829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.4039806829
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2424521970
Short name T456
Test name
Test status
Simulation time 1664707526 ps
CPU time 23.77 seconds
Started Apr 02 12:46:17 PM PDT 24
Finished Apr 02 12:46:41 PM PDT 24
Peak memory 199604 kb
Host smart-f100f2a1-bbf3-43e8-989e-8cfd547923af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424521970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2424521970
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.720020021
Short name T412
Test name
Test status
Simulation time 105308838 ps
CPU time 1.81 seconds
Started Apr 02 12:46:15 PM PDT 24
Finished Apr 02 12:46:16 PM PDT 24
Peak memory 199552 kb
Host smart-d5fed8de-51c1-4b2b-bc60-46aebee43e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720020021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.720020021
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1019505028
Short name T17
Test name
Test status
Simulation time 86860503587 ps
CPU time 795.36 seconds
Started Apr 02 12:46:17 PM PDT 24
Finished Apr 02 12:59:32 PM PDT 24
Peak memory 207928 kb
Host smart-f001da60-b6f7-43fb-938b-b3e8d41e8ae8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019505028 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1019505028
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.1629206791
Short name T236
Test name
Test status
Simulation time 72366839 ps
CPU time 1.04 seconds
Started Apr 02 12:46:19 PM PDT 24
Finished Apr 02 12:46:20 PM PDT 24
Peak memory 199232 kb
Host smart-a335b072-8dbf-4b63-941c-cdb3aab55c56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629206791 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.1629206791
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.1015744943
Short name T481
Test name
Test status
Simulation time 78950595589 ps
CPU time 507.56 seconds
Started Apr 02 12:46:18 PM PDT 24
Finished Apr 02 12:54:46 PM PDT 24
Peak memory 199608 kb
Host smart-80300a8e-b20f-4cda-9b82-f1a396c3a6f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015744943 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.1015744943
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.384944114
Short name T127
Test name
Test status
Simulation time 9168667046 ps
CPU time 27.49 seconds
Started Apr 02 12:46:23 PM PDT 24
Finished Apr 02 12:46:50 PM PDT 24
Peak memory 199708 kb
Host smart-2bc5f6ed-395c-4f81-9565-a46be5cb9bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384944114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.384944114
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.3624468338
Short name T401
Test name
Test status
Simulation time 15577283 ps
CPU time 0.58 seconds
Started Apr 02 12:44:28 PM PDT 24
Finished Apr 02 12:44:29 PM PDT 24
Peak memory 195188 kb
Host smart-762cf858-30c4-4cd0-b895-0899394346a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624468338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3624468338
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1787821324
Short name T52
Test name
Test status
Simulation time 5548411634 ps
CPU time 54.28 seconds
Started Apr 02 12:44:25 PM PDT 24
Finished Apr 02 12:45:20 PM PDT 24
Peak memory 216076 kb
Host smart-fec50332-c3b0-48f2-9418-85e53a0cd82e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1787821324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1787821324
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1705529835
Short name T551
Test name
Test status
Simulation time 2212914702 ps
CPU time 57.28 seconds
Started Apr 02 12:44:27 PM PDT 24
Finished Apr 02 12:45:24 PM PDT 24
Peak memory 199708 kb
Host smart-0e8455b5-ef05-45a1-b6ff-f0ca94755cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705529835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1705529835
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.86690719
Short name T258
Test name
Test status
Simulation time 3155416941 ps
CPU time 28.47 seconds
Started Apr 02 12:44:30 PM PDT 24
Finished Apr 02 12:44:59 PM PDT 24
Peak memory 199748 kb
Host smart-49c3618d-14da-4e94-a742-5bebd5d9db36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=86690719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.86690719
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.3213008826
Short name T18
Test name
Test status
Simulation time 805106191 ps
CPU time 45.09 seconds
Started Apr 02 12:44:27 PM PDT 24
Finished Apr 02 12:45:13 PM PDT 24
Peak memory 199672 kb
Host smart-75108afe-4c7e-4bcf-a95f-e2f25ec7269e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213008826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3213008826
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.1576933414
Short name T575
Test name
Test status
Simulation time 210944563 ps
CPU time 3.04 seconds
Started Apr 02 12:44:31 PM PDT 24
Finished Apr 02 12:44:34 PM PDT 24
Peak memory 199588 kb
Host smart-5fb73b48-8d68-4e89-92df-586958034b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576933414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1576933414
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3468572511
Short name T367
Test name
Test status
Simulation time 402809364 ps
CPU time 6.37 seconds
Started Apr 02 12:44:27 PM PDT 24
Finished Apr 02 12:44:34 PM PDT 24
Peak memory 199676 kb
Host smart-6e5cee5f-3e45-4cd9-bf00-5ec0db98e46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468572511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3468572511
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.272334100
Short name T345
Test name
Test status
Simulation time 28836180618 ps
CPU time 543.04 seconds
Started Apr 02 12:44:27 PM PDT 24
Finished Apr 02 12:53:31 PM PDT 24
Peak memory 207912 kb
Host smart-b58839c3-fd36-4c87-8aaa-293cbace5390
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272334100 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.272334100
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.1462063071
Short name T452
Test name
Test status
Simulation time 56171154 ps
CPU time 1.25 seconds
Started Apr 02 12:44:25 PM PDT 24
Finished Apr 02 12:44:26 PM PDT 24
Peak memory 199248 kb
Host smart-dabf19cf-bc5f-4540-8096-130e661fea5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462063071 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.1462063071
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.1263575200
Short name T215
Test name
Test status
Simulation time 134408120134 ps
CPU time 520.11 seconds
Started Apr 02 12:44:25 PM PDT 24
Finished Apr 02 12:53:06 PM PDT 24
Peak memory 199656 kb
Host smart-311bd378-9d1d-4420-ae6f-d25fa90fb3a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263575200 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.1263575200
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3379632316
Short name T356
Test name
Test status
Simulation time 7361616602 ps
CPU time 25.29 seconds
Started Apr 02 12:44:26 PM PDT 24
Finished Apr 02 12:44:51 PM PDT 24
Peak memory 199612 kb
Host smart-c1a03e00-0c6f-4df7-a99f-9d3f0615a977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379632316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3379632316
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1025434613
Short name T242
Test name
Test status
Simulation time 73037430 ps
CPU time 0.6 seconds
Started Apr 02 12:44:28 PM PDT 24
Finished Apr 02 12:44:29 PM PDT 24
Peak memory 195224 kb
Host smart-ece07c17-6b9b-4608-82b9-1e59faae630f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025434613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1025434613
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.1265339266
Short name T260
Test name
Test status
Simulation time 2160468548 ps
CPU time 42.61 seconds
Started Apr 02 12:44:29 PM PDT 24
Finished Apr 02 12:45:11 PM PDT 24
Peak memory 219184 kb
Host smart-2771dd6a-d42f-40d3-b0fe-db871f4ac497
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1265339266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.1265339266
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.2209092223
Short name T276
Test name
Test status
Simulation time 711776525 ps
CPU time 17.19 seconds
Started Apr 02 12:44:34 PM PDT 24
Finished Apr 02 12:44:51 PM PDT 24
Peak memory 199444 kb
Host smart-b1ac1c1d-b46b-49cc-8c6c-2f7549fba342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209092223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2209092223
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2141145564
Short name T44
Test name
Test status
Simulation time 5915291796 ps
CPU time 110.29 seconds
Started Apr 02 12:44:41 PM PDT 24
Finished Apr 02 12:46:31 PM PDT 24
Peak memory 199700 kb
Host smart-5b6ea5ee-dcfb-4532-9875-11c70dcd2b98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2141145564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2141145564
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.2114058851
Short name T31
Test name
Test status
Simulation time 4482665978 ps
CPU time 39.72 seconds
Started Apr 02 12:44:29 PM PDT 24
Finished Apr 02 12:45:09 PM PDT 24
Peak memory 199708 kb
Host smart-8f830e42-50cc-43c5-8139-c345d6e5fd88
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114058851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2114058851
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.169272733
Short name T181
Test name
Test status
Simulation time 2197644556 ps
CPU time 16.12 seconds
Started Apr 02 12:44:27 PM PDT 24
Finished Apr 02 12:44:44 PM PDT 24
Peak memory 199684 kb
Host smart-dfd0522c-e0f0-4268-a722-1c2499278b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169272733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.169272733
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.1499285848
Short name T555
Test name
Test status
Simulation time 1054418892 ps
CPU time 2.54 seconds
Started Apr 02 12:44:26 PM PDT 24
Finished Apr 02 12:44:29 PM PDT 24
Peak memory 199444 kb
Host smart-1b209f49-cfb3-4aba-b72c-153cebf16b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499285848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1499285848
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.2556300065
Short name T547
Test name
Test status
Simulation time 632020632218 ps
CPU time 2098.1 seconds
Started Apr 02 12:44:36 PM PDT 24
Finished Apr 02 01:19:35 PM PDT 24
Peak memory 217588 kb
Host smart-bb7c7df5-3b82-4547-83f1-4839a3dcf17b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556300065 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2556300065
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.637214742
Short name T440
Test name
Test status
Simulation time 69770931 ps
CPU time 1.24 seconds
Started Apr 02 12:44:41 PM PDT 24
Finished Apr 02 12:44:42 PM PDT 24
Peak memory 198512 kb
Host smart-6ad78192-6fae-4d71-8fdf-e75f995136f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637214742 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_hmac_vectors.637214742
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.1575789809
Short name T93
Test name
Test status
Simulation time 14787462563 ps
CPU time 428.45 seconds
Started Apr 02 12:44:32 PM PDT 24
Finished Apr 02 12:51:41 PM PDT 24
Peak memory 199596 kb
Host smart-535b8498-6456-4f77-9dc9-c14619367a54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575789809 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.1575789809
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.3158905843
Short name T288
Test name
Test status
Simulation time 26239271036 ps
CPU time 94.82 seconds
Started Apr 02 12:44:40 PM PDT 24
Finished Apr 02 12:46:15 PM PDT 24
Peak memory 199684 kb
Host smart-1a88d724-44b8-4dcc-a6e3-eba054387e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158905843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3158905843
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.4257725614
Short name T363
Test name
Test status
Simulation time 12783716 ps
CPU time 0.59 seconds
Started Apr 02 12:44:42 PM PDT 24
Finished Apr 02 12:44:43 PM PDT 24
Peak memory 194112 kb
Host smart-776f753f-6471-48d1-a5ce-496673ae4f88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257725614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.4257725614
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.837034425
Short name T448
Test name
Test status
Simulation time 6270739728 ps
CPU time 51.38 seconds
Started Apr 02 12:44:29 PM PDT 24
Finished Apr 02 12:45:21 PM PDT 24
Peak memory 219252 kb
Host smart-3e4bad55-2912-4500-9045-2196f76feaf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=837034425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.837034425
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1613505551
Short name T354
Test name
Test status
Simulation time 6067933226 ps
CPU time 46.91 seconds
Started Apr 02 12:44:30 PM PDT 24
Finished Apr 02 12:45:17 PM PDT 24
Peak memory 199672 kb
Host smart-b62f58f9-a1d9-4ba4-87e8-e506ea5d1784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613505551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1613505551
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.831726487
Short name T458
Test name
Test status
Simulation time 8538322007 ps
CPU time 148.42 seconds
Started Apr 02 12:44:31 PM PDT 24
Finished Apr 02 12:47:00 PM PDT 24
Peak memory 199680 kb
Host smart-c9379642-88f9-49f9-b563-956d1f8f68f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=831726487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.831726487
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.3759599381
Short name T485
Test name
Test status
Simulation time 5009880608 ps
CPU time 79.38 seconds
Started Apr 02 12:44:27 PM PDT 24
Finished Apr 02 12:45:47 PM PDT 24
Peak memory 199772 kb
Host smart-9709c92e-fc9e-4c6b-8d96-efdc3c7ebbbe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759599381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3759599381
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3396665018
Short name T329
Test name
Test status
Simulation time 6782849636 ps
CPU time 99.83 seconds
Started Apr 02 12:44:43 PM PDT 24
Finished Apr 02 12:46:24 PM PDT 24
Peak memory 199656 kb
Host smart-3aa839d4-068d-4ae2-8a7d-ccb9eb22daeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396665018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3396665018
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.394589814
Short name T140
Test name
Test status
Simulation time 576004074 ps
CPU time 6.99 seconds
Started Apr 02 12:44:32 PM PDT 24
Finished Apr 02 12:44:39 PM PDT 24
Peak memory 199596 kb
Host smart-c3f9701f-2f05-4c35-a891-5e31e2715e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394589814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.394589814
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.2376220253
Short name T501
Test name
Test status
Simulation time 467525721067 ps
CPU time 484.43 seconds
Started Apr 02 12:44:36 PM PDT 24
Finished Apr 02 12:52:41 PM PDT 24
Peak memory 199708 kb
Host smart-c34c1253-595b-4db2-8f3f-44287c79acf1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376220253 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.2376220253
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.3978821810
Short name T11
Test name
Test status
Simulation time 105105731317 ps
CPU time 3286.05 seconds
Started Apr 02 12:44:36 PM PDT 24
Finished Apr 02 01:39:23 PM PDT 24
Peak memory 248928 kb
Host smart-1cdf8b46-a99d-4975-bae3-7b75fee7f7a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3978821810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.3978821810
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.3327949447
Short name T264
Test name
Test status
Simulation time 102464759 ps
CPU time 0.96 seconds
Started Apr 02 12:44:36 PM PDT 24
Finished Apr 02 12:44:38 PM PDT 24
Peak memory 197576 kb
Host smart-b27deb11-9132-47df-aa8c-d68fbc92eb05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327949447 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.3327949447
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.1525042903
Short name T59
Test name
Test status
Simulation time 53126125048 ps
CPU time 489.69 seconds
Started Apr 02 12:44:32 PM PDT 24
Finished Apr 02 12:52:42 PM PDT 24
Peak memory 199680 kb
Host smart-05d3fbab-74b7-412e-9511-fcc6499a311c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525042903 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.1525042903
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1919627832
Short name T421
Test name
Test status
Simulation time 22329519555 ps
CPU time 79.14 seconds
Started Apr 02 12:44:31 PM PDT 24
Finished Apr 02 12:45:51 PM PDT 24
Peak memory 199660 kb
Host smart-296f6842-cc56-4172-a3fa-1d594d43f311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919627832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1919627832
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/71.hmac_stress_all_with_rand_reset.3537931924
Short name T45
Test name
Test status
Simulation time 74062277173 ps
CPU time 1038.1 seconds
Started Apr 02 12:46:24 PM PDT 24
Finished Apr 02 01:03:43 PM PDT 24
Peak memory 216160 kb
Host smart-eb2d398e-7574-4e0b-96ab-58aa170d913e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3537931924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.hmac_stress_all_with_rand_reset.3537931924
Directory /workspace/71.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.4041279964
Short name T317
Test name
Test status
Simulation time 15060561 ps
CPU time 0.61 seconds
Started Apr 02 12:44:33 PM PDT 24
Finished Apr 02 12:44:34 PM PDT 24
Peak memory 194860 kb
Host smart-2c9d109b-9005-4910-9ce5-83c58e0a5200
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041279964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.4041279964
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2674609815
Short name T239
Test name
Test status
Simulation time 1029143461 ps
CPU time 33.06 seconds
Started Apr 02 12:44:34 PM PDT 24
Finished Apr 02 12:45:07 PM PDT 24
Peak memory 217032 kb
Host smart-c5b02d42-2a62-451d-813b-dfc5e65c2cd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2674609815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2674609815
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3402164687
Short name T471
Test name
Test status
Simulation time 2495474792 ps
CPU time 30.56 seconds
Started Apr 02 12:44:42 PM PDT 24
Finished Apr 02 12:45:12 PM PDT 24
Peak memory 199680 kb
Host smart-dcf264f0-2e6f-45f8-ab2b-63f93aeb9cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402164687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3402164687
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.391402480
Short name T569
Test name
Test status
Simulation time 3112284069 ps
CPU time 94.99 seconds
Started Apr 02 12:44:34 PM PDT 24
Finished Apr 02 12:46:09 PM PDT 24
Peak memory 199532 kb
Host smart-d1cdae9e-2434-4f8d-b79f-b998308bcba2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=391402480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.391402480
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3163855536
Short name T14
Test name
Test status
Simulation time 8884119609 ps
CPU time 117.6 seconds
Started Apr 02 12:44:34 PM PDT 24
Finished Apr 02 12:46:32 PM PDT 24
Peak memory 199696 kb
Host smart-2cc3a432-f984-487b-a641-20c14f9870af
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163855536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3163855536
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1726807603
Short name T128
Test name
Test status
Simulation time 7952269447 ps
CPU time 86.02 seconds
Started Apr 02 12:44:34 PM PDT 24
Finished Apr 02 12:46:00 PM PDT 24
Peak memory 199712 kb
Host smart-1f74bf47-6743-4973-a190-6b9b255099d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726807603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1726807603
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.2545609278
Short name T390
Test name
Test status
Simulation time 32794609 ps
CPU time 1.28 seconds
Started Apr 02 12:44:33 PM PDT 24
Finished Apr 02 12:44:34 PM PDT 24
Peak memory 199548 kb
Host smart-81b79869-a214-41dc-a692-30c9f6e70830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545609278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.2545609278
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.755596895
Short name T439
Test name
Test status
Simulation time 198528898473 ps
CPU time 2740.16 seconds
Started Apr 02 12:44:32 PM PDT 24
Finished Apr 02 01:30:13 PM PDT 24
Peak memory 248176 kb
Host smart-0d4ef545-5f13-4ecb-8b4c-229c1e119ca5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755596895 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.755596895
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.3626183485
Short name T196
Test name
Test status
Simulation time 115603974 ps
CPU time 1.27 seconds
Started Apr 02 12:44:41 PM PDT 24
Finished Apr 02 12:44:43 PM PDT 24
Peak memory 199592 kb
Host smart-0e760340-dbbd-4ae7-83e1-a5f084c85aef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626183485 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.3626183485
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.2348100890
Short name T225
Test name
Test status
Simulation time 53593253797 ps
CPU time 454.39 seconds
Started Apr 02 12:44:41 PM PDT 24
Finished Apr 02 12:52:15 PM PDT 24
Peak memory 199620 kb
Host smart-68c240df-06c5-4927-963f-a49d6f61040e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348100890 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.2348100890
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2142661573
Short name T132
Test name
Test status
Simulation time 1322814412 ps
CPU time 28.77 seconds
Started Apr 02 12:44:33 PM PDT 24
Finished Apr 02 12:45:02 PM PDT 24
Peak memory 199600 kb
Host smart-cb1ace3e-7be6-4606-8f4d-2ce0122cb9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142661573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2142661573
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.4292207224
Short name T319
Test name
Test status
Simulation time 14070328 ps
CPU time 0.6 seconds
Started Apr 02 12:44:42 PM PDT 24
Finished Apr 02 12:44:43 PM PDT 24
Peak memory 195172 kb
Host smart-84455c19-d641-45e1-aa6e-242c4815a985
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292207224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.4292207224
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2608326593
Short name T360
Test name
Test status
Simulation time 106553820 ps
CPU time 2.38 seconds
Started Apr 02 12:44:38 PM PDT 24
Finished Apr 02 12:44:41 PM PDT 24
Peak memory 215644 kb
Host smart-ccb1be2c-eb42-476a-a802-ee5dbfba7c84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2608326593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2608326593
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.791781095
Short name T281
Test name
Test status
Simulation time 254395829 ps
CPU time 12.53 seconds
Started Apr 02 12:44:39 PM PDT 24
Finished Apr 02 12:44:52 PM PDT 24
Peak memory 199636 kb
Host smart-a0cdf2f9-5600-4062-8dd3-0ed20f35c14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791781095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.791781095
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1635003909
Short name T584
Test name
Test status
Simulation time 1409560794 ps
CPU time 40.48 seconds
Started Apr 02 12:44:40 PM PDT 24
Finished Apr 02 12:45:20 PM PDT 24
Peak memory 199664 kb
Host smart-bc850c41-fb14-4aa2-be76-4a604a573a10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1635003909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1635003909
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.1162388675
Short name T403
Test name
Test status
Simulation time 3514943425 ps
CPU time 46.06 seconds
Started Apr 02 12:44:36 PM PDT 24
Finished Apr 02 12:45:23 PM PDT 24
Peak memory 199708 kb
Host smart-44472d5a-eb5a-4987-b0cd-3f1a7d3315e9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162388675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1162388675
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3383580468
Short name T126
Test name
Test status
Simulation time 22827166992 ps
CPU time 111.45 seconds
Started Apr 02 12:44:42 PM PDT 24
Finished Apr 02 12:46:34 PM PDT 24
Peak memory 199700 kb
Host smart-95d4942d-91f0-4231-9049-5465ebd02bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383580468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3383580468
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2921908752
Short name T130
Test name
Test status
Simulation time 117737298 ps
CPU time 4 seconds
Started Apr 02 12:44:32 PM PDT 24
Finished Apr 02 12:44:36 PM PDT 24
Peak memory 199540 kb
Host smart-fc588e63-3b71-4267-bdcc-bdc4082e0e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921908752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2921908752
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.612080250
Short name T297
Test name
Test status
Simulation time 525939154542 ps
CPU time 1500.63 seconds
Started Apr 02 12:44:36 PM PDT 24
Finished Apr 02 01:09:37 PM PDT 24
Peak memory 199708 kb
Host smart-f32309db-b760-4c4e-b583-bbcb8d355ccd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612080250 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.612080250
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.2461073886
Short name T385
Test name
Test status
Simulation time 97941443 ps
CPU time 1.01 seconds
Started Apr 02 12:44:38 PM PDT 24
Finished Apr 02 12:44:39 PM PDT 24
Peak memory 198648 kb
Host smart-bd716a2a-e2fd-4a37-b3b2-a88f4ff23262
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461073886 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.2461073886
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.3583417020
Short name T594
Test name
Test status
Simulation time 43707865229 ps
CPU time 537.91 seconds
Started Apr 02 12:44:38 PM PDT 24
Finished Apr 02 12:53:36 PM PDT 24
Peak memory 199644 kb
Host smart-56fc3a92-610a-4e43-bfe1-d97a07e7a806
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583417020 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.3583417020
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3130735206
Short name T537
Test name
Test status
Simulation time 1188641441 ps
CPU time 25.89 seconds
Started Apr 02 12:44:36 PM PDT 24
Finished Apr 02 12:45:02 PM PDT 24
Peak memory 199644 kb
Host smart-42c875ee-1993-4f74-9a2a-5159dea69b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130735206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3130735206
Directory /workspace/9.hmac_wipe_secret/latest

Test location /workspace/coverage/default/94.hmac_stress_all_with_rand_reset.226171015
Short name T69
Test name
Test status
Simulation time 12715422266 ps
CPU time 706.87 seconds
Started Apr 02 12:46:29 PM PDT 24
Finished Apr 02 12:58:16 PM PDT 24
Peak memory 216140 kb
Host smart-407b8a17-2b98-490d-961b-302bd00c18b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=226171015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.hmac_stress_all_with_rand_reset.226171015
Directory /workspace/94.hmac_stress_all_with_rand_reset/latest
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