Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14542963	1			T1	492		T2	260174		T4	3733
all_values[1]	14542963	1			T1	492		T2	260174		T4	3733
all_values[2]	14542963	1			T1	492		T2	260174		T4	3733

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

107245

1

T2

1510

T5

222

T14

730

auto[1]

43521644

1

T1

1476

T2

779012

T4

11199

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

41261531

1

T1

1455

T2

752291

T4

11182

auto[1]

2367358

1

T1

21

T2

28231

T4

17

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	28159	1			T2	379		T5	109		T14	697
all_values[0]	auto[0]	auto[1]	404	1			T2	2		T5	2		T14	6
all_values[0]	auto[1]	auto[0]	14465640	1			T1	471		T2	259033		T4	3716
all_values[0]	auto[1]	auto[1]	48760	1			T1	21		T2	760		T4	17
all_values[1]	auto[0]	auto[0]	32728	1			T2	1125		T5	111		T14	27
all_values[1]	auto[0]	auto[1]	216	1			T2	2		T13	1		T45	4
all_values[1]	auto[1]	auto[0]	14509471	1			T1	492		T2	259047		T4	3733
all_values[1]	auto[1]	auto[1]	548	1			T14	1		T20	2		T13	1
all_values[2]	auto[0]	auto[0]	33049	1			T2	2		T38	116		T16	2
all_values[2]	auto[0]	auto[1]	12689	1			T45	7		T6	2		T23	313
all_values[2]	auto[1]	auto[0]	12192484	1			T1	492		T2	232705		T4	3733
all_values[2]	auto[1]	auto[1]	2304741	1			T2	27467		T14	33295		T15	8562