Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6908018

1

T1

9

T2

130219

T4

1508

auto[1]

2492745

1

T1

7

T2

19728

T4

2193

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2434022

1

T1

3

T2

20030

T4

1712

auto[1]

6966741

1

T1

13

T2

129917

T4

1989

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6240963

1

T1

8

T2

128388

T4

1411

auto[1]

3159800

1

T1

8

T2

21559

T4

2290

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6113132	1			T1	2		T2	141818		T4	3432
fifo_depth[1]	467166	1			T2	5232		T4	176		T5	367
fifo_depth[2]	391568	1			T2	1957		T4	67		T5	325
fifo_depth[3]	317089	1			T2	689		T4	18		T5	349
fifo_depth[4]	267671	1			T2	198		T4	7		T5	326
fifo_depth[5]	234897	1			T2	40		T4	1		T5	336
fifo_depth[6]	221763	1			T2	8		T5	316		T14	5816
fifo_depth[7]	193517	1			T2	4		T5	302		T14	5174
fifo_depth[8]	173368	1			T2	1		T5	252		T14	4525
fifo_depth[9]	118601	1			T5	177		T14	3211		T38	3
fifo_depth[10]	89292	1			T5	128		T14	2233		T38	1
fifo_depth[11]	54449	1			T5	58		T14	1577		T15	257
fifo_depth[12]	56924	1			T5	34		T14	1401		T38	1
fifo_depth[13]	26324	1			T5	17		T14	968		T15	59
fifo_depth[14]	35881	1			T5	6		T14	1049		T15	19
fifo_depth[15]	20634	1			T5	4		T14	917		T15	8
fifo_depth[16]	82451	1			T5	3		T14	3312		T15	5

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3392163

1

T1

16

T2

8129

T4

269

auto[1]

6008600

1

T2

141818

T4

3432

T5

1712

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9296231

1

T1

14

T2

149947

T4

3701

auto[1]

104532

1

T1

2

T14

2562

T16

2

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

194867

1

T1

1

T2

473

T4

37

auto[0]

auto[0]

auto[0]

auto[1]

207147

1

T1

1

T2

425

T4

15

auto[0]

auto[0]

auto[1]

auto[0]

1159082

1

T1

4

T2

4904

T4

52

auto[0]

auto[0]

auto[1]

auto[1]

223708

1

T1

2

T2

285

T5

197

auto[0]

auto[1]

auto[0]

auto[0]

412227

1

T1

1

T2

480

T4

22

auto[0]

auto[1]

auto[0]

auto[1]

395290

1

T2

502

T4

47

T5

268

auto[0]

auto[1]

auto[1]

auto[0]

375009

1

T1

3

T2

417

T4

5

auto[0]

auto[1]

auto[1]

auto[1]

424833

1

T1

4

T2

643

T4

91

auto[1]

auto[0]

auto[0]

auto[0]

216570

1

T2

4739

T4

473

T5

295

auto[1]

auto[0]

auto[0]

auto[1]

240574

1

T2

4119

T4

243

T5

262

auto[1]

auto[0]

auto[1]

auto[0]

3773678

1

T2

110613

T4

591

T14

55746

auto[1]

auto[0]

auto[1]

auto[1]

225337

1

T2

2830

T5

145

T14

3053

auto[1]

auto[1]

auto[0]

auto[0]

372778

1

T2

4805

T4

283

T5

635

auto[1]

auto[1]

auto[0]

auto[1]

394569

1

T2

4487

T4

592

T5

129

auto[1]

auto[1]

auto[1]

auto[0]

403807

1

T2

3788

T4

45

T5

129

auto[1]

auto[1]

auto[1]

auto[1]

381287

1

T2

6437

T4

1205

T5

117

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

400909

1

T1

1

T2

5212

T4

510

auto[0]

auto[0]

auto[0]

auto[1]

436034

1

T1

1

T2

4544

T4

258

auto[0]

auto[0]

auto[1]

auto[0]

4920978

1

T1

3

T2

115517

T4

643

auto[0]

auto[0]

auto[1]

auto[1]

434980

1

T1

2

T2

3115

T5

342

auto[0]

auto[1]

auto[0]

auto[0]

767117

1

T1

1

T2

5285

T4

305

auto[0]

auto[1]

auto[0]

auto[1]

779609

1

T2

4989

T4

639

T5

397

auto[0]

auto[1]

auto[1]

auto[0]

766519

1

T1

2

T2

4205

T4

50

auto[0]

auto[1]

auto[1]

auto[1]

790085

1

T1

4

T2

7080

T4

1296

auto[1]

auto[0]

auto[0]

auto[0]

10528

1

T14

154

T16

1

T20

52

auto[1]

auto[0]

auto[0]

auto[1]

11687

1

T14

147

T20

53

T73

7

auto[1]

auto[0]

auto[1]

auto[0]

11782

1

T1

1

T14

858

T20

16

auto[1]

auto[0]

auto[1]

auto[1]

14065

1

T14

6

T20

34

T73

7

auto[1]

auto[1]

auto[0]

auto[0]

17888

1

T14

266

T20

430

T73

453

auto[1]

auto[1]

auto[0]

auto[1]

10250

1

T14

416

T20

33

T73

11

auto[1]

auto[1]

auto[1]

auto[0]

12297

1

T1

1

T14

599

T16

1

auto[1]

auto[1]

auto[1]

auto[1]

16035

1

T14

116

T20

244

T73

1743

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	227098	1			T2	4739		T4	473		T5	295
fifo_depth[0]	auto[0]	auto[0]	auto[1]	252261	1			T2	4119		T4	243		T5	262
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3785460	1			T1	1		T2	110613		T4	591
fifo_depth[0]	auto[0]	auto[1]	auto[1]	239402	1			T2	2830		T5	145		T14	3059
fifo_depth[0]	auto[1]	auto[0]	auto[0]	390666	1			T2	4805		T4	283		T5	635
fifo_depth[0]	auto[1]	auto[0]	auto[1]	404819	1			T2	4487		T4	592		T5	129
fifo_depth[0]	auto[1]	auto[1]	auto[0]	416104	1			T1	1		T2	3788		T4	45
fifo_depth[0]	auto[1]	auto[1]	auto[1]	397322	1			T2	6437		T4	1205		T5	117
fifo_depth[1]	auto[0]	auto[0]	auto[0]	16570	1			T2	280		T4	24		T5	55
fifo_depth[1]	auto[0]	auto[0]	auto[1]	19041	1			T2	232		T4	9		T5	49
fifo_depth[1]	auto[0]	auto[1]	auto[0]	245252	1			T2	3434		T4	35		T14	5423
fifo_depth[1]	auto[0]	auto[1]	auto[1]	17920	1			T2	162		T5	23		T14	521
fifo_depth[1]	auto[1]	auto[0]	auto[0]	40409	1			T2	283		T4	12		T5	142
fifo_depth[1]	auto[1]	auto[0]	auto[1]	43571	1			T2	264		T4	31		T5	35
fifo_depth[1]	auto[1]	auto[1]	auto[0]	41645	1			T2	229		T4	4		T5	29
fifo_depth[1]	auto[1]	auto[1]	auto[1]	42758	1			T2	348		T4	61		T5	34
fifo_depth[2]	auto[0]	auto[0]	auto[0]	13568	1			T2	127		T4	10		T5	45
fifo_depth[2]	auto[0]	auto[0]	auto[1]	15789	1			T2	131		T4	5		T5	48
fifo_depth[2]	auto[0]	auto[1]	auto[0]	195923	1			T2	1042		T4	12		T14	5125
fifo_depth[2]	auto[0]	auto[1]	auto[1]	15070	1			T2	79		T5	21		T14	538
fifo_depth[2]	auto[1]	auto[0]	auto[0]	36136	1			T2	132		T4	7		T5	125
fifo_depth[2]	auto[1]	auto[0]	auto[1]	39515	1			T2	157		T4	10		T5	29
fifo_depth[2]	auto[1]	auto[1]	auto[0]	37205	1			T2	109		T5	24		T14	392
fifo_depth[2]	auto[1]	auto[1]	auto[1]	38362	1			T2	180		T4	23		T5	33
fifo_depth[3]	auto[0]	auto[0]	auto[0]	10495	1			T2	45		T4	3		T5	50
fifo_depth[3]	auto[0]	auto[0]	auto[1]	12362	1			T2	46		T4	1		T5	43
fifo_depth[3]	auto[0]	auto[1]	auto[0]	150026	1			T2	328		T4	1		T14	4210
fifo_depth[3]	auto[0]	auto[1]	auto[1]	12063	1			T2	27		T5	24		T14	511
fifo_depth[3]	auto[1]	auto[0]	auto[0]	31648	1			T2	47		T4	3		T5	142
fifo_depth[3]	auto[1]	auto[0]	auto[1]	34961	1			T2	64		T4	5		T5	28
fifo_depth[3]	auto[1]	auto[1]	auto[0]	31920	1			T2	53		T4	1		T5	33
fifo_depth[3]	auto[1]	auto[1]	auto[1]	33614	1			T2	79		T4	4		T5	29
fifo_depth[4]	auto[0]	auto[0]	auto[0]	9949	1			T2	14		T5	54		T14	568
fifo_depth[4]	auto[0]	auto[0]	auto[1]	11631	1			T2	13		T5	50		T14	378
fifo_depth[4]	auto[0]	auto[1]	auto[0]	109749	1			T2	80		T4	4		T14	2879
fifo_depth[4]	auto[0]	auto[1]	auto[1]	11340	1			T2	15		T5	29		T14	538
fifo_depth[4]	auto[1]	auto[0]	auto[0]	29776	1			T2	15		T5	114		T14	753
fifo_depth[4]	auto[1]	auto[0]	auto[1]	33075	1			T2	16		T5	28		T14	468
fifo_depth[4]	auto[1]	auto[1]	auto[0]	30437	1			T2	19		T5	28		T14	427
fifo_depth[4]	auto[1]	auto[1]	auto[1]	31714	1			T2	26		T4	3		T5	23
fifo_depth[5]	auto[0]	auto[0]	auto[0]	8494	1			T2	5		T5	41		T14	596
fifo_depth[5]	auto[0]	auto[0]	auto[1]	9983	1			T2	2		T5	48		T14	428
fifo_depth[5]	auto[0]	auto[1]	auto[0]	88984	1			T2	18		T14	2218		T25	2
fifo_depth[5]	auto[0]	auto[1]	auto[1]	10016	1			T2	2		T5	19		T14	587
fifo_depth[5]	auto[1]	auto[0]	auto[0]	28226	1			T2	3		T5	126		T14	781
fifo_depth[5]	auto[1]	auto[0]	auto[1]	31273	1			T4	1		T5	25		T14	480
fifo_depth[5]	auto[1]	auto[1]	auto[0]	27949	1			T2	5		T5	37		T14	437
fifo_depth[5]	auto[1]	auto[1]	auto[1]	29972	1			T2	5		T5	40		T14	733
fifo_depth[6]	auto[0]	auto[0]	auto[0]	8619	1			T2	1		T5	49		T14	538
fifo_depth[6]	auto[0]	auto[0]	auto[1]	10334	1			T2	1		T5	51		T14	427
fifo_depth[6]	auto[0]	auto[1]	auto[0]	77628	1			T2	2		T14	1904		T25	1
fifo_depth[6]	auto[0]	auto[1]	auto[1]	9509	1			T5	26		T14	551		T111	8
fifo_depth[6]	auto[1]	auto[0]	auto[0]	27590	1			T5	110		T14	728		T39	36
fifo_depth[6]	auto[1]	auto[0]	auto[1]	30516	1			T5	25		T14	488		T38	2
fifo_depth[6]	auto[1]	auto[1]	auto[0]	28078	1			T2	2		T5	24		T14	369
fifo_depth[6]	auto[1]	auto[1]	auto[1]	29489	1			T2	2		T5	31		T14	811
fifo_depth[7]	auto[0]	auto[0]	auto[0]	7724	1			T2	1		T5	37		T14	536
fifo_depth[7]	auto[0]	auto[0]	auto[1]	8837	1			T5	46		T14	391		T95	92
fifo_depth[7]	auto[0]	auto[1]	auto[0]	62240	1			T14	1550		T15	1101		T20	40
fifo_depth[7]	auto[0]	auto[1]	auto[1]	8923	1			T5	22		T14	553		T111	7
fifo_depth[7]	auto[1]	auto[0]	auto[0]	25548	1			T5	120		T14	679		T12	1
fifo_depth[7]	auto[1]	auto[0]	auto[1]	27895	1			T5	22		T14	450		T38	2
fifo_depth[7]	auto[1]	auto[1]	auto[0]	25346	1			T5	26		T14	356		T38	1
fifo_depth[7]	auto[1]	auto[1]	auto[1]	27004	1			T2	3		T5	29		T14	659
fifo_depth[8]	auto[0]	auto[0]	auto[0]	9083	1			T5	44		T14	447		T20	148
fifo_depth[8]	auto[0]	auto[0]	auto[1]	9601	1			T5	45		T14	351		T20	2
fifo_depth[8]	auto[0]	auto[1]	auto[0]	48749	1			T14	1198		T15	925		T20	38
fifo_depth[8]	auto[0]	auto[1]	auto[1]	9773	1			T5	15		T14	428		T111	5
fifo_depth[8]	auto[1]	auto[0]	auto[0]	23587	1			T5	85		T14	613		T39	29
fifo_depth[8]	auto[1]	auto[0]	auto[1]	25068	1			T2	1		T5	27		T14	358
fifo_depth[8]	auto[1]	auto[1]	auto[0]	23399	1			T5	16		T14	503		T38	1
fifo_depth[8]	auto[1]	auto[1]	auto[1]	24108	1			T5	20		T14	627		T39	218
fifo_depth[9]	auto[0]	auto[0]	auto[0]	5038	1			T5	26		T14	320		T20	53
fifo_depth[9]	auto[0]	auto[0]	auto[1]	5997	1			T5	32		T14	279		T95	84
fifo_depth[9]	auto[0]	auto[1]	auto[0]	32529	1			T14	797		T15	622		T20	11
fifo_depth[9]	auto[0]	auto[1]	auto[1]	6031	1			T5	10		T14	325		T111	1
fifo_depth[9]	auto[1]	auto[0]	auto[0]	16758	1			T5	64		T14	483		T39	25
fifo_depth[9]	auto[1]	auto[0]	auto[1]	17867	1			T5	13		T14	267		T38	1
fifo_depth[9]	auto[1]	auto[1]	auto[0]	16675	1			T5	19		T14	235		T38	2
fifo_depth[9]	auto[1]	auto[1]	auto[1]	17706	1			T5	13		T14	505		T39	158
fifo_depth[10]	auto[0]	auto[0]	auto[0]	5085	1			T5	13		T14	281		T20	135
fifo_depth[10]	auto[0]	auto[0]	auto[1]	5324	1			T5	12		T14	147		T20	1
fifo_depth[10]	auto[0]	auto[1]	auto[0]	22655	1			T14	503		T15	425		T20	56
fifo_depth[10]	auto[0]	auto[1]	auto[1]	5059	1			T5	6		T14	221		T111	1
fifo_depth[10]	auto[1]	auto[0]	auto[0]	12531	1			T5	46		T14	394		T39	10
fifo_depth[10]	auto[1]	auto[0]	auto[1]	12917	1			T5	18		T14	178		T38	1
fifo_depth[10]	auto[1]	auto[1]	auto[0]	12805	1			T5	8		T14	160		T39	64
fifo_depth[10]	auto[1]	auto[1]	auto[1]	12916	1			T5	25		T14	349		T39	113
fifo_depth[11]	auto[0]	auto[0]	auto[0]	2886	1			T5	5		T14	191		T20	51
fifo_depth[11]	auto[0]	auto[0]	auto[1]	3488	1			T5	7		T14	106		T20	7
fifo_depth[11]	auto[0]	auto[1]	auto[0]	13028	1			T14	334		T15	257		T20	43
fifo_depth[11]	auto[0]	auto[1]	auto[1]	3309	1			T5	2		T14	170		T111	3
fifo_depth[11]	auto[1]	auto[0]	auto[0]	8408	1			T5	26		T14	296		T39	9
fifo_depth[11]	auto[1]	auto[0]	auto[1]	7809	1			T5	7		T14	106		T39	36
fifo_depth[11]	auto[1]	auto[1]	auto[0]	7711	1			T5	5		T14	129		T39	58
fifo_depth[11]	auto[1]	auto[1]	auto[1]	7810	1			T5	6		T14	245		T39	64
fifo_depth[12]	auto[0]	auto[0]	auto[0]	5693	1			T5	7		T14	144		T20	147
fifo_depth[12]	auto[0]	auto[0]	auto[1]	5272	1			T5	2		T14	129		T20	19
fifo_depth[12]	auto[0]	auto[1]	auto[0]	10419	1			T14	138		T15	114		T20	119
fifo_depth[12]	auto[0]	auto[1]	auto[1]	5360	1			T14	124		T111	2		T20	84
fifo_depth[12]	auto[1]	auto[0]	auto[0]	8794	1			T5	12		T14	227		T39	1
fifo_depth[12]	auto[1]	auto[0]	auto[1]	7100	1			T5	7		T14	79		T38	1
fifo_depth[12]	auto[1]	auto[1]	auto[0]	7482	1			T5	3		T14	259		T39	23
fifo_depth[12]	auto[1]	auto[1]	auto[1]	6804	1			T5	3		T14	301		T39	29
fifo_depth[13]	auto[0]	auto[0]	auto[0]	2063	1			T5	1		T14	134		T20	51
fifo_depth[13]	auto[0]	auto[0]	auto[1]	2541	1			T5	3		T14	98		T20	13
fifo_depth[13]	auto[0]	auto[1]	auto[0]	4731	1			T14	104		T15	59		T20	34
fifo_depth[13]	auto[0]	auto[1]	auto[1]	2224	1			T14	116		T20	118		T95	6
fifo_depth[13]	auto[1]	auto[0]	auto[0]	4126	1			T5	7		T14	172		T39	3
fifo_depth[13]	auto[1]	auto[0]	auto[1]	3139	1			T5	1		T14	43		T39	9
fifo_depth[13]	auto[1]	auto[1]	auto[0]	3744	1			T5	2		T14	57		T39	8
fifo_depth[13]	auto[1]	auto[1]	auto[1]	3756	1			T5	3		T14	244		T39	17
fifo_depth[14]	auto[0]	auto[0]	auto[0]	4451	1			T14	135		T20	147		T73	44
fifo_depth[14]	auto[0]	auto[0]	auto[1]	3566	1			T14	120		T20	15		T95	3
fifo_depth[14]	auto[0]	auto[1]	auto[0]	5806	1			T14	69		T15	19		T20	149
fifo_depth[14]	auto[0]	auto[1]	auto[1]	3739	1			T14	48		T20	120		T95	1
fifo_depth[14]	auto[1]	auto[0]	auto[0]	6087	1			T5	1		T14	252		T39	1
fifo_depth[14]	auto[1]	auto[0]	auto[1]	3246	1			T5	2		T14	36		T39	5
fifo_depth[14]	auto[1]	auto[1]	auto[0]	4776	1			T5	1		T14	36		T39	5
fifo_depth[14]	auto[1]	auto[1]	auto[1]	4210	1			T5	2		T14	353		T39	4
fifo_depth[15]	auto[0]	auto[0]	auto[0]	2310	1			T14	145		T20	37		T73	78
fifo_depth[15]	auto[0]	auto[0]	auto[1]	2314	1			T14	84		T20	13		T95	1
fifo_depth[15]	auto[0]	auto[1]	auto[0]	2788	1			T14	73		T15	8		T20	15
fifo_depth[15]	auto[0]	auto[1]	auto[1]	2153	1			T14	64		T20	115		T73	46
fifo_depth[15]	auto[1]	auto[0]	auto[0]	3523	1			T5	1		T14	217		T20	45
fifo_depth[15]	auto[1]	auto[0]	auto[1]	2116	1			T5	1		T14	22		T39	2
fifo_depth[15]	auto[1]	auto[1]	auto[0]	2639	1			T14	37		T39	2		T20	1
fifo_depth[15]	auto[1]	auto[1]	auto[1]	2791	1			T5	2		T14	275		T39	5
fifo_depth[16]	auto[0]	auto[0]	auto[0]	9880	1			T14	764		T20	114		T73	45
fifo_depth[16]	auto[0]	auto[0]	auto[1]	6773	1			T14	89		T20	183		T6	233
fifo_depth[16]	auto[0]	auto[1]	auto[0]	11709	1			T14	721		T15	5		T20	95
fifo_depth[16]	auto[0]	auto[1]	auto[1]	8171	1			T14	458		T20	98		T73	79
fifo_depth[16]	auto[1]	auto[0]	auto[0]	11760	1			T5	2		T14	204		T20	79
fifo_depth[16]	auto[1]	auto[0]	auto[1]	9012	1			T14	286		T39	1		T95	1
fifo_depth[16]	auto[1]	auto[1]	auto[0]	8906	1			T14	451		T73	89		T6	177
fifo_depth[16]	auto[1]	auto[1]	auto[1]	16240	1			T5	1		T14	339		T39	1