Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	14542963	1			T1	492		T2	260174		T4	3733
all_pins[1]	14542963	1			T1	492		T2	260174		T4	3733
all_pins[2]	14542963	1			T1	492		T2	260174		T4	3733

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	41273664	1			T1	1452		T2	752287		T4	11181
values[0x1]	2355225	1			T1	24		T2	28235		T4	18
transitions[0x0=>0x1]	2355087	1			T1	24		T2	28235		T4	18
transitions[0x1=>0x0]	2355109	1			T1	24		T2	28235		T4	18

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	14493048	1			T1	468		T2	259406		T4	3715
all_pins[0]	values[0x1]	49915	1			T1	24		T2	768		T4	18
all_pins[0]	transitions[0x0=>0x1]	49860	1			T1	24		T2	768		T4	18
all_pins[0]	transitions[0x1=>0x0]	2304708	1			T2	27467		T14	33295		T15	8562
all_pins[1]	values[0x0]	14542394	1			T1	492		T2	260174		T4	3733
all_pins[1]	values[0x1]	569	1			T14	2		T20	3		T13	1
all_pins[1]	transitions[0x0=>0x1]	533	1			T14	2		T20	3		T13	1
all_pins[1]	transitions[0x1=>0x0]	49879	1			T1	24		T2	768		T4	18
all_pins[2]	values[0x0]	12238222	1			T1	492		T2	232707		T4	3733
all_pins[2]	values[0x1]	2304741	1			T2	27467		T14	33295		T15	8562
all_pins[2]	transitions[0x0=>0x1]	2304694	1			T2	27467		T14	33295		T15	8562
all_pins[2]	transitions[0x1=>0x0]	522	1			T14	2		T20	3		T13	1