Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 975 1 T2 4 T13 7 T45 27
all_values[1] 975 1 T2 4 T13 7 T45 27
all_values[2] 975 1 T2 4 T13 7 T45 27


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1497 1 T2 11 T13 11 T45 36
auto[1] 1428 1 T2 1 T13 10 T45 45


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1067 1 T2 5 T13 14 T45 26
auto[1] 1858 1 T2 7 T13 7 T45 55


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1699 1 T2 6 T13 17 T45 50
auto[1] 1226 1 T2 6 T13 4 T45 31


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 193 1 T2 2 T13 2 T45 6
all_values[0] auto[0] auto[0] auto[1] 101 1 T45 3 T6 1 T7 1
all_values[0] auto[0] auto[1] auto[0] 197 1 T13 3 T45 10 T6 5
all_values[0] auto[0] auto[1] auto[1] 90 1 T13 1 T45 1 T6 3
all_values[0] auto[1] auto[0] auto[1] 181 1 T2 2 T45 2 T6 2
all_values[0] auto[1] auto[1] auto[1] 213 1 T13 1 T45 5 T6 3
all_values[1] auto[0] auto[0] auto[0] 182 1 T2 1 T13 2 T45 4
all_values[1] auto[0] auto[0] auto[1] 123 1 T2 1 T13 1 T45 4
all_values[1] auto[0] auto[1] auto[0] 144 1 T13 1 T6 5 T7 1
all_values[1] auto[0] auto[1] auto[1] 121 1 T13 1 T45 6 T6 1
all_values[1] auto[1] auto[0] auto[1] 219 1 T2 2 T13 1 T45 4
all_values[1] auto[1] auto[1] auto[1] 186 1 T13 1 T45 9 T6 5
all_values[2] auto[0] auto[0] auto[0] 181 1 T2 1 T13 4 T45 2
all_values[2] auto[0] auto[0] auto[1] 99 1 T45 6 T6 1 T7 1
all_values[2] auto[0] auto[1] auto[0] 170 1 T2 1 T13 2 T45 4
all_values[2] auto[0] auto[1] auto[1] 98 1 T45 4 T6 1 T65 2
all_values[2] auto[1] auto[0] auto[1] 218 1 T2 2 T13 1 T45 5
all_values[2] auto[1] auto[1] auto[1] 209 1 T45 6 T6 7 T7 5


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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