Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.93 92.46 85.23 100.00 76.32 85.93 99.49 69.08


Total test records in report: 739
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html
T543 /workspace/coverage/default/7.hmac_smoke.3476948843 Apr 04 12:31:12 PM PDT 24 Apr 04 12:31:17 PM PDT 24 481449625 ps
T544 /workspace/coverage/default/49.hmac_long_msg.2384783971 Apr 04 12:31:33 PM PDT 24 Apr 04 12:32:55 PM PDT 24 2627409229 ps
T545 /workspace/coverage/default/0.hmac_test_hmac_vectors.2610430043 Apr 04 12:28:34 PM PDT 24 Apr 04 12:28:35 PM PDT 24 58495283 ps
T546 /workspace/coverage/default/43.hmac_long_msg.3378939572 Apr 04 12:32:12 PM PDT 24 Apr 04 12:33:19 PM PDT 24 3235884696 ps
T547 /workspace/coverage/default/34.hmac_datapath_stress.827336222 Apr 04 12:31:13 PM PDT 24 Apr 04 12:31:22 PM PDT 24 674867810 ps
T548 /workspace/coverage/default/14.hmac_datapath_stress.911547721 Apr 04 12:30:45 PM PDT 24 Apr 04 12:32:50 PM PDT 24 8009275151 ps
T549 /workspace/coverage/default/4.hmac_test_sha_vectors.2485418897 Apr 04 12:28:36 PM PDT 24 Apr 04 12:36:50 PM PDT 24 99279006656 ps
T550 /workspace/coverage/default/48.hmac_test_hmac_vectors.2652439589 Apr 04 12:31:41 PM PDT 24 Apr 04 12:31:42 PM PDT 24 168865782 ps
T551 /workspace/coverage/default/49.hmac_alert_test.1279810372 Apr 04 12:32:00 PM PDT 24 Apr 04 12:32:01 PM PDT 24 14412899 ps
T552 /workspace/coverage/default/22.hmac_wipe_secret.1229877412 Apr 04 12:30:46 PM PDT 24 Apr 04 12:32:07 PM PDT 24 43668946878 ps
T553 /workspace/coverage/default/17.hmac_test_hmac_vectors.1269929307 Apr 04 12:31:03 PM PDT 24 Apr 04 12:31:04 PM PDT 24 55458652 ps
T554 /workspace/coverage/default/10.hmac_stress_all.1032316130 Apr 04 12:30:31 PM PDT 24 Apr 04 12:53:51 PM PDT 24 104180168174 ps
T555 /workspace/coverage/default/18.hmac_long_msg.1194214386 Apr 04 12:30:56 PM PDT 24 Apr 04 12:33:16 PM PDT 24 25178055418 ps
T75 /workspace/coverage/default/132.hmac_stress_all_with_rand_reset.4122302136 Apr 04 12:33:28 PM PDT 24 Apr 04 12:53:54 PM PDT 24 508222731818 ps
T76 /workspace/coverage/default/29.hmac_error.1700804825 Apr 04 12:32:37 PM PDT 24 Apr 04 12:35:29 PM PDT 24 13958350502 ps
T77 /workspace/coverage/default/6.hmac_error.3206322586 Apr 04 12:30:18 PM PDT 24 Apr 04 12:32:58 PM PDT 24 19453865361 ps
T78 /workspace/coverage/default/32.hmac_smoke.284748195 Apr 04 12:32:38 PM PDT 24 Apr 04 12:32:40 PM PDT 24 108635064 ps
T31 /workspace/coverage/default/2.hmac_sec_cm.887777427 Apr 04 12:28:54 PM PDT 24 Apr 04 12:28:55 PM PDT 24 465487008 ps
T79 /workspace/coverage/default/45.hmac_error.1743714779 Apr 04 12:31:24 PM PDT 24 Apr 04 12:34:29 PM PDT 24 10632844628 ps
T80 /workspace/coverage/default/28.hmac_datapath_stress.2568440007 Apr 04 12:31:24 PM PDT 24 Apr 04 12:32:37 PM PDT 24 2389208832 ps
T81 /workspace/coverage/default/23.hmac_datapath_stress.3981601260 Apr 04 12:31:01 PM PDT 24 Apr 04 12:31:30 PM PDT 24 1615873049 ps
T82 /workspace/coverage/default/16.hmac_test_hmac_vectors.2754963001 Apr 04 12:30:53 PM PDT 24 Apr 04 12:30:54 PM PDT 24 34160798 ps
T83 /workspace/coverage/default/21.hmac_test_sha_vectors.4067634215 Apr 04 12:30:38 PM PDT 24 Apr 04 12:39:34 PM PDT 24 331691353629 ps
T556 /workspace/coverage/default/13.hmac_test_hmac_vectors.4145741209 Apr 04 12:30:37 PM PDT 24 Apr 04 12:30:38 PM PDT 24 67267384 ps
T557 /workspace/coverage/default/4.hmac_test_hmac_vectors.3541275562 Apr 04 12:28:35 PM PDT 24 Apr 04 12:28:36 PM PDT 24 43577011 ps
T558 /workspace/coverage/default/48.hmac_long_msg.2811271614 Apr 04 12:31:34 PM PDT 24 Apr 04 12:31:53 PM PDT 24 725903506 ps
T559 /workspace/coverage/default/30.hmac_test_sha_vectors.1059886742 Apr 04 12:31:08 PM PDT 24 Apr 04 12:38:29 PM PDT 24 8273070444 ps
T560 /workspace/coverage/default/48.hmac_wipe_secret.4032203077 Apr 04 12:31:34 PM PDT 24 Apr 04 12:31:46 PM PDT 24 2357039205 ps
T561 /workspace/coverage/default/35.hmac_stress_all.4008034603 Apr 04 12:31:19 PM PDT 24 Apr 04 01:09:06 PM PDT 24 40407420760 ps
T562 /workspace/coverage/default/37.hmac_back_pressure.647819436 Apr 04 12:31:21 PM PDT 24 Apr 04 12:31:50 PM PDT 24 830317712 ps
T563 /workspace/coverage/default/3.hmac_back_pressure.2291488479 Apr 04 12:28:54 PM PDT 24 Apr 04 12:29:03 PM PDT 24 468435351 ps
T564 /workspace/coverage/default/2.hmac_error.1218622561 Apr 04 12:28:55 PM PDT 24 Apr 04 12:29:51 PM PDT 24 3904232373 ps
T565 /workspace/coverage/default/21.hmac_smoke.310512801 Apr 04 12:30:46 PM PDT 24 Apr 04 12:30:50 PM PDT 24 1803632821 ps
T566 /workspace/coverage/default/15.hmac_alert_test.3844918218 Apr 04 12:30:51 PM PDT 24 Apr 04 12:30:51 PM PDT 24 38329046 ps
T567 /workspace/coverage/default/33.hmac_wipe_secret.330978347 Apr 04 12:31:39 PM PDT 24 Apr 04 12:32:49 PM PDT 24 4541582059 ps
T568 /workspace/coverage/default/42.hmac_datapath_stress.3092382169 Apr 04 12:31:24 PM PDT 24 Apr 04 12:31:43 PM PDT 24 375842786 ps
T569 /workspace/coverage/default/0.hmac_long_msg.1716646908 Apr 04 12:29:21 PM PDT 24 Apr 04 12:30:33 PM PDT 24 1274781582 ps
T570 /workspace/coverage/default/30.hmac_alert_test.82141910 Apr 04 12:31:21 PM PDT 24 Apr 04 12:31:21 PM PDT 24 59612835 ps
T571 /workspace/coverage/default/2.hmac_long_msg.1388071754 Apr 04 12:28:52 PM PDT 24 Apr 04 12:30:37 PM PDT 24 1845959301 ps
T572 /workspace/coverage/default/45.hmac_smoke.3168680973 Apr 04 12:33:14 PM PDT 24 Apr 04 12:33:20 PM PDT 24 655868616 ps
T573 /workspace/coverage/default/9.hmac_stress_all.909370986 Apr 04 12:30:54 PM PDT 24 Apr 04 12:41:46 PM PDT 24 100620540123 ps
T574 /workspace/coverage/default/41.hmac_alert_test.145096508 Apr 04 12:31:22 PM PDT 24 Apr 04 12:31:23 PM PDT 24 16530456 ps
T575 /workspace/coverage/default/14.hmac_test_hmac_vectors.3056943875 Apr 04 12:31:29 PM PDT 24 Apr 04 12:31:30 PM PDT 24 97747455 ps
T576 /workspace/coverage/default/49.hmac_error.1744037340 Apr 04 12:31:56 PM PDT 24 Apr 04 12:33:18 PM PDT 24 30964641874 ps
T577 /workspace/coverage/default/13.hmac_test_sha_vectors.3179398259 Apr 04 12:30:56 PM PDT 24 Apr 04 12:38:05 PM PDT 24 34785231142 ps
T578 /workspace/coverage/default/49.hmac_test_hmac_vectors.3809084857 Apr 04 12:31:58 PM PDT 24 Apr 04 12:32:00 PM PDT 24 161620410 ps
T579 /workspace/coverage/default/32.hmac_datapath_stress.4279337157 Apr 04 12:31:44 PM PDT 24 Apr 04 12:34:09 PM PDT 24 2520107062 ps
T580 /workspace/coverage/default/29.hmac_datapath_stress.3502051492 Apr 04 12:32:08 PM PDT 24 Apr 04 12:34:17 PM PDT 24 2118906138 ps
T581 /workspace/coverage/default/40.hmac_back_pressure.2621930617 Apr 04 12:31:20 PM PDT 24 Apr 04 12:31:24 PM PDT 24 393701829 ps
T582 /workspace/coverage/default/34.hmac_back_pressure.1904034223 Apr 04 12:31:59 PM PDT 24 Apr 04 12:32:04 PM PDT 24 508283787 ps
T583 /workspace/coverage/default/39.hmac_test_sha_vectors.2082937896 Apr 04 12:31:21 PM PDT 24 Apr 04 12:38:45 PM PDT 24 31344322694 ps
T584 /workspace/coverage/default/3.hmac_stress_all.3947261593 Apr 04 12:28:21 PM PDT 24 Apr 04 12:48:02 PM PDT 24 22749955860 ps
T585 /workspace/coverage/default/13.hmac_long_msg.672346339 Apr 04 12:30:46 PM PDT 24 Apr 04 12:31:16 PM PDT 24 8950647115 ps
T586 /workspace/coverage/default/42.hmac_back_pressure.2846114611 Apr 04 12:33:53 PM PDT 24 Apr 04 12:34:46 PM PDT 24 1733169343 ps
T587 /workspace/coverage/default/0.hmac_alert_test.1320268870 Apr 04 12:28:38 PM PDT 24 Apr 04 12:28:39 PM PDT 24 11322586 ps
T588 /workspace/coverage/default/39.hmac_wipe_secret.3101896330 Apr 04 12:31:13 PM PDT 24 Apr 04 12:32:11 PM PDT 24 5955104772 ps
T589 /workspace/coverage/default/25.hmac_stress_all.3589556698 Apr 04 12:31:15 PM PDT 24 Apr 04 12:33:48 PM PDT 24 7418506961 ps
T590 /workspace/coverage/default/6.hmac_alert_test.3043675707 Apr 04 12:31:01 PM PDT 24 Apr 04 12:31:02 PM PDT 24 34580793 ps
T591 /workspace/coverage/default/17.hmac_back_pressure.3609179528 Apr 04 12:30:42 PM PDT 24 Apr 04 12:30:48 PM PDT 24 1058266646 ps
T592 /workspace/coverage/default/41.hmac_long_msg.344521674 Apr 04 12:32:42 PM PDT 24 Apr 04 12:34:23 PM PDT 24 23899579015 ps
T593 /workspace/coverage/default/45.hmac_datapath_stress.1469853355 Apr 04 12:33:13 PM PDT 24 Apr 04 12:33:36 PM PDT 24 789020094 ps
T594 /workspace/coverage/default/46.hmac_back_pressure.3435039111 Apr 04 12:32:42 PM PDT 24 Apr 04 12:32:48 PM PDT 24 578231531 ps
T595 /workspace/coverage/default/10.hmac_wipe_secret.3678220839 Apr 04 12:30:41 PM PDT 24 Apr 04 12:31:32 PM PDT 24 15451956087 ps
T596 /workspace/coverage/default/16.hmac_burst_wr.1135770800 Apr 04 12:30:40 PM PDT 24 Apr 04 12:30:51 PM PDT 24 778395305 ps
T597 /workspace/coverage/default/13.hmac_datapath_stress.1919804585 Apr 04 12:30:29 PM PDT 24 Apr 04 12:32:36 PM PDT 24 2153979062 ps
T598 /workspace/coverage/default/18.hmac_datapath_stress.30205961 Apr 04 12:30:53 PM PDT 24 Apr 04 12:31:38 PM PDT 24 5339642039 ps
T599 /workspace/coverage/default/12.hmac_stress_all.3316987396 Apr 04 12:30:38 PM PDT 24 Apr 04 12:30:40 PM PDT 24 562100838 ps
T600 /workspace/coverage/default/27.hmac_stress_all_with_rand_reset.3529394992 Apr 04 12:31:14 PM PDT 24 Apr 04 12:36:06 PM PDT 24 8950129695 ps
T601 /workspace/coverage/default/7.hmac_back_pressure.1868872623 Apr 04 12:31:18 PM PDT 24 Apr 04 12:32:27 PM PDT 24 3466250137 ps
T602 /workspace/coverage/default/73.hmac_stress_all_with_rand_reset.1709818638 Apr 04 12:32:51 PM PDT 24 Apr 04 12:41:25 PM PDT 24 10009142635 ps
T603 /workspace/coverage/default/31.hmac_wipe_secret.1987480934 Apr 04 12:31:20 PM PDT 24 Apr 04 12:31:24 PM PDT 24 195150257 ps
T604 /workspace/coverage/default/12.hmac_back_pressure.1117586999 Apr 04 12:30:37 PM PDT 24 Apr 04 12:31:22 PM PDT 24 2259643056 ps
T605 /workspace/coverage/default/44.hmac_test_hmac_vectors.282743987 Apr 04 12:31:27 PM PDT 24 Apr 04 12:31:28 PM PDT 24 118589224 ps
T606 /workspace/coverage/default/48.hmac_smoke.16817424 Apr 04 12:31:53 PM PDT 24 Apr 04 12:31:56 PM PDT 24 58907839 ps
T607 /workspace/coverage/cover_reg_top/38.hmac_intr_test.524386995 Apr 04 03:09:30 PM PDT 24 Apr 04 03:09:31 PM PDT 24 30585991 ps
T53 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.227162116 Apr 04 03:08:55 PM PDT 24 Apr 04 03:09:01 PM PDT 24 307217500 ps
T54 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2285783786 Apr 04 03:09:14 PM PDT 24 Apr 04 03:09:15 PM PDT 24 72959437 ps
T55 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.843751311 Apr 04 03:08:57 PM PDT 24 Apr 04 03:08:58 PM PDT 24 42794287 ps
T608 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2685776391 Apr 04 03:09:13 PM PDT 24 Apr 04 03:09:17 PM PDT 24 371870646 ps
T609 /workspace/coverage/cover_reg_top/9.hmac_intr_test.3328376965 Apr 04 03:09:10 PM PDT 24 Apr 04 03:09:11 PM PDT 24 23078453 ps
T50 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.4046202977 Apr 04 03:09:15 PM PDT 24 Apr 04 03:09:18 PM PDT 24 350472705 ps
T610 /workspace/coverage/cover_reg_top/24.hmac_intr_test.2606420982 Apr 04 03:09:28 PM PDT 24 Apr 04 03:09:29 PM PDT 24 81046947 ps
T611 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2465695877 Apr 04 03:09:28 PM PDT 24 Apr 04 03:09:29 PM PDT 24 16149282 ps
T84 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2383080312 Apr 04 03:08:55 PM PDT 24 Apr 04 03:09:09 PM PDT 24 323995221 ps
T612 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2317812062 Apr 04 03:08:57 PM PDT 24 Apr 04 03:08:57 PM PDT 24 21940207 ps
T613 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3431181775 Apr 04 03:09:09 PM PDT 24 Apr 04 03:09:11 PM PDT 24 38775660 ps
T614 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.4043437555 Apr 04 03:08:58 PM PDT 24 Apr 04 03:09:00 PM PDT 24 33460800 ps
T51 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2047009752 Apr 04 03:09:06 PM PDT 24 Apr 04 03:09:08 PM PDT 24 349235457 ps
T615 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3379212031 Apr 04 03:08:59 PM PDT 24 Apr 04 03:09:02 PM PDT 24 321237293 ps
T71 /workspace/coverage/cover_reg_top/46.hmac_intr_test.2431084273 Apr 04 03:09:32 PM PDT 24 Apr 04 03:09:34 PM PDT 24 14077815 ps
T616 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1459466300 Apr 04 03:09:12 PM PDT 24 Apr 04 03:09:15 PM PDT 24 447652737 ps
T617 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2769081258 Apr 04 03:09:25 PM PDT 24 Apr 04 03:09:26 PM PDT 24 193162043 ps
T618 /workspace/coverage/cover_reg_top/25.hmac_intr_test.4244693274 Apr 04 03:09:26 PM PDT 24 Apr 04 03:09:26 PM PDT 24 15363842 ps
T619 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2247521907 Apr 04 03:08:57 PM PDT 24 Apr 04 03:08:58 PM PDT 24 56288458 ps
T620 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1511592831 Apr 04 03:08:57 PM PDT 24 Apr 04 03:09:00 PM PDT 24 121075399 ps
T621 /workspace/coverage/cover_reg_top/31.hmac_intr_test.2577286032 Apr 04 03:09:27 PM PDT 24 Apr 04 03:09:28 PM PDT 24 98776436 ps
T622 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1541481414 Apr 04 03:09:24 PM PDT 24 Apr 04 03:09:25 PM PDT 24 22104719 ps
T623 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3794740914 Apr 04 03:09:08 PM PDT 24 Apr 04 03:09:11 PM PDT 24 260409601 ps
T624 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2160939254 Apr 04 03:09:11 PM PDT 24 Apr 04 03:09:12 PM PDT 24 30416197 ps
T85 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2284521266 Apr 04 03:08:55 PM PDT 24 Apr 04 03:08:56 PM PDT 24 20221945 ps
T625 /workspace/coverage/cover_reg_top/10.hmac_intr_test.137948 Apr 04 03:09:11 PM PDT 24 Apr 04 03:09:12 PM PDT 24 14046468 ps
T626 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.76020890 Apr 04 03:08:56 PM PDT 24 Apr 04 03:08:58 PM PDT 24 90540040 ps
T627 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2188303763 Apr 04 03:09:14 PM PDT 24 Apr 04 03:09:16 PM PDT 24 96062030 ps
T52 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2984595805 Apr 04 03:09:11 PM PDT 24 Apr 04 03:09:13 PM PDT 24 321560729 ps
T628 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3255639471 Apr 04 03:09:11 PM PDT 24 Apr 04 03:09:13 PM PDT 24 24273830 ps
T629 /workspace/coverage/cover_reg_top/37.hmac_intr_test.3024071184 Apr 04 03:09:30 PM PDT 24 Apr 04 03:09:31 PM PDT 24 42861955 ps
T86 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3305154283 Apr 04 03:08:56 PM PDT 24 Apr 04 03:08:57 PM PDT 24 16544990 ps
T630 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.91224027 Apr 04 03:08:54 PM PDT 24 Apr 04 03:08:56 PM PDT 24 242895227 ps
T631 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1567324035 Apr 04 03:08:53 PM PDT 24 Apr 04 03:08:59 PM PDT 24 112467758 ps
T632 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.156565590 Apr 04 03:09:12 PM PDT 24 Apr 04 03:09:14 PM PDT 24 25284643 ps
T633 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1618197611 Apr 04 03:08:56 PM PDT 24 Apr 04 03:08:57 PM PDT 24 44457613 ps
T96 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.31458911 Apr 04 03:08:57 PM PDT 24 Apr 04 03:09:00 PM PDT 24 415010646 ps
T634 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2508951985 Apr 04 03:08:59 PM PDT 24 Apr 04 03:09:00 PM PDT 24 28348768 ps
T635 /workspace/coverage/cover_reg_top/2.hmac_intr_test.685296107 Apr 04 03:08:56 PM PDT 24 Apr 04 03:08:56 PM PDT 24 27986450 ps
T636 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1166683958 Apr 04 03:09:13 PM PDT 24 Apr 04 03:09:14 PM PDT 24 13678916 ps
T637 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.443949988 Apr 04 03:09:12 PM PDT 24 Apr 04 03:09:15 PM PDT 24 1005393671 ps
T99 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2503401023 Apr 04 03:08:54 PM PDT 24 Apr 04 03:08:56 PM PDT 24 336795372 ps
T638 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1309848459 Apr 04 03:09:25 PM PDT 24 Apr 04 03:09:28 PM PDT 24 474019570 ps
T639 /workspace/coverage/cover_reg_top/22.hmac_intr_test.2956564700 Apr 04 03:09:27 PM PDT 24 Apr 04 03:09:28 PM PDT 24 15575257 ps
T640 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.902510785 Apr 04 03:09:12 PM PDT 24 Apr 04 03:09:15 PM PDT 24 45787109 ps
T641 /workspace/coverage/cover_reg_top/43.hmac_intr_test.1595251243 Apr 04 03:09:25 PM PDT 24 Apr 04 03:09:25 PM PDT 24 55570489 ps
T100 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1715122302 Apr 04 03:09:11 PM PDT 24 Apr 04 03:09:13 PM PDT 24 102579933 ps
T642 /workspace/coverage/cover_reg_top/23.hmac_intr_test.336468224 Apr 04 03:09:26 PM PDT 24 Apr 04 03:09:26 PM PDT 24 12412149 ps
T643 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1466631217 Apr 04 03:09:14 PM PDT 24 Apr 04 03:23:47 PM PDT 24 91136617577 ps
T644 /workspace/coverage/cover_reg_top/49.hmac_intr_test.3029906668 Apr 04 03:09:28 PM PDT 24 Apr 04 03:09:29 PM PDT 24 100855260 ps
T87 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3255959896 Apr 04 03:09:13 PM PDT 24 Apr 04 03:09:14 PM PDT 24 110017829 ps
T645 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3638728973 Apr 04 03:09:28 PM PDT 24 Apr 04 03:09:30 PM PDT 24 311605538 ps
T646 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1678875879 Apr 04 03:09:13 PM PDT 24 Apr 04 03:09:17 PM PDT 24 261210611 ps
T647 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1922644506 Apr 04 03:09:24 PM PDT 24 Apr 04 03:09:25 PM PDT 24 14431384 ps
T648 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.4190660583 Apr 04 03:09:13 PM PDT 24 Apr 04 03:24:23 PM PDT 24 260875519894 ps
T649 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3616327671 Apr 04 03:09:24 PM PDT 24 Apr 04 03:09:24 PM PDT 24 21660643 ps
T650 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.781165596 Apr 04 03:08:59 PM PDT 24 Apr 04 03:09:00 PM PDT 24 30803385 ps
T88 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.812309207 Apr 04 03:08:55 PM PDT 24 Apr 04 03:08:56 PM PDT 24 41277962 ps
T651 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1393537654 Apr 04 03:09:15 PM PDT 24 Apr 04 03:09:16 PM PDT 24 82445874 ps
T89 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1213801176 Apr 04 03:09:10 PM PDT 24 Apr 04 03:09:11 PM PDT 24 24368648 ps
T652 /workspace/coverage/cover_reg_top/40.hmac_intr_test.2532005931 Apr 04 03:09:28 PM PDT 24 Apr 04 03:09:29 PM PDT 24 38893421 ps
T653 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.202474598 Apr 04 03:09:27 PM PDT 24 Apr 04 03:09:29 PM PDT 24 29120773 ps
T654 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3127459862 Apr 04 03:08:55 PM PDT 24 Apr 04 03:08:56 PM PDT 24 64854263 ps
T655 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2509338062 Apr 04 03:08:56 PM PDT 24 Apr 04 03:08:59 PM PDT 24 184411734 ps
T656 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2720439983 Apr 04 03:09:10 PM PDT 24 Apr 04 03:09:13 PM PDT 24 266253334 ps
T104 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2458931164 Apr 04 03:09:13 PM PDT 24 Apr 04 03:09:15 PM PDT 24 216165354 ps
T657 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1849728090 Apr 04 03:08:56 PM PDT 24 Apr 04 03:08:57 PM PDT 24 66690427 ps
T658 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2480944644 Apr 04 03:08:55 PM PDT 24 Apr 04 03:08:58 PM PDT 24 211945031 ps
T659 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.4046251661 Apr 04 03:09:12 PM PDT 24 Apr 04 03:09:14 PM PDT 24 42966218 ps
T105 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3903289930 Apr 04 03:08:58 PM PDT 24 Apr 04 03:09:01 PM PDT 24 212631695 ps
T660 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1174896431 Apr 04 03:08:55 PM PDT 24 Apr 04 03:08:57 PM PDT 24 35283165 ps
T661 /workspace/coverage/cover_reg_top/15.hmac_intr_test.3070996319 Apr 04 03:09:15 PM PDT 24 Apr 04 03:09:15 PM PDT 24 17021065 ps
T106 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.462420588 Apr 04 03:09:26 PM PDT 24 Apr 04 03:09:28 PM PDT 24 182288056 ps
T662 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3157169195 Apr 04 03:09:14 PM PDT 24 Apr 04 03:09:17 PM PDT 24 489056363 ps
T663 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3702112490 Apr 04 03:09:13 PM PDT 24 Apr 04 03:09:14 PM PDT 24 39729801 ps
T90 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3865855746 Apr 04 03:08:56 PM PDT 24 Apr 04 03:08:57 PM PDT 24 31250075 ps
T664 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.451644768 Apr 04 03:09:13 PM PDT 24 Apr 04 03:15:01 PM PDT 24 67993214090 ps
T665 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3813028746 Apr 04 03:09:12 PM PDT 24 Apr 04 03:09:16 PM PDT 24 231988233 ps
T666 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2210165130 Apr 04 03:08:55 PM PDT 24 Apr 04 03:08:57 PM PDT 24 408762979 ps
T667 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3374073198 Apr 04 03:09:08 PM PDT 24 Apr 04 03:09:11 PM PDT 24 22410377 ps
T668 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3794035825 Apr 04 03:09:27 PM PDT 24 Apr 04 03:09:30 PM PDT 24 620550243 ps
T669 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2823236951 Apr 04 03:09:11 PM PDT 24 Apr 04 03:09:12 PM PDT 24 119733460 ps
T91 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3855153883 Apr 04 03:09:27 PM PDT 24 Apr 04 03:09:28 PM PDT 24 46862809 ps
T670 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1210718885 Apr 04 03:09:27 PM PDT 24 Apr 04 03:09:29 PM PDT 24 107886410 ps
T671 /workspace/coverage/cover_reg_top/47.hmac_intr_test.4263442308 Apr 04 03:09:29 PM PDT 24 Apr 04 03:09:30 PM PDT 24 11039170 ps
T672 /workspace/coverage/cover_reg_top/26.hmac_intr_test.3835865140 Apr 04 03:09:26 PM PDT 24 Apr 04 03:09:26 PM PDT 24 18367576 ps
T101 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2049313796 Apr 04 03:09:24 PM PDT 24 Apr 04 03:09:30 PM PDT 24 557921236 ps
T673 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.625387970 Apr 04 03:09:13 PM PDT 24 Apr 04 03:09:15 PM PDT 24 297753713 ps
T674 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2072949706 Apr 04 03:09:25 PM PDT 24 Apr 04 03:09:26 PM PDT 24 12784601 ps
T675 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3541552098 Apr 04 03:08:56 PM PDT 24 Apr 04 03:08:58 PM PDT 24 89143313 ps
T676 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3479915750 Apr 04 03:09:12 PM PDT 24 Apr 04 03:09:12 PM PDT 24 85124761 ps
T108 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.145418762 Apr 04 03:09:12 PM PDT 24 Apr 04 03:09:13 PM PDT 24 254453776 ps
T677 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2161553181 Apr 04 03:09:14 PM PDT 24 Apr 04 03:09:16 PM PDT 24 859578528 ps
T94 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1279367473 Apr 04 03:08:58 PM PDT 24 Apr 04 03:09:07 PM PDT 24 1471566807 ps
T678 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.4066577852 Apr 04 03:08:52 PM PDT 24 Apr 04 03:08:54 PM PDT 24 1471948494 ps
T679 /workspace/coverage/cover_reg_top/17.hmac_intr_test.1950349228 Apr 04 03:09:27 PM PDT 24 Apr 04 03:09:28 PM PDT 24 23086697 ps
T680 /workspace/coverage/cover_reg_top/7.hmac_intr_test.1359491703 Apr 04 03:09:13 PM PDT 24 Apr 04 03:09:14 PM PDT 24 52696297 ps
T681 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1520788650 Apr 04 03:08:53 PM PDT 24 Apr 04 03:08:59 PM PDT 24 548884965 ps
T109 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2156166318 Apr 04 03:08:57 PM PDT 24 Apr 04 03:08:59 PM PDT 24 162842132 ps
T682 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1023459771 Apr 04 03:09:12 PM PDT 24 Apr 04 03:09:14 PM PDT 24 23181718 ps
T683 /workspace/coverage/cover_reg_top/35.hmac_intr_test.301916745 Apr 04 03:09:27 PM PDT 24 Apr 04 03:09:27 PM PDT 24 51602637 ps
T684 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3912599858 Apr 04 03:08:55 PM PDT 24 Apr 04 03:08:59 PM PDT 24 237876615 ps
T685 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.929300776 Apr 04 03:09:13 PM PDT 24 Apr 04 03:09:15 PM PDT 24 40349886 ps
T686 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2492715415 Apr 04 03:09:13 PM PDT 24 Apr 04 03:09:15 PM PDT 24 1092378094 ps
T687 /workspace/coverage/cover_reg_top/48.hmac_intr_test.1965312546 Apr 04 03:09:28 PM PDT 24 Apr 04 03:09:29 PM PDT 24 24118155 ps
T688 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2338888549 Apr 04 03:09:11 PM PDT 24 Apr 04 03:09:14 PM PDT 24 230945651 ps
T689 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1295326064 Apr 04 03:09:10 PM PDT 24 Apr 04 03:09:13 PM PDT 24 155417666 ps
T690 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2924580822 Apr 04 03:08:55 PM PDT 24 Apr 04 03:08:58 PM PDT 24 241441045 ps
T691 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2083430561 Apr 04 03:09:24 PM PDT 24 Apr 04 03:09:25 PM PDT 24 39782657 ps
T92 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3704628856 Apr 04 03:08:54 PM PDT 24 Apr 04 03:08:55 PM PDT 24 19395709 ps
T692 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1518375083 Apr 04 03:09:07 PM PDT 24 Apr 04 03:09:09 PM PDT 24 147859542 ps
T693 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2375608242 Apr 04 03:09:10 PM PDT 24 Apr 04 03:09:13 PM PDT 24 416131287 ps
T694 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1343867191 Apr 04 03:09:26 PM PDT 24 Apr 04 03:09:26 PM PDT 24 13581166 ps
T695 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3013797108 Apr 04 03:08:58 PM PDT 24 Apr 04 03:08:59 PM PDT 24 56858206 ps
T93 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1926993088 Apr 04 03:09:06 PM PDT 24 Apr 04 03:09:10 PM PDT 24 687147623 ps
T696 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2219681947 Apr 04 03:08:58 PM PDT 24 Apr 04 03:09:07 PM PDT 24 1859637409 ps
T697 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3159806138 Apr 04 03:08:51 PM PDT 24 Apr 04 03:08:51 PM PDT 24 41978341 ps
T698 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1935829621 Apr 04 03:09:25 PM PDT 24 Apr 04 03:09:26 PM PDT 24 36816210 ps
T107 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3894404625 Apr 04 03:09:13 PM PDT 24 Apr 04 03:09:18 PM PDT 24 252270096 ps
T699 /workspace/coverage/cover_reg_top/29.hmac_intr_test.1455320994 Apr 04 03:09:29 PM PDT 24 Apr 04 03:09:30 PM PDT 24 17976686 ps
T700 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1067643687 Apr 04 03:08:56 PM PDT 24 Apr 04 03:17:21 PM PDT 24 166574899366 ps
T701 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1129313830 Apr 04 03:09:27 PM PDT 24 Apr 04 03:09:29 PM PDT 24 175186042 ps
T702 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3655694837 Apr 04 03:08:55 PM PDT 24 Apr 04 03:08:59 PM PDT 24 620742067 ps
T703 /workspace/coverage/cover_reg_top/1.hmac_intr_test.4121077923 Apr 04 03:08:53 PM PDT 24 Apr 04 03:08:54 PM PDT 24 33797971 ps
T704 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.759634601 Apr 04 03:09:13 PM PDT 24 Apr 04 03:09:16 PM PDT 24 40218701 ps
T705 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3547745139 Apr 04 03:09:13 PM PDT 24 Apr 04 03:09:14 PM PDT 24 12761942 ps
T706 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3790540309 Apr 04 03:09:11 PM PDT 24 Apr 04 03:24:41 PM PDT 24 319963884080 ps
T707 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.754317427 Apr 04 03:08:59 PM PDT 24 Apr 04 03:09:00 PM PDT 24 25940045 ps
T708 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2050931292 Apr 04 03:08:55 PM PDT 24 Apr 04 03:08:57 PM PDT 24 96577008 ps
T709 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.761300262 Apr 04 03:09:29 PM PDT 24 Apr 04 03:09:30 PM PDT 24 51810552 ps
T710 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1937664158 Apr 04 03:09:28 PM PDT 24 Apr 04 03:09:29 PM PDT 24 48602355 ps
T711 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2495949792 Apr 04 03:09:16 PM PDT 24 Apr 04 03:09:17 PM PDT 24 299241192 ps
T712 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.418791873 Apr 04 03:09:09 PM PDT 24 Apr 04 03:09:12 PM PDT 24 37302264 ps
T713 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1438121319 Apr 04 03:09:25 PM PDT 24 Apr 04 03:09:26 PM PDT 24 32148646 ps
T714 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3078086098 Apr 04 03:09:09 PM PDT 24 Apr 04 03:09:13 PM PDT 24 552882997 ps
T715 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3079881201 Apr 04 03:08:59 PM PDT 24 Apr 04 03:09:00 PM PDT 24 22186126 ps
T716 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.41908192 Apr 04 03:09:12 PM PDT 24 Apr 04 03:09:15 PM PDT 24 148116386 ps
T717 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2519703971 Apr 04 03:09:28 PM PDT 24 Apr 04 03:09:28 PM PDT 24 158230980 ps
T718 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3162426138 Apr 04 03:08:55 PM PDT 24 Apr 04 03:09:05 PM PDT 24 425950756 ps
T719 /workspace/coverage/cover_reg_top/30.hmac_intr_test.3484142713 Apr 04 03:09:24 PM PDT 24 Apr 04 03:09:25 PM PDT 24 98376638 ps
T720 /workspace/coverage/cover_reg_top/3.hmac_intr_test.2515752982 Apr 04 03:08:57 PM PDT 24 Apr 04 03:08:57 PM PDT 24 16821983 ps
T721 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2010617384 Apr 04 03:09:31 PM PDT 24 Apr 04 03:09:31 PM PDT 24 16892202 ps
T722 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2356504177 Apr 04 03:09:14 PM PDT 24 Apr 04 03:09:15 PM PDT 24 18281461 ps
T102 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2471860945 Apr 04 03:09:10 PM PDT 24 Apr 04 03:09:15 PM PDT 24 1119636705 ps
T723 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.289116848 Apr 04 03:09:14 PM PDT 24 Apr 04 03:09:17 PM PDT 24 182785852 ps
T103 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3791842377 Apr 04 03:08:54 PM PDT 24 Apr 04 03:08:58 PM PDT 24 144758397 ps
T724 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1229035487 Apr 04 03:09:28 PM PDT 24 Apr 04 03:09:29 PM PDT 24 61261126 ps
T97 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1091696961 Apr 04 03:08:57 PM PDT 24 Apr 04 03:09:01 PM PDT 24 268946976 ps
T725 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2642476854 Apr 04 03:09:28 PM PDT 24 Apr 04 03:09:29 PM PDT 24 105608255 ps
T726 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.4269855041 Apr 04 03:08:57 PM PDT 24 Apr 04 03:08:58 PM PDT 24 86515516 ps
T727 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2137822351 Apr 04 03:09:12 PM PDT 24 Apr 04 03:09:14 PM PDT 24 16754164 ps
T728 /workspace/coverage/cover_reg_top/14.hmac_intr_test.2690729476 Apr 04 03:09:10 PM PDT 24 Apr 04 03:09:12 PM PDT 24 79902642 ps
T98 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3390631891 Apr 04 03:09:12 PM PDT 24 Apr 04 03:09:15 PM PDT 24 1164022377 ps
T729 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.427481290 Apr 04 03:09:11 PM PDT 24 Apr 04 03:09:13 PM PDT 24 39222994 ps
T730 /workspace/coverage/cover_reg_top/4.hmac_intr_test.1290708966 Apr 04 03:08:56 PM PDT 24 Apr 04 03:08:57 PM PDT 24 13244241 ps
T731 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1638583659 Apr 04 03:09:25 PM PDT 24 Apr 04 03:09:27 PM PDT 24 165205683 ps
T732 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3004615870 Apr 04 03:08:56 PM PDT 24 Apr 04 03:08:58 PM PDT 24 159921626 ps
T733 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2308173183 Apr 04 03:09:26 PM PDT 24 Apr 04 03:09:27 PM PDT 24 119360018 ps
T734 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2181671481 Apr 04 03:09:15 PM PDT 24 Apr 04 03:09:17 PM PDT 24 149003995 ps
T735 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3535263721 Apr 04 03:09:24 PM PDT 24 Apr 04 03:09:25 PM PDT 24 13276833 ps
T736 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3056046859 Apr 04 03:08:57 PM PDT 24 Apr 04 03:08:58 PM PDT 24 44360724 ps
T737 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.385851032 Apr 04 03:09:26 PM PDT 24 Apr 04 03:09:29 PM PDT 24 145613274 ps
T738 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1244343272 Apr 04 03:09:12 PM PDT 24 Apr 04 03:09:14 PM PDT 24 102678344 ps
T739 /workspace/coverage/cover_reg_top/6.hmac_intr_test.2455132752 Apr 04 03:09:08 PM PDT 24 Apr 04 03:09:10 PM PDT 24 17564967 ps

Test location /workspace/coverage/default/33.hmac_stress_all.979038573
Short name T14
Test name
Test status
Simulation time 33088382354 ps
CPU time 1595.95 seconds
Started Apr 04 12:32:08 PM PDT 24
Finished Apr 04 12:58:45 PM PDT 24
Peak memory 229484 kb
Host smart-3ae29480-1356-41f5-9781-8e156a1c3ebc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979038573 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.979038573
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/134.hmac_stress_all_with_rand_reset.3720027284
Short name T6
Test name
Test status
Simulation time 253129539338 ps
CPU time 2494 seconds
Started Apr 04 12:33:25 PM PDT 24
Finished Apr 04 01:15:00 PM PDT 24
Peak memory 240300 kb
Host smart-e21f19ba-650f-4d9b-9222-29a9830cc2d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3720027284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.hmac_stress_all_with_rand_reset.3720027284
Directory /workspace/134.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.4064453942
Short name T27
Test name
Test status
Simulation time 62558446 ps
CPU time 0.99 seconds
Started Apr 04 12:28:36 PM PDT 24
Finished Apr 04 12:28:37 PM PDT 24
Peak memory 217892 kb
Host smart-af38a0fd-3994-427b-9f7e-cc3b0bf596b6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064453942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.4064453942
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.4046202977
Short name T50
Test name
Test status
Simulation time 350472705 ps
CPU time 3.15 seconds
Started Apr 04 03:09:15 PM PDT 24
Finished Apr 04 03:09:18 PM PDT 24
Peak memory 199016 kb
Host smart-e392cc80-bae1-47ba-8918-d0d6314fc781
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046202977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.4046202977
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/75.hmac_stress_all_with_rand_reset.1173548742
Short name T9
Test name
Test status
Simulation time 97421664469 ps
CPU time 2111.61 seconds
Started Apr 04 12:32:52 PM PDT 24
Finished Apr 04 01:08:04 PM PDT 24
Peak memory 264732 kb
Host smart-93c2fade-b12d-4ef5-92a7-9cc6bc17cf83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1173548742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.hmac_stress_all_with_rand_reset.1173548742
Directory /workspace/75.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.hmac_stress_all_with_rand_reset.3326203655
Short name T10
Test name
Test status
Simulation time 46976256129 ps
CPU time 1389.15 seconds
Started Apr 04 12:30:40 PM PDT 24
Finished Apr 04 12:53:49 PM PDT 24
Peak memory 248824 kb
Host smart-1859890a-01fc-46e8-a424-ffd377648cef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3326203655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all_with_rand_reset.3326203655
Directory /workspace/10.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3865855746
Short name T90
Test name
Test status
Simulation time 31250075 ps
CPU time 0.84 seconds
Started Apr 04 03:08:56 PM PDT 24
Finished Apr 04 03:08:57 PM PDT 24
Peak memory 197864 kb
Host smart-173c1ec8-6e2f-4ec1-b545-6b879531d44a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865855746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3865855746
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/default/0.hmac_stress_all.1856098185
Short name T42
Test name
Test status
Simulation time 46869079885 ps
CPU time 2627.51 seconds
Started Apr 04 12:28:21 PM PDT 24
Finished Apr 04 01:12:09 PM PDT 24
Peak memory 199572 kb
Host smart-48295adc-c510-40f3-ac56-6f1e18dd3268
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856098185 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.1856098185
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1488619059
Short name T2
Test name
Test status
Simulation time 127650935437 ps
CPU time 1683.06 seconds
Started Apr 04 12:31:47 PM PDT 24
Finished Apr 04 12:59:50 PM PDT 24
Peak memory 215028 kb
Host smart-fbd0b4dd-46d8-4c91-bd3d-35ed1eeb12b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488619059 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1488619059
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1950926798
Short name T17
Test name
Test status
Simulation time 22386595 ps
CPU time 0.63 seconds
Started Apr 04 12:33:26 PM PDT 24
Finished Apr 04 12:33:27 PM PDT 24
Peak memory 192804 kb
Host smart-5690616e-bffc-4532-8c06-cdd582ed2963
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950926798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1950926798
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2471860945
Short name T102
Test name
Test status
Simulation time 1119636705 ps
CPU time 4.37 seconds
Started Apr 04 03:09:10 PM PDT 24
Finished Apr 04 03:09:15 PM PDT 24
Peak memory 198880 kb
Host smart-20dc6990-d32c-4aa7-b7d7-637c341af0db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471860945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.2471860945
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2458931164
Short name T104
Test name
Test status
Simulation time 216165354 ps
CPU time 1.59 seconds
Started Apr 04 03:09:13 PM PDT 24
Finished Apr 04 03:09:15 PM PDT 24
Peak memory 198816 kb
Host smart-d0c59a4c-27d7-4032-8a24-2b8290ba1510
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458931164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2458931164
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3390631891
Short name T98
Test name
Test status
Simulation time 1164022377 ps
CPU time 3.01 seconds
Started Apr 04 03:09:12 PM PDT 24
Finished Apr 04 03:09:15 PM PDT 24
Peak memory 199136 kb
Host smart-39fe0d04-4f7d-483d-a4a5-0eb4ef707a36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390631891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3390631891
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3655694837
Short name T702
Test name
Test status
Simulation time 620742067 ps
CPU time 3.35 seconds
Started Apr 04 03:08:55 PM PDT 24
Finished Apr 04 03:08:59 PM PDT 24
Peak memory 198972 kb
Host smart-fc1620d9-c236-43a5-8be6-a0e8e0f0b741
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655694837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3655694837
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1520788650
Short name T681
Test name
Test status
Simulation time 548884965 ps
CPU time 5.79 seconds
Started Apr 04 03:08:53 PM PDT 24
Finished Apr 04 03:08:59 PM PDT 24
Peak memory 197832 kb
Host smart-56db10f9-4a1f-4b4d-8651-85578aa8729b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520788650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1520788650
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3079881201
Short name T715
Test name
Test status
Simulation time 22186126 ps
CPU time 0.77 seconds
Started Apr 04 03:08:59 PM PDT 24
Finished Apr 04 03:09:00 PM PDT 24
Peak memory 196980 kb
Host smart-61901e78-ab58-4134-91f4-a26c7c525372
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079881201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3079881201
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2210165130
Short name T666
Test name
Test status
Simulation time 408762979 ps
CPU time 1.76 seconds
Started Apr 04 03:08:55 PM PDT 24
Finished Apr 04 03:08:57 PM PDT 24
Peak memory 199132 kb
Host smart-357afb30-33dd-45ea-aaa0-07d8c84d982b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210165130 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2210165130
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.781165596
Short name T650
Test name
Test status
Simulation time 30803385 ps
CPU time 0.97 seconds
Started Apr 04 03:08:59 PM PDT 24
Finished Apr 04 03:09:00 PM PDT 24
Peak memory 198568 kb
Host smart-2ce1d198-8605-4a69-9f51-6030806cc37e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781165596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.781165596
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2508951985
Short name T634
Test name
Test status
Simulation time 28348768 ps
CPU time 0.64 seconds
Started Apr 04 03:08:59 PM PDT 24
Finished Apr 04 03:09:00 PM PDT 24
Peak memory 193728 kb
Host smart-7942a46b-857a-4cba-8601-e1e97529204d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508951985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2508951985
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1849728090
Short name T657
Test name
Test status
Simulation time 66690427 ps
CPU time 1.49 seconds
Started Apr 04 03:08:56 PM PDT 24
Finished Apr 04 03:08:57 PM PDT 24
Peak memory 199076 kb
Host smart-d2332ead-6ea7-41a9-8636-cc3db48e7401
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849728090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.1849728090
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2247521907
Short name T619
Test name
Test status
Simulation time 56288458 ps
CPU time 1.62 seconds
Started Apr 04 03:08:57 PM PDT 24
Finished Apr 04 03:08:58 PM PDT 24
Peak memory 199056 kb
Host smart-7e0c06fe-b116-4a74-a0a3-eacd88af753b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247521907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2247521907
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3541552098
Short name T675
Test name
Test status
Simulation time 89143313 ps
CPU time 1.8 seconds
Started Apr 04 03:08:56 PM PDT 24
Finished Apr 04 03:08:58 PM PDT 24
Peak memory 199004 kb
Host smart-dc0c0025-636c-4423-bdb2-43a465516794
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541552098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3541552098
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2480944644
Short name T658
Test name
Test status
Simulation time 211945031 ps
CPU time 3.03 seconds
Started Apr 04 03:08:55 PM PDT 24
Finished Apr 04 03:08:58 PM PDT 24
Peak memory 197532 kb
Host smart-b7f1f83c-3f18-493a-82ed-d461b5e08ba2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480944644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.2480944644
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1279367473
Short name T94
Test name
Test status
Simulation time 1471566807 ps
CPU time 9.65 seconds
Started Apr 04 03:08:58 PM PDT 24
Finished Apr 04 03:09:07 PM PDT 24
Peak memory 197956 kb
Host smart-8f985842-9295-4e27-b167-cd1c1c6bfe13
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279367473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1279367473
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1067643687
Short name T700
Test name
Test status
Simulation time 166574899366 ps
CPU time 505 seconds
Started Apr 04 03:08:56 PM PDT 24
Finished Apr 04 03:17:21 PM PDT 24
Peak memory 215584 kb
Host smart-2f7631ea-5941-4a78-97d8-3952ab1dcc74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067643687 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1067643687
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3013797108
Short name T695
Test name
Test status
Simulation time 56858206 ps
CPU time 0.65 seconds
Started Apr 04 03:08:58 PM PDT 24
Finished Apr 04 03:08:59 PM PDT 24
Peak memory 196488 kb
Host smart-f2f7e421-df92-454a-b7eb-8d29c77b3d17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013797108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.3013797108
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.4121077923
Short name T703
Test name
Test status
Simulation time 33797971 ps
CPU time 0.59 seconds
Started Apr 04 03:08:53 PM PDT 24
Finished Apr 04 03:08:54 PM PDT 24
Peak memory 193936 kb
Host smart-52737dc4-c99e-44c9-b2d6-063c51467aa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121077923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.4121077923
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.91224027
Short name T630
Test name
Test status
Simulation time 242895227 ps
CPU time 1.18 seconds
Started Apr 04 03:08:54 PM PDT 24
Finished Apr 04 03:08:56 PM PDT 24
Peak memory 199020 kb
Host smart-e0d307dd-7563-4ef4-a774-9112f0c7b5f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91224027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_o
utstanding.91224027
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3127459862
Short name T654
Test name
Test status
Simulation time 64854263 ps
CPU time 1.49 seconds
Started Apr 04 03:08:55 PM PDT 24
Finished Apr 04 03:08:56 PM PDT 24
Peak memory 199160 kb
Host smart-ddeaf7dc-9043-4b47-80d1-5b75ed2512ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127459862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3127459862
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2503401023
Short name T99
Test name
Test status
Simulation time 336795372 ps
CPU time 1.84 seconds
Started Apr 04 03:08:54 PM PDT 24
Finished Apr 04 03:08:56 PM PDT 24
Peak memory 199088 kb
Host smart-fd2c29f6-8f15-4375-b0b5-edef77b22df8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503401023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2503401023
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3790540309
Short name T706
Test name
Test status
Simulation time 319963884080 ps
CPU time 929.24 seconds
Started Apr 04 03:09:11 PM PDT 24
Finished Apr 04 03:24:41 PM PDT 24
Peak memory 215612 kb
Host smart-e5a30364-c026-4a4e-b3e0-6b909f5ca5c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790540309 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3790540309
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1213801176
Short name T89
Test name
Test status
Simulation time 24368648 ps
CPU time 0.69 seconds
Started Apr 04 03:09:10 PM PDT 24
Finished Apr 04 03:09:11 PM PDT 24
Peak memory 196664 kb
Host smart-c6e0bfa5-b3d8-40f5-a3ab-66b587b21c18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213801176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1213801176
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.137948
Short name T625
Test name
Test status
Simulation time 14046468 ps
CPU time 0.62 seconds
Started Apr 04 03:09:11 PM PDT 24
Finished Apr 04 03:09:12 PM PDT 24
Peak memory 193940 kb
Host smart-05661592-49c6-41c3-9d29-28a2483d7d1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.137948
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3255639471
Short name T628
Test name
Test status
Simulation time 24273830 ps
CPU time 1.08 seconds
Started Apr 04 03:09:11 PM PDT 24
Finished Apr 04 03:09:13 PM PDT 24
Peak memory 198024 kb
Host smart-75bcb641-88d1-467f-aae1-a8ebf845a2a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255639471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.3255639471
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2720439983
Short name T656
Test name
Test status
Simulation time 266253334 ps
CPU time 2.54 seconds
Started Apr 04 03:09:10 PM PDT 24
Finished Apr 04 03:09:13 PM PDT 24
Peak memory 198988 kb
Host smart-f0077b8a-de11-47ac-a055-64d5734558a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720439983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2720439983
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3894404625
Short name T107
Test name
Test status
Simulation time 252270096 ps
CPU time 4.25 seconds
Started Apr 04 03:09:13 PM PDT 24
Finished Apr 04 03:09:18 PM PDT 24
Peak memory 199080 kb
Host smart-e1263a42-3408-4dcc-adc5-8ba762986328
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894404625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3894404625
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.427481290
Short name T729
Test name
Test status
Simulation time 39222994 ps
CPU time 1.16 seconds
Started Apr 04 03:09:11 PM PDT 24
Finished Apr 04 03:09:13 PM PDT 24
Peak memory 198932 kb
Host smart-d8738a4f-0fac-48bf-808e-6fbfbdb70289
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427481290 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.427481290
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1244343272
Short name T738
Test name
Test status
Simulation time 102678344 ps
CPU time 0.9 seconds
Started Apr 04 03:09:12 PM PDT 24
Finished Apr 04 03:09:14 PM PDT 24
Peak memory 198288 kb
Host smart-68ddbe6f-64ca-41be-9a2f-33e5d733257b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244343272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1244343272
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1166683958
Short name T636
Test name
Test status
Simulation time 13678916 ps
CPU time 0.59 seconds
Started Apr 04 03:09:13 PM PDT 24
Finished Apr 04 03:09:14 PM PDT 24
Peak memory 193872 kb
Host smart-074b19aa-ff16-47cb-8eff-13bd3a76f64f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166683958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1166683958
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2375608242
Short name T693
Test name
Test status
Simulation time 416131287 ps
CPU time 2.19 seconds
Started Apr 04 03:09:10 PM PDT 24
Finished Apr 04 03:09:13 PM PDT 24
Peak memory 198828 kb
Host smart-31099141-2ef4-4b65-8bd9-bc977ccb9e94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375608242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2375608242
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.902510785
Short name T640
Test name
Test status
Simulation time 45787109 ps
CPU time 2.29 seconds
Started Apr 04 03:09:12 PM PDT 24
Finished Apr 04 03:09:15 PM PDT 24
Peak memory 199020 kb
Host smart-01b5fb04-6e8c-46fa-a877-6fc7b8a537cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902510785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.902510785
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.145418762
Short name T108
Test name
Test status
Simulation time 254453776 ps
CPU time 1.77 seconds
Started Apr 04 03:09:12 PM PDT 24
Finished Apr 04 03:09:13 PM PDT 24
Peak memory 199092 kb
Host smart-07d48a97-6f75-41ed-80e2-0dbcfcf0232c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145418762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.145418762
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1023459771
Short name T682
Test name
Test status
Simulation time 23181718 ps
CPU time 1.27 seconds
Started Apr 04 03:09:12 PM PDT 24
Finished Apr 04 03:09:14 PM PDT 24
Peak memory 199084 kb
Host smart-b03a5f75-82e2-4e3a-abd7-829cf3dfc383
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023459771 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1023459771
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2285783786
Short name T54
Test name
Test status
Simulation time 72959437 ps
CPU time 0.71 seconds
Started Apr 04 03:09:14 PM PDT 24
Finished Apr 04 03:09:15 PM PDT 24
Peak memory 196728 kb
Host smart-cfbf6fb8-4171-4639-8e4e-2ca4b0dad6d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285783786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2285783786
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2160939254
Short name T624
Test name
Test status
Simulation time 30416197 ps
CPU time 0.58 seconds
Started Apr 04 03:09:11 PM PDT 24
Finished Apr 04 03:09:12 PM PDT 24
Peak memory 193644 kb
Host smart-797c2e23-4e5b-4852-b43b-ddb914c5a3b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160939254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2160939254
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2181671481
Short name T734
Test name
Test status
Simulation time 149003995 ps
CPU time 2.42 seconds
Started Apr 04 03:09:15 PM PDT 24
Finished Apr 04 03:09:17 PM PDT 24
Peak memory 198848 kb
Host smart-b271015e-6b0e-4909-a517-4d8f3241985e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181671481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2181671481
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2685776391
Short name T608
Test name
Test status
Simulation time 371870646 ps
CPU time 3.42 seconds
Started Apr 04 03:09:13 PM PDT 24
Finished Apr 04 03:09:17 PM PDT 24
Peak memory 199112 kb
Host smart-ab9077ce-dfe2-4dd2-a8d3-0cdecc1563ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685776391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2685776391
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1295326064
Short name T689
Test name
Test status
Simulation time 155417666 ps
CPU time 1.84 seconds
Started Apr 04 03:09:10 PM PDT 24
Finished Apr 04 03:09:13 PM PDT 24
Peak memory 199004 kb
Host smart-6bd80b62-5c41-4dc1-8f8e-50923aedb9ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295326064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1295326064
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.289116848
Short name T723
Test name
Test status
Simulation time 182785852 ps
CPU time 2.13 seconds
Started Apr 04 03:09:14 PM PDT 24
Finished Apr 04 03:09:17 PM PDT 24
Peak memory 199128 kb
Host smart-433d8acc-bf39-4fd9-9af3-801de48b8173
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289116848 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.289116848
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3255959896
Short name T87
Test name
Test status
Simulation time 110017829 ps
CPU time 0.9 seconds
Started Apr 04 03:09:13 PM PDT 24
Finished Apr 04 03:09:14 PM PDT 24
Peak memory 198576 kb
Host smart-4af91dc8-8779-45a3-91bb-7909e3058e4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255959896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3255959896
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3431181775
Short name T613
Test name
Test status
Simulation time 38775660 ps
CPU time 0.59 seconds
Started Apr 04 03:09:09 PM PDT 24
Finished Apr 04 03:09:11 PM PDT 24
Peak memory 193900 kb
Host smart-5297390d-f235-4ebf-8ee6-2903a83de1dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431181775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3431181775
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.418791873
Short name T712
Test name
Test status
Simulation time 37302264 ps
CPU time 1.61 seconds
Started Apr 04 03:09:09 PM PDT 24
Finished Apr 04 03:09:12 PM PDT 24
Peak memory 199012 kb
Host smart-dd2dcc5d-b830-452b-bc5d-6d7cb799bcb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418791873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr
_outstanding.418791873
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.156565590
Short name T632
Test name
Test status
Simulation time 25284643 ps
CPU time 1.43 seconds
Started Apr 04 03:09:12 PM PDT 24
Finished Apr 04 03:09:14 PM PDT 24
Peak memory 199156 kb
Host smart-b8ba745e-20e0-450a-ad1a-feaff4acb26b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156565590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.156565590
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1715122302
Short name T100
Test name
Test status
Simulation time 102579933 ps
CPU time 1.66 seconds
Started Apr 04 03:09:11 PM PDT 24
Finished Apr 04 03:09:13 PM PDT 24
Peak memory 199108 kb
Host smart-024b9857-7615-4646-9f65-a1d6a365d4db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715122302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1715122302
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.4190660583
Short name T648
Test name
Test status
Simulation time 260875519894 ps
CPU time 909.54 seconds
Started Apr 04 03:09:13 PM PDT 24
Finished Apr 04 03:24:23 PM PDT 24
Peak memory 215272 kb
Host smart-5e6352bb-8902-4df3-a10e-8962c1df547d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190660583 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.4190660583
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2188303763
Short name T627
Test name
Test status
Simulation time 96062030 ps
CPU time 0.99 seconds
Started Apr 04 03:09:14 PM PDT 24
Finished Apr 04 03:09:16 PM PDT 24
Peak memory 198068 kb
Host smart-8c47511c-e280-4ddd-92e7-c69fd697964b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188303763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2188303763
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.2690729476
Short name T728
Test name
Test status
Simulation time 79902642 ps
CPU time 0.6 seconds
Started Apr 04 03:09:10 PM PDT 24
Finished Apr 04 03:09:12 PM PDT 24
Peak memory 193624 kb
Host smart-7e34208b-59ce-441a-bc47-41af2f04ea54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690729476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2690729476
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2161553181
Short name T677
Test name
Test status
Simulation time 859578528 ps
CPU time 1.92 seconds
Started Apr 04 03:09:14 PM PDT 24
Finished Apr 04 03:09:16 PM PDT 24
Peak memory 199032 kb
Host smart-b683585f-9c46-4c88-bb07-cd96700d4bd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161553181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2161553181
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.759634601
Short name T704
Test name
Test status
Simulation time 40218701 ps
CPU time 2.26 seconds
Started Apr 04 03:09:13 PM PDT 24
Finished Apr 04 03:09:16 PM PDT 24
Peak memory 199120 kb
Host smart-ba436446-2feb-4404-ac6b-389cadea3295
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759634601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.759634601
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.4046251661
Short name T659
Test name
Test status
Simulation time 42966218 ps
CPU time 1.21 seconds
Started Apr 04 03:09:12 PM PDT 24
Finished Apr 04 03:09:14 PM PDT 24
Peak memory 198980 kb
Host smart-9220d1b8-4939-462a-8fb0-ad22682644ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046251661 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.4046251661
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2356504177
Short name T722
Test name
Test status
Simulation time 18281461 ps
CPU time 0.9 seconds
Started Apr 04 03:09:14 PM PDT 24
Finished Apr 04 03:09:15 PM PDT 24
Peak memory 198332 kb
Host smart-45400b39-a700-4255-9424-9762a6fe1403
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356504177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2356504177
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.3070996319
Short name T661
Test name
Test status
Simulation time 17021065 ps
CPU time 0.63 seconds
Started Apr 04 03:09:15 PM PDT 24
Finished Apr 04 03:09:15 PM PDT 24
Peak memory 193644 kb
Host smart-93b90b47-1647-435e-913f-67b1f7714987
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070996319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.3070996319
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3157169195
Short name T662
Test name
Test status
Simulation time 489056363 ps
CPU time 2.32 seconds
Started Apr 04 03:09:14 PM PDT 24
Finished Apr 04 03:09:17 PM PDT 24
Peak memory 199028 kb
Host smart-45b86d40-b04c-4c61-b459-ba636cebfb75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157169195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3157169195
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1678875879
Short name T646
Test name
Test status
Simulation time 261210611 ps
CPU time 3.39 seconds
Started Apr 04 03:09:13 PM PDT 24
Finished Apr 04 03:09:17 PM PDT 24
Peak memory 199180 kb
Host smart-796c1a44-db7a-45c0-bc7b-7d00c487a42c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678875879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1678875879
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2495949792
Short name T711
Test name
Test status
Simulation time 299241192 ps
CPU time 1.28 seconds
Started Apr 04 03:09:16 PM PDT 24
Finished Apr 04 03:09:17 PM PDT 24
Peak memory 199132 kb
Host smart-5e9d42c7-2d4d-4720-8788-692859c1969c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495949792 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2495949792
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2137822351
Short name T727
Test name
Test status
Simulation time 16754164 ps
CPU time 0.96 seconds
Started Apr 04 03:09:12 PM PDT 24
Finished Apr 04 03:09:14 PM PDT 24
Peak memory 198296 kb
Host smart-560a9b0f-379b-435d-84dd-0191f022cd3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137822351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2137822351
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3547745139
Short name T705
Test name
Test status
Simulation time 12761942 ps
CPU time 0.56 seconds
Started Apr 04 03:09:13 PM PDT 24
Finished Apr 04 03:09:14 PM PDT 24
Peak memory 193720 kb
Host smart-88bf6c20-f1df-47e7-b19e-6f8e14ee720a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547745139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3547745139
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.625387970
Short name T673
Test name
Test status
Simulation time 297753713 ps
CPU time 1.19 seconds
Started Apr 04 03:09:13 PM PDT 24
Finished Apr 04 03:09:15 PM PDT 24
Peak memory 198584 kb
Host smart-8cb5b7e5-a3a0-4aaf-8c00-c4bf377ac2ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625387970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr
_outstanding.625387970
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.41908192
Short name T716
Test name
Test status
Simulation time 148116386 ps
CPU time 1.97 seconds
Started Apr 04 03:09:12 PM PDT 24
Finished Apr 04 03:09:15 PM PDT 24
Peak memory 199140 kb
Host smart-9016ccea-6f26-43eb-9bb2-5cc2d63247d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41908192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.41908192
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1210718885
Short name T670
Test name
Test status
Simulation time 107886410 ps
CPU time 2.32 seconds
Started Apr 04 03:09:27 PM PDT 24
Finished Apr 04 03:09:29 PM PDT 24
Peak memory 199128 kb
Host smart-d283b547-21ea-45da-8ae0-5dbdb09bce4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210718885 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1210718885
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2642476854
Short name T725
Test name
Test status
Simulation time 105608255 ps
CPU time 0.82 seconds
Started Apr 04 03:09:28 PM PDT 24
Finished Apr 04 03:09:29 PM PDT 24
Peak memory 197712 kb
Host smart-09d331a5-6d60-4607-8e88-e49b0b3a9200
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642476854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2642476854
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1950349228
Short name T679
Test name
Test status
Simulation time 23086697 ps
CPU time 0.62 seconds
Started Apr 04 03:09:27 PM PDT 24
Finished Apr 04 03:09:28 PM PDT 24
Peak memory 193876 kb
Host smart-36fe5a62-f78d-438f-b2c1-7bbea09f1c10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950349228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1950349228
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3638728973
Short name T645
Test name
Test status
Simulation time 311605538 ps
CPU time 1.83 seconds
Started Apr 04 03:09:28 PM PDT 24
Finished Apr 04 03:09:30 PM PDT 24
Peak memory 198640 kb
Host smart-9ed07d8b-757b-4615-8a3b-537b902ed464
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638728973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3638728973
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1459466300
Short name T616
Test name
Test status
Simulation time 447652737 ps
CPU time 2.33 seconds
Started Apr 04 03:09:12 PM PDT 24
Finished Apr 04 03:09:15 PM PDT 24
Peak memory 199112 kb
Host smart-cdebad62-fe01-4b23-bd15-1111cac6783b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459466300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1459466300
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.462420588
Short name T106
Test name
Test status
Simulation time 182288056 ps
CPU time 1.77 seconds
Started Apr 04 03:09:26 PM PDT 24
Finished Apr 04 03:09:28 PM PDT 24
Peak memory 199076 kb
Host smart-82b101d1-c959-4b85-9627-06c8285bdc1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462420588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.462420588
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.385851032
Short name T737
Test name
Test status
Simulation time 145613274 ps
CPU time 2.89 seconds
Started Apr 04 03:09:26 PM PDT 24
Finished Apr 04 03:09:29 PM PDT 24
Peak memory 199132 kb
Host smart-7b3b1763-35bf-43ed-a413-73b0695d9c7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385851032 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.385851032
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.761300262
Short name T709
Test name
Test status
Simulation time 51810552 ps
CPU time 0.91 seconds
Started Apr 04 03:09:29 PM PDT 24
Finished Apr 04 03:09:30 PM PDT 24
Peak memory 198752 kb
Host smart-fb16c1ee-2566-4dab-a4a9-50742aaaea49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761300262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.761300262
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1541481414
Short name T622
Test name
Test status
Simulation time 22104719 ps
CPU time 0.57 seconds
Started Apr 04 03:09:24 PM PDT 24
Finished Apr 04 03:09:25 PM PDT 24
Peak memory 193916 kb
Host smart-ff556b38-2b85-48df-a9be-1fc26a67a3d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541481414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1541481414
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1638583659
Short name T731
Test name
Test status
Simulation time 165205683 ps
CPU time 1.77 seconds
Started Apr 04 03:09:25 PM PDT 24
Finished Apr 04 03:09:27 PM PDT 24
Peak memory 198744 kb
Host smart-863b79d2-b528-4d3a-8f1c-6e8b91a939a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638583659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.1638583659
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.202474598
Short name T653
Test name
Test status
Simulation time 29120773 ps
CPU time 1.51 seconds
Started Apr 04 03:09:27 PM PDT 24
Finished Apr 04 03:09:29 PM PDT 24
Peak memory 199116 kb
Host smart-93e0eeab-fd1c-4015-b035-d30aa37afcd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202474598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.202474598
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2049313796
Short name T101
Test name
Test status
Simulation time 557921236 ps
CPU time 5.06 seconds
Started Apr 04 03:09:24 PM PDT 24
Finished Apr 04 03:09:30 PM PDT 24
Peak memory 199060 kb
Host smart-df611dc1-3643-48b2-80c3-99b7c6c8219c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049313796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2049313796
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1129313830
Short name T701
Test name
Test status
Simulation time 175186042 ps
CPU time 2.46 seconds
Started Apr 04 03:09:27 PM PDT 24
Finished Apr 04 03:09:29 PM PDT 24
Peak memory 199080 kb
Host smart-182c52dc-1b46-4dba-8f09-1fbff3f1b05e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129313830 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1129313830
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3855153883
Short name T91
Test name
Test status
Simulation time 46862809 ps
CPU time 0.7 seconds
Started Apr 04 03:09:27 PM PDT 24
Finished Apr 04 03:09:28 PM PDT 24
Peak memory 196528 kb
Host smart-a18898eb-b430-4ee4-963d-3b004c51507b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855153883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3855153883
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1438121319
Short name T713
Test name
Test status
Simulation time 32148646 ps
CPU time 0.64 seconds
Started Apr 04 03:09:25 PM PDT 24
Finished Apr 04 03:09:26 PM PDT 24
Peak memory 193888 kb
Host smart-d19f45a4-cee2-47d0-bcb8-beda7a120b13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438121319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1438121319
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1937664158
Short name T710
Test name
Test status
Simulation time 48602355 ps
CPU time 1.21 seconds
Started Apr 04 03:09:28 PM PDT 24
Finished Apr 04 03:09:29 PM PDT 24
Peak memory 199020 kb
Host smart-d88c8e15-5adb-40a9-ad6b-769a9a2aa24e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937664158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1937664158
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1309848459
Short name T638
Test name
Test status
Simulation time 474019570 ps
CPU time 3.37 seconds
Started Apr 04 03:09:25 PM PDT 24
Finished Apr 04 03:09:28 PM PDT 24
Peak memory 199112 kb
Host smart-88949638-baca-43bc-8259-615234e99235
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309848459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1309848459
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3794035825
Short name T668
Test name
Test status
Simulation time 620550243 ps
CPU time 1.87 seconds
Started Apr 04 03:09:27 PM PDT 24
Finished Apr 04 03:09:30 PM PDT 24
Peak memory 199068 kb
Host smart-734723c1-e67a-4985-a81f-a6117cc8f6dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794035825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3794035825
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2219681947
Short name T696
Test name
Test status
Simulation time 1859637409 ps
CPU time 8.96 seconds
Started Apr 04 03:08:58 PM PDT 24
Finished Apr 04 03:09:07 PM PDT 24
Peak memory 199028 kb
Host smart-15bb1135-c0e2-43d5-bc53-e07404fcb698
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219681947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.2219681947
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1567324035
Short name T631
Test name
Test status
Simulation time 112467758 ps
CPU time 5.03 seconds
Started Apr 04 03:08:53 PM PDT 24
Finished Apr 04 03:08:59 PM PDT 24
Peak memory 198028 kb
Host smart-11f75e6c-c048-4f67-8032-39802152db5e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567324035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.1567324035
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.754317427
Short name T707
Test name
Test status
Simulation time 25940045 ps
CPU time 0.73 seconds
Started Apr 04 03:08:59 PM PDT 24
Finished Apr 04 03:09:00 PM PDT 24
Peak memory 196408 kb
Host smart-da4cb01c-4cab-4abd-957b-a2d3f9c1cc75
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754317427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.754317427
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3379212031
Short name T615
Test name
Test status
Simulation time 321237293 ps
CPU time 3.04 seconds
Started Apr 04 03:08:59 PM PDT 24
Finished Apr 04 03:09:02 PM PDT 24
Peak memory 214532 kb
Host smart-cc6a6310-4c19-42b1-9e1b-e6f3620c718b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379212031 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3379212031
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.4269855041
Short name T726
Test name
Test status
Simulation time 86515516 ps
CPU time 0.97 seconds
Started Apr 04 03:08:57 PM PDT 24
Finished Apr 04 03:08:58 PM PDT 24
Peak memory 198356 kb
Host smart-3fe6f9a1-bec4-4dbd-8216-0c45052a49a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269855041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.4269855041
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.685296107
Short name T635
Test name
Test status
Simulation time 27986450 ps
CPU time 0.59 seconds
Started Apr 04 03:08:56 PM PDT 24
Finished Apr 04 03:08:56 PM PDT 24
Peak memory 193668 kb
Host smart-c96d82ec-c823-4040-8e37-4080b182b6af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685296107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.685296107
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1174896431
Short name T660
Test name
Test status
Simulation time 35283165 ps
CPU time 1.6 seconds
Started Apr 04 03:08:55 PM PDT 24
Finished Apr 04 03:08:57 PM PDT 24
Peak memory 198976 kb
Host smart-cef16227-9961-4c9a-8621-08e65949f0f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174896431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1174896431
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2924580822
Short name T690
Test name
Test status
Simulation time 241441045 ps
CPU time 2.58 seconds
Started Apr 04 03:08:55 PM PDT 24
Finished Apr 04 03:08:58 PM PDT 24
Peak memory 199052 kb
Host smart-7814f3d6-8712-4cf4-a5cc-e2abbec7ea44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924580822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2924580822
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3903289930
Short name T105
Test name
Test status
Simulation time 212631695 ps
CPU time 2.83 seconds
Started Apr 04 03:08:58 PM PDT 24
Finished Apr 04 03:09:01 PM PDT 24
Peak memory 199132 kb
Host smart-5cda1261-e94d-4489-ba4e-55cc11cb3834
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903289930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3903289930
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2465695877
Short name T611
Test name
Test status
Simulation time 16149282 ps
CPU time 0.63 seconds
Started Apr 04 03:09:28 PM PDT 24
Finished Apr 04 03:09:29 PM PDT 24
Peak memory 193944 kb
Host smart-9026d643-1db2-446d-a836-4cfc749efcbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465695877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2465695877
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1229035487
Short name T724
Test name
Test status
Simulation time 61261126 ps
CPU time 0.56 seconds
Started Apr 04 03:09:28 PM PDT 24
Finished Apr 04 03:09:29 PM PDT 24
Peak memory 193892 kb
Host smart-aba183c9-1eb5-45c0-a3c4-dda44625639f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229035487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1229035487
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.2956564700
Short name T639
Test name
Test status
Simulation time 15575257 ps
CPU time 0.59 seconds
Started Apr 04 03:09:27 PM PDT 24
Finished Apr 04 03:09:28 PM PDT 24
Peak memory 193624 kb
Host smart-8ff89d15-1d63-4d66-9691-f48800558e30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956564700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.2956564700
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.336468224
Short name T642
Test name
Test status
Simulation time 12412149 ps
CPU time 0.59 seconds
Started Apr 04 03:09:26 PM PDT 24
Finished Apr 04 03:09:26 PM PDT 24
Peak memory 193616 kb
Host smart-0e0b8d32-e5a0-4dc9-8529-edeb0f662cd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336468224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.336468224
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2606420982
Short name T610
Test name
Test status
Simulation time 81046947 ps
CPU time 0.6 seconds
Started Apr 04 03:09:28 PM PDT 24
Finished Apr 04 03:09:29 PM PDT 24
Peak memory 193692 kb
Host smart-3bc05e79-e486-439f-a785-82e925c55fa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606420982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2606420982
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.4244693274
Short name T618
Test name
Test status
Simulation time 15363842 ps
CPU time 0.62 seconds
Started Apr 04 03:09:26 PM PDT 24
Finished Apr 04 03:09:26 PM PDT 24
Peak memory 193944 kb
Host smart-794d2e81-8156-412e-b800-2907a8ea5650
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244693274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.4244693274
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3835865140
Short name T672
Test name
Test status
Simulation time 18367576 ps
CPU time 0.61 seconds
Started Apr 04 03:09:26 PM PDT 24
Finished Apr 04 03:09:26 PM PDT 24
Peak memory 193668 kb
Host smart-06794514-f1f2-40ae-85d4-4427a9d94c32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835865140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3835865140
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1922644506
Short name T647
Test name
Test status
Simulation time 14431384 ps
CPU time 0.63 seconds
Started Apr 04 03:09:24 PM PDT 24
Finished Apr 04 03:09:25 PM PDT 24
Peak memory 193684 kb
Host smart-e8233d3f-a6aa-4a9c-b5e3-aa51db7dd546
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922644506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1922644506
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2519703971
Short name T717
Test name
Test status
Simulation time 158230980 ps
CPU time 0.59 seconds
Started Apr 04 03:09:28 PM PDT 24
Finished Apr 04 03:09:28 PM PDT 24
Peak memory 193828 kb
Host smart-6e2a19c1-1dd0-4533-838b-ae4285892b56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519703971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2519703971
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1455320994
Short name T699
Test name
Test status
Simulation time 17976686 ps
CPU time 0.6 seconds
Started Apr 04 03:09:29 PM PDT 24
Finished Apr 04 03:09:30 PM PDT 24
Peak memory 193736 kb
Host smart-93ea0e65-3eb8-40a6-b54d-aea11ca15f0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455320994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1455320994
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.227162116
Short name T53
Test name
Test status
Simulation time 307217500 ps
CPU time 5.95 seconds
Started Apr 04 03:08:55 PM PDT 24
Finished Apr 04 03:09:01 PM PDT 24
Peak memory 199028 kb
Host smart-a1d6f665-45bd-4fb0-8675-0b7955c754f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227162116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.227162116
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2383080312
Short name T84
Test name
Test status
Simulation time 323995221 ps
CPU time 14.48 seconds
Started Apr 04 03:08:55 PM PDT 24
Finished Apr 04 03:09:09 PM PDT 24
Peak memory 197872 kb
Host smart-2f27a9ca-491b-4f4c-90d5-9efbc6bf7c90
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383080312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2383080312
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1618197611
Short name T633
Test name
Test status
Simulation time 44457613 ps
CPU time 1 seconds
Started Apr 04 03:08:56 PM PDT 24
Finished Apr 04 03:08:57 PM PDT 24
Peak memory 198856 kb
Host smart-0eac2a0f-147d-45bd-a0c8-e62e24aadd93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618197611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1618197611
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.843751311
Short name T55
Test name
Test status
Simulation time 42794287 ps
CPU time 1.22 seconds
Started Apr 04 03:08:57 PM PDT 24
Finished Apr 04 03:08:58 PM PDT 24
Peak memory 199128 kb
Host smart-4931f61f-78bd-4258-bb1e-2158ce25324d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843751311 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.843751311
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.812309207
Short name T88
Test name
Test status
Simulation time 41277962 ps
CPU time 0.66 seconds
Started Apr 04 03:08:55 PM PDT 24
Finished Apr 04 03:08:56 PM PDT 24
Peak memory 196768 kb
Host smart-24710af7-7f45-444b-b2a6-bf6c292dd7e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812309207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.812309207
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2515752982
Short name T720
Test name
Test status
Simulation time 16821983 ps
CPU time 0.59 seconds
Started Apr 04 03:08:57 PM PDT 24
Finished Apr 04 03:08:57 PM PDT 24
Peak memory 193924 kb
Host smart-022e8803-0ddc-4009-9275-702075043986
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515752982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2515752982
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3056046859
Short name T736
Test name
Test status
Simulation time 44360724 ps
CPU time 1.19 seconds
Started Apr 04 03:08:57 PM PDT 24
Finished Apr 04 03:08:58 PM PDT 24
Peak memory 197232 kb
Host smart-b130f003-99b2-4148-8527-cf57806e54fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056046859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3056046859
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3912599858
Short name T684
Test name
Test status
Simulation time 237876615 ps
CPU time 3.33 seconds
Started Apr 04 03:08:55 PM PDT 24
Finished Apr 04 03:08:59 PM PDT 24
Peak memory 199140 kb
Host smart-eeece514-cc89-424e-9daf-fa7b70909749
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912599858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.3912599858
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.3791842377
Short name T103
Test name
Test status
Simulation time 144758397 ps
CPU time 3.87 seconds
Started Apr 04 03:08:54 PM PDT 24
Finished Apr 04 03:08:58 PM PDT 24
Peak memory 199056 kb
Host smart-637dbef1-eeb6-4e8d-8dfb-98b7b82e1957
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791842377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.3791842377
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.3484142713
Short name T719
Test name
Test status
Simulation time 98376638 ps
CPU time 0.62 seconds
Started Apr 04 03:09:24 PM PDT 24
Finished Apr 04 03:09:25 PM PDT 24
Peak memory 193732 kb
Host smart-1d4b9690-db89-4b13-afc0-a5afa4822b7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484142713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.3484142713
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.2577286032
Short name T621
Test name
Test status
Simulation time 98776436 ps
CPU time 0.61 seconds
Started Apr 04 03:09:27 PM PDT 24
Finished Apr 04 03:09:28 PM PDT 24
Peak memory 193696 kb
Host smart-83debc5a-f8a7-450e-bc39-298aabb46390
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577286032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2577286032
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3535263721
Short name T735
Test name
Test status
Simulation time 13276833 ps
CPU time 0.6 seconds
Started Apr 04 03:09:24 PM PDT 24
Finished Apr 04 03:09:25 PM PDT 24
Peak memory 193580 kb
Host smart-0d4eb13a-40c0-4e15-9e88-5d42b83b9633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535263721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3535263721
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2010617384
Short name T721
Test name
Test status
Simulation time 16892202 ps
CPU time 0.61 seconds
Started Apr 04 03:09:31 PM PDT 24
Finished Apr 04 03:09:31 PM PDT 24
Peak memory 193728 kb
Host smart-90e20986-eafa-410e-b2ce-f0ef1fa342a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010617384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2010617384
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1935829621
Short name T698
Test name
Test status
Simulation time 36816210 ps
CPU time 0.58 seconds
Started Apr 04 03:09:25 PM PDT 24
Finished Apr 04 03:09:26 PM PDT 24
Peak memory 193672 kb
Host smart-17f4a0a1-293f-4c5e-bdfd-328a1f01d68b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935829621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1935829621
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.301916745
Short name T683
Test name
Test status
Simulation time 51602637 ps
CPU time 0.61 seconds
Started Apr 04 03:09:27 PM PDT 24
Finished Apr 04 03:09:27 PM PDT 24
Peak memory 193640 kb
Host smart-4b1ac38d-c49b-473f-8551-4756968f5e05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301916745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.301916745
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2083430561
Short name T691
Test name
Test status
Simulation time 39782657 ps
CPU time 0.59 seconds
Started Apr 04 03:09:24 PM PDT 24
Finished Apr 04 03:09:25 PM PDT 24
Peak memory 193632 kb
Host smart-ee2f4441-ade3-4970-b9dd-5b6e15d37bc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083430561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2083430561
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.3024071184
Short name T629
Test name
Test status
Simulation time 42861955 ps
CPU time 0.62 seconds
Started Apr 04 03:09:30 PM PDT 24
Finished Apr 04 03:09:31 PM PDT 24
Peak memory 193884 kb
Host smart-8852704d-ef2c-4c97-bda0-2d47d35e452b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024071184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.3024071184
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.524386995
Short name T607
Test name
Test status
Simulation time 30585991 ps
CPU time 0.58 seconds
Started Apr 04 03:09:30 PM PDT 24
Finished Apr 04 03:09:31 PM PDT 24
Peak memory 193648 kb
Host smart-2e463dab-4ad1-4289-b621-e6f573895b1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524386995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.524386995
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1343867191
Short name T694
Test name
Test status
Simulation time 13581166 ps
CPU time 0.57 seconds
Started Apr 04 03:09:26 PM PDT 24
Finished Apr 04 03:09:26 PM PDT 24
Peak memory 193540 kb
Host smart-8db09b47-6630-4365-a487-3631cf58492a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343867191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1343867191
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1926993088
Short name T93
Test name
Test status
Simulation time 687147623 ps
CPU time 3.26 seconds
Started Apr 04 03:09:06 PM PDT 24
Finished Apr 04 03:09:10 PM PDT 24
Peak memory 198100 kb
Host smart-45a89a9d-6c0a-485a-adcb-5daa0113a916
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926993088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1926993088
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3162426138
Short name T718
Test name
Test status
Simulation time 425950756 ps
CPU time 9.86 seconds
Started Apr 04 03:08:55 PM PDT 24
Finished Apr 04 03:09:05 PM PDT 24
Peak memory 197920 kb
Host smart-57fa8c0d-3394-438e-8072-42f9aa8ef800
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162426138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3162426138
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3704628856
Short name T92
Test name
Test status
Simulation time 19395709 ps
CPU time 0.81 seconds
Started Apr 04 03:08:54 PM PDT 24
Finished Apr 04 03:08:55 PM PDT 24
Peak memory 197992 kb
Host smart-960c7e31-d65c-4559-b140-6d01ecc555ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704628856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3704628856
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1518375083
Short name T692
Test name
Test status
Simulation time 147859542 ps
CPU time 1.13 seconds
Started Apr 04 03:09:07 PM PDT 24
Finished Apr 04 03:09:09 PM PDT 24
Peak memory 199008 kb
Host smart-9a63f5e7-853a-41e7-9ea9-76fe551443fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518375083 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1518375083
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2284521266
Short name T85
Test name
Test status
Simulation time 20221945 ps
CPU time 0.69 seconds
Started Apr 04 03:08:55 PM PDT 24
Finished Apr 04 03:08:56 PM PDT 24
Peak memory 196760 kb
Host smart-2142a313-1fee-405a-ba7c-795ed0502f57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284521266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2284521266
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.1290708966
Short name T730
Test name
Test status
Simulation time 13244241 ps
CPU time 0.56 seconds
Started Apr 04 03:08:56 PM PDT 24
Finished Apr 04 03:08:57 PM PDT 24
Peak memory 193724 kb
Host smart-7895150b-327f-47a0-9bc0-6303b59500ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290708966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1290708966
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3004615870
Short name T732
Test name
Test status
Simulation time 159921626 ps
CPU time 2.09 seconds
Started Apr 04 03:08:56 PM PDT 24
Finished Apr 04 03:08:58 PM PDT 24
Peak memory 199080 kb
Host smart-346401e3-65bb-40f5-a7e9-57effd8d7d51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004615870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3004615870
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1511592831
Short name T620
Test name
Test status
Simulation time 121075399 ps
CPU time 3.34 seconds
Started Apr 04 03:08:57 PM PDT 24
Finished Apr 04 03:09:00 PM PDT 24
Peak memory 199004 kb
Host smart-9d1fcba0-7226-4de5-94ff-c9f19b3adbeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511592831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1511592831
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.31458911
Short name T96
Test name
Test status
Simulation time 415010646 ps
CPU time 2.87 seconds
Started Apr 04 03:08:57 PM PDT 24
Finished Apr 04 03:09:00 PM PDT 24
Peak memory 198976 kb
Host smart-63fdfbaf-ba86-4b1a-bfa0-1ed4fabeaf1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31458911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.31458911
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.2532005931
Short name T652
Test name
Test status
Simulation time 38893421 ps
CPU time 0.6 seconds
Started Apr 04 03:09:28 PM PDT 24
Finished Apr 04 03:09:29 PM PDT 24
Peak memory 193916 kb
Host smart-b67b9cdc-6e5b-4f6f-a53e-6591cdfb943a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532005931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2532005931
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2769081258
Short name T617
Test name
Test status
Simulation time 193162043 ps
CPU time 0.63 seconds
Started Apr 04 03:09:25 PM PDT 24
Finished Apr 04 03:09:26 PM PDT 24
Peak memory 193720 kb
Host smart-f65f6339-8176-49f9-a855-569d62ac1a05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769081258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2769081258
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3616327671
Short name T649
Test name
Test status
Simulation time 21660643 ps
CPU time 0.55 seconds
Started Apr 04 03:09:24 PM PDT 24
Finished Apr 04 03:09:24 PM PDT 24
Peak memory 193708 kb
Host smart-503411d1-5e72-4923-bdf9-8b63b5d0c951
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616327671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3616327671
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.1595251243
Short name T641
Test name
Test status
Simulation time 55570489 ps
CPU time 0.61 seconds
Started Apr 04 03:09:25 PM PDT 24
Finished Apr 04 03:09:25 PM PDT 24
Peak memory 193720 kb
Host smart-7e2bb770-109f-414e-98bf-6460ffc4328b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595251243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1595251243
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2072949706
Short name T674
Test name
Test status
Simulation time 12784601 ps
CPU time 0.53 seconds
Started Apr 04 03:09:25 PM PDT 24
Finished Apr 04 03:09:26 PM PDT 24
Peak memory 193660 kb
Host smart-dd41684d-5b5e-4440-b9c6-aec85b5a3691
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072949706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2072949706
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2308173183
Short name T733
Test name
Test status
Simulation time 119360018 ps
CPU time 0.56 seconds
Started Apr 04 03:09:26 PM PDT 24
Finished Apr 04 03:09:27 PM PDT 24
Peak memory 193932 kb
Host smart-da71aea2-bd01-409c-a953-a6f0b329e985
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308173183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2308173183
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.2431084273
Short name T71
Test name
Test status
Simulation time 14077815 ps
CPU time 0.58 seconds
Started Apr 04 03:09:32 PM PDT 24
Finished Apr 04 03:09:34 PM PDT 24
Peak memory 193676 kb
Host smart-5e245a1a-b8a7-42b7-8207-a4d4845c0235
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431084273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2431084273
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.4263442308
Short name T671
Test name
Test status
Simulation time 11039170 ps
CPU time 0.61 seconds
Started Apr 04 03:09:29 PM PDT 24
Finished Apr 04 03:09:30 PM PDT 24
Peak memory 193652 kb
Host smart-414e8857-dbe3-423b-8504-8ce5ed8142e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263442308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.4263442308
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1965312546
Short name T687
Test name
Test status
Simulation time 24118155 ps
CPU time 0.6 seconds
Started Apr 04 03:09:28 PM PDT 24
Finished Apr 04 03:09:29 PM PDT 24
Peak memory 193688 kb
Host smart-45102596-475c-48f2-979a-2d20573d6374
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965312546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1965312546
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.3029906668
Short name T644
Test name
Test status
Simulation time 100855260 ps
CPU time 0.62 seconds
Started Apr 04 03:09:28 PM PDT 24
Finished Apr 04 03:09:29 PM PDT 24
Peak memory 193900 kb
Host smart-fecd30a6-5134-4d06-8ded-af95fb573c7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029906668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3029906668
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3374073198
Short name T667
Test name
Test status
Simulation time 22410377 ps
CPU time 1.2 seconds
Started Apr 04 03:09:08 PM PDT 24
Finished Apr 04 03:09:11 PM PDT 24
Peak memory 199004 kb
Host smart-52a2e7ca-2f3c-4cc5-ba63-18a26ca99b2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374073198 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3374073198
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3305154283
Short name T86
Test name
Test status
Simulation time 16544990 ps
CPU time 0.85 seconds
Started Apr 04 03:08:56 PM PDT 24
Finished Apr 04 03:08:57 PM PDT 24
Peak memory 198864 kb
Host smart-f2702b7b-049f-4866-a2ab-7c68ce16d53b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305154283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3305154283
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2317812062
Short name T612
Test name
Test status
Simulation time 21940207 ps
CPU time 0.58 seconds
Started Apr 04 03:08:57 PM PDT 24
Finished Apr 04 03:08:57 PM PDT 24
Peak memory 193672 kb
Host smart-540d2820-0305-4840-a0f9-478e4566ac98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317812062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2317812062
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.4043437555
Short name T614
Test name
Test status
Simulation time 33460800 ps
CPU time 1.59 seconds
Started Apr 04 03:08:58 PM PDT 24
Finished Apr 04 03:09:00 PM PDT 24
Peak memory 198688 kb
Host smart-468e2dec-5349-4ceb-9b96-c3a1896e74cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043437555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.4043437555
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3794740914
Short name T623
Test name
Test status
Simulation time 260409601 ps
CPU time 1.67 seconds
Started Apr 04 03:09:08 PM PDT 24
Finished Apr 04 03:09:11 PM PDT 24
Peak memory 199144 kb
Host smart-2001d310-f9c1-4397-acfb-96d5d1b3dbca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794740914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3794740914
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1091696961
Short name T97
Test name
Test status
Simulation time 268946976 ps
CPU time 4.48 seconds
Started Apr 04 03:08:57 PM PDT 24
Finished Apr 04 03:09:01 PM PDT 24
Peak memory 199084 kb
Host smart-0a149169-e5cb-4f37-906f-151fcfe8aacd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091696961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1091696961
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.76020890
Short name T626
Test name
Test status
Simulation time 90540040 ps
CPU time 1.68 seconds
Started Apr 04 03:08:56 PM PDT 24
Finished Apr 04 03:08:58 PM PDT 24
Peak memory 199108 kb
Host smart-b9e2ec98-2c27-42e2-867d-55e352a38e23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76020890 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.76020890
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3159806138
Short name T697
Test name
Test status
Simulation time 41978341 ps
CPU time 0.69 seconds
Started Apr 04 03:08:51 PM PDT 24
Finished Apr 04 03:08:51 PM PDT 24
Peak memory 196964 kb
Host smart-020b7f76-a806-451f-aaed-8a9a1bc9ca04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159806138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3159806138
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2455132752
Short name T739
Test name
Test status
Simulation time 17564967 ps
CPU time 0.6 seconds
Started Apr 04 03:09:08 PM PDT 24
Finished Apr 04 03:09:10 PM PDT 24
Peak memory 193932 kb
Host smart-850bef1d-f211-4fe7-8225-8ed50344e25a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455132752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2455132752
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.4066577852
Short name T678
Test name
Test status
Simulation time 1471948494 ps
CPU time 2.31 seconds
Started Apr 04 03:08:52 PM PDT 24
Finished Apr 04 03:08:54 PM PDT 24
Peak memory 199004 kb
Host smart-5cc00f8e-2de0-4e9f-b2bb-65b017198909
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066577852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.4066577852
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2050931292
Short name T708
Test name
Test status
Simulation time 96577008 ps
CPU time 1.92 seconds
Started Apr 04 03:08:55 PM PDT 24
Finished Apr 04 03:08:57 PM PDT 24
Peak memory 199136 kb
Host smart-342e0ba3-f70b-4f58-bac3-0ab1d44905a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050931292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2050931292
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2156166318
Short name T109
Test name
Test status
Simulation time 162842132 ps
CPU time 1.83 seconds
Started Apr 04 03:08:57 PM PDT 24
Finished Apr 04 03:08:59 PM PDT 24
Peak memory 199084 kb
Host smart-b5eb3da5-733b-490c-ab2e-0e2324e05be9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156166318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2156166318
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1466631217
Short name T643
Test name
Test status
Simulation time 91136617577 ps
CPU time 872.17 seconds
Started Apr 04 03:09:14 PM PDT 24
Finished Apr 04 03:23:47 PM PDT 24
Peak memory 215536 kb
Host smart-b30d8594-9bf3-4107-9c4e-e36b8d798d86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466631217 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1466631217
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3479915750
Short name T676
Test name
Test status
Simulation time 85124761 ps
CPU time 0.72 seconds
Started Apr 04 03:09:12 PM PDT 24
Finished Apr 04 03:09:12 PM PDT 24
Peak memory 196868 kb
Host smart-3f81626b-dffc-49d8-89ac-d51ba5c0108a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479915750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3479915750
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1359491703
Short name T680
Test name
Test status
Simulation time 52696297 ps
CPU time 0.61 seconds
Started Apr 04 03:09:13 PM PDT 24
Finished Apr 04 03:09:14 PM PDT 24
Peak memory 193888 kb
Host smart-2e374593-e98f-4821-8ec9-51069c0348d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359491703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1359491703
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2492715415
Short name T686
Test name
Test status
Simulation time 1092378094 ps
CPU time 1.94 seconds
Started Apr 04 03:09:13 PM PDT 24
Finished Apr 04 03:09:15 PM PDT 24
Peak memory 198800 kb
Host smart-eec340fa-5c72-4336-aec1-38577af25f09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492715415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2492715415
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2509338062
Short name T655
Test name
Test status
Simulation time 184411734 ps
CPU time 2.68 seconds
Started Apr 04 03:08:56 PM PDT 24
Finished Apr 04 03:08:59 PM PDT 24
Peak memory 199128 kb
Host smart-8e1b009e-77ec-49d4-a568-746b63255ac2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509338062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2509338062
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2047009752
Short name T51
Test name
Test status
Simulation time 349235457 ps
CPU time 1.77 seconds
Started Apr 04 03:09:06 PM PDT 24
Finished Apr 04 03:09:08 PM PDT 24
Peak memory 199120 kb
Host smart-16d5acc3-80bd-4c2c-b68a-50e1de2ca248
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047009752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2047009752
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.451644768
Short name T664
Test name
Test status
Simulation time 67993214090 ps
CPU time 348.04 seconds
Started Apr 04 03:09:13 PM PDT 24
Finished Apr 04 03:15:01 PM PDT 24
Peak memory 215604 kb
Host smart-2f799a40-3ee8-415d-b29f-77e4591d4e2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451644768 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.451644768
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2823236951
Short name T669
Test name
Test status
Simulation time 119733460 ps
CPU time 0.93 seconds
Started Apr 04 03:09:11 PM PDT 24
Finished Apr 04 03:09:12 PM PDT 24
Peak memory 198336 kb
Host smart-b991b950-d3f2-49d8-8698-dc323b7cbf81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823236951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2823236951
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3702112490
Short name T663
Test name
Test status
Simulation time 39729801 ps
CPU time 0.63 seconds
Started Apr 04 03:09:13 PM PDT 24
Finished Apr 04 03:09:14 PM PDT 24
Peak memory 193928 kb
Host smart-8309094e-76c2-463b-995b-cc4b4706db88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702112490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3702112490
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2338888549
Short name T688
Test name
Test status
Simulation time 230945651 ps
CPU time 2.42 seconds
Started Apr 04 03:09:11 PM PDT 24
Finished Apr 04 03:09:14 PM PDT 24
Peak memory 198672 kb
Host smart-9bca9e6a-2af4-41df-8312-4e065df39b38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338888549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.2338888549
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3813028746
Short name T665
Test name
Test status
Simulation time 231988233 ps
CPU time 3.64 seconds
Started Apr 04 03:09:12 PM PDT 24
Finished Apr 04 03:09:16 PM PDT 24
Peak memory 199160 kb
Host smart-fa88e459-11c7-4196-a380-466c1d5aaeae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813028746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3813028746
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.929300776
Short name T685
Test name
Test status
Simulation time 40349886 ps
CPU time 1.35 seconds
Started Apr 04 03:09:13 PM PDT 24
Finished Apr 04 03:09:15 PM PDT 24
Peak memory 198960 kb
Host smart-c9831415-46a3-406d-a52f-487f64f0ef41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929300776 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.929300776
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1393537654
Short name T651
Test name
Test status
Simulation time 82445874 ps
CPU time 0.69 seconds
Started Apr 04 03:09:15 PM PDT 24
Finished Apr 04 03:09:16 PM PDT 24
Peak memory 196924 kb
Host smart-86983d02-e657-4d3a-b52d-b6bc288baf16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393537654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1393537654
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.3328376965
Short name T609
Test name
Test status
Simulation time 23078453 ps
CPU time 0.57 seconds
Started Apr 04 03:09:10 PM PDT 24
Finished Apr 04 03:09:11 PM PDT 24
Peak memory 193620 kb
Host smart-f09f8d20-145f-446e-92bf-5da02d92a5cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328376965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3328376965
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3078086098
Short name T714
Test name
Test status
Simulation time 552882997 ps
CPU time 2.28 seconds
Started Apr 04 03:09:09 PM PDT 24
Finished Apr 04 03:09:13 PM PDT 24
Peak memory 199052 kb
Host smart-23ed8a0d-0950-4b00-966b-6b764c69c389
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078086098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.3078086098
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.443949988
Short name T637
Test name
Test status
Simulation time 1005393671 ps
CPU time 2.98 seconds
Started Apr 04 03:09:12 PM PDT 24
Finished Apr 04 03:09:15 PM PDT 24
Peak memory 199028 kb
Host smart-a80bd5b7-d3c7-4da4-9fda-2950a51e1c14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443949988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.443949988
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2984595805
Short name T52
Test name
Test status
Simulation time 321560729 ps
CPU time 1.82 seconds
Started Apr 04 03:09:11 PM PDT 24
Finished Apr 04 03:09:13 PM PDT 24
Peak memory 199112 kb
Host smart-1ed1c8d8-5896-4cc4-b64b-f1699f08e7da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984595805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2984595805
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1320268870
Short name T587
Test name
Test status
Simulation time 11322586 ps
CPU time 0.6 seconds
Started Apr 04 12:28:38 PM PDT 24
Finished Apr 04 12:28:39 PM PDT 24
Peak memory 193988 kb
Host smart-aca9e9ed-463b-46b1-b8ab-97a530e59208
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320268870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1320268870
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.1593534112
Short name T415
Test name
Test status
Simulation time 1436444972 ps
CPU time 54.24 seconds
Started Apr 04 12:28:13 PM PDT 24
Finished Apr 04 12:29:08 PM PDT 24
Peak memory 219960 kb
Host smart-43a4feb1-05ae-48e1-acda-a2a6eecce2c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1593534112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.1593534112
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.2808475117
Short name T309
Test name
Test status
Simulation time 1135097496 ps
CPU time 5.65 seconds
Started Apr 04 12:29:22 PM PDT 24
Finished Apr 04 12:29:28 PM PDT 24
Peak memory 199348 kb
Host smart-f80b8453-8e1d-46f0-b46f-8301f82c1730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808475117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2808475117
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.119921036
Short name T175
Test name
Test status
Simulation time 1836713176 ps
CPU time 18.37 seconds
Started Apr 04 12:28:07 PM PDT 24
Finished Apr 04 12:28:26 PM PDT 24
Peak memory 199492 kb
Host smart-37e095e7-c893-400a-8603-cce4703270a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=119921036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.119921036
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1340787475
Short name T523
Test name
Test status
Simulation time 17546164584 ps
CPU time 110.41 seconds
Started Apr 04 12:28:08 PM PDT 24
Finished Apr 04 12:29:59 PM PDT 24
Peak memory 199492 kb
Host smart-739900f5-dda6-4bad-8787-fbbf54cc86ad
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340787475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1340787475
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1716646908
Short name T569
Test name
Test status
Simulation time 1274781582 ps
CPU time 71.21 seconds
Started Apr 04 12:29:21 PM PDT 24
Finished Apr 04 12:30:33 PM PDT 24
Peak memory 199152 kb
Host smart-ae298398-bba7-46b2-81e7-149f2adb3ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716646908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1716646908
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.4084481020
Short name T38
Test name
Test status
Simulation time 102813385 ps
CPU time 2.11 seconds
Started Apr 04 12:27:58 PM PDT 24
Finished Apr 04 12:28:01 PM PDT 24
Peak memory 199444 kb
Host smart-59422603-f1e0-4922-b977-33e366386157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084481020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.4084481020
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.2610430043
Short name T545
Test name
Test status
Simulation time 58495283 ps
CPU time 1.4 seconds
Started Apr 04 12:28:34 PM PDT 24
Finished Apr 04 12:28:35 PM PDT 24
Peak memory 199412 kb
Host smart-3f58c51d-a0f2-4b32-b58b-755a131198b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610430043 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.2610430043
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.3704679385
Short name T317
Test name
Test status
Simulation time 8662650059 ps
CPU time 472.86 seconds
Started Apr 04 12:28:21 PM PDT 24
Finished Apr 04 12:36:14 PM PDT 24
Peak memory 199600 kb
Host smart-c3cc7037-5707-4398-a51f-d11deaf65520
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704679385 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.3704679385
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3670753887
Short name T524
Test name
Test status
Simulation time 30193362962 ps
CPU time 30.06 seconds
Started Apr 04 12:28:15 PM PDT 24
Finished Apr 04 12:28:45 PM PDT 24
Peak memory 199476 kb
Host smart-43f235dd-281c-45ce-a71a-6dade6bf4721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670753887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3670753887
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.440146861
Short name T3
Test name
Test status
Simulation time 13669521 ps
CPU time 0.55 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:28:54 PM PDT 24
Peak memory 194712 kb
Host smart-d3333588-0f6b-4a53-a87b-e3283b545fdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440146861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.440146861
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.1885077545
Short name T196
Test name
Test status
Simulation time 316401397 ps
CPU time 12.12 seconds
Started Apr 04 12:29:45 PM PDT 24
Finished Apr 04 12:29:57 PM PDT 24
Peak memory 230660 kb
Host smart-526fe1e2-44a5-4689-a9bf-8993c09b04f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1885077545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.1885077545
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.77091495
Short name T378
Test name
Test status
Simulation time 320797141 ps
CPU time 6.55 seconds
Started Apr 04 12:29:50 PM PDT 24
Finished Apr 04 12:29:57 PM PDT 24
Peak memory 199520 kb
Host smart-a693762b-7814-49b6-a600-a8db62d40aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77091495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.77091495
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.4208946227
Short name T207
Test name
Test status
Simulation time 3273108810 ps
CPU time 99.74 seconds
Started Apr 04 12:28:48 PM PDT 24
Finished Apr 04 12:30:28 PM PDT 24
Peak memory 199480 kb
Host smart-0e518ad4-d2eb-463e-9a46-d7487e4ff26b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4208946227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.4208946227
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.4061130154
Short name T458
Test name
Test status
Simulation time 14454455223 ps
CPU time 253.06 seconds
Started Apr 04 12:29:16 PM PDT 24
Finished Apr 04 12:33:29 PM PDT 24
Peak memory 199564 kb
Host smart-7b6555ea-24ee-4ee1-b5b8-20662ac94a43
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061130154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.4061130154
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2713610733
Short name T25
Test name
Test status
Simulation time 647670981 ps
CPU time 2.9 seconds
Started Apr 04 12:29:53 PM PDT 24
Finished Apr 04 12:29:56 PM PDT 24
Peak memory 199464 kb
Host smart-ab0f8220-da5f-4c47-ab75-858668a0427e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713610733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2713610733
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.4107529721
Short name T29
Test name
Test status
Simulation time 78675411 ps
CPU time 0.85 seconds
Started Apr 04 12:28:52 PM PDT 24
Finished Apr 04 12:28:53 PM PDT 24
Peak memory 217252 kb
Host smart-99a0f989-dc7d-40cd-be32-6c2b86f22857
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107529721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.4107529721
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3865487250
Short name T211
Test name
Test status
Simulation time 276916006 ps
CPU time 1.94 seconds
Started Apr 04 12:29:41 PM PDT 24
Finished Apr 04 12:29:43 PM PDT 24
Peak memory 199364 kb
Host smart-b80e9499-0f49-4530-8d8c-1081d249dd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865487250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3865487250
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.2475447587
Short name T43
Test name
Test status
Simulation time 78165008225 ps
CPU time 634.29 seconds
Started Apr 04 12:28:52 PM PDT 24
Finished Apr 04 12:39:26 PM PDT 24
Peak memory 198688 kb
Host smart-507f3c4f-aa30-4b19-ab93-c67460f7bfcf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475447587 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2475447587
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.4221858141
Short name T290
Test name
Test status
Simulation time 530531580 ps
CPU time 1.2 seconds
Started Apr 04 12:28:55 PM PDT 24
Finished Apr 04 12:28:56 PM PDT 24
Peak memory 199412 kb
Host smart-1866f4a1-ba03-4e90-be20-b69c5d483cb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221858141 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.4221858141
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.1604781423
Short name T273
Test name
Test status
Simulation time 7774085701 ps
CPU time 408.14 seconds
Started Apr 04 12:29:00 PM PDT 24
Finished Apr 04 12:35:49 PM PDT 24
Peak memory 199576 kb
Host smart-c40ab2ef-edd4-4ad9-a2bf-60cf7cf5419e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604781423 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.1604781423
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.2995789735
Short name T385
Test name
Test status
Simulation time 2942890249 ps
CPU time 54.88 seconds
Started Apr 04 12:29:00 PM PDT 24
Finished Apr 04 12:29:55 PM PDT 24
Peak memory 199656 kb
Host smart-1cf92f3d-a9dd-4ec1-b29b-a34813f437db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995789735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2995789735
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.4081424060
Short name T327
Test name
Test status
Simulation time 35746455 ps
CPU time 0.57 seconds
Started Apr 04 12:31:01 PM PDT 24
Finished Apr 04 12:31:01 PM PDT 24
Peak memory 194928 kb
Host smart-42a1c7e3-3ef7-4c24-9ad3-3ed80f2fbe01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081424060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.4081424060
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1893065592
Short name T496
Test name
Test status
Simulation time 6813420127 ps
CPU time 32.84 seconds
Started Apr 04 12:30:54 PM PDT 24
Finished Apr 04 12:31:27 PM PDT 24
Peak memory 207788 kb
Host smart-1f5e6504-1d2c-4919-9f3b-fe561f6ebedf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1893065592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1893065592
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2424619231
Short name T124
Test name
Test status
Simulation time 3531327423 ps
CPU time 51.41 seconds
Started Apr 04 12:31:44 PM PDT 24
Finished Apr 04 12:32:35 PM PDT 24
Peak memory 199628 kb
Host smart-7112fa70-fa2d-462d-8b60-f68e228e3adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424619231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2424619231
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1992335288
Short name T244
Test name
Test status
Simulation time 1570319633 ps
CPU time 90.23 seconds
Started Apr 04 12:30:40 PM PDT 24
Finished Apr 04 12:32:11 PM PDT 24
Peak memory 199396 kb
Host smart-6e9e18a9-16f0-48ff-9d27-f28e7e811071
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1992335288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1992335288
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.1557540331
Short name T511
Test name
Test status
Simulation time 29856149939 ps
CPU time 122.92 seconds
Started Apr 04 12:30:39 PM PDT 24
Finished Apr 04 12:32:42 PM PDT 24
Peak memory 199636 kb
Host smart-36fdbe4a-a1fc-4d5c-b7df-e09e3d1bcf0e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557540331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1557540331
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.1533449818
Short name T239
Test name
Test status
Simulation time 5260518268 ps
CPU time 89.05 seconds
Started Apr 04 12:30:38 PM PDT 24
Finished Apr 04 12:32:07 PM PDT 24
Peak memory 199636 kb
Host smart-2a3ce26b-e5b9-4d69-8c11-cfa13df3948a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533449818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1533449818
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.4009161622
Short name T242
Test name
Test status
Simulation time 476493259 ps
CPU time 7.27 seconds
Started Apr 04 12:30:28 PM PDT 24
Finished Apr 04 12:30:36 PM PDT 24
Peak memory 199476 kb
Host smart-dcefb8f4-84e8-48cc-818e-ddaba264062b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009161622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.4009161622
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1032316130
Short name T554
Test name
Test status
Simulation time 104180168174 ps
CPU time 1399.62 seconds
Started Apr 04 12:30:31 PM PDT 24
Finished Apr 04 12:53:51 PM PDT 24
Peak memory 215940 kb
Host smart-f920abdd-ca64-460f-989e-ef0b477111e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032316130 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1032316130
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.2887362846
Short name T318
Test name
Test status
Simulation time 213530056 ps
CPU time 1.24 seconds
Started Apr 04 12:30:42 PM PDT 24
Finished Apr 04 12:30:43 PM PDT 24
Peak memory 199424 kb
Host smart-3c1584a8-a716-46af-9233-b259a4fd5267
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887362846 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.2887362846
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.206322339
Short name T230
Test name
Test status
Simulation time 117472136265 ps
CPU time 460.8 seconds
Started Apr 04 12:30:32 PM PDT 24
Finished Apr 04 12:38:13 PM PDT 24
Peak memory 199600 kb
Host smart-32376a3e-8cf2-4e8b-9694-87906f1855d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206322339 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.206322339
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.3678220839
Short name T595
Test name
Test status
Simulation time 15451956087 ps
CPU time 51.09 seconds
Started Apr 04 12:30:41 PM PDT 24
Finished Apr 04 12:31:32 PM PDT 24
Peak memory 199656 kb
Host smart-cbfe3a96-0f2c-4771-bdf3-80a293ce3fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678220839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.3678220839
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3103708221
Short name T352
Test name
Test status
Simulation time 26987278 ps
CPU time 0.61 seconds
Started Apr 04 12:30:41 PM PDT 24
Finished Apr 04 12:30:42 PM PDT 24
Peak memory 195192 kb
Host smart-560ccf2b-f2d2-4c59-bf3a-3ebbbf60c0f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103708221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3103708221
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1800320289
Short name T328
Test name
Test status
Simulation time 2344049352 ps
CPU time 36.18 seconds
Started Apr 04 12:31:48 PM PDT 24
Finished Apr 04 12:32:24 PM PDT 24
Peak memory 208124 kb
Host smart-6c28c6ba-3c7e-4334-b269-e075e0dde6be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1800320289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1800320289
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.2961237482
Short name T372
Test name
Test status
Simulation time 8257616484 ps
CPU time 27.93 seconds
Started Apr 04 12:30:53 PM PDT 24
Finished Apr 04 12:31:21 PM PDT 24
Peak memory 199480 kb
Host smart-caa3fa00-7c3d-4a58-a7ee-2251a6359f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961237482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.2961237482
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.2482727204
Short name T329
Test name
Test status
Simulation time 238831125 ps
CPU time 13.2 seconds
Started Apr 04 12:30:36 PM PDT 24
Finished Apr 04 12:30:49 PM PDT 24
Peak memory 199460 kb
Host smart-9e409f1d-4206-4ed1-904d-865f087e704c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2482727204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2482727204
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.4196494497
Short name T21
Test name
Test status
Simulation time 12499945597 ps
CPU time 171.54 seconds
Started Apr 04 12:30:38 PM PDT 24
Finished Apr 04 12:33:30 PM PDT 24
Peak memory 199668 kb
Host smart-61e3fb27-7a98-4e2d-8844-18c6ff6dbdca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196494497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.4196494497
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3826503454
Short name T514
Test name
Test status
Simulation time 479480290 ps
CPU time 28.26 seconds
Started Apr 04 12:30:36 PM PDT 24
Finished Apr 04 12:31:05 PM PDT 24
Peak memory 199456 kb
Host smart-51b5bc57-70bc-4b31-a7f8-7106e76803fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826503454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3826503454
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2424620994
Short name T330
Test name
Test status
Simulation time 716884317 ps
CPU time 5.49 seconds
Started Apr 04 12:30:31 PM PDT 24
Finished Apr 04 12:30:37 PM PDT 24
Peak memory 199528 kb
Host smart-acc65a40-c4d1-4436-9930-e2f9b62a3623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424620994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2424620994
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.772956614
Short name T46
Test name
Test status
Simulation time 156149899756 ps
CPU time 1209.7 seconds
Started Apr 04 12:30:25 PM PDT 24
Finished Apr 04 12:50:36 PM PDT 24
Peak memory 234624 kb
Host smart-e68214e1-135b-4ad2-9ae0-f15d78c0d225
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772956614 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.772956614
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.578054929
Short name T34
Test name
Test status
Simulation time 32208177 ps
CPU time 1.22 seconds
Started Apr 04 12:30:53 PM PDT 24
Finished Apr 04 12:30:54 PM PDT 24
Peak memory 199412 kb
Host smart-e7ff1461-8373-4e12-8880-a114bfd1a9ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578054929 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_test_hmac_vectors.578054929
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.3726365289
Short name T295
Test name
Test status
Simulation time 13897921548 ps
CPU time 395.71 seconds
Started Apr 04 12:30:38 PM PDT 24
Finished Apr 04 12:37:14 PM PDT 24
Peak memory 199636 kb
Host smart-cf319d96-169f-4867-9a6f-bdf29b7dd8f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726365289 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.3726365289
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2919121361
Short name T363
Test name
Test status
Simulation time 1499997190 ps
CPU time 7.1 seconds
Started Apr 04 12:30:37 PM PDT 24
Finished Apr 04 12:30:44 PM PDT 24
Peak memory 199540 kb
Host smart-682808f7-9587-4275-969a-31eccc5a6708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919121361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2919121361
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1920065813
Short name T494
Test name
Test status
Simulation time 11971074 ps
CPU time 0.59 seconds
Started Apr 04 12:30:46 PM PDT 24
Finished Apr 04 12:30:47 PM PDT 24
Peak memory 194984 kb
Host smart-7d6bc9f3-100f-4a42-9558-21c32c979acf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920065813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1920065813
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1117586999
Short name T604
Test name
Test status
Simulation time 2259643056 ps
CPU time 44.88 seconds
Started Apr 04 12:30:37 PM PDT 24
Finished Apr 04 12:31:22 PM PDT 24
Peak memory 238616 kb
Host smart-687e60b9-ec41-4aa2-bfc8-0c8ec02f22bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1117586999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1117586999
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.294790714
Short name T216
Test name
Test status
Simulation time 960212606 ps
CPU time 18.17 seconds
Started Apr 04 12:30:44 PM PDT 24
Finished Apr 04 12:31:07 PM PDT 24
Peak memory 199496 kb
Host smart-c56675d9-d33b-4ffa-baa7-8b9b0a120356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294790714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.294790714
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.4015310385
Short name T388
Test name
Test status
Simulation time 1373418851 ps
CPU time 53.16 seconds
Started Apr 04 12:30:50 PM PDT 24
Finished Apr 04 12:31:43 PM PDT 24
Peak memory 199460 kb
Host smart-ebb5c8c8-7f56-48d2-836d-d8a692060de7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4015310385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.4015310385
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2132433816
Short name T22
Test name
Test status
Simulation time 2369884710 ps
CPU time 122.56 seconds
Started Apr 04 12:30:48 PM PDT 24
Finished Apr 04 12:32:51 PM PDT 24
Peak memory 199592 kb
Host smart-79bab018-d5b0-4c20-bf98-4a74be382992
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132433816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2132433816
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.250592605
Short name T64
Test name
Test status
Simulation time 14693173801 ps
CPU time 50.78 seconds
Started Apr 04 12:30:53 PM PDT 24
Finished Apr 04 12:31:44 PM PDT 24
Peak memory 199544 kb
Host smart-fa4ae290-3752-48a3-9656-0531872f4f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250592605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.250592605
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.2867202684
Short name T432
Test name
Test status
Simulation time 351686481 ps
CPU time 4.25 seconds
Started Apr 04 12:30:37 PM PDT 24
Finished Apr 04 12:30:42 PM PDT 24
Peak memory 199552 kb
Host smart-1c913d02-2f7f-4c1c-900d-221a96076487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867202684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2867202684
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3316987396
Short name T599
Test name
Test status
Simulation time 562100838 ps
CPU time 2.3 seconds
Started Apr 04 12:30:38 PM PDT 24
Finished Apr 04 12:30:40 PM PDT 24
Peak memory 199448 kb
Host smart-ec755034-97aa-4e9e-b14c-d6f59b47d3ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316987396 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3316987396
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.3294511045
Short name T319
Test name
Test status
Simulation time 791908491 ps
CPU time 1.02 seconds
Started Apr 04 12:30:42 PM PDT 24
Finished Apr 04 12:30:44 PM PDT 24
Peak memory 198676 kb
Host smart-787764a0-6080-4b7d-9ed0-eda776fb043d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294511045 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.3294511045
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.3942618014
Short name T178
Test name
Test status
Simulation time 79289924639 ps
CPU time 452.45 seconds
Started Apr 04 12:30:32 PM PDT 24
Finished Apr 04 12:38:04 PM PDT 24
Peak memory 199564 kb
Host smart-6b249671-f446-4119-bf67-3ff125918dd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942618014 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.3942618014
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2783773651
Short name T438
Test name
Test status
Simulation time 3549232138 ps
CPU time 40.76 seconds
Started Apr 04 12:30:51 PM PDT 24
Finished Apr 04 12:31:32 PM PDT 24
Peak memory 199572 kb
Host smart-39478919-7958-4631-88ef-4a552293e185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783773651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2783773651
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/124.hmac_stress_all_with_rand_reset.3408060125
Short name T19
Test name
Test status
Simulation time 17173378711 ps
CPU time 322.19 seconds
Started Apr 04 12:31:57 PM PDT 24
Finished Apr 04 12:37:20 PM PDT 24
Peak memory 216136 kb
Host smart-8e048d7d-9892-40a2-9d0a-685fb5dfb8c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3408060125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.hmac_stress_all_with_rand_reset.3408060125
Directory /workspace/124.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1058981570
Short name T339
Test name
Test status
Simulation time 18421469 ps
CPU time 0.58 seconds
Started Apr 04 12:30:57 PM PDT 24
Finished Apr 04 12:30:58 PM PDT 24
Peak memory 194772 kb
Host smart-96a5c8ce-5b44-4e4c-8259-eaeeb79137e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058981570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1058981570
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3566020783
Short name T49
Test name
Test status
Simulation time 289969884 ps
CPU time 8.25 seconds
Started Apr 04 12:30:41 PM PDT 24
Finished Apr 04 12:30:49 PM PDT 24
Peak memory 207692 kb
Host smart-495a63db-4f2b-43a9-8f35-8805e634a2e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3566020783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3566020783
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1831982380
Short name T539
Test name
Test status
Simulation time 174400885 ps
CPU time 8.22 seconds
Started Apr 04 12:30:37 PM PDT 24
Finished Apr 04 12:30:46 PM PDT 24
Peak memory 199460 kb
Host smart-f7c990e5-091d-4c2a-93bd-6099806bb6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831982380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1831982380
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1919804585
Short name T597
Test name
Test status
Simulation time 2153979062 ps
CPU time 126.4 seconds
Started Apr 04 12:30:29 PM PDT 24
Finished Apr 04 12:32:36 PM PDT 24
Peak memory 199496 kb
Host smart-4b42c678-6a6e-4fd1-9c67-08f4f0887577
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1919804585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1919804585
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2316714853
Short name T272
Test name
Test status
Simulation time 12558139233 ps
CPU time 53.79 seconds
Started Apr 04 12:30:54 PM PDT 24
Finished Apr 04 12:31:48 PM PDT 24
Peak memory 199608 kb
Host smart-2de596c9-6b79-42b3-9fbb-774e3de9491a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316714853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2316714853
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.672346339
Short name T585
Test name
Test status
Simulation time 8950647115 ps
CPU time 29.61 seconds
Started Apr 04 12:30:46 PM PDT 24
Finished Apr 04 12:31:16 PM PDT 24
Peak memory 199536 kb
Host smart-340c1784-12f7-48b4-89c7-42debbf3676f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672346339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.672346339
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1143331974
Short name T223
Test name
Test status
Simulation time 199879840 ps
CPU time 5.82 seconds
Started Apr 04 12:30:46 PM PDT 24
Finished Apr 04 12:30:53 PM PDT 24
Peak memory 199444 kb
Host smart-273b4ded-166f-4e8f-ad16-db131377c565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143331974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1143331974
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.764093487
Short name T367
Test name
Test status
Simulation time 40934097653 ps
CPU time 2145.27 seconds
Started Apr 04 12:30:39 PM PDT 24
Finished Apr 04 01:06:25 PM PDT 24
Peak memory 215312 kb
Host smart-46de7a84-651a-4530-946e-26b852b67eaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764093487 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.764093487
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_stress_all_with_rand_reset.217624536
Short name T41
Test name
Test status
Simulation time 9515278119 ps
CPU time 496.87 seconds
Started Apr 04 12:30:55 PM PDT 24
Finished Apr 04 12:39:12 PM PDT 24
Peak memory 225752 kb
Host smart-6dc5ed56-71d8-4180-b747-bde50ab7e35f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=217624536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all_with_rand_reset.217624536
Directory /workspace/13.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.4145741209
Short name T556
Test name
Test status
Simulation time 67267384 ps
CPU time 1.3 seconds
Started Apr 04 12:30:37 PM PDT 24
Finished Apr 04 12:30:38 PM PDT 24
Peak memory 199372 kb
Host smart-c6617a83-729e-4e2c-b9c6-b1e95a891aad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145741209 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.4145741209
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.3179398259
Short name T577
Test name
Test status
Simulation time 34785231142 ps
CPU time 428.41 seconds
Started Apr 04 12:30:56 PM PDT 24
Finished Apr 04 12:38:05 PM PDT 24
Peak memory 199580 kb
Host smart-b2103ad3-fa8a-40e2-ac6c-1b8913ad9417
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179398259 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.3179398259
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.1607867766
Short name T364
Test name
Test status
Simulation time 415021917 ps
CPU time 8.01 seconds
Started Apr 04 12:30:37 PM PDT 24
Finished Apr 04 12:30:46 PM PDT 24
Peak memory 199416 kb
Host smart-16ed99fb-b21a-4e05-9e79-a8f19d6221ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607867766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.1607867766
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/132.hmac_stress_all_with_rand_reset.4122302136
Short name T75
Test name
Test status
Simulation time 508222731818 ps
CPU time 1226.17 seconds
Started Apr 04 12:33:28 PM PDT 24
Finished Apr 04 12:53:54 PM PDT 24
Peak memory 230188 kb
Host smart-15504fbc-6da3-4598-80e6-03237038f4bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4122302136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.hmac_stress_all_with_rand_reset.4122302136
Directory /workspace/132.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2693200612
Short name T448
Test name
Test status
Simulation time 850906784 ps
CPU time 33.97 seconds
Started Apr 04 12:32:10 PM PDT 24
Finished Apr 04 12:32:44 PM PDT 24
Peak memory 222008 kb
Host smart-2d025e53-e034-439c-a70e-615889bd140c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2693200612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2693200612
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.4024729763
Short name T444
Test name
Test status
Simulation time 116468226 ps
CPU time 1.24 seconds
Started Apr 04 12:30:56 PM PDT 24
Finished Apr 04 12:30:57 PM PDT 24
Peak memory 199516 kb
Host smart-9d27aa77-a596-4aa7-b537-ffee8f76eaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024729763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.4024729763
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.911547721
Short name T548
Test name
Test status
Simulation time 8009275151 ps
CPU time 124.14 seconds
Started Apr 04 12:30:45 PM PDT 24
Finished Apr 04 12:32:50 PM PDT 24
Peak memory 199588 kb
Host smart-49c31aa6-1094-4182-a0dc-035311bd7368
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=911547721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.911547721
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.4169831192
Short name T395
Test name
Test status
Simulation time 1297758351 ps
CPU time 6.54 seconds
Started Apr 04 12:30:40 PM PDT 24
Finished Apr 04 12:30:46 PM PDT 24
Peak memory 199468 kb
Host smart-5ad8fdc9-2b3b-4db8-910d-ab9cc112bfd6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169831192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.4169831192
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.2258309185
Short name T341
Test name
Test status
Simulation time 5510300932 ps
CPU time 19.71 seconds
Started Apr 04 12:32:06 PM PDT 24
Finished Apr 04 12:32:26 PM PDT 24
Peak memory 199640 kb
Host smart-7f88216b-78e2-427f-883a-29ecebcaba02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258309185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2258309185
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.2007768987
Short name T198
Test name
Test status
Simulation time 2595696984 ps
CPU time 7.29 seconds
Started Apr 04 12:30:38 PM PDT 24
Finished Apr 04 12:30:46 PM PDT 24
Peak memory 199652 kb
Host smart-2d7841bc-5cd8-4b7c-81fa-3a7d861aa170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007768987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2007768987
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2293199171
Short name T214
Test name
Test status
Simulation time 4128765327 ps
CPU time 26.68 seconds
Started Apr 04 12:31:15 PM PDT 24
Finished Apr 04 12:31:42 PM PDT 24
Peak memory 199600 kb
Host smart-5c5ad0ea-ce6b-4ef9-bf25-b4d4c5d0e7c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293199171 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2293199171
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.3056943875
Short name T575
Test name
Test status
Simulation time 97747455 ps
CPU time 1.17 seconds
Started Apr 04 12:31:29 PM PDT 24
Finished Apr 04 12:31:30 PM PDT 24
Peak memory 199204 kb
Host smart-c2e5fa48-c041-4c79-ad4d-0f7861daaecd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056943875 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.3056943875
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.3506634595
Short name T408
Test name
Test status
Simulation time 154625636522 ps
CPU time 528.24 seconds
Started Apr 04 12:30:51 PM PDT 24
Finished Apr 04 12:39:40 PM PDT 24
Peak memory 199644 kb
Host smart-0094b6e4-838d-4644-a33f-365c58bea2fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506634595 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.3506634595
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.939658054
Short name T459
Test name
Test status
Simulation time 1581681777 ps
CPU time 14.29 seconds
Started Apr 04 12:31:25 PM PDT 24
Finished Apr 04 12:31:40 PM PDT 24
Peak memory 199440 kb
Host smart-1c968c4f-9752-42f4-8344-3abd866721e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939658054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.939658054
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.3844918218
Short name T566
Test name
Test status
Simulation time 38329046 ps
CPU time 0.56 seconds
Started Apr 04 12:30:51 PM PDT 24
Finished Apr 04 12:30:51 PM PDT 24
Peak memory 194952 kb
Host smart-49c4c71f-f3e3-4b4e-a708-c731f9343361
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844918218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3844918218
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1930607486
Short name T529
Test name
Test status
Simulation time 16458931960 ps
CPU time 62.27 seconds
Started Apr 04 12:30:39 PM PDT 24
Finished Apr 04 12:31:42 PM PDT 24
Peak memory 224280 kb
Host smart-4d2c544c-a786-46fa-b223-f1d02861d524
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1930607486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1930607486
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2991114124
Short name T517
Test name
Test status
Simulation time 1186878975 ps
CPU time 59.93 seconds
Started Apr 04 12:30:52 PM PDT 24
Finished Apr 04 12:31:52 PM PDT 24
Peak memory 199564 kb
Host smart-ecf585e7-ea8f-4aec-ad2f-fda6b5d19c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991114124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2991114124
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1573867213
Short name T379
Test name
Test status
Simulation time 1637024160 ps
CPU time 87.41 seconds
Started Apr 04 12:30:55 PM PDT 24
Finished Apr 04 12:32:23 PM PDT 24
Peak memory 199452 kb
Host smart-50fc28c8-d89e-4fae-a182-b846b733d70a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1573867213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1573867213
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2857499215
Short name T252
Test name
Test status
Simulation time 8688468453 ps
CPU time 26.23 seconds
Started Apr 04 12:30:41 PM PDT 24
Finished Apr 04 12:31:07 PM PDT 24
Peak memory 199640 kb
Host smart-c02b8a6e-a562-4819-b1cd-f6360251a4d2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857499215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2857499215
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2488067268
Short name T275
Test name
Test status
Simulation time 7763580461 ps
CPU time 30.23 seconds
Started Apr 04 12:30:36 PM PDT 24
Finished Apr 04 12:31:06 PM PDT 24
Peak memory 199592 kb
Host smart-c5238a65-e470-40bf-8fe8-970b6d2a5e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488067268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2488067268
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2678965587
Short name T218
Test name
Test status
Simulation time 144223472 ps
CPU time 2.59 seconds
Started Apr 04 12:30:54 PM PDT 24
Finished Apr 04 12:30:57 PM PDT 24
Peak memory 199548 kb
Host smart-e1e935f0-9bef-4f18-a0fa-31e8e40d8673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678965587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2678965587
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.793909146
Short name T453
Test name
Test status
Simulation time 19428942928 ps
CPU time 204.46 seconds
Started Apr 04 12:31:10 PM PDT 24
Finished Apr 04 12:34:35 PM PDT 24
Peak memory 231104 kb
Host smart-9cb38e64-2899-426d-bff8-b976da2bd660
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793909146 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.793909146
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.3835934333
Short name T428
Test name
Test status
Simulation time 57682586 ps
CPU time 1.23 seconds
Started Apr 04 12:30:53 PM PDT 24
Finished Apr 04 12:30:55 PM PDT 24
Peak memory 199456 kb
Host smart-a2204ac4-eed3-4f34-aae8-08767b232d41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835934333 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.3835934333
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.1831524189
Short name T467
Test name
Test status
Simulation time 28192565764 ps
CPU time 485.55 seconds
Started Apr 04 12:30:38 PM PDT 24
Finished Apr 04 12:38:43 PM PDT 24
Peak memory 199568 kb
Host smart-6b2ba594-f888-443b-999a-4951823b5595
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831524189 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.1831524189
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.4077621954
Short name T133
Test name
Test status
Simulation time 2236295884 ps
CPU time 22.69 seconds
Started Apr 04 12:30:55 PM PDT 24
Finished Apr 04 12:31:18 PM PDT 24
Peak memory 199580 kb
Host smart-13e1b2f8-8001-4b90-b028-971fbd74b697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077621954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.4077621954
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/154.hmac_stress_all_with_rand_reset.2760285006
Short name T57
Test name
Test status
Simulation time 41160223184 ps
CPU time 1063.23 seconds
Started Apr 04 12:32:05 PM PDT 24
Finished Apr 04 12:49:48 PM PDT 24
Peak memory 243844 kb
Host smart-7ae3b364-2949-4955-95d8-e912aa6bea5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2760285006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.hmac_stress_all_with_rand_reset.2760285006
Directory /workspace/154.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2698072894
Short name T495
Test name
Test status
Simulation time 42266538 ps
CPU time 0.61 seconds
Started Apr 04 12:30:55 PM PDT 24
Finished Apr 04 12:30:56 PM PDT 24
Peak memory 195124 kb
Host smart-04b9b3b7-bd1c-4ff4-b883-f0a42bf3a541
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698072894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2698072894
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.3940374406
Short name T451
Test name
Test status
Simulation time 1072912836 ps
CPU time 39.44 seconds
Started Apr 04 12:31:27 PM PDT 24
Finished Apr 04 12:32:07 PM PDT 24
Peak memory 207628 kb
Host smart-18d9ec97-4972-4edc-9c76-f9833252c4ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3940374406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.3940374406
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1135770800
Short name T596
Test name
Test status
Simulation time 778395305 ps
CPU time 11.29 seconds
Started Apr 04 12:30:40 PM PDT 24
Finished Apr 04 12:30:51 PM PDT 24
Peak memory 199592 kb
Host smart-79f902d8-0384-43e8-9a28-13cae8980026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135770800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1135770800
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.1401259560
Short name T357
Test name
Test status
Simulation time 8064397225 ps
CPU time 111.74 seconds
Started Apr 04 12:30:40 PM PDT 24
Finished Apr 04 12:32:32 PM PDT 24
Peak memory 199644 kb
Host smart-f71e10b1-575c-47ea-b767-28215eee99f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1401259560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1401259560
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.4022686143
Short name T236
Test name
Test status
Simulation time 531336969 ps
CPU time 7.27 seconds
Started Apr 04 12:30:59 PM PDT 24
Finished Apr 04 12:31:07 PM PDT 24
Peak memory 199492 kb
Host smart-911b4b86-0b77-4f93-87e8-c7475c72bc6e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022686143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.4022686143
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1097006925
Short name T261
Test name
Test status
Simulation time 3062389153 ps
CPU time 87.12 seconds
Started Apr 04 12:30:42 PM PDT 24
Finished Apr 04 12:32:09 PM PDT 24
Peak memory 199580 kb
Host smart-dc50747d-eda9-4997-98b0-f5777e63e3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097006925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1097006925
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.764449112
Short name T158
Test name
Test status
Simulation time 1666783570 ps
CPU time 5.4 seconds
Started Apr 04 12:30:37 PM PDT 24
Finished Apr 04 12:30:42 PM PDT 24
Peak memory 199436 kb
Host smart-c7b9e34e-5994-4e31-92b8-3eaad09edd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764449112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.764449112
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.2732974608
Short name T131
Test name
Test status
Simulation time 12870851740 ps
CPU time 255.88 seconds
Started Apr 04 12:30:58 PM PDT 24
Finished Apr 04 12:35:15 PM PDT 24
Peak memory 199568 kb
Host smart-a860fce0-b027-4774-af33-615e40f89a91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732974608 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2732974608
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.2754963001
Short name T82
Test name
Test status
Simulation time 34160798 ps
CPU time 1.07 seconds
Started Apr 04 12:30:53 PM PDT 24
Finished Apr 04 12:30:54 PM PDT 24
Peak memory 199052 kb
Host smart-f709fb82-d79b-43d8-9b80-a4d2d9538d41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754963001 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.2754963001
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.2025582744
Short name T417
Test name
Test status
Simulation time 151858444056 ps
CPU time 479.18 seconds
Started Apr 04 12:30:56 PM PDT 24
Finished Apr 04 12:38:55 PM PDT 24
Peak memory 199600 kb
Host smart-ec3a0a04-21a2-43e4-9bb4-8b7556594d1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025582744 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.2025582744
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3917406756
Short name T277
Test name
Test status
Simulation time 6004773188 ps
CPU time 62.99 seconds
Started Apr 04 12:30:41 PM PDT 24
Finished Apr 04 12:31:44 PM PDT 24
Peak memory 199480 kb
Host smart-4bb49e4c-4cbf-4cce-860b-4e39689c760b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917406756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3917406756
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/166.hmac_stress_all_with_rand_reset.3643456129
Short name T56
Test name
Test status
Simulation time 158079944724 ps
CPU time 1194.23 seconds
Started Apr 04 12:33:28 PM PDT 24
Finished Apr 04 12:53:22 PM PDT 24
Peak memory 248080 kb
Host smart-54cbeb8c-5c0a-4ece-9b0d-7b976670e0ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3643456129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.hmac_stress_all_with_rand_reset.3643456129
Directory /workspace/166.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3037775090
Short name T63
Test name
Test status
Simulation time 13449225 ps
CPU time 0.61 seconds
Started Apr 04 12:30:52 PM PDT 24
Finished Apr 04 12:30:53 PM PDT 24
Peak memory 195100 kb
Host smart-eb3b21e6-f814-4924-be31-585a11f8bbb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037775090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3037775090
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3609179528
Short name T591
Test name
Test status
Simulation time 1058266646 ps
CPU time 5.49 seconds
Started Apr 04 12:30:42 PM PDT 24
Finished Apr 04 12:30:48 PM PDT 24
Peak memory 199460 kb
Host smart-7b9a8c4a-0a9f-4814-bffb-d52952164873
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3609179528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3609179528
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.34388646
Short name T452
Test name
Test status
Simulation time 374656268 ps
CPU time 2.28 seconds
Started Apr 04 12:31:04 PM PDT 24
Finished Apr 04 12:31:07 PM PDT 24
Peak memory 199472 kb
Host smart-26872c5f-593e-4aaa-934a-56880ad49694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34388646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.34388646
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.1264267281
Short name T225
Test name
Test status
Simulation time 11997438866 ps
CPU time 86.01 seconds
Started Apr 04 12:30:54 PM PDT 24
Finished Apr 04 12:32:20 PM PDT 24
Peak memory 199588 kb
Host smart-01113bbb-e815-4f93-bf3c-fd0657162d06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1264267281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1264267281
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.4043522236
Short name T205
Test name
Test status
Simulation time 35659035777 ps
CPU time 319.86 seconds
Started Apr 04 12:32:25 PM PDT 24
Finished Apr 04 12:37:45 PM PDT 24
Peak memory 199600 kb
Host smart-d78ff032-807b-44a4-b059-02e4599172a7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043522236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.4043522236
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2823326097
Short name T337
Test name
Test status
Simulation time 24554893783 ps
CPU time 80.81 seconds
Started Apr 04 12:31:20 PM PDT 24
Finished Apr 04 12:32:41 PM PDT 24
Peak memory 199568 kb
Host smart-a94b429e-ddd7-4a2b-8226-6edc66e56117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823326097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2823326097
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.1703176486
Short name T449
Test name
Test status
Simulation time 167323955 ps
CPU time 1.47 seconds
Started Apr 04 12:31:04 PM PDT 24
Finished Apr 04 12:31:05 PM PDT 24
Peak memory 199504 kb
Host smart-522257d6-5476-4f41-95f5-763ae9269715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703176486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.1703176486
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2344231635
Short name T307
Test name
Test status
Simulation time 4526093911 ps
CPU time 221.04 seconds
Started Apr 04 12:31:20 PM PDT 24
Finished Apr 04 12:35:01 PM PDT 24
Peak memory 215952 kb
Host smart-47d0af63-0323-40e4-9474-bc94f6bbccc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344231635 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2344231635
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.1269929307
Short name T553
Test name
Test status
Simulation time 55458652 ps
CPU time 1.09 seconds
Started Apr 04 12:31:03 PM PDT 24
Finished Apr 04 12:31:04 PM PDT 24
Peak memory 198672 kb
Host smart-4b961bca-ee6d-4d77-b076-f94f3e9eba12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269929307 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.1269929307
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.2842603249
Short name T193
Test name
Test status
Simulation time 29079883467 ps
CPU time 483.96 seconds
Started Apr 04 12:30:39 PM PDT 24
Finished Apr 04 12:38:44 PM PDT 24
Peak memory 199604 kb
Host smart-43ce1204-e8c2-4d19-a42a-a4167e08077b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842603249 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.2842603249
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.2580104112
Short name T148
Test name
Test status
Simulation time 162728670 ps
CPU time 8.81 seconds
Started Apr 04 12:31:16 PM PDT 24
Finished Apr 04 12:31:25 PM PDT 24
Peak memory 199456 kb
Host smart-f5c31257-aa99-4388-82f2-ad9029d37e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580104112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.2580104112
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3474286546
Short name T185
Test name
Test status
Simulation time 36784432 ps
CPU time 0.65 seconds
Started Apr 04 12:31:12 PM PDT 24
Finished Apr 04 12:31:13 PM PDT 24
Peak memory 195096 kb
Host smart-fae21207-c7b7-4bd2-9046-d2567cb878ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474286546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3474286546
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1833321260
Short name T32
Test name
Test status
Simulation time 1056028806 ps
CPU time 39.22 seconds
Started Apr 04 12:30:38 PM PDT 24
Finished Apr 04 12:31:17 PM PDT 24
Peak memory 207664 kb
Host smart-65f82c94-46c5-41b4-acf7-70bfa9957d8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1833321260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1833321260
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.4081127253
Short name T447
Test name
Test status
Simulation time 1959646549 ps
CPU time 11.57 seconds
Started Apr 04 12:31:30 PM PDT 24
Finished Apr 04 12:31:42 PM PDT 24
Peak memory 199504 kb
Host smart-97bf1a21-e70d-4907-8e9b-557a7bc2a8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081127253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.4081127253
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.30205961
Short name T598
Test name
Test status
Simulation time 5339642039 ps
CPU time 45.26 seconds
Started Apr 04 12:30:53 PM PDT 24
Finished Apr 04 12:31:38 PM PDT 24
Peak memory 199616 kb
Host smart-b3f957b8-d9d5-49d0-865c-acb63ba98987
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=30205961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.30205961
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.2779416667
Short name T47
Test name
Test status
Simulation time 16889715061 ps
CPU time 172.27 seconds
Started Apr 04 12:30:53 PM PDT 24
Finished Apr 04 12:33:46 PM PDT 24
Peak memory 199600 kb
Host smart-64381799-f94e-4f85-a214-0b1b8c0ccb59
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779416667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2779416667
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1194214386
Short name T555
Test name
Test status
Simulation time 25178055418 ps
CPU time 140.05 seconds
Started Apr 04 12:30:56 PM PDT 24
Finished Apr 04 12:33:16 PM PDT 24
Peak memory 199632 kb
Host smart-520733f6-36b1-40cf-941b-ec622ec72edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194214386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1194214386
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.816030816
Short name T465
Test name
Test status
Simulation time 3832448805 ps
CPU time 5.72 seconds
Started Apr 04 12:30:58 PM PDT 24
Finished Apr 04 12:31:05 PM PDT 24
Peak memory 199644 kb
Host smart-eb35e15d-7f91-41e7-9630-1c8a79beaa00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816030816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.816030816
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3842233101
Short name T66
Test name
Test status
Simulation time 57033049397 ps
CPU time 689.42 seconds
Started Apr 04 12:31:24 PM PDT 24
Finished Apr 04 12:42:54 PM PDT 24
Peak memory 199600 kb
Host smart-f5b153ab-519d-4676-b1fe-999f2a01d67b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842233101 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3842233101
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.3742254693
Short name T358
Test name
Test status
Simulation time 274639730 ps
CPU time 0.99 seconds
Started Apr 04 12:31:26 PM PDT 24
Finished Apr 04 12:31:27 PM PDT 24
Peak memory 198892 kb
Host smart-fc825176-d94b-4974-ac86-15812352b7e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742254693 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.3742254693
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.2542149944
Short name T140
Test name
Test status
Simulation time 56605913091 ps
CPU time 380.71 seconds
Started Apr 04 12:30:53 PM PDT 24
Finished Apr 04 12:37:15 PM PDT 24
Peak memory 199604 kb
Host smart-e0a2441a-6c7f-4362-9fc9-97d1c4eba20e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542149944 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.2542149944
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.3657441522
Short name T220
Test name
Test status
Simulation time 2031115241 ps
CPU time 20.61 seconds
Started Apr 04 12:31:21 PM PDT 24
Finished Apr 04 12:31:42 PM PDT 24
Peak memory 199524 kb
Host smart-658c7998-a128-49f9-96dd-73830abeff2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657441522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3657441522
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2853315036
Short name T484
Test name
Test status
Simulation time 50754067 ps
CPU time 0.55 seconds
Started Apr 04 12:31:31 PM PDT 24
Finished Apr 04 12:31:32 PM PDT 24
Peak memory 193892 kb
Host smart-20539777-0edf-41d9-84cf-3f4d75790d0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853315036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2853315036
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2461768853
Short name T285
Test name
Test status
Simulation time 316644976 ps
CPU time 10.92 seconds
Started Apr 04 12:30:58 PM PDT 24
Finished Apr 04 12:31:09 PM PDT 24
Peak memory 199484 kb
Host smart-a691e46c-cca7-4c5c-9904-8984e63f5120
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2461768853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2461768853
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1939038214
Short name T421
Test name
Test status
Simulation time 3941475055 ps
CPU time 47.95 seconds
Started Apr 04 12:30:49 PM PDT 24
Finished Apr 04 12:31:37 PM PDT 24
Peak memory 199584 kb
Host smart-1287cbaa-5a18-4df0-8fd4-d4f696e5ebea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939038214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1939038214
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1662268650
Short name T255
Test name
Test status
Simulation time 2915741200 ps
CPU time 85.31 seconds
Started Apr 04 12:30:50 PM PDT 24
Finished Apr 04 12:32:16 PM PDT 24
Peak memory 199592 kb
Host smart-a542f3cb-dd71-488c-a59f-7e91013fb44e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1662268650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1662268650
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3228611562
Short name T445
Test name
Test status
Simulation time 5388489967 ps
CPU time 93.61 seconds
Started Apr 04 12:31:06 PM PDT 24
Finished Apr 04 12:32:39 PM PDT 24
Peak memory 199580 kb
Host smart-71164ea7-bdde-4b54-8ceb-4c4de7a8da55
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228611562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3228611562
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.4220722924
Short name T419
Test name
Test status
Simulation time 1431329744 ps
CPU time 87.48 seconds
Started Apr 04 12:30:40 PM PDT 24
Finished Apr 04 12:32:07 PM PDT 24
Peak memory 199484 kb
Host smart-a210f925-869d-4743-92ef-4909d8feca94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220722924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.4220722924
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1632114784
Short name T333
Test name
Test status
Simulation time 1625470647 ps
CPU time 3.3 seconds
Started Apr 04 12:31:06 PM PDT 24
Finished Apr 04 12:31:09 PM PDT 24
Peak memory 199508 kb
Host smart-3a195544-f758-44ed-bd88-419ea363bdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632114784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1632114784
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.999887954
Short name T398
Test name
Test status
Simulation time 102965936405 ps
CPU time 1003.78 seconds
Started Apr 04 12:31:22 PM PDT 24
Finished Apr 04 12:48:06 PM PDT 24
Peak memory 240552 kb
Host smart-9fbccdc8-82a0-4f88-ba1a-c000d38e7d2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999887954 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.999887954
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_stress_all_with_rand_reset.96299920
Short name T8
Test name
Test status
Simulation time 44570004872 ps
CPU time 642.42 seconds
Started Apr 04 12:30:47 PM PDT 24
Finished Apr 04 12:41:30 PM PDT 24
Peak memory 247124 kb
Host smart-373f0168-92be-4c8a-8ffc-06e4b96a693d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=96299920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all_with_rand_reset.96299920
Directory /workspace/19.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.3385221479
Short name T518
Test name
Test status
Simulation time 101507539 ps
CPU time 1.35 seconds
Started Apr 04 12:31:18 PM PDT 24
Finished Apr 04 12:31:20 PM PDT 24
Peak memory 199508 kb
Host smart-2e6d618f-043d-44ac-a892-3fbcbda183b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385221479 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.3385221479
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.2827060234
Short name T143
Test name
Test status
Simulation time 8588766764 ps
CPU time 457.59 seconds
Started Apr 04 12:31:01 PM PDT 24
Finished Apr 04 12:38:39 PM PDT 24
Peak memory 199652 kb
Host smart-8df84ff6-054d-40b3-836f-19dc1a5e7512
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827060234 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.2827060234
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3887979514
Short name T474
Test name
Test status
Simulation time 6284157232 ps
CPU time 5.56 seconds
Started Apr 04 12:31:26 PM PDT 24
Finished Apr 04 12:31:31 PM PDT 24
Peak memory 199556 kb
Host smart-4d5726e6-ad74-4ff6-b2f0-505bd4bd0601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887979514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3887979514
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/194.hmac_stress_all_with_rand_reset.601217279
Short name T365
Test name
Test status
Simulation time 65956424771 ps
CPU time 455.99 seconds
Started Apr 04 12:33:25 PM PDT 24
Finished Apr 04 12:41:02 PM PDT 24
Peak memory 222672 kb
Host smart-dc941454-2f75-4716-bc92-0661a1d6b625
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=601217279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.hmac_stress_all_with_rand_reset.601217279
Directory /workspace/194.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2667544570
Short name T412
Test name
Test status
Simulation time 11384786 ps
CPU time 0.53 seconds
Started Apr 04 12:28:58 PM PDT 24
Finished Apr 04 12:28:59 PM PDT 24
Peak memory 193792 kb
Host smart-3823727e-8ec2-4bd3-89f4-7bc7d0e2f643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667544570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2667544570
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.2124954394
Short name T284
Test name
Test status
Simulation time 3222857826 ps
CPU time 31.83 seconds
Started Apr 04 12:29:00 PM PDT 24
Finished Apr 04 12:29:32 PM PDT 24
Peak memory 232324 kb
Host smart-5d604e69-281d-4795-b8e8-edef1ec5add6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2124954394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.2124954394
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2270130891
Short name T298
Test name
Test status
Simulation time 1213776391 ps
CPU time 28.94 seconds
Started Apr 04 12:28:57 PM PDT 24
Finished Apr 04 12:29:26 PM PDT 24
Peak memory 199380 kb
Host smart-f33694be-c606-4b35-9b18-6174c6e0ae34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270130891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2270130891
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3288963063
Short name T336
Test name
Test status
Simulation time 5253130879 ps
CPU time 146.21 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:31:19 PM PDT 24
Peak memory 199312 kb
Host smart-0e06811e-ae95-442c-82ec-eb5222286621
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3288963063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3288963063
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.1218622561
Short name T564
Test name
Test status
Simulation time 3904232373 ps
CPU time 55.33 seconds
Started Apr 04 12:28:55 PM PDT 24
Finished Apr 04 12:29:51 PM PDT 24
Peak memory 198388 kb
Host smart-7791ea37-8a65-4990-b0ec-6bcff16e4609
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218622561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.1218622561
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.1388071754
Short name T571
Test name
Test status
Simulation time 1845959301 ps
CPU time 104.71 seconds
Started Apr 04 12:28:52 PM PDT 24
Finished Apr 04 12:30:37 PM PDT 24
Peak memory 199120 kb
Host smart-bc064a3a-65ad-4cf3-9103-43c4c23b1a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388071754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1388071754
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.887777427
Short name T31
Test name
Test status
Simulation time 465487008 ps
CPU time 0.99 seconds
Started Apr 04 12:28:54 PM PDT 24
Finished Apr 04 12:28:55 PM PDT 24
Peak memory 218928 kb
Host smart-9b4ba758-57e2-4930-a091-c2164a15433f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887777427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.887777427
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.3531848733
Short name T519
Test name
Test status
Simulation time 3604173664 ps
CPU time 6.45 seconds
Started Apr 04 12:28:54 PM PDT 24
Finished Apr 04 12:29:00 PM PDT 24
Peak memory 199492 kb
Host smart-888cc51c-7386-4a3e-b6fe-d8a29c4f8a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531848733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3531848733
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.297463947
Short name T472
Test name
Test status
Simulation time 222222269277 ps
CPU time 909.7 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:44:03 PM PDT 24
Peak memory 214928 kb
Host smart-a603dd42-8557-4cde-b08f-0fcd3f66bb84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297463947 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.297463947
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.1367101781
Short name T115
Test name
Test status
Simulation time 80864429 ps
CPU time 1.06 seconds
Started Apr 04 12:28:57 PM PDT 24
Finished Apr 04 12:28:58 PM PDT 24
Peak memory 197388 kb
Host smart-97b58f48-e574-4f99-99ba-06f4bdac8d92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367101781 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.1367101781
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.2384037934
Short name T461
Test name
Test status
Simulation time 16115620239 ps
CPU time 422.41 seconds
Started Apr 04 12:28:52 PM PDT 24
Finished Apr 04 12:35:55 PM PDT 24
Peak memory 199164 kb
Host smart-799105e7-ee94-486b-b87f-e6f1b69d8fbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384037934 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.2384037934
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.1161098582
Short name T171
Test name
Test status
Simulation time 29334852765 ps
CPU time 87.97 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:30:21 PM PDT 24
Peak memory 199256 kb
Host smart-8a6997f6-d178-4df6-ba23-594a04fef80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161098582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1161098582
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.621493559
Short name T232
Test name
Test status
Simulation time 36721619 ps
CPU time 0.59 seconds
Started Apr 04 12:30:52 PM PDT 24
Finished Apr 04 12:30:53 PM PDT 24
Peak memory 193960 kb
Host smart-8ae3cab5-2e6a-498a-931e-28a8738a5d3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621493559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.621493559
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2066860920
Short name T439
Test name
Test status
Simulation time 1282409708 ps
CPU time 39.8 seconds
Started Apr 04 12:31:14 PM PDT 24
Finished Apr 04 12:31:54 PM PDT 24
Peak memory 215988 kb
Host smart-e03f5cf6-72a2-4772-a5d6-c25741a1c6b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2066860920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2066860920
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2470172590
Short name T186
Test name
Test status
Simulation time 846244017 ps
CPU time 17.44 seconds
Started Apr 04 12:30:48 PM PDT 24
Finished Apr 04 12:31:06 PM PDT 24
Peak memory 199456 kb
Host smart-a3f18ffb-7d0b-47ea-b7a4-f3ef91c0c338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470172590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2470172590
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1603879024
Short name T39
Test name
Test status
Simulation time 1129520231 ps
CPU time 64.39 seconds
Started Apr 04 12:31:13 PM PDT 24
Finished Apr 04 12:32:18 PM PDT 24
Peak memory 199512 kb
Host smart-43fc590c-60fb-4e79-9ff7-85b9465d1897
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1603879024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1603879024
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3447108795
Short name T24
Test name
Test status
Simulation time 2015321568 ps
CPU time 27.67 seconds
Started Apr 04 12:30:49 PM PDT 24
Finished Apr 04 12:31:17 PM PDT 24
Peak memory 199572 kb
Host smart-aad4e2ba-0110-4c2f-b395-ee10c45615fc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447108795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3447108795
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1049623640
Short name T540
Test name
Test status
Simulation time 21908217005 ps
CPU time 26.08 seconds
Started Apr 04 12:31:09 PM PDT 24
Finished Apr 04 12:31:36 PM PDT 24
Peak memory 199584 kb
Host smart-95b22b5a-acd5-4e1c-8fbc-0caa2702f63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049623640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1049623640
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.3638917807
Short name T492
Test name
Test status
Simulation time 1540376511 ps
CPU time 5.52 seconds
Started Apr 04 12:30:38 PM PDT 24
Finished Apr 04 12:30:44 PM PDT 24
Peak memory 199548 kb
Host smart-b87bd1e2-9718-43c6-bc41-88b8be4cd248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638917807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3638917807
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2528500023
Short name T426
Test name
Test status
Simulation time 32772754298 ps
CPU time 442.78 seconds
Started Apr 04 12:30:41 PM PDT 24
Finished Apr 04 12:38:04 PM PDT 24
Peak memory 199412 kb
Host smart-8626a32c-fbf6-4c31-ae86-0954dfc87cf7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528500023 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2528500023
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.1529929075
Short name T350
Test name
Test status
Simulation time 90094346 ps
CPU time 0.94 seconds
Started Apr 04 12:30:46 PM PDT 24
Finished Apr 04 12:30:48 PM PDT 24
Peak memory 198368 kb
Host smart-60ee9b6f-3a86-420f-8f60-1f36f0a11b9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529929075 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.1529929075
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.2721140128
Short name T15
Test name
Test status
Simulation time 30182999551 ps
CPU time 409.24 seconds
Started Apr 04 12:31:25 PM PDT 24
Finished Apr 04 12:38:15 PM PDT 24
Peak memory 199572 kb
Host smart-2b95fc95-b601-4a5a-96fa-823f1685556c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721140128 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.2721140128
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.592995580
Short name T62
Test name
Test status
Simulation time 2220172774 ps
CPU time 54.04 seconds
Started Apr 04 12:30:43 PM PDT 24
Finished Apr 04 12:31:37 PM PDT 24
Peak memory 199572 kb
Host smart-8df7e6ef-ce10-4884-b49b-8a33a6343231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592995580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.592995580
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.427733186
Short name T487
Test name
Test status
Simulation time 35757209 ps
CPU time 0.59 seconds
Started Apr 04 12:30:50 PM PDT 24
Finished Apr 04 12:30:51 PM PDT 24
Peak memory 195044 kb
Host smart-786c2165-71ec-4a0a-94ba-b3206a209f8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427733186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.427733186
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.2579792501
Short name T368
Test name
Test status
Simulation time 1265110873 ps
CPU time 41.56 seconds
Started Apr 04 12:30:40 PM PDT 24
Finished Apr 04 12:31:22 PM PDT 24
Peak memory 224072 kb
Host smart-5a44eab6-f495-4596-b42e-21c77b34332d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2579792501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.2579792501
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2159776842
Short name T506
Test name
Test status
Simulation time 2697213235 ps
CPU time 35.41 seconds
Started Apr 04 12:32:23 PM PDT 24
Finished Apr 04 12:32:58 PM PDT 24
Peak memory 199588 kb
Host smart-5929da5a-4234-4bb4-b9ba-d961c5be61b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159776842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2159776842
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1321131475
Short name T476
Test name
Test status
Simulation time 6333884555 ps
CPU time 62.74 seconds
Started Apr 04 12:30:39 PM PDT 24
Finished Apr 04 12:31:42 PM PDT 24
Peak memory 199608 kb
Host smart-e0dafedf-88f5-4778-9684-6fd39b449f76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1321131475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1321131475
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.2471125720
Short name T450
Test name
Test status
Simulation time 411946432 ps
CPU time 20.6 seconds
Started Apr 04 12:30:57 PM PDT 24
Finished Apr 04 12:31:18 PM PDT 24
Peak memory 199428 kb
Host smart-ae91db1c-cff9-48c9-b76f-1eda57724d01
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471125720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2471125720
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.206241426
Short name T114
Test name
Test status
Simulation time 8931922785 ps
CPU time 44.45 seconds
Started Apr 04 12:30:40 PM PDT 24
Finished Apr 04 12:31:24 PM PDT 24
Peak memory 199612 kb
Host smart-00047fea-deaa-4b98-af6d-9dc987a8b1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206241426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.206241426
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.310512801
Short name T565
Test name
Test status
Simulation time 1803632821 ps
CPU time 3.83 seconds
Started Apr 04 12:30:46 PM PDT 24
Finished Apr 04 12:30:50 PM PDT 24
Peak memory 199388 kb
Host smart-dd444911-bf3f-4f4f-b606-bd0c5fc2cc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310512801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.310512801
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2503190031
Short name T293
Test name
Test status
Simulation time 123486806900 ps
CPU time 1602.29 seconds
Started Apr 04 12:30:43 PM PDT 24
Finished Apr 04 12:57:27 PM PDT 24
Peak memory 225188 kb
Host smart-1dc829b5-d26a-4842-97a4-92d6d535b6bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503190031 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2503190031
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.2949692984
Short name T33
Test name
Test status
Simulation time 183385935 ps
CPU time 1.03 seconds
Started Apr 04 12:30:47 PM PDT 24
Finished Apr 04 12:30:48 PM PDT 24
Peak memory 198800 kb
Host smart-60d0b6df-4ca7-4670-ac7b-831ab0fb9d86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949692984 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.2949692984
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.4067634215
Short name T83
Test name
Test status
Simulation time 331691353629 ps
CPU time 535.66 seconds
Started Apr 04 12:30:38 PM PDT 24
Finished Apr 04 12:39:34 PM PDT 24
Peak memory 199568 kb
Host smart-430ecf73-dad5-4611-8a95-3cbc641ec7be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067634215 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.4067634215
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2058542795
Short name T434
Test name
Test status
Simulation time 25859341246 ps
CPU time 104.77 seconds
Started Apr 04 12:31:25 PM PDT 24
Finished Apr 04 12:33:10 PM PDT 24
Peak memory 199588 kb
Host smart-47aeb6a1-89f9-431f-8623-d58779263011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058542795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2058542795
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1178527676
Short name T235
Test name
Test status
Simulation time 42805454 ps
CPU time 0.56 seconds
Started Apr 04 12:30:40 PM PDT 24
Finished Apr 04 12:30:41 PM PDT 24
Peak memory 194052 kb
Host smart-0581100e-600a-4db7-aae7-3a41563c3566
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178527676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1178527676
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2806292205
Short name T139
Test name
Test status
Simulation time 1939953494 ps
CPU time 40.21 seconds
Started Apr 04 12:31:31 PM PDT 24
Finished Apr 04 12:32:11 PM PDT 24
Peak memory 223912 kb
Host smart-8069c547-8cda-4e64-8fad-b147bda19702
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2806292205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2806292205
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1616771403
Short name T73
Test name
Test status
Simulation time 925294420 ps
CPU time 43.65 seconds
Started Apr 04 12:31:20 PM PDT 24
Finished Apr 04 12:32:03 PM PDT 24
Peak memory 199440 kb
Host smart-8d24d56a-a8fc-4133-ab61-12a4fd0e5d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616771403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1616771403
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3993718854
Short name T294
Test name
Test status
Simulation time 1251319690 ps
CPU time 31.73 seconds
Started Apr 04 12:30:54 PM PDT 24
Finished Apr 04 12:31:26 PM PDT 24
Peak memory 199404 kb
Host smart-614e14ad-3f65-4559-994f-2b699097a370
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3993718854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3993718854
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2925568516
Short name T184
Test name
Test status
Simulation time 7887952871 ps
CPU time 111.21 seconds
Started Apr 04 12:30:55 PM PDT 24
Finished Apr 04 12:32:46 PM PDT 24
Peak memory 199636 kb
Host smart-95a90cb4-2e2d-4e74-acbd-e323248e6f02
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925568516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2925568516
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2537532344
Short name T542
Test name
Test status
Simulation time 63393908938 ps
CPU time 109.71 seconds
Started Apr 04 12:30:46 PM PDT 24
Finished Apr 04 12:32:36 PM PDT 24
Peak memory 199512 kb
Host smart-70bb2e98-2ccd-4be9-88ee-e069872c281f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537532344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2537532344
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1059550838
Short name T345
Test name
Test status
Simulation time 2040196941 ps
CPU time 7.19 seconds
Started Apr 04 12:32:32 PM PDT 24
Finished Apr 04 12:32:39 PM PDT 24
Peak memory 199420 kb
Host smart-70e54d9c-3799-4458-9666-e9461fb31f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059550838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1059550838
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.3265470067
Short name T270
Test name
Test status
Simulation time 179450888522 ps
CPU time 2690.42 seconds
Started Apr 04 12:31:20 PM PDT 24
Finished Apr 04 01:16:11 PM PDT 24
Peak memory 199636 kb
Host smart-e7f49c4b-7b46-43d9-9ea1-4d2f3a90c818
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265470067 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3265470067
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.190288009
Short name T234
Test name
Test status
Simulation time 78398190 ps
CPU time 1.07 seconds
Started Apr 04 12:31:23 PM PDT 24
Finished Apr 04 12:31:24 PM PDT 24
Peak memory 198880 kb
Host smart-ff6f5855-4355-406a-b429-a700a849ade4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190288009 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_hmac_vectors.190288009
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.1940237698
Short name T320
Test name
Test status
Simulation time 92405338243 ps
CPU time 549.09 seconds
Started Apr 04 12:30:51 PM PDT 24
Finished Apr 04 12:40:01 PM PDT 24
Peak memory 199552 kb
Host smart-1277d3c4-e1a0-4db3-b190-0e4f387e6511
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940237698 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.1940237698
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.1229877412
Short name T552
Test name
Test status
Simulation time 43668946878 ps
CPU time 80.95 seconds
Started Apr 04 12:30:46 PM PDT 24
Finished Apr 04 12:32:07 PM PDT 24
Peak memory 199592 kb
Host smart-fc562941-3108-4488-b0d9-23eadb8897a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229877412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1229877412
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.3218164692
Short name T291
Test name
Test status
Simulation time 14018699 ps
CPU time 0.58 seconds
Started Apr 04 12:30:55 PM PDT 24
Finished Apr 04 12:30:56 PM PDT 24
Peak memory 194056 kb
Host smart-569cc224-4cea-437b-81f1-af60fe71d72f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218164692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3218164692
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.4186212218
Short name T296
Test name
Test status
Simulation time 4478478179 ps
CPU time 40.32 seconds
Started Apr 04 12:31:06 PM PDT 24
Finished Apr 04 12:31:46 PM PDT 24
Peak memory 215080 kb
Host smart-af9095eb-8e19-4f4b-b613-6e156480d5cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4186212218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.4186212218
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.3237214821
Short name T136
Test name
Test status
Simulation time 212317463 ps
CPU time 1.6 seconds
Started Apr 04 12:31:06 PM PDT 24
Finished Apr 04 12:31:08 PM PDT 24
Peak memory 199480 kb
Host smart-b1ab6450-5b98-4c5b-84a2-5e52d57f66ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237214821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3237214821
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.3981601260
Short name T81
Test name
Test status
Simulation time 1615873049 ps
CPU time 28.12 seconds
Started Apr 04 12:31:01 PM PDT 24
Finished Apr 04 12:31:30 PM PDT 24
Peak memory 199488 kb
Host smart-c479e81a-11c0-4867-ad16-88569e0dc636
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3981601260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.3981601260
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1975290728
Short name T493
Test name
Test status
Simulation time 39808561955 ps
CPU time 118.27 seconds
Started Apr 04 12:30:53 PM PDT 24
Finished Apr 04 12:32:52 PM PDT 24
Peak memory 199616 kb
Host smart-6eaa0152-30f9-4fba-9ac9-ed7855aaaa72
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975290728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1975290728
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3876060671
Short name T118
Test name
Test status
Simulation time 737315840 ps
CPU time 45.07 seconds
Started Apr 04 12:31:01 PM PDT 24
Finished Apr 04 12:31:46 PM PDT 24
Peak memory 199448 kb
Host smart-f38df184-de77-4f25-9120-5bfc12f08564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876060671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3876060671
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1877833951
Short name T279
Test name
Test status
Simulation time 84501908 ps
CPU time 2.63 seconds
Started Apr 04 12:31:24 PM PDT 24
Finished Apr 04 12:31:27 PM PDT 24
Peak memory 199556 kb
Host smart-bc9d48ee-aec4-4ede-9f8f-eb5e102cb78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877833951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1877833951
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.2436583389
Short name T257
Test name
Test status
Simulation time 7080968259 ps
CPU time 55.31 seconds
Started Apr 04 12:30:48 PM PDT 24
Finished Apr 04 12:31:44 PM PDT 24
Peak memory 199576 kb
Host smart-c0050bcf-da3b-47e2-b5aa-dc06f2b913d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436583389 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.2436583389
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.340466739
Short name T199
Test name
Test status
Simulation time 41961912 ps
CPU time 0.94 seconds
Started Apr 04 12:31:10 PM PDT 24
Finished Apr 04 12:31:12 PM PDT 24
Peak memory 198788 kb
Host smart-d6151ae5-4bb8-4be6-8811-74a0790da767
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340466739 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_hmac_vectors.340466739
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.3648937567
Short name T535
Test name
Test status
Simulation time 49345784164 ps
CPU time 433.94 seconds
Started Apr 04 12:31:18 PM PDT 24
Finished Apr 04 12:38:32 PM PDT 24
Peak memory 199576 kb
Host smart-df239bd6-8c8f-4bea-aa04-8ec07219d4ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648937567 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.3648937567
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1302865763
Short name T526
Test name
Test status
Simulation time 11563109773 ps
CPU time 35.45 seconds
Started Apr 04 12:30:55 PM PDT 24
Finished Apr 04 12:31:31 PM PDT 24
Peak memory 199552 kb
Host smart-4b0501eb-df85-4cfa-a3be-0302f59f8d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302865763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1302865763
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2706125280
Short name T433
Test name
Test status
Simulation time 45086506 ps
CPU time 0.55 seconds
Started Apr 04 12:33:27 PM PDT 24
Finished Apr 04 12:33:28 PM PDT 24
Peak memory 194828 kb
Host smart-6d73fe2c-e3a2-40d3-8af5-28ea2cc81092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706125280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2706125280
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2821840876
Short name T163
Test name
Test status
Simulation time 876392268 ps
CPU time 32.77 seconds
Started Apr 04 12:31:05 PM PDT 24
Finished Apr 04 12:31:38 PM PDT 24
Peak memory 224160 kb
Host smart-c8aa851c-23e4-4f10-a066-ea0adc5910d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2821840876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2821840876
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3082233626
Short name T250
Test name
Test status
Simulation time 16183555449 ps
CPU time 41.6 seconds
Started Apr 04 12:31:27 PM PDT 24
Finished Apr 04 12:32:08 PM PDT 24
Peak memory 199600 kb
Host smart-c63ffee3-e7d3-4b41-845c-8355c3a987b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082233626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3082233626
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1938558147
Short name T486
Test name
Test status
Simulation time 3711098315 ps
CPU time 28.27 seconds
Started Apr 04 12:31:33 PM PDT 24
Finished Apr 04 12:32:01 PM PDT 24
Peak memory 199628 kb
Host smart-4fe7af86-0566-46c9-9bbe-8cbb57eae5c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1938558147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1938558147
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3686457340
Short name T304
Test name
Test status
Simulation time 4192043382 ps
CPU time 51.53 seconds
Started Apr 04 12:31:33 PM PDT 24
Finished Apr 04 12:32:25 PM PDT 24
Peak memory 199656 kb
Host smart-7b096aa8-54bd-4a3d-ae07-4d5bee98be0e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686457340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3686457340
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1774168651
Short name T229
Test name
Test status
Simulation time 768667440 ps
CPU time 11 seconds
Started Apr 04 12:31:14 PM PDT 24
Finished Apr 04 12:31:25 PM PDT 24
Peak memory 199556 kb
Host smart-6598b377-3410-460a-aac6-a56aee7732df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774168651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1774168651
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2678174684
Short name T280
Test name
Test status
Simulation time 229601241 ps
CPU time 3.44 seconds
Started Apr 04 12:30:39 PM PDT 24
Finished Apr 04 12:30:42 PM PDT 24
Peak memory 199460 kb
Host smart-340c77aa-b9ba-4468-8bbc-14eb98422c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678174684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2678174684
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.2648797078
Short name T510
Test name
Test status
Simulation time 141628963827 ps
CPU time 455.62 seconds
Started Apr 04 12:31:16 PM PDT 24
Finished Apr 04 12:38:52 PM PDT 24
Peak memory 199568 kb
Host smart-06bfe353-54c8-4eb5-ab8d-db742b576c31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648797078 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2648797078
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.3034187599
Short name T170
Test name
Test status
Simulation time 32527143 ps
CPU time 1.14 seconds
Started Apr 04 12:31:18 PM PDT 24
Finished Apr 04 12:31:20 PM PDT 24
Peak memory 199388 kb
Host smart-6da04e00-d475-4803-ba27-1256b7ca2cbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034187599 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.3034187599
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2353365251
Short name T462
Test name
Test status
Simulation time 667403560 ps
CPU time 17.95 seconds
Started Apr 04 12:31:10 PM PDT 24
Finished Apr 04 12:31:28 PM PDT 24
Peak memory 199504 kb
Host smart-40a90a03-31f0-4736-9835-7e29aa9555ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353365251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2353365251
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2376661457
Short name T498
Test name
Test status
Simulation time 20015167 ps
CPU time 0.6 seconds
Started Apr 04 12:31:44 PM PDT 24
Finished Apr 04 12:31:45 PM PDT 24
Peak memory 195088 kb
Host smart-cf9acfd7-d86d-4223-b3ed-47da7fcb90ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376661457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2376661457
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1585182895
Short name T206
Test name
Test status
Simulation time 1444723480 ps
CPU time 50.58 seconds
Started Apr 04 12:31:06 PM PDT 24
Finished Apr 04 12:31:57 PM PDT 24
Peak memory 223996 kb
Host smart-1fe96aab-42b0-4312-8475-e4328b958d7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1585182895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1585182895
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1912345123
Short name T172
Test name
Test status
Simulation time 2273806783 ps
CPU time 29.95 seconds
Started Apr 04 12:33:26 PM PDT 24
Finished Apr 04 12:33:56 PM PDT 24
Peak memory 196828 kb
Host smart-8571b166-bc27-4f4d-b360-13adbb1582ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912345123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1912345123
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.20016508
Short name T138
Test name
Test status
Simulation time 956812257 ps
CPU time 54.97 seconds
Started Apr 04 12:31:44 PM PDT 24
Finished Apr 04 12:32:39 PM PDT 24
Peak memory 199500 kb
Host smart-920014f9-b15e-41f8-9a67-7023fc3538b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20016508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.20016508
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.1127416804
Short name T213
Test name
Test status
Simulation time 59420849060 ps
CPU time 195.28 seconds
Started Apr 04 12:31:39 PM PDT 24
Finished Apr 04 12:34:55 PM PDT 24
Peak memory 199588 kb
Host smart-70c6844e-cb57-4ffd-908c-e4297ccaf52c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127416804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.1127416804
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3979011199
Short name T455
Test name
Test status
Simulation time 877420900 ps
CPU time 13.14 seconds
Started Apr 04 12:31:25 PM PDT 24
Finished Apr 04 12:31:38 PM PDT 24
Peak memory 199432 kb
Host smart-ea93eb9f-5a4e-440e-bb3b-30ddcdeb2937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979011199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3979011199
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.1304222728
Short name T130
Test name
Test status
Simulation time 444379495 ps
CPU time 4 seconds
Started Apr 04 12:31:11 PM PDT 24
Finished Apr 04 12:31:15 PM PDT 24
Peak memory 199384 kb
Host smart-fc5e15ee-d2e1-4add-87ce-a4cf21ae1d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304222728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1304222728
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.3589556698
Short name T589
Test name
Test status
Simulation time 7418506961 ps
CPU time 152.6 seconds
Started Apr 04 12:31:15 PM PDT 24
Finished Apr 04 12:33:48 PM PDT 24
Peak memory 216020 kb
Host smart-6b7e2a0b-be2f-4900-873b-bb622fdf70c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589556698 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.3589556698
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.3207826426
Short name T527
Test name
Test status
Simulation time 203308674 ps
CPU time 1.25 seconds
Started Apr 04 12:32:05 PM PDT 24
Finished Apr 04 12:32:06 PM PDT 24
Peak memory 199280 kb
Host smart-d181fc93-bf70-4e08-8c7a-b3247ad1ec9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207826426 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.3207826426
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.3078611402
Short name T164
Test name
Test status
Simulation time 36203096604 ps
CPU time 474.39 seconds
Started Apr 04 12:31:02 PM PDT 24
Finished Apr 04 12:38:56 PM PDT 24
Peak memory 199648 kb
Host smart-84b7772f-76c6-4704-9aea-dc3f3050a8a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078611402 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.3078611402
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.330802627
Short name T4
Test name
Test status
Simulation time 2144578684 ps
CPU time 29.21 seconds
Started Apr 04 12:31:03 PM PDT 24
Finished Apr 04 12:31:33 PM PDT 24
Peak memory 199432 kb
Host smart-b7b0533a-bd31-403f-a359-ae0ea0070575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330802627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.330802627
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1906288402
Short name T147
Test name
Test status
Simulation time 13972655 ps
CPU time 0.58 seconds
Started Apr 04 12:31:07 PM PDT 24
Finished Apr 04 12:31:07 PM PDT 24
Peak memory 194780 kb
Host smart-7a9e3441-332e-4239-92a1-dd63212a43d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906288402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1906288402
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.1702197902
Short name T16
Test name
Test status
Simulation time 1588279970 ps
CPU time 33.12 seconds
Started Apr 04 12:31:11 PM PDT 24
Finished Apr 04 12:31:44 PM PDT 24
Peak memory 215856 kb
Host smart-bfa4ec16-d64f-4bfa-9d26-f7c25971ee87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1702197902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1702197902
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1565721940
Short name T442
Test name
Test status
Simulation time 3176578188 ps
CPU time 38.88 seconds
Started Apr 04 12:32:03 PM PDT 24
Finished Apr 04 12:32:42 PM PDT 24
Peak memory 199572 kb
Host smart-118d55b2-4a8e-4e99-bbd1-8d9555cabe70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565721940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1565721940
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3080150230
Short name T405
Test name
Test status
Simulation time 7192115817 ps
CPU time 113.82 seconds
Started Apr 04 12:31:12 PM PDT 24
Finished Apr 04 12:33:06 PM PDT 24
Peak memory 199604 kb
Host smart-4f11c9cc-4f13-453c-acd7-2d3b02d86b32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3080150230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3080150230
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.2664430150
Short name T520
Test name
Test status
Simulation time 7866938734 ps
CPU time 84.18 seconds
Started Apr 04 12:33:28 PM PDT 24
Finished Apr 04 12:34:52 PM PDT 24
Peak memory 199400 kb
Host smart-35dcc3f8-b155-4fa7-bbd0-0aebd207ed7b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664430150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2664430150
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1090549050
Short name T389
Test name
Test status
Simulation time 21333687492 ps
CPU time 101.99 seconds
Started Apr 04 12:31:14 PM PDT 24
Finished Apr 04 12:32:57 PM PDT 24
Peak memory 199660 kb
Host smart-c0ad980e-9a02-4df1-aad6-24e8558404a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090549050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1090549050
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.4047249143
Short name T387
Test name
Test status
Simulation time 156464488 ps
CPU time 4.69 seconds
Started Apr 04 12:31:41 PM PDT 24
Finished Apr 04 12:31:46 PM PDT 24
Peak memory 199500 kb
Host smart-cb77bb56-448e-4b35-ba4b-dd22416f4fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047249143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.4047249143
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.18803296
Short name T68
Test name
Test status
Simulation time 224964637969 ps
CPU time 2783.49 seconds
Started Apr 04 12:32:09 PM PDT 24
Finished Apr 04 01:18:33 PM PDT 24
Peak memory 227668 kb
Host smart-c2018ae4-bbca-45f9-a132-508c554c6fae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18803296 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.18803296
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.2774544557
Short name T413
Test name
Test status
Simulation time 40038014 ps
CPU time 0.97 seconds
Started Apr 04 12:31:01 PM PDT 24
Finished Apr 04 12:31:02 PM PDT 24
Peak memory 197836 kb
Host smart-1172c5d5-6d93-4408-86d5-ad25b592e5ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774544557 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.2774544557
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.1891440651
Short name T404
Test name
Test status
Simulation time 48231832119 ps
CPU time 406.91 seconds
Started Apr 04 12:31:15 PM PDT 24
Finished Apr 04 12:38:02 PM PDT 24
Peak memory 199504 kb
Host smart-b530013b-3d63-426d-9602-e82f9060ce1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891440651 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.1891440651
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3825782656
Short name T5
Test name
Test status
Simulation time 2669199725 ps
CPU time 32.24 seconds
Started Apr 04 12:31:57 PM PDT 24
Finished Apr 04 12:32:29 PM PDT 24
Peak memory 199644 kb
Host smart-97b8c95c-3423-4d23-ba39-b52bfa3971f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825782656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3825782656
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.749256409
Short name T127
Test name
Test status
Simulation time 21510397 ps
CPU time 0.58 seconds
Started Apr 04 12:31:20 PM PDT 24
Finished Apr 04 12:31:20 PM PDT 24
Peak memory 195144 kb
Host smart-56f8109e-f01e-4e2e-bd4d-28f92b36f1da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749256409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.749256409
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3336730755
Short name T189
Test name
Test status
Simulation time 14658722750 ps
CPU time 29.38 seconds
Started Apr 04 12:32:05 PM PDT 24
Finished Apr 04 12:32:35 PM PDT 24
Peak memory 221504 kb
Host smart-00150935-7435-468b-a1f1-78f7a3ec47e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3336730755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3336730755
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.2907983653
Short name T187
Test name
Test status
Simulation time 1338175981 ps
CPU time 5.67 seconds
Started Apr 04 12:32:09 PM PDT 24
Finished Apr 04 12:32:15 PM PDT 24
Peak memory 199452 kb
Host smart-f4588ab1-d0ff-4cb4-abea-735807fe7e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907983653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2907983653
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1347835182
Short name T258
Test name
Test status
Simulation time 7170023439 ps
CPU time 63.47 seconds
Started Apr 04 12:32:05 PM PDT 24
Finished Apr 04 12:33:09 PM PDT 24
Peak memory 199604 kb
Host smart-ff2933ed-3df1-4c92-bbea-91b8ce4c49d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1347835182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1347835182
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.527856691
Short name T509
Test name
Test status
Simulation time 14990306440 ps
CPU time 195.2 seconds
Started Apr 04 12:31:05 PM PDT 24
Finished Apr 04 12:34:20 PM PDT 24
Peak memory 199584 kb
Host smart-f57de7ed-6d06-473b-b6f9-11239269e97b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527856691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.527856691
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2302292054
Short name T384
Test name
Test status
Simulation time 15462356882 ps
CPU time 70.01 seconds
Started Apr 04 12:31:47 PM PDT 24
Finished Apr 04 12:32:57 PM PDT 24
Peak memory 199620 kb
Host smart-b2373db6-3bc5-49f6-b78d-8d54a5f3d003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302292054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2302292054
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2304962877
Short name T500
Test name
Test status
Simulation time 66404923 ps
CPU time 1.18 seconds
Started Apr 04 12:31:22 PM PDT 24
Finished Apr 04 12:31:23 PM PDT 24
Peak memory 199252 kb
Host smart-8740f248-ec94-4dd2-bc8a-b0c7df521284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304962877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2304962877
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2386199644
Short name T301
Test name
Test status
Simulation time 21543758475 ps
CPU time 141.11 seconds
Started Apr 04 12:32:37 PM PDT 24
Finished Apr 04 12:34:59 PM PDT 24
Peak memory 197052 kb
Host smart-4a940936-0375-40d9-b3ab-b8d564bc9e00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386199644 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2386199644
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_stress_all_with_rand_reset.3529394992
Short name T600
Test name
Test status
Simulation time 8950129695 ps
CPU time 292.44 seconds
Started Apr 04 12:31:14 PM PDT 24
Finished Apr 04 12:36:06 PM PDT 24
Peak memory 216100 kb
Host smart-2fc4421e-847f-4095-84dc-169439882577
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3529394992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all_with_rand_reset.3529394992
Directory /workspace/27.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.3560953412
Short name T219
Test name
Test status
Simulation time 110991181 ps
CPU time 1.34 seconds
Started Apr 04 12:31:54 PM PDT 24
Finished Apr 04 12:31:55 PM PDT 24
Peak memory 199516 kb
Host smart-f3d39a8a-2ee1-42e1-b1c6-a2a7aa9213f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560953412 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.3560953412
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.1090893041
Short name T469
Test name
Test status
Simulation time 31822056488 ps
CPU time 386.41 seconds
Started Apr 04 12:33:26 PM PDT 24
Finished Apr 04 12:39:53 PM PDT 24
Peak memory 196992 kb
Host smart-18946308-62a6-48a8-8ad1-098a8bf9250a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090893041 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.1090893041
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1718376332
Short name T488
Test name
Test status
Simulation time 1649287998 ps
CPU time 75.63 seconds
Started Apr 04 12:30:55 PM PDT 24
Finished Apr 04 12:32:11 PM PDT 24
Peak memory 199552 kb
Host smart-ba3ce428-6d9e-4d8d-8832-1a92cb7bc613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718376332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1718376332
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1373090120
Short name T343
Test name
Test status
Simulation time 19380390 ps
CPU time 0.6 seconds
Started Apr 04 12:31:19 PM PDT 24
Finished Apr 04 12:31:20 PM PDT 24
Peak memory 195164 kb
Host smart-5c016d83-05fb-4b9e-aa44-530264556c6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373090120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1373090120
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2472971754
Short name T400
Test name
Test status
Simulation time 1342549231 ps
CPU time 31.11 seconds
Started Apr 04 12:31:47 PM PDT 24
Finished Apr 04 12:32:19 PM PDT 24
Peak memory 224088 kb
Host smart-4d8802e9-2bd1-4d01-9759-89730e356aa9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2472971754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2472971754
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.2309764749
Short name T409
Test name
Test status
Simulation time 19809145332 ps
CPU time 66 seconds
Started Apr 04 12:31:40 PM PDT 24
Finished Apr 04 12:32:47 PM PDT 24
Peak memory 199584 kb
Host smart-9b60cee3-cac3-45ad-bb57-28c4f82a1440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309764749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2309764749
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.2568440007
Short name T80
Test name
Test status
Simulation time 2389208832 ps
CPU time 73.43 seconds
Started Apr 04 12:31:24 PM PDT 24
Finished Apr 04 12:32:37 PM PDT 24
Peak memory 199588 kb
Host smart-464f9a21-d2a7-4523-92d8-f8b34968a6a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2568440007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2568440007
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1998814284
Short name T312
Test name
Test status
Simulation time 58752308254 ps
CPU time 177.82 seconds
Started Apr 04 12:33:26 PM PDT 24
Finished Apr 04 12:36:24 PM PDT 24
Peak memory 197624 kb
Host smart-93f568ac-5819-409d-9ddc-e49a2acb2fbe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998814284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1998814284
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1941113012
Short name T485
Test name
Test status
Simulation time 17256841360 ps
CPU time 73.26 seconds
Started Apr 04 12:32:10 PM PDT 24
Finished Apr 04 12:33:23 PM PDT 24
Peak memory 199604 kb
Host smart-92937d63-bd1d-4a66-a860-2993f4339eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941113012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1941113012
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1200002829
Short name T177
Test name
Test status
Simulation time 361504098 ps
CPU time 5.46 seconds
Started Apr 04 12:31:35 PM PDT 24
Finished Apr 04 12:31:41 PM PDT 24
Peak memory 199552 kb
Host smart-37364804-7ac4-4906-848f-bfb4fcc48361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200002829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1200002829
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2546470235
Short name T126
Test name
Test status
Simulation time 45420857178 ps
CPU time 468.87 seconds
Started Apr 04 12:31:21 PM PDT 24
Finished Apr 04 12:39:10 PM PDT 24
Peak memory 247184 kb
Host smart-375cfa40-6dc2-4e7d-9071-12923cb0d6bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546470235 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2546470235
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.865781330
Short name T392
Test name
Test status
Simulation time 29545311 ps
CPU time 1.11 seconds
Started Apr 04 12:32:37 PM PDT 24
Finished Apr 04 12:32:39 PM PDT 24
Peak memory 196248 kb
Host smart-e03ffa57-1cee-412d-ba19-f880e8dcde09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865781330 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_hmac_vectors.865781330
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.647397234
Short name T254
Test name
Test status
Simulation time 29679824148 ps
CPU time 480.96 seconds
Started Apr 04 12:32:52 PM PDT 24
Finished Apr 04 12:40:53 PM PDT 24
Peak memory 198716 kb
Host smart-9ea56d06-15a6-4d8f-83a4-9c5d579b66aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647397234 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.647397234
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.342873801
Short name T376
Test name
Test status
Simulation time 1363220858 ps
CPU time 19.59 seconds
Started Apr 04 12:31:45 PM PDT 24
Finished Apr 04 12:32:05 PM PDT 24
Peak memory 199492 kb
Host smart-1ca76ddb-90c8-4ae5-8816-60a46c35cc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342873801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.342873801
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1686201566
Short name T188
Test name
Test status
Simulation time 14082580 ps
CPU time 0.57 seconds
Started Apr 04 12:31:10 PM PDT 24
Finished Apr 04 12:31:11 PM PDT 24
Peak memory 194056 kb
Host smart-f0fc3464-cdc7-4afe-bfd6-b0c6619a6c19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686201566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1686201566
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3415862395
Short name T425
Test name
Test status
Simulation time 467614654 ps
CPU time 7.78 seconds
Started Apr 04 12:31:48 PM PDT 24
Finished Apr 04 12:31:56 PM PDT 24
Peak memory 215456 kb
Host smart-b5aff3f0-3ff6-435b-a9df-d65fb3ea023c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3415862395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3415862395
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.3311736200
Short name T377
Test name
Test status
Simulation time 4897644066 ps
CPU time 23.1 seconds
Started Apr 04 12:32:37 PM PDT 24
Finished Apr 04 12:33:01 PM PDT 24
Peak memory 196700 kb
Host smart-59056272-5ad8-418d-b1e1-43c026606dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311736200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3311736200
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3502051492
Short name T580
Test name
Test status
Simulation time 2118906138 ps
CPU time 128.89 seconds
Started Apr 04 12:32:08 PM PDT 24
Finished Apr 04 12:34:17 PM PDT 24
Peak memory 199468 kb
Host smart-62034310-831a-4f5a-80b6-87b443385bdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3502051492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3502051492
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.1700804825
Short name T76
Test name
Test status
Simulation time 13958350502 ps
CPU time 171.2 seconds
Started Apr 04 12:32:37 PM PDT 24
Finished Apr 04 12:35:29 PM PDT 24
Peak memory 197220 kb
Host smart-70391718-01db-4a3e-ab17-aa1bd2c86c6b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700804825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1700804825
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2866737356
Short name T117
Test name
Test status
Simulation time 6249332434 ps
CPU time 63.45 seconds
Started Apr 04 12:30:59 PM PDT 24
Finished Apr 04 12:32:03 PM PDT 24
Peak memory 199632 kb
Host smart-15c0a109-df33-49e3-b2a7-c4cf53b04b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866737356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2866737356
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2328606425
Short name T399
Test name
Test status
Simulation time 318716984 ps
CPU time 3.85 seconds
Started Apr 04 12:31:42 PM PDT 24
Finished Apr 04 12:31:46 PM PDT 24
Peak memory 199460 kb
Host smart-10204cc5-21fa-40fd-994f-817e7d41a1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328606425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2328606425
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2898730746
Short name T65
Test name
Test status
Simulation time 153655301234 ps
CPU time 625.9 seconds
Started Apr 04 12:31:24 PM PDT 24
Finished Apr 04 12:41:51 PM PDT 24
Peak memory 199648 kb
Host smart-703c706f-dd87-466f-bbcc-217c63a207d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898730746 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2898730746
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.2473163547
Short name T125
Test name
Test status
Simulation time 49768991 ps
CPU time 0.96 seconds
Started Apr 04 12:33:25 PM PDT 24
Finished Apr 04 12:33:26 PM PDT 24
Peak memory 198648 kb
Host smart-c5df8f44-a1a6-4b14-b186-0774bc7166ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473163547 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.2473163547
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.3906513304
Short name T129
Test name
Test status
Simulation time 7765015265 ps
CPU time 414.74 seconds
Started Apr 04 12:31:42 PM PDT 24
Finished Apr 04 12:38:36 PM PDT 24
Peak memory 199636 kb
Host smart-2be5cf01-1b75-4af3-8430-285a13e4a990
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906513304 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.3906513304
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1552166174
Short name T241
Test name
Test status
Simulation time 677292006 ps
CPU time 3.02 seconds
Started Apr 04 12:31:11 PM PDT 24
Finished Apr 04 12:31:14 PM PDT 24
Peak memory 199540 kb
Host smart-8757c509-20be-41a4-ab6a-2ae389a818ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552166174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1552166174
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.595860615
Short name T297
Test name
Test status
Simulation time 26470920 ps
CPU time 0.65 seconds
Started Apr 04 12:28:20 PM PDT 24
Finished Apr 04 12:28:21 PM PDT 24
Peak memory 194992 kb
Host smart-1e1a535b-006e-42cb-9e05-69e4f191c94e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595860615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.595860615
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.2291488479
Short name T563
Test name
Test status
Simulation time 468435351 ps
CPU time 8.7 seconds
Started Apr 04 12:28:54 PM PDT 24
Finished Apr 04 12:29:03 PM PDT 24
Peak memory 215528 kb
Host smart-85c05be4-ce47-4dc1-acae-ad7dd4628579
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2291488479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2291488479
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1697714086
Short name T502
Test name
Test status
Simulation time 12991119205 ps
CPU time 35.48 seconds
Started Apr 04 12:29:03 PM PDT 24
Finished Apr 04 12:29:39 PM PDT 24
Peak memory 198216 kb
Host smart-ef2e1bd2-a69b-47d1-9222-0ee9e84c9e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697714086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1697714086
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3442509740
Short name T74
Test name
Test status
Simulation time 2198748841 ps
CPU time 121.72 seconds
Started Apr 04 12:29:04 PM PDT 24
Finished Apr 04 12:31:06 PM PDT 24
Peak memory 198604 kb
Host smart-f7ef2e96-8b03-4936-84eb-0f4610253783
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3442509740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3442509740
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2609847425
Short name T366
Test name
Test status
Simulation time 1027823643 ps
CPU time 52.2 seconds
Started Apr 04 12:29:04 PM PDT 24
Finished Apr 04 12:29:56 PM PDT 24
Peak memory 199116 kb
Host smart-1f9ca3e6-4789-439d-a4eb-fa5cdeab734f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609847425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2609847425
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.62329713
Short name T406
Test name
Test status
Simulation time 21942987216 ps
CPU time 90.27 seconds
Started Apr 04 12:29:03 PM PDT 24
Finished Apr 04 12:30:33 PM PDT 24
Peak memory 198704 kb
Host smart-6527510b-fb0f-4afc-9601-7767af3dcf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62329713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.62329713
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1059106819
Short name T30
Test name
Test status
Simulation time 86547152 ps
CPU time 0.88 seconds
Started Apr 04 12:29:21 PM PDT 24
Finished Apr 04 12:29:23 PM PDT 24
Peak memory 217648 kb
Host smart-83e4e8eb-c756-42e2-bcba-cc05a1b9be66
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059106819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1059106819
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.1910872637
Short name T416
Test name
Test status
Simulation time 204355233 ps
CPU time 3.99 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:28:57 PM PDT 24
Peak memory 199288 kb
Host smart-f894a089-3ba7-41c2-bcd3-6e055673fc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910872637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1910872637
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3947261593
Short name T584
Test name
Test status
Simulation time 22749955860 ps
CPU time 1179.81 seconds
Started Apr 04 12:28:21 PM PDT 24
Finished Apr 04 12:48:02 PM PDT 24
Peak memory 215944 kb
Host smart-c9dfcd70-1f1c-4b1f-91c9-7bfdb170a3e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947261593 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3947261593
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.3797531782
Short name T134
Test name
Test status
Simulation time 77440600 ps
CPU time 0.99 seconds
Started Apr 04 12:28:50 PM PDT 24
Finished Apr 04 12:28:52 PM PDT 24
Peak memory 196800 kb
Host smart-38efdc0d-db2c-49aa-abf4-81135d2bd3b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797531782 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.3797531782
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.2040908062
Short name T322
Test name
Test status
Simulation time 175417692373 ps
CPU time 535.09 seconds
Started Apr 04 12:29:07 PM PDT 24
Finished Apr 04 12:38:03 PM PDT 24
Peak memory 199552 kb
Host smart-733a353e-a482-46e2-b423-fd842e5f7fb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040908062 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.2040908062
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1065361132
Short name T335
Test name
Test status
Simulation time 2048984212 ps
CPU time 18.9 seconds
Started Apr 04 12:29:07 PM PDT 24
Finished Apr 04 12:29:27 PM PDT 24
Peak memory 199420 kb
Host smart-db3be429-e6e3-4b1c-a72a-b55d5a847ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065361132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1065361132
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.82141910
Short name T570
Test name
Test status
Simulation time 59612835 ps
CPU time 0.65 seconds
Started Apr 04 12:31:21 PM PDT 24
Finished Apr 04 12:31:21 PM PDT 24
Peak memory 195060 kb
Host smart-a1a77d87-29d3-4dc0-8915-e14eeba8d77a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82141910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.82141910
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1424464554
Short name T477
Test name
Test status
Simulation time 2010392545 ps
CPU time 53.7 seconds
Started Apr 04 12:31:41 PM PDT 24
Finished Apr 04 12:32:35 PM PDT 24
Peak memory 245936 kb
Host smart-01a39822-dd73-474b-a8ac-d2584ef332ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1424464554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1424464554
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.2519464745
Short name T159
Test name
Test status
Simulation time 2724636873 ps
CPU time 26.66 seconds
Started Apr 04 12:32:17 PM PDT 24
Finished Apr 04 12:32:44 PM PDT 24
Peak memory 199628 kb
Host smart-061134a0-059b-4dc7-b727-fba4d9341863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519464745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.2519464745
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.1635759037
Short name T393
Test name
Test status
Simulation time 9064063383 ps
CPU time 133.9 seconds
Started Apr 04 12:33:25 PM PDT 24
Finished Apr 04 12:35:39 PM PDT 24
Peak memory 199316 kb
Host smart-b0314a3e-c1ea-4c81-98fc-387d56aec3ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1635759037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1635759037
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.38147335
Short name T155
Test name
Test status
Simulation time 14117714755 ps
CPU time 37.8 seconds
Started Apr 04 12:32:23 PM PDT 24
Finished Apr 04 12:33:01 PM PDT 24
Peak memory 199592 kb
Host smart-709ff33b-4947-4e38-bc24-b4169dac683f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38147335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.38147335
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.849224319
Short name T60
Test name
Test status
Simulation time 7036619602 ps
CPU time 102.18 seconds
Started Apr 04 12:31:22 PM PDT 24
Finished Apr 04 12:33:04 PM PDT 24
Peak memory 199596 kb
Host smart-f0a2a91b-824e-4385-baf9-4c0ffb7a3630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849224319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.849224319
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.255694387
Short name T149
Test name
Test status
Simulation time 281952303 ps
CPU time 3.48 seconds
Started Apr 04 12:31:29 PM PDT 24
Finished Apr 04 12:31:34 PM PDT 24
Peak memory 199452 kb
Host smart-19d8262c-b248-4237-8905-b83479467578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255694387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.255694387
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.2309381267
Short name T315
Test name
Test status
Simulation time 244997805749 ps
CPU time 837.55 seconds
Started Apr 04 12:31:03 PM PDT 24
Finished Apr 04 12:45:02 PM PDT 24
Peak memory 248008 kb
Host smart-1ad717fb-f52b-48df-952e-a4fbdc3e60c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309381267 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2309381267
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.3215790678
Short name T168
Test name
Test status
Simulation time 197650127 ps
CPU time 1.1 seconds
Started Apr 04 12:30:57 PM PDT 24
Finished Apr 04 12:30:58 PM PDT 24
Peak memory 198968 kb
Host smart-2929ddad-7b03-4cc5-8497-ef7a0566522c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215790678 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.3215790678
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.1059886742
Short name T559
Test name
Test status
Simulation time 8273070444 ps
CPU time 440.53 seconds
Started Apr 04 12:31:08 PM PDT 24
Finished Apr 04 12:38:29 PM PDT 24
Peak memory 199504 kb
Host smart-45decf62-1f6b-47bd-be16-d16b8f531844
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059886742 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.1059886742
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2760552001
Short name T116
Test name
Test status
Simulation time 4138030024 ps
CPU time 44.81 seconds
Started Apr 04 12:31:02 PM PDT 24
Finished Apr 04 12:31:48 PM PDT 24
Peak memory 199572 kb
Host smart-e006f5fd-e2ec-4967-b4d9-58a9d4313352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760552001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2760552001
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.4089541432
Short name T215
Test name
Test status
Simulation time 27122573 ps
CPU time 0.56 seconds
Started Apr 04 12:33:27 PM PDT 24
Finished Apr 04 12:33:28 PM PDT 24
Peak memory 194976 kb
Host smart-b434e7f1-3dfe-4120-9aa6-0a90cd639981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089541432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.4089541432
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1081169651
Short name T521
Test name
Test status
Simulation time 470013293 ps
CPU time 15.1 seconds
Started Apr 04 12:30:59 PM PDT 24
Finished Apr 04 12:31:15 PM PDT 24
Peak memory 207700 kb
Host smart-c4681946-4260-4d76-b3e9-957f406aaaf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1081169651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1081169651
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1265303338
Short name T256
Test name
Test status
Simulation time 2457224085 ps
CPU time 28.12 seconds
Started Apr 04 12:31:03 PM PDT 24
Finished Apr 04 12:31:32 PM PDT 24
Peak memory 199640 kb
Host smart-a22b6b28-6b57-4296-bebe-0c966f94bc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265303338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1265303338
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1341194946
Short name T391
Test name
Test status
Simulation time 4594296664 ps
CPU time 134.9 seconds
Started Apr 04 12:31:13 PM PDT 24
Finished Apr 04 12:33:28 PM PDT 24
Peak memory 199668 kb
Host smart-5c27f198-5564-47b0-a60f-e64b16bbe506
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1341194946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1341194946
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.2055295713
Short name T361
Test name
Test status
Simulation time 6645492935 ps
CPU time 164.82 seconds
Started Apr 04 12:32:39 PM PDT 24
Finished Apr 04 12:35:24 PM PDT 24
Peak memory 199300 kb
Host smart-bb55d5ac-44cc-40de-bd59-94af6028b6a5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055295713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2055295713
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3541372845
Short name T210
Test name
Test status
Simulation time 2668073744 ps
CPU time 42.44 seconds
Started Apr 04 12:32:37 PM PDT 24
Finished Apr 04 12:33:21 PM PDT 24
Peak memory 198036 kb
Host smart-2980b7e1-4f59-45e8-bca1-00f6171e7bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541372845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3541372845
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1640740246
Short name T233
Test name
Test status
Simulation time 17159299 ps
CPU time 0.67 seconds
Started Apr 04 12:31:05 PM PDT 24
Finished Apr 04 12:31:05 PM PDT 24
Peak memory 196132 kb
Host smart-6818e819-d284-4f52-9cb0-1b7cffac401b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640740246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1640740246
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.4232720055
Short name T200
Test name
Test status
Simulation time 839879483 ps
CPU time 40.46 seconds
Started Apr 04 12:32:05 PM PDT 24
Finished Apr 04 12:32:46 PM PDT 24
Peak memory 199516 kb
Host smart-2156ca0a-101c-49af-9aed-3c9760c3cadc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232720055 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.4232720055
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.1745421180
Short name T110
Test name
Test status
Simulation time 549989675 ps
CPU time 1.31 seconds
Started Apr 04 12:31:01 PM PDT 24
Finished Apr 04 12:31:02 PM PDT 24
Peak memory 199476 kb
Host smart-2ea330e3-9707-40e3-a201-11d46bfcb5ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745421180 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.1745421180
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.2861370381
Short name T457
Test name
Test status
Simulation time 34801330712 ps
CPU time 478.46 seconds
Started Apr 04 12:31:03 PM PDT 24
Finished Apr 04 12:39:02 PM PDT 24
Peak memory 199632 kb
Host smart-c4626c9f-8dc1-4f22-8665-2f96c526c749
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861370381 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.2861370381
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1987480934
Short name T603
Test name
Test status
Simulation time 195150257 ps
CPU time 4.73 seconds
Started Apr 04 12:31:20 PM PDT 24
Finished Apr 04 12:31:24 PM PDT 24
Peak memory 199612 kb
Host smart-2dc114c1-3afd-49a6-9aea-d753e2ad05d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987480934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1987480934
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1661910388
Short name T132
Test name
Test status
Simulation time 15975909 ps
CPU time 0.6 seconds
Started Apr 04 12:31:13 PM PDT 24
Finished Apr 04 12:31:14 PM PDT 24
Peak memory 195152 kb
Host smart-a186c67f-9208-4b53-9eb1-8c70fad75694
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661910388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1661910388
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3399327582
Short name T202
Test name
Test status
Simulation time 979137623 ps
CPU time 34.71 seconds
Started Apr 04 12:31:11 PM PDT 24
Finished Apr 04 12:31:45 PM PDT 24
Peak memory 213012 kb
Host smart-7a1826e6-5e19-4838-acb3-acc0de414391
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3399327582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3399327582
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.2295937212
Short name T289
Test name
Test status
Simulation time 3503911622 ps
CPU time 51.69 seconds
Started Apr 04 12:31:14 PM PDT 24
Finished Apr 04 12:32:06 PM PDT 24
Peak memory 199660 kb
Host smart-231035dd-f4cf-428f-852a-40bea605a979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295937212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2295937212
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.4279337157
Short name T579
Test name
Test status
Simulation time 2520107062 ps
CPU time 144.45 seconds
Started Apr 04 12:31:44 PM PDT 24
Finished Apr 04 12:34:09 PM PDT 24
Peak memory 199544 kb
Host smart-1755c843-74ba-47f5-bc5b-96f664fe1963
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4279337157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.4279337157
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3659867162
Short name T473
Test name
Test status
Simulation time 5705390726 ps
CPU time 30.16 seconds
Started Apr 04 12:31:39 PM PDT 24
Finished Apr 04 12:32:09 PM PDT 24
Peak memory 199584 kb
Host smart-1c569134-6eba-4873-9809-46d8403b27a1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659867162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3659867162
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.152545961
Short name T528
Test name
Test status
Simulation time 1149771540 ps
CPU time 21.7 seconds
Started Apr 04 12:31:04 PM PDT 24
Finished Apr 04 12:31:25 PM PDT 24
Peak memory 199500 kb
Host smart-10411d2f-2441-4899-b0ae-e2f89c9d1fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152545961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.152545961
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.284748195
Short name T78
Test name
Test status
Simulation time 108635064 ps
CPU time 1.6 seconds
Started Apr 04 12:32:38 PM PDT 24
Finished Apr 04 12:32:40 PM PDT 24
Peak memory 199124 kb
Host smart-9b249ad4-205d-4ed6-ab94-7f4ccd3b0c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284748195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.284748195
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.876840549
Short name T302
Test name
Test status
Simulation time 493680546682 ps
CPU time 1748.89 seconds
Started Apr 04 12:31:01 PM PDT 24
Finished Apr 04 01:00:11 PM PDT 24
Peak memory 239688 kb
Host smart-e6c0b0b4-6bc7-45f9-a7c5-207c7fdbdb8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876840549 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.876840549
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.1285185484
Short name T407
Test name
Test status
Simulation time 53802535 ps
CPU time 1.21 seconds
Started Apr 04 12:31:17 PM PDT 24
Finished Apr 04 12:31:18 PM PDT 24
Peak memory 199424 kb
Host smart-43df7bcf-1062-45d8-b434-e721b0bc2df6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285185484 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.1285185484
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.2040402772
Short name T249
Test name
Test status
Simulation time 30789088498 ps
CPU time 427.56 seconds
Started Apr 04 12:31:01 PM PDT 24
Finished Apr 04 12:38:09 PM PDT 24
Peak memory 199632 kb
Host smart-31c8b3da-6e65-480a-a86c-bf758af54d7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040402772 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.2040402772
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.565040027
Short name T26
Test name
Test status
Simulation time 1538018522 ps
CPU time 7.3 seconds
Started Apr 04 12:31:11 PM PDT 24
Finished Apr 04 12:31:18 PM PDT 24
Peak memory 199372 kb
Host smart-1502759a-7bad-4d5a-9cef-fcde9ea5b6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565040027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.565040027
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.592641938
Short name T18
Test name
Test status
Simulation time 45311704 ps
CPU time 0.66 seconds
Started Apr 04 12:32:37 PM PDT 24
Finished Apr 04 12:32:39 PM PDT 24
Peak memory 192300 kb
Host smart-a68d9880-4d1a-4577-bcce-db4dfb870c59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592641938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.592641938
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.2138001400
Short name T538
Test name
Test status
Simulation time 881180008 ps
CPU time 28.64 seconds
Started Apr 04 12:31:10 PM PDT 24
Finished Apr 04 12:31:39 PM PDT 24
Peak memory 215928 kb
Host smart-8325e16f-81db-4cbe-af72-48b093a8406e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2138001400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2138001400
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.4123780835
Short name T508
Test name
Test status
Simulation time 230785241 ps
CPU time 3.93 seconds
Started Apr 04 12:33:25 PM PDT 24
Finished Apr 04 12:33:29 PM PDT 24
Peak memory 198140 kb
Host smart-0baa3091-97fd-4b1c-8c15-32c489d71313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123780835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.4123780835
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.3315347655
Short name T403
Test name
Test status
Simulation time 24476054 ps
CPU time 0.88 seconds
Started Apr 04 12:31:01 PM PDT 24
Finished Apr 04 12:31:02 PM PDT 24
Peak memory 197776 kb
Host smart-2795a9ef-5a35-4fcb-8946-fcdc71139b93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3315347655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3315347655
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.2395393370
Short name T429
Test name
Test status
Simulation time 2603080889 ps
CPU time 146.41 seconds
Started Apr 04 12:30:57 PM PDT 24
Finished Apr 04 12:33:24 PM PDT 24
Peak memory 199604 kb
Host smart-ec4170af-434a-4cc3-98d4-08f11e3789ae
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395393370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2395393370
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.361146961
Short name T201
Test name
Test status
Simulation time 25098250278 ps
CPU time 77.49 seconds
Started Apr 04 12:33:27 PM PDT 24
Finished Apr 04 12:34:45 PM PDT 24
Peak memory 199484 kb
Host smart-ccd69ae0-772e-462b-b1bb-f754974e7ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361146961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.361146961
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.4070648949
Short name T503
Test name
Test status
Simulation time 3897607140 ps
CPU time 5.44 seconds
Started Apr 04 12:33:26 PM PDT 24
Finished Apr 04 12:33:32 PM PDT 24
Peak memory 199444 kb
Host smart-894cb783-d8f1-4f53-b584-03611101d0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070648949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.4070648949
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.569260787
Short name T292
Test name
Test status
Simulation time 271372204 ps
CPU time 1.16 seconds
Started Apr 04 12:31:09 PM PDT 24
Finished Apr 04 12:31:11 PM PDT 24
Peak memory 199212 kb
Host smart-0b065e00-8893-4cdd-9ed8-a0fba737de0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569260787 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.hmac_test_hmac_vectors.569260787
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.3568460112
Short name T154
Test name
Test status
Simulation time 46462045304 ps
CPU time 531.43 seconds
Started Apr 04 12:32:40 PM PDT 24
Finished Apr 04 12:41:32 PM PDT 24
Peak memory 199448 kb
Host smart-9e8feef4-3af5-4549-82b3-42703dede335
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568460112 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.3568460112
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.330978347
Short name T567
Test name
Test status
Simulation time 4541582059 ps
CPU time 70.11 seconds
Started Apr 04 12:31:39 PM PDT 24
Finished Apr 04 12:32:49 PM PDT 24
Peak memory 199592 kb
Host smart-374defee-58b9-4ae3-a88e-e9a71c4c6c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330978347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.330978347
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.4004367795
Short name T174
Test name
Test status
Simulation time 16233598 ps
CPU time 0.69 seconds
Started Apr 04 12:31:10 PM PDT 24
Finished Apr 04 12:31:11 PM PDT 24
Peak memory 195116 kb
Host smart-b1c08d6d-513c-4041-b363-1f2a39726d78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004367795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.4004367795
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.1904034223
Short name T582
Test name
Test status
Simulation time 508283787 ps
CPU time 4.85 seconds
Started Apr 04 12:31:59 PM PDT 24
Finished Apr 04 12:32:04 PM PDT 24
Peak memory 207608 kb
Host smart-8cd56698-b73d-46b7-bd7b-0928097891b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1904034223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1904034223
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.69098004
Short name T36
Test name
Test status
Simulation time 4726778363 ps
CPU time 65.63 seconds
Started Apr 04 12:31:22 PM PDT 24
Finished Apr 04 12:32:28 PM PDT 24
Peak memory 199600 kb
Host smart-32095c8a-00f7-47a1-8b7f-d1f52b92b7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69098004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.69098004
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.827336222
Short name T547
Test name
Test status
Simulation time 674867810 ps
CPU time 8.23 seconds
Started Apr 04 12:31:13 PM PDT 24
Finished Apr 04 12:31:22 PM PDT 24
Peak memory 199500 kb
Host smart-7d196438-fb08-4e10-acb8-c8adaf6a6f18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=827336222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.827336222
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.788857559
Short name T266
Test name
Test status
Simulation time 4278169571 ps
CPU time 78.82 seconds
Started Apr 04 12:31:14 PM PDT 24
Finished Apr 04 12:32:33 PM PDT 24
Peak memory 199548 kb
Host smart-ee61be8c-a7ea-410f-8d25-faa7ebf42430
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788857559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.788857559
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.4265311473
Short name T95
Test name
Test status
Simulation time 1962592092 ps
CPU time 62.31 seconds
Started Apr 04 12:31:54 PM PDT 24
Finished Apr 04 12:32:56 PM PDT 24
Peak memory 199448 kb
Host smart-17f6aa2b-8da6-490e-8e09-1b20895a01a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265311473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.4265311473
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.772376726
Short name T435
Test name
Test status
Simulation time 266193456 ps
CPU time 2.53 seconds
Started Apr 04 12:32:39 PM PDT 24
Finished Apr 04 12:32:42 PM PDT 24
Peak memory 199376 kb
Host smart-c283b78b-fc2f-4b8c-8af0-b9456f4aafec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772376726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.772376726
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.1019033950
Short name T237
Test name
Test status
Simulation time 21852339826 ps
CPU time 1150.94 seconds
Started Apr 04 12:31:09 PM PDT 24
Finished Apr 04 12:50:21 PM PDT 24
Peak memory 215612 kb
Host smart-9d50606d-6f2f-4f6f-856d-a171a7548d6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019033950 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1019033950
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.1606597586
Short name T342
Test name
Test status
Simulation time 117964681 ps
CPU time 1.23 seconds
Started Apr 04 12:31:24 PM PDT 24
Finished Apr 04 12:31:25 PM PDT 24
Peak memory 199508 kb
Host smart-55400729-363e-4652-96ad-aab3fecc02b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606597586 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.1606597586
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.2752363375
Short name T326
Test name
Test status
Simulation time 10055016431 ps
CPU time 425.94 seconds
Started Apr 04 12:31:16 PM PDT 24
Finished Apr 04 12:38:22 PM PDT 24
Peak memory 199652 kb
Host smart-20f2b3a3-31ae-4075-a535-d6a441415d74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752363375 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.2752363375
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1348099037
Short name T141
Test name
Test status
Simulation time 6132204320 ps
CPU time 47.73 seconds
Started Apr 04 12:31:15 PM PDT 24
Finished Apr 04 12:32:03 PM PDT 24
Peak memory 199636 kb
Host smart-6358579e-f63a-4d71-9654-9bdd8964a8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348099037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1348099037
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.568726950
Short name T311
Test name
Test status
Simulation time 16459635 ps
CPU time 0.56 seconds
Started Apr 04 12:31:15 PM PDT 24
Finished Apr 04 12:31:15 PM PDT 24
Peak memory 193988 kb
Host smart-93101777-9f22-4773-8bd4-7a0a10601069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568726950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.568726950
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.3832473855
Short name T507
Test name
Test status
Simulation time 1713335704 ps
CPU time 37.8 seconds
Started Apr 04 12:31:26 PM PDT 24
Finished Apr 04 12:32:04 PM PDT 24
Peak memory 232200 kb
Host smart-fc1d625c-013c-4ee0-b216-1a155da5d3c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3832473855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3832473855
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.678679215
Short name T303
Test name
Test status
Simulation time 752101938 ps
CPU time 41.23 seconds
Started Apr 04 12:31:40 PM PDT 24
Finished Apr 04 12:32:22 PM PDT 24
Peak memory 199432 kb
Host smart-8abd93ee-c64b-45c1-81ae-96714aa43500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678679215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.678679215
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2400820369
Short name T386
Test name
Test status
Simulation time 5296909720 ps
CPU time 43.65 seconds
Started Apr 04 12:31:23 PM PDT 24
Finished Apr 04 12:32:06 PM PDT 24
Peak memory 199644 kb
Host smart-880223cb-e76e-4be5-bf27-032ea97e46e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2400820369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2400820369
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3281764819
Short name T181
Test name
Test status
Simulation time 551721765 ps
CPU time 9.47 seconds
Started Apr 04 12:31:14 PM PDT 24
Finished Apr 04 12:31:24 PM PDT 24
Peak memory 199512 kb
Host smart-e721dead-b4f0-4aa5-94d0-a443f7834168
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281764819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3281764819
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1484167740
Short name T59
Test name
Test status
Simulation time 1761935367 ps
CPU time 34.54 seconds
Started Apr 04 12:31:41 PM PDT 24
Finished Apr 04 12:32:16 PM PDT 24
Peak memory 199456 kb
Host smart-32c27ee9-80d6-48a6-a228-e17f11007180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484167740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1484167740
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.3178401038
Short name T390
Test name
Test status
Simulation time 89495810 ps
CPU time 1.5 seconds
Started Apr 04 12:31:24 PM PDT 24
Finished Apr 04 12:31:26 PM PDT 24
Peak memory 199444 kb
Host smart-610ec0b9-0e2e-452d-9b17-e7a8aae65664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178401038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3178401038
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.4008034603
Short name T561
Test name
Test status
Simulation time 40407420760 ps
CPU time 2266.07 seconds
Started Apr 04 12:31:19 PM PDT 24
Finished Apr 04 01:09:06 PM PDT 24
Peak memory 215724 kb
Host smart-f1f56c50-0649-4957-8af6-510ca8fe53d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008034603 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.4008034603
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.331482184
Short name T204
Test name
Test status
Simulation time 456258964 ps
CPU time 1.36 seconds
Started Apr 04 12:31:09 PM PDT 24
Finished Apr 04 12:31:11 PM PDT 24
Peak memory 199516 kb
Host smart-1cd40e3d-0105-4efc-a995-e32d75c20b96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331482184 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_hmac_vectors.331482184
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.1420597182
Short name T314
Test name
Test status
Simulation time 13011982672 ps
CPU time 376.88 seconds
Started Apr 04 12:31:17 PM PDT 24
Finished Apr 04 12:37:34 PM PDT 24
Peak memory 199608 kb
Host smart-ccf3970b-d5d5-46bd-9ed7-09d82231cced
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420597182 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.1420597182
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.330785710
Short name T226
Test name
Test status
Simulation time 7825362266 ps
CPU time 95.99 seconds
Started Apr 04 12:31:43 PM PDT 24
Finished Apr 04 12:33:19 PM PDT 24
Peak memory 199588 kb
Host smart-c9e14634-dc45-4a3a-95ad-aebf24f69cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330785710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.330785710
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1826155540
Short name T137
Test name
Test status
Simulation time 38234187 ps
CPU time 0.61 seconds
Started Apr 04 12:33:21 PM PDT 24
Finished Apr 04 12:33:23 PM PDT 24
Peak memory 193352 kb
Host smart-a30cbe74-b8d5-4838-a9ab-e5bc0fc2f410
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826155540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1826155540
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.758147406
Short name T271
Test name
Test status
Simulation time 1303006290 ps
CPU time 48.33 seconds
Started Apr 04 12:31:18 PM PDT 24
Finished Apr 04 12:32:07 PM PDT 24
Peak memory 231868 kb
Host smart-01184149-f2ab-42fa-8ee0-e55c92e38f1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=758147406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.758147406
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.953710646
Short name T491
Test name
Test status
Simulation time 8484116471 ps
CPU time 34.99 seconds
Started Apr 04 12:31:17 PM PDT 24
Finished Apr 04 12:31:52 PM PDT 24
Peak memory 199592 kb
Host smart-26213700-41b7-467b-b922-35ddccb8234a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953710646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.953710646
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3181808632
Short name T533
Test name
Test status
Simulation time 1974366216 ps
CPU time 56.89 seconds
Started Apr 04 12:31:59 PM PDT 24
Finished Apr 04 12:32:56 PM PDT 24
Peak memory 199428 kb
Host smart-277148b8-a659-46b8-981c-89a145eb7f37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3181808632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3181808632
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3351535756
Short name T306
Test name
Test status
Simulation time 5228821401 ps
CPU time 91.17 seconds
Started Apr 04 12:31:30 PM PDT 24
Finished Apr 04 12:33:01 PM PDT 24
Peak memory 199588 kb
Host smart-3fec860e-69b8-4b89-8997-04b55f4856bb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351535756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3351535756
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3352386815
Short name T260
Test name
Test status
Simulation time 10842800609 ps
CPU time 82.67 seconds
Started Apr 04 12:32:03 PM PDT 24
Finished Apr 04 12:33:26 PM PDT 24
Peak memory 199584 kb
Host smart-d909d9c9-fd4d-4110-a903-883585774432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352386815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3352386815
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.254617362
Short name T463
Test name
Test status
Simulation time 134418301 ps
CPU time 2.29 seconds
Started Apr 04 12:31:15 PM PDT 24
Finished Apr 04 12:31:17 PM PDT 24
Peak memory 199484 kb
Host smart-7beb9618-f266-4ac1-925b-ce7520da0dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254617362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.254617362
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.4059177382
Short name T264
Test name
Test status
Simulation time 74099217294 ps
CPU time 475.95 seconds
Started Apr 04 12:31:21 PM PDT 24
Finished Apr 04 12:39:18 PM PDT 24
Peak memory 240576 kb
Host smart-bf92ceab-c0ed-4e45-9fd6-0ce2a301f7c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059177382 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.4059177382
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.553612541
Short name T360
Test name
Test status
Simulation time 176174656 ps
CPU time 1.25 seconds
Started Apr 04 12:31:47 PM PDT 24
Finished Apr 04 12:31:49 PM PDT 24
Peak memory 199316 kb
Host smart-93b98a4d-ddd3-45d6-8455-e8bfa04e50b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553612541 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.hmac_test_hmac_vectors.553612541
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.3884970565
Short name T513
Test name
Test status
Simulation time 113738316451 ps
CPU time 493.97 seconds
Started Apr 04 12:31:41 PM PDT 24
Finished Apr 04 12:39:55 PM PDT 24
Peak memory 199592 kb
Host smart-f0ae8906-ee36-497e-be6e-76f228840aff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884970565 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.3884970565
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1503613992
Short name T375
Test name
Test status
Simulation time 3313295953 ps
CPU time 20.87 seconds
Started Apr 04 12:31:36 PM PDT 24
Finished Apr 04 12:31:57 PM PDT 24
Peak memory 199544 kb
Host smart-385ff6a9-99a4-447f-bd0b-b49dea091ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503613992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1503613992
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.2783754983
Short name T504
Test name
Test status
Simulation time 20221994 ps
CPU time 0.57 seconds
Started Apr 04 12:31:21 PM PDT 24
Finished Apr 04 12:31:22 PM PDT 24
Peak memory 195184 kb
Host smart-2e9b06f6-8cb0-4bd6-9b5a-ff5616541757
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783754983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2783754983
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.647819436
Short name T562
Test name
Test status
Simulation time 830317712 ps
CPU time 28.06 seconds
Started Apr 04 12:31:21 PM PDT 24
Finished Apr 04 12:31:50 PM PDT 24
Peak memory 225456 kb
Host smart-8b5e3a1d-046d-4243-ac09-27db7978d8c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=647819436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.647819436
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1573593870
Short name T169
Test name
Test status
Simulation time 1778867784 ps
CPU time 28.13 seconds
Started Apr 04 12:31:23 PM PDT 24
Finished Apr 04 12:31:51 PM PDT 24
Peak memory 199488 kb
Host smart-deadd387-c498-4dab-8ff1-2c4adceb7723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573593870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1573593870
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2112312533
Short name T276
Test name
Test status
Simulation time 2105152964 ps
CPU time 124.79 seconds
Started Apr 04 12:31:23 PM PDT 24
Finished Apr 04 12:33:28 PM PDT 24
Peak memory 199460 kb
Host smart-76249451-31c0-437f-a0dd-8f0f614d19b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2112312533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2112312533
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.2672918695
Short name T338
Test name
Test status
Simulation time 4131510968 ps
CPU time 154.88 seconds
Started Apr 04 12:31:21 PM PDT 24
Finished Apr 04 12:33:56 PM PDT 24
Peak memory 199588 kb
Host smart-8ad4abed-4139-4a35-9afb-eaf00e9fbb77
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672918695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2672918695
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2757823762
Short name T162
Test name
Test status
Simulation time 1679770292 ps
CPU time 23.95 seconds
Started Apr 04 12:31:21 PM PDT 24
Finished Apr 04 12:31:45 PM PDT 24
Peak memory 199516 kb
Host smart-111e5217-461e-42a3-bdc2-adac2f8b98b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757823762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2757823762
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.93275802
Short name T245
Test name
Test status
Simulation time 454712493 ps
CPU time 6.24 seconds
Started Apr 04 12:31:44 PM PDT 24
Finished Apr 04 12:31:50 PM PDT 24
Peak memory 199436 kb
Host smart-66353cd3-7bc5-4281-bc09-4be568c045fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93275802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.93275802
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.1716687623
Short name T490
Test name
Test status
Simulation time 36914966700 ps
CPU time 915.6 seconds
Started Apr 04 12:31:13 PM PDT 24
Finished Apr 04 12:46:29 PM PDT 24
Peak memory 199584 kb
Host smart-651a3105-1684-4744-85ae-31d07839bb5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716687623 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.1716687623
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.1317454293
Short name T530
Test name
Test status
Simulation time 182134483 ps
CPU time 1.46 seconds
Started Apr 04 12:31:56 PM PDT 24
Finished Apr 04 12:31:57 PM PDT 24
Peak memory 199380 kb
Host smart-9d276793-5d51-4f29-9163-01caf7423a9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317454293 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.1317454293
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.1033121315
Short name T151
Test name
Test status
Simulation time 27760589771 ps
CPU time 444.56 seconds
Started Apr 04 12:31:23 PM PDT 24
Finished Apr 04 12:38:47 PM PDT 24
Peak memory 199652 kb
Host smart-4fe79131-793c-46e4-ac79-92ab7b119653
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033121315 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.1033121315
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2425979583
Short name T323
Test name
Test status
Simulation time 40531329288 ps
CPU time 87.16 seconds
Started Apr 04 12:31:21 PM PDT 24
Finished Apr 04 12:32:49 PM PDT 24
Peak memory 199648 kb
Host smart-ef22b561-0e2c-44a6-bd44-b84c3c9c18da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425979583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2425979583
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3297192726
Short name T197
Test name
Test status
Simulation time 14245760 ps
CPU time 0.61 seconds
Started Apr 04 12:31:49 PM PDT 24
Finished Apr 04 12:31:49 PM PDT 24
Peak memory 195120 kb
Host smart-b257a37f-534d-40c1-8049-af781c8a5bfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297192726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3297192726
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2659468659
Short name T466
Test name
Test status
Simulation time 743132369 ps
CPU time 6.31 seconds
Started Apr 04 12:33:27 PM PDT 24
Finished Apr 04 12:33:34 PM PDT 24
Peak memory 199340 kb
Host smart-a64d720a-0e61-43a7-bbe0-c64a0064c5eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2659468659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2659468659
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.2567582326
Short name T355
Test name
Test status
Simulation time 186586521 ps
CPU time 9.44 seconds
Started Apr 04 12:32:04 PM PDT 24
Finished Apr 04 12:32:14 PM PDT 24
Peak memory 199516 kb
Host smart-24feac7c-c006-4157-86d4-69f17cea6a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567582326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.2567582326
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3186902589
Short name T243
Test name
Test status
Simulation time 1026721681 ps
CPU time 11.74 seconds
Started Apr 04 12:33:25 PM PDT 24
Finished Apr 04 12:33:37 PM PDT 24
Peak memory 197756 kb
Host smart-2ea6b8e7-8ca1-448c-ac84-f535cb4dfb92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3186902589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3186902589
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2982250058
Short name T44
Test name
Test status
Simulation time 6540040605 ps
CPU time 88.01 seconds
Started Apr 04 12:33:25 PM PDT 24
Finished Apr 04 12:34:54 PM PDT 24
Peak memory 198284 kb
Host smart-3d222077-0528-434e-8ede-c9038fda52a5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982250058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2982250058
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.2252336717
Short name T231
Test name
Test status
Simulation time 11493822515 ps
CPU time 93.63 seconds
Started Apr 04 12:31:14 PM PDT 24
Finished Apr 04 12:32:48 PM PDT 24
Peak memory 199596 kb
Host smart-bd8f7f5f-6de5-43d3-85d8-c6111a77ec1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252336717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2252336717
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1851142132
Short name T119
Test name
Test status
Simulation time 231508800 ps
CPU time 1.85 seconds
Started Apr 04 12:31:15 PM PDT 24
Finished Apr 04 12:31:17 PM PDT 24
Peak memory 199544 kb
Host smart-1e6e73ab-fc20-43a6-a88a-38590f295b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851142132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1851142132
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.2998513927
Short name T480
Test name
Test status
Simulation time 133522242116 ps
CPU time 665.93 seconds
Started Apr 04 12:31:25 PM PDT 24
Finished Apr 04 12:42:36 PM PDT 24
Peak memory 199576 kb
Host smart-dd35d579-0ae6-4341-9ab9-816df6031fc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998513927 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.2998513927
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.1761068097
Short name T152
Test name
Test status
Simulation time 106983121 ps
CPU time 1.17 seconds
Started Apr 04 12:33:53 PM PDT 24
Finished Apr 04 12:33:55 PM PDT 24
Peak memory 198912 kb
Host smart-96cc04eb-880d-41a9-8285-bff3f27479aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761068097 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.1761068097
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.1093866968
Short name T122
Test name
Test status
Simulation time 208798220171 ps
CPU time 512.79 seconds
Started Apr 04 12:31:36 PM PDT 24
Finished Apr 04 12:40:09 PM PDT 24
Peak memory 199616 kb
Host smart-0be8b5f8-a767-4564-baf0-71ed2b13ffc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093866968 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.1093866968
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.1311514052
Short name T248
Test name
Test status
Simulation time 565249942 ps
CPU time 14.41 seconds
Started Apr 04 12:31:24 PM PDT 24
Finished Apr 04 12:31:38 PM PDT 24
Peak memory 199504 kb
Host smart-6a7e71b1-0ff9-4cf1-9315-478369a4d898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311514052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1311514052
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2188782789
Short name T501
Test name
Test status
Simulation time 13532223 ps
CPU time 0.58 seconds
Started Apr 04 12:31:21 PM PDT 24
Finished Apr 04 12:31:22 PM PDT 24
Peak memory 194808 kb
Host smart-fc43f0a3-d962-42cf-9d8d-a2def1f30203
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188782789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2188782789
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1120065190
Short name T227
Test name
Test status
Simulation time 815196102 ps
CPU time 15.42 seconds
Started Apr 04 12:31:22 PM PDT 24
Finished Apr 04 12:31:38 PM PDT 24
Peak memory 207692 kb
Host smart-efde1bf8-6edf-43a9-b639-30c44d547cf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1120065190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1120065190
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1479221724
Short name T305
Test name
Test status
Simulation time 3115438936 ps
CPU time 49.01 seconds
Started Apr 04 12:33:15 PM PDT 24
Finished Apr 04 12:34:05 PM PDT 24
Peak memory 199312 kb
Host smart-1e3af932-3ddd-42f8-a291-d1fb22cae1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479221724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1479221724
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1963429576
Short name T369
Test name
Test status
Simulation time 8193848266 ps
CPU time 119.87 seconds
Started Apr 04 12:31:21 PM PDT 24
Finished Apr 04 12:33:21 PM PDT 24
Peak memory 199664 kb
Host smart-01d81062-b282-4d49-ae4a-6fa5b961d95e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1963429576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1963429576
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3324039956
Short name T497
Test name
Test status
Simulation time 62771471395 ps
CPU time 77.67 seconds
Started Apr 04 12:31:21 PM PDT 24
Finished Apr 04 12:32:39 PM PDT 24
Peak memory 199656 kb
Host smart-463c8f31-d7a2-4c7b-901c-28ffa4c5188b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324039956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3324039956
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.2090096799
Short name T268
Test name
Test status
Simulation time 27834474956 ps
CPU time 51.8 seconds
Started Apr 04 12:31:17 PM PDT 24
Finished Apr 04 12:32:10 PM PDT 24
Peak memory 199660 kb
Host smart-48ff67d7-32c0-4efe-b04b-b3d9aa135d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090096799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.2090096799
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3117893147
Short name T362
Test name
Test status
Simulation time 193036854 ps
CPU time 5.39 seconds
Started Apr 04 12:31:16 PM PDT 24
Finished Apr 04 12:31:22 PM PDT 24
Peak memory 199428 kb
Host smart-3bbd4d5d-0ed8-4364-b95e-a7c444cf5120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117893147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3117893147
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.563176762
Short name T69
Test name
Test status
Simulation time 66984479068 ps
CPU time 1014.36 seconds
Started Apr 04 12:32:38 PM PDT 24
Finished Apr 04 12:49:32 PM PDT 24
Peak memory 240044 kb
Host smart-9759eb42-7c20-4f2d-ab33-d08e57d007bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563176762 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.563176762
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.149281155
Short name T209
Test name
Test status
Simulation time 636213728 ps
CPU time 1.06 seconds
Started Apr 04 12:31:54 PM PDT 24
Finished Apr 04 12:31:55 PM PDT 24
Peak memory 198996 kb
Host smart-d9661f24-8673-4eba-9bd4-60e2a9191859
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149281155 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.hmac_test_hmac_vectors.149281155
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.2082937896
Short name T583
Test name
Test status
Simulation time 31344322694 ps
CPU time 443.44 seconds
Started Apr 04 12:31:21 PM PDT 24
Finished Apr 04 12:38:45 PM PDT 24
Peak memory 199648 kb
Host smart-da04063a-f34b-4beb-bec7-87870ac3eb50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082937896 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.2082937896
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3101896330
Short name T588
Test name
Test status
Simulation time 5955104772 ps
CPU time 57.13 seconds
Started Apr 04 12:31:13 PM PDT 24
Finished Apr 04 12:32:11 PM PDT 24
Peak memory 199560 kb
Host smart-ddb0f348-a742-4974-90bf-7c3908bf7de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101896330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3101896330
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.850183344
Short name T251
Test name
Test status
Simulation time 12251375 ps
CPU time 0.59 seconds
Started Apr 04 12:29:04 PM PDT 24
Finished Apr 04 12:29:05 PM PDT 24
Peak memory 194752 kb
Host smart-32dc3195-0325-4923-813a-f8d428799f61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850183344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.850183344
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.2843406779
Short name T194
Test name
Test status
Simulation time 1184323378 ps
CPU time 46.97 seconds
Started Apr 04 12:28:51 PM PDT 24
Finished Apr 04 12:29:38 PM PDT 24
Peak memory 228076 kb
Host smart-65314bfe-4c03-4bd0-98f2-0a69187235bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2843406779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2843406779
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.136028959
Short name T228
Test name
Test status
Simulation time 36132795 ps
CPU time 1.82 seconds
Started Apr 04 12:28:35 PM PDT 24
Finished Apr 04 12:28:37 PM PDT 24
Peak memory 199380 kb
Host smart-0afe359c-647c-4972-99b7-657723a1ecd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136028959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.136028959
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2928986679
Short name T166
Test name
Test status
Simulation time 15326824 ps
CPU time 0.7 seconds
Started Apr 04 12:28:13 PM PDT 24
Finished Apr 04 12:28:14 PM PDT 24
Peak memory 196680 kb
Host smart-4ec78090-1fb5-4a84-b8b3-14d35854da97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2928986679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2928986679
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.3504939959
Short name T167
Test name
Test status
Simulation time 138674404564 ps
CPU time 125.54 seconds
Started Apr 04 12:28:30 PM PDT 24
Finished Apr 04 12:30:36 PM PDT 24
Peak memory 199624 kb
Host smart-f17a9aad-c12a-4f31-a705-a56abac7ad99
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504939959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3504939959
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.4021664397
Short name T402
Test name
Test status
Simulation time 2787721094 ps
CPU time 84.27 seconds
Started Apr 04 12:28:21 PM PDT 24
Finished Apr 04 12:29:45 PM PDT 24
Peak memory 199608 kb
Host smart-3b166b0a-909d-4ea9-a970-46428af309af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021664397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.4021664397
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1250395724
Short name T28
Test name
Test status
Simulation time 63471372 ps
CPU time 0.78 seconds
Started Apr 04 12:28:48 PM PDT 24
Finished Apr 04 12:28:49 PM PDT 24
Peak memory 217888 kb
Host smart-6af82db3-0e04-42b6-ad1d-b2c1d75ba74a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250395724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1250395724
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.2927556661
Short name T191
Test name
Test status
Simulation time 371858067 ps
CPU time 5.77 seconds
Started Apr 04 12:28:21 PM PDT 24
Finished Apr 04 12:28:27 PM PDT 24
Peak memory 199416 kb
Host smart-e62cde92-9ac0-4243-9a90-e7bdd4dac8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927556661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2927556661
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1207083275
Short name T45
Test name
Test status
Simulation time 269463619720 ps
CPU time 1038.1 seconds
Started Apr 04 12:29:05 PM PDT 24
Finished Apr 04 12:46:23 PM PDT 24
Peak memory 239448 kb
Host smart-e6b8378d-d313-4864-86de-9be65250d720
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207083275 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1207083275
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.3541275562
Short name T557
Test name
Test status
Simulation time 43577011 ps
CPU time 1.02 seconds
Started Apr 04 12:28:35 PM PDT 24
Finished Apr 04 12:28:36 PM PDT 24
Peak memory 198792 kb
Host smart-1acd14c6-7861-4e24-802a-6a904f51755d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541275562 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.3541275562
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.2485418897
Short name T549
Test name
Test status
Simulation time 99279006656 ps
CPU time 493.54 seconds
Started Apr 04 12:28:36 PM PDT 24
Finished Apr 04 12:36:50 PM PDT 24
Peak memory 199584 kb
Host smart-f0fe53ca-39bf-48af-ad50-6a47fd009073
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485418897 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.2485418897
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2582699218
Short name T423
Test name
Test status
Simulation time 26362683072 ps
CPU time 61.99 seconds
Started Apr 04 12:28:51 PM PDT 24
Finished Apr 04 12:29:53 PM PDT 24
Peak memory 199552 kb
Host smart-92d5d58f-4a56-4b8d-af12-be127ce072fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582699218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2582699218
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.4134002575
Short name T150
Test name
Test status
Simulation time 14381806 ps
CPU time 0.56 seconds
Started Apr 04 12:33:53 PM PDT 24
Finished Apr 04 12:33:54 PM PDT 24
Peak memory 194772 kb
Host smart-8ace143d-5d7c-41d6-b1ee-270845d84a69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134002575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.4134002575
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.2621930617
Short name T581
Test name
Test status
Simulation time 393701829 ps
CPU time 3.43 seconds
Started Apr 04 12:31:20 PM PDT 24
Finished Apr 04 12:31:24 PM PDT 24
Peak memory 199492 kb
Host smart-262819db-8056-4293-9419-f2fdd60f015c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2621930617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2621930617
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3916090607
Short name T240
Test name
Test status
Simulation time 1531657393 ps
CPU time 24.04 seconds
Started Apr 04 12:31:14 PM PDT 24
Finished Apr 04 12:31:38 PM PDT 24
Peak memory 199488 kb
Host smart-cca43771-8aca-4812-840a-1d1d57c2ab06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916090607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3916090607
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.354558078
Short name T534
Test name
Test status
Simulation time 3980112598 ps
CPU time 59.71 seconds
Started Apr 04 12:31:32 PM PDT 24
Finished Apr 04 12:32:31 PM PDT 24
Peak memory 199620 kb
Host smart-b9942773-c126-4dba-b15c-7ac040f92e13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=354558078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.354558078
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.421926838
Short name T381
Test name
Test status
Simulation time 208080468 ps
CPU time 11.73 seconds
Started Apr 04 12:31:51 PM PDT 24
Finished Apr 04 12:32:03 PM PDT 24
Peak memory 199528 kb
Host smart-69a8bfd0-1f12-45d8-9c37-33aa65d7f220
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421926838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.421926838
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.2350386414
Short name T525
Test name
Test status
Simulation time 1474349018 ps
CPU time 21.65 seconds
Started Apr 04 12:31:14 PM PDT 24
Finished Apr 04 12:31:36 PM PDT 24
Peak memory 199504 kb
Host smart-69b6bbf9-0917-4822-8083-402aff5271e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350386414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2350386414
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2762114232
Short name T160
Test name
Test status
Simulation time 193653969 ps
CPU time 1.83 seconds
Started Apr 04 12:31:23 PM PDT 24
Finished Apr 04 12:31:25 PM PDT 24
Peak memory 199552 kb
Host smart-466d8d78-d860-4d74-9029-a0140fb52a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762114232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2762114232
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.4279981063
Short name T316
Test name
Test status
Simulation time 40018427 ps
CPU time 0.97 seconds
Started Apr 04 12:33:15 PM PDT 24
Finished Apr 04 12:33:17 PM PDT 24
Peak memory 197852 kb
Host smart-d69551c7-48a8-4dc3-b6ad-660a0e78a57d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279981063 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.4279981063
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.2683989895
Short name T183
Test name
Test status
Simulation time 30623702310 ps
CPU time 473.03 seconds
Started Apr 04 12:31:20 PM PDT 24
Finished Apr 04 12:39:13 PM PDT 24
Peak memory 199648 kb
Host smart-9878f33f-001a-4e91-8d9a-f65d1637f7b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683989895 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.2683989895
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.793675759
Short name T288
Test name
Test status
Simulation time 4220359209 ps
CPU time 29.86 seconds
Started Apr 04 12:31:16 PM PDT 24
Finished Apr 04 12:31:46 PM PDT 24
Peak memory 199524 kb
Host smart-105602ad-7f4d-4cd0-b0ff-9974b4b1ad58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793675759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.793675759
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.145096508
Short name T574
Test name
Test status
Simulation time 16530456 ps
CPU time 0.57 seconds
Started Apr 04 12:31:22 PM PDT 24
Finished Apr 04 12:31:23 PM PDT 24
Peak memory 195108 kb
Host smart-be1a8c01-90e9-4811-a1f7-73d1e6c4a054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145096508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.145096508
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.97016819
Short name T192
Test name
Test status
Simulation time 2043559223 ps
CPU time 39.47 seconds
Started Apr 04 12:32:47 PM PDT 24
Finished Apr 04 12:33:27 PM PDT 24
Peak memory 215400 kb
Host smart-af47c492-cd22-4ba6-ab4f-22624b623e7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=97016819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.97016819
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2420596153
Short name T281
Test name
Test status
Simulation time 5922645319 ps
CPU time 47.02 seconds
Started Apr 04 12:31:32 PM PDT 24
Finished Apr 04 12:32:19 PM PDT 24
Peak memory 199616 kb
Host smart-2174a989-b60e-4bc4-9c3b-1e5f2cbf2f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420596153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2420596153
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1508178268
Short name T446
Test name
Test status
Simulation time 8366878626 ps
CPU time 115.96 seconds
Started Apr 04 12:31:21 PM PDT 24
Finished Apr 04 12:33:17 PM PDT 24
Peak memory 199668 kb
Host smart-883f6d41-668a-4cb6-b571-55b464784ad2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1508178268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1508178268
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.381345389
Short name T23
Test name
Test status
Simulation time 1543154491 ps
CPU time 88.04 seconds
Started Apr 04 12:31:11 PM PDT 24
Finished Apr 04 12:32:39 PM PDT 24
Peak memory 199468 kb
Host smart-97b2f132-a4b8-4601-9b60-ea554bc63ac9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381345389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.381345389
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.344521674
Short name T592
Test name
Test status
Simulation time 23899579015 ps
CPU time 100.59 seconds
Started Apr 04 12:32:42 PM PDT 24
Finished Apr 04 12:34:23 PM PDT 24
Peak memory 199604 kb
Host smart-3a5f0f10-147b-46c5-a770-31aed70533fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344521674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.344521674
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.4135018122
Short name T267
Test name
Test status
Simulation time 52671334 ps
CPU time 1.73 seconds
Started Apr 04 12:31:23 PM PDT 24
Finished Apr 04 12:31:25 PM PDT 24
Peak memory 199548 kb
Host smart-c5059b60-a85d-4a35-91b2-779f9948937a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135018122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.4135018122
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1986862380
Short name T67
Test name
Test status
Simulation time 65008542563 ps
CPU time 487.64 seconds
Started Apr 04 12:31:22 PM PDT 24
Finished Apr 04 12:39:30 PM PDT 24
Peak memory 199660 kb
Host smart-cafdb6c5-22c5-4a40-a82e-11b1c5b1067a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986862380 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1986862380
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_stress_all_with_rand_reset.2072090034
Short name T7
Test name
Test status
Simulation time 43428830131 ps
CPU time 803.54 seconds
Started Apr 04 12:33:53 PM PDT 24
Finished Apr 04 12:47:17 PM PDT 24
Peak memory 256168 kb
Host smart-c3cbb074-273b-44b8-9544-9218881232b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2072090034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all_with_rand_reset.2072090034
Directory /workspace/41.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.3229385038
Short name T515
Test name
Test status
Simulation time 58916914 ps
CPU time 1.27 seconds
Started Apr 04 12:31:20 PM PDT 24
Finished Apr 04 12:31:22 PM PDT 24
Peak memory 199476 kb
Host smart-6de896d1-86a2-4413-8e38-4874417eb49f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229385038 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.3229385038
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.1789046967
Short name T374
Test name
Test status
Simulation time 113317405439 ps
CPU time 480.75 seconds
Started Apr 04 12:31:21 PM PDT 24
Finished Apr 04 12:39:22 PM PDT 24
Peak memory 199628 kb
Host smart-c779073a-ce00-45fd-ba54-5c57e3f3ebd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789046967 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.1789046967
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.1763463301
Short name T217
Test name
Test status
Simulation time 5206189361 ps
CPU time 70.18 seconds
Started Apr 04 12:31:45 PM PDT 24
Finished Apr 04 12:32:55 PM PDT 24
Peak memory 199660 kb
Host smart-271011f2-52cb-408a-928f-72c0c26cc563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763463301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1763463301
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.371332435
Short name T325
Test name
Test status
Simulation time 52022018 ps
CPU time 0.56 seconds
Started Apr 04 12:31:24 PM PDT 24
Finished Apr 04 12:31:24 PM PDT 24
Peak memory 195124 kb
Host smart-028c2325-dd0d-4e31-b815-978e6978ce4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371332435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.371332435
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2846114611
Short name T586
Test name
Test status
Simulation time 1733169343 ps
CPU time 52.68 seconds
Started Apr 04 12:33:53 PM PDT 24
Finished Apr 04 12:34:46 PM PDT 24
Peak memory 221784 kb
Host smart-fd18a5bf-d4cc-4062-ba0e-0ca5e314cb15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2846114611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2846114611
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2108007761
Short name T153
Test name
Test status
Simulation time 939307827 ps
CPU time 42.16 seconds
Started Apr 04 12:33:14 PM PDT 24
Finished Apr 04 12:33:57 PM PDT 24
Peak memory 199108 kb
Host smart-b4ff37dc-37aa-4880-8b28-4058017076c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108007761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2108007761
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.3092382169
Short name T568
Test name
Test status
Simulation time 375842786 ps
CPU time 18.15 seconds
Started Apr 04 12:31:24 PM PDT 24
Finished Apr 04 12:31:43 PM PDT 24
Peak memory 199480 kb
Host smart-16651912-e712-4613-81fe-ad41a9680092
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3092382169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3092382169
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.1753106639
Short name T265
Test name
Test status
Simulation time 2048239411 ps
CPU time 89.21 seconds
Started Apr 04 12:31:51 PM PDT 24
Finished Apr 04 12:33:20 PM PDT 24
Peak memory 199488 kb
Host smart-052822ce-bfbe-417c-8e77-4992c496a278
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753106639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.1753106639
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.917335283
Short name T286
Test name
Test status
Simulation time 6814559536 ps
CPU time 78.32 seconds
Started Apr 04 12:33:14 PM PDT 24
Finished Apr 04 12:34:33 PM PDT 24
Peak memory 199204 kb
Host smart-103ee802-09bb-461d-8ef2-172f758d0121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917335283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.917335283
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.699359132
Short name T156
Test name
Test status
Simulation time 344638246 ps
CPU time 2.63 seconds
Started Apr 04 12:31:27 PM PDT 24
Finished Apr 04 12:31:29 PM PDT 24
Peak memory 199512 kb
Host smart-4f250784-839d-40be-8eef-92f937150311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699359132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.699359132
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3478191287
Short name T70
Test name
Test status
Simulation time 209556374626 ps
CPU time 1295.87 seconds
Started Apr 04 12:31:55 PM PDT 24
Finished Apr 04 12:53:31 PM PDT 24
Peak memory 199604 kb
Host smart-94fd64cf-dafb-4690-9d13-343d6a8c0037
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478191287 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3478191287
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.660204072
Short name T224
Test name
Test status
Simulation time 96505422 ps
CPU time 1.01 seconds
Started Apr 04 12:31:32 PM PDT 24
Finished Apr 04 12:31:33 PM PDT 24
Peak memory 197860 kb
Host smart-7be65e2c-e233-4efd-94d0-1cb956c0479b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660204072 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_test_hmac_vectors.660204072
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.2429882140
Short name T334
Test name
Test status
Simulation time 7929867344 ps
CPU time 423.13 seconds
Started Apr 04 12:33:26 PM PDT 24
Finished Apr 04 12:40:30 PM PDT 24
Peak memory 199468 kb
Host smart-8f0bfb70-07af-4759-b90f-f9ec8d8ca79d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429882140 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.2429882140
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3887281312
Short name T479
Test name
Test status
Simulation time 16430560073 ps
CPU time 74.82 seconds
Started Apr 04 12:32:30 PM PDT 24
Finished Apr 04 12:33:45 PM PDT 24
Peak memory 199588 kb
Host smart-da98a721-94e6-4a64-95e4-30496c4fd6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887281312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3887281312
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3096887065
Short name T471
Test name
Test status
Simulation time 14914403 ps
CPU time 0.64 seconds
Started Apr 04 12:31:18 PM PDT 24
Finished Apr 04 12:31:19 PM PDT 24
Peak memory 195040 kb
Host smart-0ba844df-450f-495d-8492-e0cba2b8cf39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096887065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3096887065
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1744154829
Short name T418
Test name
Test status
Simulation time 1827546212 ps
CPU time 33.62 seconds
Started Apr 04 12:31:56 PM PDT 24
Finished Apr 04 12:32:30 PM PDT 24
Peak memory 212972 kb
Host smart-a4f74ece-224b-4c72-9150-60c76843c33f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1744154829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1744154829
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2146155870
Short name T128
Test name
Test status
Simulation time 1109832470 ps
CPU time 11.17 seconds
Started Apr 04 12:33:13 PM PDT 24
Finished Apr 04 12:33:25 PM PDT 24
Peak memory 197300 kb
Host smart-5f1df0e9-bb06-48b0-bbca-402d30a9446d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146155870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2146155870
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.3140574497
Short name T499
Test name
Test status
Simulation time 42687609306 ps
CPU time 129.53 seconds
Started Apr 04 12:31:23 PM PDT 24
Finished Apr 04 12:33:33 PM PDT 24
Peak memory 199676 kb
Host smart-73d9cf78-8164-4080-801f-6293aeeb02cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3140574497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.3140574497
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.473791909
Short name T278
Test name
Test status
Simulation time 1369528242 ps
CPU time 71.53 seconds
Started Apr 04 12:31:22 PM PDT 24
Finished Apr 04 12:32:34 PM PDT 24
Peak memory 199508 kb
Host smart-6bda321c-8e2b-48da-9f73-528b8fa64032
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473791909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.473791909
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3378939572
Short name T546
Test name
Test status
Simulation time 3235884696 ps
CPU time 66.81 seconds
Started Apr 04 12:32:12 PM PDT 24
Finished Apr 04 12:33:19 PM PDT 24
Peak memory 199608 kb
Host smart-3d843652-155a-4e15-8692-17afd40cf2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378939572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3378939572
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.3645540555
Short name T321
Test name
Test status
Simulation time 395460708 ps
CPU time 2.91 seconds
Started Apr 04 12:32:43 PM PDT 24
Finished Apr 04 12:32:46 PM PDT 24
Peak memory 199196 kb
Host smart-a5991039-6ee4-4816-9807-18b88e05c8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645540555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3645540555
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1972452370
Short name T481
Test name
Test status
Simulation time 53030468411 ps
CPU time 493.28 seconds
Started Apr 04 12:32:43 PM PDT 24
Finished Apr 04 12:40:57 PM PDT 24
Peak memory 215688 kb
Host smart-75786750-a3ac-42cb-83a1-8f603e63b7a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972452370 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1972452370
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.3301986558
Short name T505
Test name
Test status
Simulation time 30640093 ps
CPU time 1.36 seconds
Started Apr 04 12:31:30 PM PDT 24
Finished Apr 04 12:31:32 PM PDT 24
Peak memory 199524 kb
Host smart-fd2c1df9-0ecc-4d7c-b485-cb6fefa570c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301986558 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.3301986558
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.1621190936
Short name T190
Test name
Test status
Simulation time 32266867908 ps
CPU time 394.16 seconds
Started Apr 04 12:31:23 PM PDT 24
Finished Apr 04 12:37:57 PM PDT 24
Peak memory 199648 kb
Host smart-90677ee6-ad08-49a8-9cd3-02a841860ae7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621190936 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.1621190936
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2545136142
Short name T468
Test name
Test status
Simulation time 1180375507 ps
CPU time 56.79 seconds
Started Apr 04 12:32:03 PM PDT 24
Finished Apr 04 12:33:01 PM PDT 24
Peak memory 199484 kb
Host smart-683f319b-bca0-4693-954a-65dc6e0cea96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545136142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2545136142
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1629823241
Short name T443
Test name
Test status
Simulation time 50212511 ps
CPU time 0.56 seconds
Started Apr 04 12:31:27 PM PDT 24
Finished Apr 04 12:31:28 PM PDT 24
Peak memory 194900 kb
Host smart-e8e1d050-9513-4b07-aaf1-91ba365a7569
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629823241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1629823241
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2981364951
Short name T478
Test name
Test status
Simulation time 4175678833 ps
CPU time 35.24 seconds
Started Apr 04 12:31:23 PM PDT 24
Finished Apr 04 12:31:58 PM PDT 24
Peak memory 215872 kb
Host smart-3b2c2c56-ba0f-44ca-b88c-54cfb2a082a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2981364951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2981364951
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3556682722
Short name T135
Test name
Test status
Simulation time 3826822162 ps
CPU time 44.01 seconds
Started Apr 04 12:32:34 PM PDT 24
Finished Apr 04 12:33:19 PM PDT 24
Peak memory 198776 kb
Host smart-1e917691-b59c-4262-a431-9a8f234d64a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556682722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3556682722
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.469505637
Short name T394
Test name
Test status
Simulation time 712331333 ps
CPU time 38.63 seconds
Started Apr 04 12:31:53 PM PDT 24
Finished Apr 04 12:32:31 PM PDT 24
Peak memory 199456 kb
Host smart-d4c6d0ff-c4e8-46bd-b149-5d9eb2eb286e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=469505637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.469505637
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.586371538
Short name T12
Test name
Test status
Simulation time 4744884892 ps
CPU time 81.78 seconds
Started Apr 04 12:31:34 PM PDT 24
Finished Apr 04 12:32:56 PM PDT 24
Peak memory 199624 kb
Host smart-24970f82-d3e2-41a6-a7a7-a3d0f01ff0b6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586371538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.586371538
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.3288602072
Short name T145
Test name
Test status
Simulation time 1142611483 ps
CPU time 62.52 seconds
Started Apr 04 12:32:42 PM PDT 24
Finished Apr 04 12:33:46 PM PDT 24
Peak memory 199128 kb
Host smart-95f6f524-feeb-4671-8203-a664b9f8e356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288602072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3288602072
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.4076891646
Short name T411
Test name
Test status
Simulation time 376544535 ps
CPU time 2.88 seconds
Started Apr 04 12:33:13 PM PDT 24
Finished Apr 04 12:33:17 PM PDT 24
Peak memory 197784 kb
Host smart-201e8fb3-c31a-4baf-898d-28491ca057b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076891646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.4076891646
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.330793355
Short name T340
Test name
Test status
Simulation time 34391210035 ps
CPU time 615.78 seconds
Started Apr 04 12:33:14 PM PDT 24
Finished Apr 04 12:43:30 PM PDT 24
Peak memory 214472 kb
Host smart-9f889880-c495-420b-8f75-11d0f63b88d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330793355 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.330793355
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.282743987
Short name T605
Test name
Test status
Simulation time 118589224 ps
CPU time 1.27 seconds
Started Apr 04 12:31:27 PM PDT 24
Finished Apr 04 12:31:28 PM PDT 24
Peak memory 199408 kb
Host smart-1ae07ec6-66c4-4eac-9e20-1d1234116ba9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282743987 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.hmac_test_hmac_vectors.282743987
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.3517675919
Short name T72
Test name
Test status
Simulation time 39690925134 ps
CPU time 502.64 seconds
Started Apr 04 12:33:13 PM PDT 24
Finished Apr 04 12:41:37 PM PDT 24
Peak memory 197724 kb
Host smart-5feb0e99-bd33-45d3-bf96-77f165bae065
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517675919 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.3517675919
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2379838489
Short name T470
Test name
Test status
Simulation time 2603384347 ps
CPU time 43.73 seconds
Started Apr 04 12:31:24 PM PDT 24
Finished Apr 04 12:32:08 PM PDT 24
Peak memory 199672 kb
Host smart-5474a581-a866-4de2-9137-d900718e263e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379838489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2379838489
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.3630728727
Short name T397
Test name
Test status
Simulation time 24431178 ps
CPU time 0.57 seconds
Started Apr 04 12:33:14 PM PDT 24
Finished Apr 04 12:33:15 PM PDT 24
Peak memory 193796 kb
Host smart-a46bb078-ed07-4332-8e21-aa483cf30813
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630728727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3630728727
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.2039472790
Short name T482
Test name
Test status
Simulation time 1244620112 ps
CPU time 42.81 seconds
Started Apr 04 12:32:43 PM PDT 24
Finished Apr 04 12:33:26 PM PDT 24
Peak memory 224368 kb
Host smart-7a1d2794-c5ab-4f49-9cec-65a7d97d9343
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2039472790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.2039472790
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.806950240
Short name T176
Test name
Test status
Simulation time 3324864132 ps
CPU time 24.46 seconds
Started Apr 04 12:31:27 PM PDT 24
Finished Apr 04 12:31:52 PM PDT 24
Peak memory 199568 kb
Host smart-e599d130-7984-497f-b88a-a1e743a9951d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806950240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.806950240
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1469853355
Short name T593
Test name
Test status
Simulation time 789020094 ps
CPU time 22.16 seconds
Started Apr 04 12:33:13 PM PDT 24
Finished Apr 04 12:33:36 PM PDT 24
Peak memory 197468 kb
Host smart-604b6d0d-5953-4d35-8b0c-450f14d83f09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1469853355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1469853355
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1743714779
Short name T79
Test name
Test status
Simulation time 10632844628 ps
CPU time 185.02 seconds
Started Apr 04 12:31:24 PM PDT 24
Finished Apr 04 12:34:29 PM PDT 24
Peak memory 199600 kb
Host smart-b26d493d-bc35-48ca-9080-2be1fbfdca64
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743714779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1743714779
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.4153919490
Short name T299
Test name
Test status
Simulation time 4204811319 ps
CPU time 111.37 seconds
Started Apr 04 12:32:42 PM PDT 24
Finished Apr 04 12:34:35 PM PDT 24
Peak memory 199252 kb
Host smart-6371e51b-fa7b-4d90-b298-389cba62262d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153919490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.4153919490
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3168680973
Short name T572
Test name
Test status
Simulation time 655868616 ps
CPU time 4.97 seconds
Started Apr 04 12:33:14 PM PDT 24
Finished Apr 04 12:33:20 PM PDT 24
Peak memory 199148 kb
Host smart-f3a5a7a5-eb46-4a73-b870-385cd60bcf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168680973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3168680973
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.1980290133
Short name T440
Test name
Test status
Simulation time 33890208 ps
CPU time 0.72 seconds
Started Apr 04 12:32:10 PM PDT 24
Finished Apr 04 12:32:11 PM PDT 24
Peak memory 197184 kb
Host smart-fada19e1-b77d-4a0b-91c5-b829a6c7257b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980290133 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1980290133
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.621763632
Short name T373
Test name
Test status
Simulation time 475191349 ps
CPU time 1.24 seconds
Started Apr 04 12:32:10 PM PDT 24
Finished Apr 04 12:32:12 PM PDT 24
Peak memory 199112 kb
Host smart-edd2f378-d28a-4168-9aee-097e9aea594f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621763632 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_hmac_vectors.621763632
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.453485543
Short name T161
Test name
Test status
Simulation time 28776343594 ps
CPU time 513.05 seconds
Started Apr 04 12:32:00 PM PDT 24
Finished Apr 04 12:40:34 PM PDT 24
Peak memory 199636 kb
Host smart-b8e27506-10f8-4798-8003-1d2a2404ec7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453485543 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.453485543
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.4073810944
Short name T522
Test name
Test status
Simulation time 19124569009 ps
CPU time 78.57 seconds
Started Apr 04 12:31:28 PM PDT 24
Finished Apr 04 12:32:47 PM PDT 24
Peak memory 199588 kb
Host smart-2c4a4bd8-7a8f-4bcf-89cb-58ea27ad1583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073810944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.4073810944
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.1813523781
Short name T142
Test name
Test status
Simulation time 13976397 ps
CPU time 0.63 seconds
Started Apr 04 12:32:01 PM PDT 24
Finished Apr 04 12:32:02 PM PDT 24
Peak memory 194904 kb
Host smart-67ca1b89-67e2-4dc2-b8b8-bdd6e81cadf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813523781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.1813523781
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3435039111
Short name T594
Test name
Test status
Simulation time 578231531 ps
CPU time 4.78 seconds
Started Apr 04 12:32:42 PM PDT 24
Finished Apr 04 12:32:48 PM PDT 24
Peak memory 199208 kb
Host smart-57cc3a75-2241-44f9-aae8-0fb2515b4307
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3435039111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3435039111
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1420823443
Short name T120
Test name
Test status
Simulation time 543178915 ps
CPU time 11.3 seconds
Started Apr 04 12:33:26 PM PDT 24
Finished Apr 04 12:33:38 PM PDT 24
Peak memory 199360 kb
Host smart-ee0f3e98-5f6f-4a88-8821-b5954922a64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420823443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1420823443
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.1256347558
Short name T353
Test name
Test status
Simulation time 596208201 ps
CPU time 33.22 seconds
Started Apr 04 12:33:13 PM PDT 24
Finished Apr 04 12:33:47 PM PDT 24
Peak memory 197300 kb
Host smart-1d570983-1767-49d4-af4f-fb05b256d9aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1256347558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1256347558
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2084365863
Short name T313
Test name
Test status
Simulation time 35992924212 ps
CPU time 112.88 seconds
Started Apr 04 12:31:27 PM PDT 24
Finished Apr 04 12:33:25 PM PDT 24
Peak memory 199568 kb
Host smart-d1696a3d-5213-46e9-bf20-4621fcdd385c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084365863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2084365863
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1136308930
Short name T283
Test name
Test status
Simulation time 3180371620 ps
CPU time 47.9 seconds
Started Apr 04 12:31:27 PM PDT 24
Finished Apr 04 12:32:15 PM PDT 24
Peak memory 199552 kb
Host smart-8c51a645-0b12-4b67-9d9c-ce3a6cba1957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136308930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1136308930
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3330012255
Short name T460
Test name
Test status
Simulation time 603142339 ps
CPU time 6.68 seconds
Started Apr 04 12:32:42 PM PDT 24
Finished Apr 04 12:32:50 PM PDT 24
Peak memory 199196 kb
Host smart-142e9a40-3e64-4dcb-b98d-ba1041a0552d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330012255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3330012255
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1346188050
Short name T441
Test name
Test status
Simulation time 63149468355 ps
CPU time 803.97 seconds
Started Apr 04 12:32:42 PM PDT 24
Finished Apr 04 12:46:07 PM PDT 24
Peak memory 247228 kb
Host smart-a410f16a-000c-46ab-af2f-cf3b3d255146
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346188050 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1346188050
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.3242120484
Short name T427
Test name
Test status
Simulation time 148329480 ps
CPU time 1.14 seconds
Started Apr 04 12:31:23 PM PDT 24
Finished Apr 04 12:31:25 PM PDT 24
Peak memory 199136 kb
Host smart-69146bc9-c307-4483-ae1a-3cafa3440a56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242120484 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.3242120484
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.321028554
Short name T537
Test name
Test status
Simulation time 31007092009 ps
CPU time 426.81 seconds
Started Apr 04 12:31:25 PM PDT 24
Finished Apr 04 12:38:32 PM PDT 24
Peak memory 199540 kb
Host smart-ff172038-0b61-4d1b-86a5-bf2aacdc5f39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321028554 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.321028554
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.4191751665
Short name T371
Test name
Test status
Simulation time 8155583232 ps
CPU time 75.81 seconds
Started Apr 04 12:33:15 PM PDT 24
Finished Apr 04 12:34:31 PM PDT 24
Peak memory 199192 kb
Host smart-0d005ab7-3b65-4b14-b3e7-b6925c71a009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191751665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.4191751665
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3460544759
Short name T382
Test name
Test status
Simulation time 11540281 ps
CPU time 0.57 seconds
Started Apr 04 12:31:27 PM PDT 24
Finished Apr 04 12:31:28 PM PDT 24
Peak memory 193952 kb
Host smart-84e9d4dd-bf67-4829-8a9f-eb8388590a75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460544759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3460544759
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1224763970
Short name T531
Test name
Test status
Simulation time 1084128380 ps
CPU time 41.26 seconds
Started Apr 04 12:31:32 PM PDT 24
Finished Apr 04 12:32:18 PM PDT 24
Peak memory 229732 kb
Host smart-2f9eb320-c4bd-40ed-8a16-849ab136e2f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1224763970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1224763970
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2089754992
Short name T454
Test name
Test status
Simulation time 1486362565 ps
CPU time 22.92 seconds
Started Apr 04 12:31:38 PM PDT 24
Finished Apr 04 12:32:01 PM PDT 24
Peak memory 199524 kb
Host smart-7b7f6f19-1d2a-45a1-baa1-7a78b2d05b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089754992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2089754992
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2186559242
Short name T359
Test name
Test status
Simulation time 2099875927 ps
CPU time 61.39 seconds
Started Apr 04 12:32:50 PM PDT 24
Finished Apr 04 12:33:51 PM PDT 24
Peak memory 199500 kb
Host smart-d2948426-cb2e-4209-b110-d59a5d074cfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2186559242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2186559242
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2061364267
Short name T212
Test name
Test status
Simulation time 3901956040 ps
CPU time 48.06 seconds
Started Apr 04 12:34:13 PM PDT 24
Finished Apr 04 12:35:01 PM PDT 24
Peak memory 199508 kb
Host smart-f1591375-8a91-41b5-ac26-2702619d712a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061364267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2061364267
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3032304834
Short name T208
Test name
Test status
Simulation time 582472141 ps
CPU time 33.16 seconds
Started Apr 04 12:31:39 PM PDT 24
Finished Apr 04 12:32:12 PM PDT 24
Peak memory 199452 kb
Host smart-0232a42d-4da0-4d02-94c7-89ca6c4b1e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032304834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3032304834
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3474947277
Short name T282
Test name
Test status
Simulation time 311926384 ps
CPU time 3.69 seconds
Started Apr 04 12:32:51 PM PDT 24
Finished Apr 04 12:32:55 PM PDT 24
Peak memory 199460 kb
Host smart-218e3a97-a9d4-4575-b008-522078d08556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474947277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3474947277
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.2228261996
Short name T422
Test name
Test status
Simulation time 23425768458 ps
CPU time 1153.3 seconds
Started Apr 04 12:32:43 PM PDT 24
Finished Apr 04 12:51:57 PM PDT 24
Peak memory 230928 kb
Host smart-c7495045-76c2-49f9-b880-3e9708fac506
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228261996 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2228261996
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.2418323098
Short name T380
Test name
Test status
Simulation time 239200860 ps
CPU time 1.05 seconds
Started Apr 04 12:32:53 PM PDT 24
Finished Apr 04 12:32:54 PM PDT 24
Peak memory 198632 kb
Host smart-9f763c3b-a855-4bc5-b4df-bd6cb97cb650
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418323098 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.2418323098
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.2023456027
Short name T410
Test name
Test status
Simulation time 28236316529 ps
CPU time 400.11 seconds
Started Apr 04 12:31:54 PM PDT 24
Finished Apr 04 12:38:35 PM PDT 24
Peak memory 199608 kb
Host smart-1e6b03db-365d-4d04-9ddb-e6b96785e51b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023456027 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.2023456027
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.2611949304
Short name T346
Test name
Test status
Simulation time 2293121639 ps
CPU time 53.11 seconds
Started Apr 04 12:31:32 PM PDT 24
Finished Apr 04 12:32:26 PM PDT 24
Peak memory 199532 kb
Host smart-4c5bdb91-c766-4c41-af84-d2d6411dc8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611949304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2611949304
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1206840537
Short name T274
Test name
Test status
Simulation time 12938396 ps
CPU time 0.58 seconds
Started Apr 04 12:32:56 PM PDT 24
Finished Apr 04 12:32:57 PM PDT 24
Peak memory 194048 kb
Host smart-df6e1054-e7b4-4b2f-b693-8bc5e24ae35c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206840537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1206840537
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2511644970
Short name T396
Test name
Test status
Simulation time 82307079 ps
CPU time 4.12 seconds
Started Apr 04 12:31:31 PM PDT 24
Finished Apr 04 12:31:35 PM PDT 24
Peak memory 207672 kb
Host smart-c51503bc-0abd-482c-b5c2-2baca4267e1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2511644970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2511644970
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.660499769
Short name T437
Test name
Test status
Simulation time 12557393236 ps
CPU time 53.88 seconds
Started Apr 04 12:31:53 PM PDT 24
Finished Apr 04 12:32:47 PM PDT 24
Peak memory 199632 kb
Host smart-2a8e0cd5-1d3e-4779-bb6a-272951104c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660499769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.660499769
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2750061995
Short name T262
Test name
Test status
Simulation time 4538282377 ps
CPU time 59.07 seconds
Started Apr 04 12:34:13 PM PDT 24
Finished Apr 04 12:35:13 PM PDT 24
Peak memory 199560 kb
Host smart-ce6736d0-a4d6-42ff-b493-c62f3a9ddd97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2750061995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2750061995
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.3444359204
Short name T287
Test name
Test status
Simulation time 17063437022 ps
CPU time 162.44 seconds
Started Apr 04 12:32:09 PM PDT 24
Finished Apr 04 12:34:57 PM PDT 24
Peak memory 199648 kb
Host smart-03aa6793-b12a-4884-bdf6-8e3e96883fed
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444359204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3444359204
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2811271614
Short name T558
Test name
Test status
Simulation time 725903506 ps
CPU time 18.91 seconds
Started Apr 04 12:31:34 PM PDT 24
Finished Apr 04 12:31:53 PM PDT 24
Peak memory 199496 kb
Host smart-70d42ff1-a205-4572-ab9c-38184a366967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811271614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2811271614
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.16817424
Short name T606
Test name
Test status
Simulation time 58907839 ps
CPU time 1.84 seconds
Started Apr 04 12:31:53 PM PDT 24
Finished Apr 04 12:31:56 PM PDT 24
Peak memory 199460 kb
Host smart-b99e989f-db1c-4dca-a2e9-3542f6481ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16817424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.16817424
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.4148683416
Short name T179
Test name
Test status
Simulation time 39545626290 ps
CPU time 714.18 seconds
Started Apr 04 12:31:54 PM PDT 24
Finished Apr 04 12:43:48 PM PDT 24
Peak memory 199616 kb
Host smart-133523c0-84a9-4e98-946d-cd411c9049f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148683416 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.4148683416
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.2652439589
Short name T550
Test name
Test status
Simulation time 168865782 ps
CPU time 1.01 seconds
Started Apr 04 12:31:41 PM PDT 24
Finished Apr 04 12:31:42 PM PDT 24
Peak memory 197920 kb
Host smart-b3ccfff2-b127-4520-8a93-aff70e0d6b90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652439589 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.2652439589
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.3574283100
Short name T332
Test name
Test status
Simulation time 380381287499 ps
CPU time 469.32 seconds
Started Apr 04 12:31:33 PM PDT 24
Finished Apr 04 12:39:22 PM PDT 24
Peak memory 199612 kb
Host smart-e0218a13-3440-48bd-8ab3-d2ae24dbd3bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574283100 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.3574283100
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.4032203077
Short name T560
Test name
Test status
Simulation time 2357039205 ps
CPU time 11.36 seconds
Started Apr 04 12:31:34 PM PDT 24
Finished Apr 04 12:31:46 PM PDT 24
Peak memory 199628 kb
Host smart-df33c334-1859-4633-ba41-26bc975586fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032203077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.4032203077
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1279810372
Short name T551
Test name
Test status
Simulation time 14412899 ps
CPU time 0.59 seconds
Started Apr 04 12:32:00 PM PDT 24
Finished Apr 04 12:32:01 PM PDT 24
Peak memory 195068 kb
Host smart-fce5654d-678f-4579-a84f-83cc3a4a8c24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279810372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1279810372
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1086603397
Short name T35
Test name
Test status
Simulation time 2835518927 ps
CPU time 24.93 seconds
Started Apr 04 12:32:28 PM PDT 24
Finished Apr 04 12:32:53 PM PDT 24
Peak memory 215996 kb
Host smart-bda372d9-3118-46c6-95f5-54880c3a62de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1086603397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1086603397
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1867438194
Short name T356
Test name
Test status
Simulation time 1142802627 ps
CPU time 53.52 seconds
Started Apr 04 12:31:33 PM PDT 24
Finished Apr 04 12:32:27 PM PDT 24
Peak memory 199460 kb
Host smart-e7c442f1-d2fb-48b8-95be-d78a2ec32ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867438194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1867438194
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.761877453
Short name T263
Test name
Test status
Simulation time 4353263940 ps
CPU time 124.28 seconds
Started Apr 04 12:32:10 PM PDT 24
Finished Apr 04 12:34:15 PM PDT 24
Peak memory 199556 kb
Host smart-0047f36e-46b2-4b5f-9c7d-3eb4894d6a12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=761877453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.761877453
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.1744037340
Short name T576
Test name
Test status
Simulation time 30964641874 ps
CPU time 81.96 seconds
Started Apr 04 12:31:56 PM PDT 24
Finished Apr 04 12:33:18 PM PDT 24
Peak memory 199636 kb
Host smart-777f3964-eb8d-4780-ba26-b6d6ae0f15c1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744037340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1744037340
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2384783971
Short name T544
Test name
Test status
Simulation time 2627409229 ps
CPU time 81.66 seconds
Started Apr 04 12:31:33 PM PDT 24
Finished Apr 04 12:32:55 PM PDT 24
Peak memory 199720 kb
Host smart-c3822507-34f9-4054-bc7e-20af00ec342a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384783971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2384783971
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.1264378688
Short name T121
Test name
Test status
Simulation time 795296919 ps
CPU time 5.78 seconds
Started Apr 04 12:31:30 PM PDT 24
Finished Apr 04 12:31:36 PM PDT 24
Peak memory 199484 kb
Host smart-b333172f-23fb-4b96-b06c-a630acdc3aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264378688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1264378688
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.761571049
Short name T351
Test name
Test status
Simulation time 91900046776 ps
CPU time 1775.68 seconds
Started Apr 04 12:32:52 PM PDT 24
Finished Apr 04 01:02:28 PM PDT 24
Peak memory 235432 kb
Host smart-4bf8ff0b-d8f6-4a7d-93d3-468e40e7056a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761571049 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.761571049
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.3809084857
Short name T578
Test name
Test status
Simulation time 161620410 ps
CPU time 1.05 seconds
Started Apr 04 12:31:58 PM PDT 24
Finished Apr 04 12:32:00 PM PDT 24
Peak memory 198888 kb
Host smart-2f75e897-a9f6-4599-a02b-eb1fe9b31044
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809084857 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.3809084857
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.2217871680
Short name T203
Test name
Test status
Simulation time 111748234068 ps
CPU time 479.22 seconds
Started Apr 04 12:31:36 PM PDT 24
Finished Apr 04 12:39:35 PM PDT 24
Peak memory 199648 kb
Host smart-3fbb5dbe-539e-4979-87c6-cd15e0b6f173
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217871680 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.2217871680
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.2824221297
Short name T246
Test name
Test status
Simulation time 3355079379 ps
CPU time 47.03 seconds
Started Apr 04 12:32:50 PM PDT 24
Finished Apr 04 12:33:39 PM PDT 24
Peak memory 199620 kb
Host smart-796482fb-7740-4b52-a582-21acd09c9274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824221297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.2824221297
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1848374876
Short name T401
Test name
Test status
Simulation time 13880999 ps
CPU time 0.57 seconds
Started Apr 04 12:29:04 PM PDT 24
Finished Apr 04 12:29:05 PM PDT 24
Peak memory 194960 kb
Host smart-491a29c5-4f1b-4d69-bfee-d6a531d22223
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848374876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1848374876
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.4213156866
Short name T1
Test name
Test status
Simulation time 2168062844 ps
CPU time 22.64 seconds
Started Apr 04 12:29:45 PM PDT 24
Finished Apr 04 12:30:08 PM PDT 24
Peak memory 226892 kb
Host smart-65a497c9-dc96-4768-8a2c-9984c56882b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4213156866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.4213156866
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.4085452842
Short name T165
Test name
Test status
Simulation time 1631654070 ps
CPU time 15.13 seconds
Started Apr 04 12:29:46 PM PDT 24
Finished Apr 04 12:30:01 PM PDT 24
Peak memory 199400 kb
Host smart-d8fa2c41-ec39-46b3-a233-b825d045beff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085452842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.4085452842
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2402653403
Short name T541
Test name
Test status
Simulation time 16689786776 ps
CPU time 129.04 seconds
Started Apr 04 12:29:52 PM PDT 24
Finished Apr 04 12:32:02 PM PDT 24
Peak memory 199568 kb
Host smart-a5b2e98c-bcfa-49b7-9015-220b183a94cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2402653403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2402653403
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.3743231573
Short name T238
Test name
Test status
Simulation time 49072312 ps
CPU time 2.58 seconds
Started Apr 04 12:28:54 PM PDT 24
Finished Apr 04 12:28:57 PM PDT 24
Peak memory 199320 kb
Host smart-0ec37cf9-25cc-4ff6-ace1-ec5fb8653963
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743231573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3743231573
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.1073918667
Short name T157
Test name
Test status
Simulation time 2968750055 ps
CPU time 49.27 seconds
Started Apr 04 12:28:35 PM PDT 24
Finished Apr 04 12:29:24 PM PDT 24
Peak memory 199536 kb
Host smart-082f89a9-890c-4911-8fbf-e69984fc1e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073918667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1073918667
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.4178450649
Short name T182
Test name
Test status
Simulation time 431758638 ps
CPU time 6.83 seconds
Started Apr 04 12:28:13 PM PDT 24
Finished Apr 04 12:28:21 PM PDT 24
Peak memory 199496 kb
Host smart-bf96ac09-7122-4a03-b274-5641ea2100a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178450649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.4178450649
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.2233602965
Short name T348
Test name
Test status
Simulation time 5130818978 ps
CPU time 74.62 seconds
Started Apr 04 12:33:27 PM PDT 24
Finished Apr 04 12:34:42 PM PDT 24
Peak memory 199316 kb
Host smart-5afc0c4b-bc57-4d36-8f0d-fcf9c2158be7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233602965 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.2233602965
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.3645475266
Short name T58
Test name
Test status
Simulation time 467404902995 ps
CPU time 1544.03 seconds
Started Apr 04 12:28:55 PM PDT 24
Finished Apr 04 12:54:39 PM PDT 24
Peak memory 224244 kb
Host smart-6c8f8877-6fd4-4ce6-bb1c-8262f6fbc098
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3645475266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3645475266
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.3848736154
Short name T383
Test name
Test status
Simulation time 66527582 ps
CPU time 1.18 seconds
Started Apr 04 12:29:36 PM PDT 24
Finished Apr 04 12:29:37 PM PDT 24
Peak memory 198436 kb
Host smart-62fbb692-4e25-4ae0-938a-dadceb954f01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848736154 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.3848736154
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.1637028237
Short name T489
Test name
Test status
Simulation time 43256048715 ps
CPU time 537.87 seconds
Started Apr 04 12:28:52 PM PDT 24
Finished Apr 04 12:37:50 PM PDT 24
Peak memory 199420 kb
Host smart-52d019f1-bfd8-4055-9705-78b8ec593440
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637028237 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.1637028237
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.305819836
Short name T420
Test name
Test status
Simulation time 3248945618 ps
CPU time 41.49 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:29:35 PM PDT 24
Peak memory 198616 kb
Host smart-b213bab3-833b-41b5-9be2-387fc8cfc16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305819836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.305819836
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.3043675707
Short name T590
Test name
Test status
Simulation time 34580793 ps
CPU time 0.58 seconds
Started Apr 04 12:31:01 PM PDT 24
Finished Apr 04 12:31:02 PM PDT 24
Peak memory 195052 kb
Host smart-cf8c252d-56fe-44a7-b7df-61f95ef99737
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043675707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.3043675707
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3782948711
Short name T40
Test name
Test status
Simulation time 1780778573 ps
CPU time 16.48 seconds
Started Apr 04 12:30:30 PM PDT 24
Finished Apr 04 12:30:47 PM PDT 24
Peak memory 224144 kb
Host smart-de34adb1-6ea3-495f-acfa-3915f3aec48c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3782948711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3782948711
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.2316864254
Short name T20
Test name
Test status
Simulation time 628688490 ps
CPU time 29.46 seconds
Started Apr 04 12:30:35 PM PDT 24
Finished Apr 04 12:31:04 PM PDT 24
Peak memory 199460 kb
Host smart-7cea2489-3039-47a5-b56c-8ee08be522bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316864254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2316864254
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2660917836
Short name T222
Test name
Test status
Simulation time 258836379 ps
CPU time 15.29 seconds
Started Apr 04 12:31:10 PM PDT 24
Finished Apr 04 12:31:26 PM PDT 24
Peak memory 199340 kb
Host smart-1fbded43-04cd-4d35-ae33-dfcbaca0cc34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2660917836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2660917836
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3206322586
Short name T77
Test name
Test status
Simulation time 19453865361 ps
CPU time 159.72 seconds
Started Apr 04 12:30:18 PM PDT 24
Finished Apr 04 12:32:58 PM PDT 24
Peak memory 199900 kb
Host smart-3585374e-e2d8-4836-bc7e-cb9b4f2011a8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206322586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3206322586
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1822785041
Short name T111
Test name
Test status
Simulation time 26125525 ps
CPU time 1.32 seconds
Started Apr 04 12:28:54 PM PDT 24
Finished Apr 04 12:28:55 PM PDT 24
Peak memory 199376 kb
Host smart-8fe39eac-8c64-4281-80ae-dc610a77184e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822785041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1822785041
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3084765647
Short name T180
Test name
Test status
Simulation time 191519264 ps
CPU time 0.79 seconds
Started Apr 04 12:28:54 PM PDT 24
Finished Apr 04 12:28:55 PM PDT 24
Peak memory 197224 kb
Host smart-08ba900f-773f-4829-8a2d-9c4ebfa6118a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084765647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3084765647
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.73437902
Short name T456
Test name
Test status
Simulation time 17845896469 ps
CPU time 336.22 seconds
Started Apr 04 12:30:55 PM PDT 24
Finished Apr 04 12:36:32 PM PDT 24
Peak memory 231784 kb
Host smart-3807a8df-cf04-4359-89ca-d9e7a4c2c247
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73437902 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.73437902
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.4100018556
Short name T436
Test name
Test status
Simulation time 42617815 ps
CPU time 0.98 seconds
Started Apr 04 12:30:29 PM PDT 24
Finished Apr 04 12:30:30 PM PDT 24
Peak memory 198732 kb
Host smart-268024eb-a873-40de-a088-0b4c7d19167b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100018556 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.4100018556
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.798488040
Short name T146
Test name
Test status
Simulation time 106137571004 ps
CPU time 438.77 seconds
Started Apr 04 12:30:54 PM PDT 24
Finished Apr 04 12:38:13 PM PDT 24
Peak memory 199516 kb
Host smart-7a958e3a-6973-4e25-aca3-9a309a7d1b96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798488040 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.798488040
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1184842965
Short name T144
Test name
Test status
Simulation time 6257048569 ps
CPU time 40.65 seconds
Started Apr 04 12:30:29 PM PDT 24
Finished Apr 04 12:31:10 PM PDT 24
Peak memory 199612 kb
Host smart-3b14daa4-ef8e-4f71-aaf8-3e1e4db6d488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184842965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1184842965
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/63.hmac_stress_all_with_rand_reset.1591032155
Short name T483
Test name
Test status
Simulation time 15480938945 ps
CPU time 722.39 seconds
Started Apr 04 12:31:51 PM PDT 24
Finished Apr 04 12:43:54 PM PDT 24
Peak memory 240676 kb
Host smart-cb95201c-2fef-4dfc-acaf-149b99f66555
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1591032155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.hmac_stress_all_with_rand_reset.1591032155
Directory /workspace/63.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.1344693706
Short name T253
Test name
Test status
Simulation time 36853815 ps
CPU time 0.57 seconds
Started Apr 04 12:30:37 PM PDT 24
Finished Apr 04 12:30:38 PM PDT 24
Peak memory 194784 kb
Host smart-b20662c9-546e-4842-9e52-bf45578d50fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344693706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1344693706
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1868872623
Short name T601
Test name
Test status
Simulation time 3466250137 ps
CPU time 69.39 seconds
Started Apr 04 12:31:18 PM PDT 24
Finished Apr 04 12:32:27 PM PDT 24
Peak memory 224204 kb
Host smart-e6bf275d-cd21-497d-9d3d-9f963e219463
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1868872623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1868872623
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2863245142
Short name T61
Test name
Test status
Simulation time 21821997971 ps
CPU time 39.35 seconds
Started Apr 04 12:31:44 PM PDT 24
Finished Apr 04 12:32:23 PM PDT 24
Peak memory 199556 kb
Host smart-2be11be3-a6a2-4204-a749-21fb663e59e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863245142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2863245142
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.348803487
Short name T349
Test name
Test status
Simulation time 1527236029 ps
CPU time 22.02 seconds
Started Apr 04 12:30:56 PM PDT 24
Finished Apr 04 12:31:19 PM PDT 24
Peak memory 199460 kb
Host smart-55e3fdb7-3ccc-4179-926e-a4e5fc402f05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=348803487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.348803487
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.96958207
Short name T532
Test name
Test status
Simulation time 2490242543 ps
CPU time 35.06 seconds
Started Apr 04 12:30:56 PM PDT 24
Finished Apr 04 12:31:31 PM PDT 24
Peak memory 199608 kb
Host smart-49b7af78-ebd9-4fb7-8c18-08dd3c81e144
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96958207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.96958207
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3519097803
Short name T195
Test name
Test status
Simulation time 10900522310 ps
CPU time 50.31 seconds
Started Apr 04 12:30:35 PM PDT 24
Finished Apr 04 12:31:25 PM PDT 24
Peak memory 199540 kb
Host smart-a29c9190-f810-4dd1-9b88-9473dc4014d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519097803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3519097803
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.3476948843
Short name T543
Test name
Test status
Simulation time 481449625 ps
CPU time 5.06 seconds
Started Apr 04 12:31:12 PM PDT 24
Finished Apr 04 12:31:17 PM PDT 24
Peak memory 199496 kb
Host smart-c7a109e2-d63c-4b24-980b-fe0104f8d340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476948843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3476948843
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.3016810519
Short name T300
Test name
Test status
Simulation time 33409402882 ps
CPU time 492.26 seconds
Started Apr 04 12:30:24 PM PDT 24
Finished Apr 04 12:38:36 PM PDT 24
Peak memory 199664 kb
Host smart-a616b3eb-bcaa-4476-80ee-1dc22263613d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016810519 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.3016810519
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.4059497322
Short name T310
Test name
Test status
Simulation time 422805081 ps
CPU time 1.34 seconds
Started Apr 04 12:31:39 PM PDT 24
Finished Apr 04 12:31:41 PM PDT 24
Peak memory 199492 kb
Host smart-a9ad7791-e2d4-4f6d-a332-4e033e236a11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059497322 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.4059497322
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.1522325974
Short name T173
Test name
Test status
Simulation time 103593479287 ps
CPU time 477.87 seconds
Started Apr 04 12:30:56 PM PDT 24
Finished Apr 04 12:38:54 PM PDT 24
Peak memory 199600 kb
Host smart-393b4159-bdad-4d0c-ab08-cdff2d36b2b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522325974 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.1522325974
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.3366692554
Short name T308
Test name
Test status
Simulation time 17792274162 ps
CPU time 95.62 seconds
Started Apr 04 12:31:44 PM PDT 24
Finished Apr 04 12:33:20 PM PDT 24
Peak memory 199536 kb
Host smart-ab1725bd-6155-4652-94c3-0d54e12206be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366692554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3366692554
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/73.hmac_stress_all_with_rand_reset.1709818638
Short name T602
Test name
Test status
Simulation time 10009142635 ps
CPU time 513.27 seconds
Started Apr 04 12:32:51 PM PDT 24
Finished Apr 04 12:41:25 PM PDT 24
Peak memory 242776 kb
Host smart-f3adecaa-ce72-4702-ac32-a1db690256c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1709818638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.hmac_stress_all_with_rand_reset.1709818638
Directory /workspace/73.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.hmac_stress_all_with_rand_reset.873979314
Short name T516
Test name
Test status
Simulation time 16594193174 ps
CPU time 329.73 seconds
Started Apr 04 12:32:51 PM PDT 24
Finished Apr 04 12:38:21 PM PDT 24
Peak memory 231836 kb
Host smart-6b7529a4-3854-4ff7-b7ee-9106b68f0433
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=873979314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.hmac_stress_all_with_rand_reset.873979314
Directory /workspace/74.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.hmac_stress_all_with_rand_reset.465309315
Short name T11
Test name
Test status
Simulation time 14711284665 ps
CPU time 151.51 seconds
Started Apr 04 12:32:24 PM PDT 24
Finished Apr 04 12:34:55 PM PDT 24
Peak memory 215856 kb
Host smart-dbe3e89c-f808-4b20-a4be-02ad630633fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=465309315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.hmac_stress_all_with_rand_reset.465309315
Directory /workspace/78.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3358916169
Short name T269
Test name
Test status
Simulation time 13123861 ps
CPU time 0.57 seconds
Started Apr 04 12:30:33 PM PDT 24
Finished Apr 04 12:30:34 PM PDT 24
Peak memory 193984 kb
Host smart-287b4f18-34d5-4974-99e4-80dd8f336f61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358916169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3358916169
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.37828660
Short name T48
Test name
Test status
Simulation time 584001195 ps
CPU time 3.72 seconds
Started Apr 04 12:30:32 PM PDT 24
Finished Apr 04 12:30:35 PM PDT 24
Peak memory 215792 kb
Host smart-922cece1-fced-4204-9d1d-13dcfd70a2b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37828660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.37828660
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.185308686
Short name T347
Test name
Test status
Simulation time 2742154918 ps
CPU time 41.42 seconds
Started Apr 04 12:30:30 PM PDT 24
Finished Apr 04 12:31:12 PM PDT 24
Peak memory 199576 kb
Host smart-83d284f7-fd81-4592-82cc-baa099d2b407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185308686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.185308686
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.1485917457
Short name T424
Test name
Test status
Simulation time 1762177009 ps
CPU time 103.92 seconds
Started Apr 04 12:30:31 PM PDT 24
Finished Apr 04 12:32:15 PM PDT 24
Peak memory 199468 kb
Host smart-c4ec6b4d-1e08-4e3b-bcaa-cb87871e670a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1485917457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1485917457
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.4065401431
Short name T344
Test name
Test status
Simulation time 18016705662 ps
CPU time 121.74 seconds
Started Apr 04 12:30:43 PM PDT 24
Finished Apr 04 12:32:45 PM PDT 24
Peak memory 199644 kb
Host smart-3a4c579b-b062-4bbf-be2d-d6bcd35eeec9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065401431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.4065401431
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.907826549
Short name T112
Test name
Test status
Simulation time 71623252 ps
CPU time 3.43 seconds
Started Apr 04 12:30:41 PM PDT 24
Finished Apr 04 12:30:44 PM PDT 24
Peak memory 199276 kb
Host smart-24ef3161-0785-4b05-95e1-64404095c252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907826549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.907826549
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.2338713643
Short name T464
Test name
Test status
Simulation time 146263606 ps
CPU time 4.34 seconds
Started Apr 04 12:30:36 PM PDT 24
Finished Apr 04 12:30:40 PM PDT 24
Peak memory 199440 kb
Host smart-e00999ae-ec4d-44c9-a6e5-8140ee8d83ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338713643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.2338713643
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.155211442
Short name T13
Test name
Test status
Simulation time 669823521192 ps
CPU time 1609.68 seconds
Started Apr 04 12:30:36 PM PDT 24
Finished Apr 04 12:57:26 PM PDT 24
Peak memory 232360 kb
Host smart-8103d3a5-69c5-4653-a29d-da337bf4cfdd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155211442 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.155211442
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.3804724278
Short name T247
Test name
Test status
Simulation time 49103890 ps
CPU time 1.03 seconds
Started Apr 04 12:30:37 PM PDT 24
Finished Apr 04 12:30:38 PM PDT 24
Peak memory 198908 kb
Host smart-34faf283-2704-4aba-8a6c-a88b4b53c56d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804724278 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.3804724278
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.80746149
Short name T123
Test name
Test status
Simulation time 8245925459 ps
CPU time 476.74 seconds
Started Apr 04 12:30:25 PM PDT 24
Finished Apr 04 12:38:22 PM PDT 24
Peak memory 199600 kb
Host smart-f0ad9c8c-5ed3-4836-8a0e-3e40b9e19a23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80746149 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.80746149
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2383959296
Short name T259
Test name
Test status
Simulation time 2339385135 ps
CPU time 76.73 seconds
Started Apr 04 12:30:42 PM PDT 24
Finished Apr 04 12:31:59 PM PDT 24
Peak memory 199628 kb
Host smart-c0286003-f6d4-4a4a-9eaa-3f58b91443d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383959296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2383959296
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2375145477
Short name T113
Test name
Test status
Simulation time 13338921 ps
CPU time 0.59 seconds
Started Apr 04 12:31:02 PM PDT 24
Finished Apr 04 12:31:03 PM PDT 24
Peak memory 194060 kb
Host smart-4bbdfa8b-07a9-4049-88ca-7625b25e4e51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375145477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2375145477
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.986398454
Short name T475
Test name
Test status
Simulation time 1869374342 ps
CPU time 34.89 seconds
Started Apr 04 12:30:32 PM PDT 24
Finished Apr 04 12:31:07 PM PDT 24
Peak memory 223788 kb
Host smart-4ff11e78-b246-411c-a410-8c2152a92949
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=986398454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.986398454
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.884089882
Short name T431
Test name
Test status
Simulation time 306471552 ps
CPU time 14.73 seconds
Started Apr 04 12:30:39 PM PDT 24
Finished Apr 04 12:30:54 PM PDT 24
Peak memory 199508 kb
Host smart-3a6f07ed-a708-4f2e-baa4-f243f87a8681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884089882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.884089882
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.2187634112
Short name T37
Test name
Test status
Simulation time 3286087906 ps
CPU time 194.12 seconds
Started Apr 04 12:30:55 PM PDT 24
Finished Apr 04 12:34:09 PM PDT 24
Peak memory 199616 kb
Host smart-eb1e113f-0554-46d0-94de-c08aa1012144
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2187634112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2187634112
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.929670303
Short name T430
Test name
Test status
Simulation time 3182910613 ps
CPU time 119.21 seconds
Started Apr 04 12:30:34 PM PDT 24
Finished Apr 04 12:32:34 PM PDT 24
Peak memory 199588 kb
Host smart-1764966e-eedb-4d43-b5a0-b44d602230ea
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929670303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.929670303
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.1546594725
Short name T331
Test name
Test status
Simulation time 27630650404 ps
CPU time 121.91 seconds
Started Apr 04 12:30:35 PM PDT 24
Finished Apr 04 12:32:37 PM PDT 24
Peak memory 199648 kb
Host smart-25670897-d4f2-4631-b15a-bc1aa8fbf657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546594725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1546594725
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.797513274
Short name T354
Test name
Test status
Simulation time 441348006 ps
CPU time 6.42 seconds
Started Apr 04 12:30:31 PM PDT 24
Finished Apr 04 12:30:37 PM PDT 24
Peak memory 199460 kb
Host smart-c251678f-0a3f-497d-8f1c-e95dd097326a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797513274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.797513274
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.909370986
Short name T573
Test name
Test status
Simulation time 100620540123 ps
CPU time 652.32 seconds
Started Apr 04 12:30:54 PM PDT 24
Finished Apr 04 12:41:46 PM PDT 24
Peak memory 199488 kb
Host smart-a1124cc0-37f9-4f27-a211-ba01997b56c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909370986 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.909370986
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.200854661
Short name T512
Test name
Test status
Simulation time 140231969 ps
CPU time 0.97 seconds
Started Apr 04 12:31:41 PM PDT 24
Finished Apr 04 12:31:42 PM PDT 24
Peak memory 197816 kb
Host smart-b762258b-b917-4391-8701-35b900fd3f2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200854661 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.hmac_test_hmac_vectors.200854661
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.709172232
Short name T221
Test name
Test status
Simulation time 7753667138 ps
CPU time 410.46 seconds
Started Apr 04 12:30:33 PM PDT 24
Finished Apr 04 12:37:24 PM PDT 24
Peak memory 199636 kb
Host smart-28648b78-990f-4db2-9c5f-52ffaddb29e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709172232 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.709172232
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.2468557197
Short name T414
Test name
Test status
Simulation time 6330764081 ps
CPU time 45.04 seconds
Started Apr 04 12:30:35 PM PDT 24
Finished Apr 04 12:31:20 PM PDT 24
Peak memory 199540 kb
Host smart-66500e6d-af6d-4995-87ce-d7ba90859abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468557197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2468557197
Directory /workspace/9.hmac_wipe_secret/latest

Test location /workspace/coverage/default/94.hmac_stress_all_with_rand_reset.1191947107
Short name T370
Test name
Test status
Simulation time 33032286603 ps
CPU time 891.1 seconds
Started Apr 04 12:32:40 PM PDT 24
Finished Apr 04 12:47:32 PM PDT 24
Peak memory 248816 kb
Host smart-29249e47-6abe-4456-b4d6-7c5c7097558e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1191947107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.hmac_stress_all_with_rand_reset.1191947107
Directory /workspace/94.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.hmac_stress_all_with_rand_reset.3514894407
Short name T324
Test name
Test status
Simulation time 30985980551 ps
CPU time 663.72 seconds
Started Apr 04 12:32:31 PM PDT 24
Finished Apr 04 12:43:35 PM PDT 24
Peak memory 218936 kb
Host smart-060d23b1-4cd3-4519-9ec6-8532b2dac240
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3514894407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.hmac_stress_all_with_rand_reset.3514894407
Directory /workspace/95.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.hmac_stress_all_with_rand_reset.1008400006
Short name T536
Test name
Test status
Simulation time 45070113519 ps
CPU time 2270.92 seconds
Started Apr 04 12:32:51 PM PDT 24
Finished Apr 04 01:10:43 PM PDT 24
Peak memory 245776 kb
Host smart-c91a7c36-e028-47a1-9137-db78140815f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1008400006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.hmac_stress_all_with_rand_reset.1008400006
Directory /workspace/99.hmac_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%