Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14881760	1			T1	3146		T3	7716		T4	123413
all_values[1]	14881760	1			T1	3146		T3	7716		T4	123413
all_values[2]	14881760	1			T1	3146		T3	7716		T4	123413

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

88512

1

T1

2

T3

623

T4

214

auto[1]

44556768

1

T1

9436

T3

22525

T4

370025

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42351450

1

T1

9421

T3

15749

T4

338529

auto[1]

2293830

1

T1

17

T3

7399

T4

31710

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	36376	1			T5	10		T7	206		T56	80
all_values[0]	auto[0]	auto[1]	471	1			T5	2		T7	4		T56	2
all_values[0]	auto[1]	auto[0]	14795451	1			T1	3129		T3	7715		T4	123113
all_values[0]	auto[1]	auto[1]	49462	1			T1	17		T3	1		T4	300
all_values[1]	auto[0]	auto[0]	31793	1			T1	2		T3	623		T5	5
all_values[1]	auto[0]	auto[1]	193	1			T5	1		T15	4		T12	3
all_values[1]	auto[1]	auto[0]	14849284	1			T1	3144		T3	7093		T4	123413
all_values[1]	auto[1]	auto[1]	490	1			T5	7		T15	2		T12	5
all_values[2]	auto[0]	auto[0]	16290	1			T4	2		T5	5		T24	4
all_values[2]	auto[0]	auto[1]	3389	1			T4	212		T5	4		T15	4
all_values[2]	auto[1]	auto[0]	12622256	1			T1	3146		T3	318		T4	92001
all_values[2]	auto[1]	auto[1]	2239825	1			T3	7398		T4	31198		T5	44099