Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7101153

1

T1

1656

T3

307

T4

47329

auto[1]

2478853

1

T1

1463

T3

7

T4

14093

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2522355

1

T1

896

T3

269

T4

11119

auto[1]

7057651

1

T1

2223

T3

45

T4

50303

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6430637

1

T1

1384

T3

48

T4

51067

auto[1]

3149369

1

T1

1735

T3

266

T4

10355

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6442586	1			T1	2816		T3	314		T4	56923
fifo_depth[1]	472288	1			T1	162		T4	2416		T5	9291
fifo_depth[2]	383057	1			T1	83		T4	1216		T5	9099
fifo_depth[3]	308761	1			T1	34		T4	574		T5	7783
fifo_depth[4]	265701	1			T1	20		T4	219		T5	6521
fifo_depth[5]	234166	1			T1	2		T4	58		T5	5720
fifo_depth[6]	221290	1			T1	1		T4	11		T5	5242
fifo_depth[7]	194266	1			T1	1		T4	4		T5	4614
fifo_depth[8]	170289	1			T5	3651		T7	2848		T24	2
fifo_depth[9]	119460	1			T4	1		T5	2643		T7	2064
fifo_depth[10]	88742	1			T5	2093		T7	1409		T24	2
fifo_depth[11]	53610	1			T5	1206		T7	838		T25	30
fifo_depth[12]	45212	1			T5	971		T7	389		T25	19
fifo_depth[13]	24262	1			T5	579		T7	159		T25	7
fifo_depth[14]	27276	1			T5	694		T7	73		T25	2
fifo_depth[15]	18162	1			T5	464		T7	22		T56	8
fifo_depth[16]	68594	1			T5	2730		T7	13		T56	2

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3234346

1

T1

303

T4

4499

T5

78347

auto[1]

6345660

1

T1

2816

T3

314

T4

56923

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9483080

1

T1

3119

T3

314

T4

61422

auto[1]

96926

1

T5

3726

T7

388

T17

3

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

221312

1

T1

13

T4

217

T5

5165

auto[0]

auto[0]

auto[0]

auto[1]

209408

1

T1

54

T4

285

T5

7409

auto[0]

auto[0]

auto[1]

auto[0]

1039056

1

T1

43

T4

2586

T5

26895

auto[0]

auto[0]

auto[1]

auto[1]

196455

1

T1

31

T4

474

T5

1948

auto[0]

auto[1]

auto[0]

auto[0]

410005

1

T1

26

T4

258

T5

11683

auto[0]

auto[1]

auto[0]

auto[1]

401055

1

T1

2

T4

361

T5

9655

auto[0]

auto[1]

auto[1]

auto[0]

368723

1

T1

73

T4

217

T5

6380

auto[0]

auto[1]

auto[1]

auto[1]

388332

1

T1

61

T4

101

T5

9212

auto[1]

auto[0]

auto[0]

auto[0]

235364

1

T1

79

T3

3

T4

2527

auto[1]

auto[0]

auto[0]

auto[1]

239944

1

T1

478

T4

2296

T5

3846

auto[1]

auto[0]

auto[1]

auto[0]

4040361

1

T1

435

T3

39

T4

37341

auto[1]

auto[0]

auto[1]

auto[1]

248737

1

T1

251

T3

6

T4

5341

auto[1]

auto[1]

auto[0]

auto[0]

402568

1

T1

241

T3

265

T4

2542

auto[1]

auto[1]

auto[0]

auto[1]

402699

1

T1

3

T3

1

T4

2633

auto[1]

auto[1]

auto[1]

auto[0]

383764

1

T1

746

T4

1641

T5

2668

auto[1]

auto[1]

auto[1]

auto[1]

392223

1

T1

583

T4

2602

T5

3010

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

446115

1

T1

92

T3

3

T4

2744

auto[0]

auto[0]

auto[0]

auto[1]

439952

1

T1

532

T4

2581

T5

11161

auto[0]

auto[0]

auto[1]

auto[0]

5070598

1

T1

478

T3

39

T4

39927

auto[0]

auto[0]

auto[1]

auto[1]

435956

1

T1

282

T3

6

T4

5815

auto[0]

auto[1]

auto[0]

auto[0]

799628

1

T1

267

T3

265

T4

2800

auto[0]

auto[1]

auto[0]

auto[1]

787568

1

T1

5

T3

1

T4

2994

auto[0]

auto[1]

auto[1]

auto[0]

734809

1

T1

819

T4

1858

T5

8993

auto[0]

auto[1]

auto[1]

auto[1]

768454

1

T1

644

T4

2703

T5

10115

auto[1]

auto[0]

auto[0]

auto[0]

10561

1

T5

272

T7

78

T18

1

auto[1]

auto[0]

auto[0]

auto[1]

9400

1

T5

94

T7

39

T21

96

auto[1]

auto[0]

auto[1]

auto[0]

8819

1

T5

247

T7

2

T51

1

auto[1]

auto[0]

auto[1]

auto[1]

9236

1

T5

108

T21

253

T14

216

auto[1]

auto[1]

auto[0]

auto[0]

12945

1

T5

114

T7

129

T18

2

auto[1]

auto[1]

auto[0]

auto[1]

16186

1

T5

729

T7

138

T18

1

auto[1]

auto[1]

auto[1]

auto[0]

17678

1

T5

55

T17

2

T51

2

auto[1]

auto[1]

auto[1]

auto[1]

12101

1

T5

2107

T7

2

T17

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	245925	1			T1	79		T3	3		T4	2527
fifo_depth[0]	auto[0]	auto[0]	auto[1]	249344	1			T1	478		T4	2296		T5	3940
fifo_depth[0]	auto[0]	auto[1]	auto[0]	4049180	1			T1	435		T3	39		T4	37341
fifo_depth[0]	auto[0]	auto[1]	auto[1]	257973	1			T1	251		T3	6		T4	5341
fifo_depth[0]	auto[1]	auto[0]	auto[0]	415513	1			T1	241		T3	265		T4	2542
fifo_depth[0]	auto[1]	auto[0]	auto[1]	418885	1			T1	3		T3	1		T4	2633
fifo_depth[0]	auto[1]	auto[1]	auto[0]	401442	1			T1	746		T4	1641		T5	2723
fifo_depth[0]	auto[1]	auto[1]	auto[1]	404324	1			T1	583		T4	2602		T5	5117
fifo_depth[1]	auto[0]	auto[0]	auto[0]	19664	1			T1	5		T4	96		T5	211
fifo_depth[1]	auto[0]	auto[0]	auto[1]	20190	1			T1	32		T4	124		T5	559
fifo_depth[1]	auto[0]	auto[1]	auto[0]	239995	1			T1	26		T4	1544		T5	5713
fifo_depth[1]	auto[0]	auto[1]	auto[1]	19138	1			T1	12		T4	220		T5	99
fifo_depth[1]	auto[1]	auto[0]	auto[0]	44744	1			T1	14		T4	117		T5	927
fifo_depth[1]	auto[1]	auto[0]	auto[1]	43502	1			T1	1		T4	167		T5	701
fifo_depth[1]	auto[1]	auto[1]	auto[0]	41475	1			T1	39		T4	105		T5	503
fifo_depth[1]	auto[1]	auto[1]	auto[1]	43580	1			T1	33		T4	43		T5	578
fifo_depth[2]	auto[0]	auto[0]	auto[0]	16419	1			T1	5		T4	76		T5	205
fifo_depth[2]	auto[0]	auto[0]	auto[1]	17241	1			T1	12		T4	88		T5	536
fifo_depth[2]	auto[0]	auto[1]	auto[0]	178135	1			T1	10		T4	632		T5	5539
fifo_depth[2]	auto[0]	auto[1]	auto[1]	16050	1			T1	9		T4	132		T5	100
fifo_depth[2]	auto[1]	auto[0]	auto[0]	40365	1			T1	8		T4	78		T5	930
fifo_depth[2]	auto[1]	auto[0]	auto[1]	38623	1			T1	1		T4	115		T5	711
fifo_depth[2]	auto[1]	auto[1]	auto[0]	37375	1			T1	25		T4	63		T5	528
fifo_depth[2]	auto[1]	auto[1]	auto[1]	38849	1			T1	13		T4	32		T5	550
fifo_depth[3]	auto[0]	auto[0]	auto[0]	13375	1			T1	1		T4	21		T5	181
fifo_depth[3]	auto[0]	auto[0]	auto[1]	13798	1			T1	5		T4	44		T5	495
fifo_depth[3]	auto[0]	auto[1]	auto[0]	132627	1			T1	5		T4	287		T5	4329
fifo_depth[3]	auto[0]	auto[1]	auto[1]	12354	1			T1	7		T4	85		T5	99
fifo_depth[3]	auto[1]	auto[0]	auto[0]	35649	1			T1	2		T4	35		T5	930
fifo_depth[3]	auto[1]	auto[0]	auto[1]	34102	1			T4	58		T5	719		T7	521
fifo_depth[3]	auto[1]	auto[1]	auto[0]	32532	1			T1	3		T4	28		T5	486
fifo_depth[3]	auto[1]	auto[1]	auto[1]	34324	1			T1	11		T4	16		T5	544
fifo_depth[4]	auto[0]	auto[0]	auto[0]	13185	1			T1	2		T4	13		T5	164
fifo_depth[4]	auto[0]	auto[0]	auto[1]	13779	1			T1	4		T4	22		T5	537
fifo_depth[4]	auto[0]	auto[1]	auto[0]	96047	1			T1	2		T4	99		T5	2950
fifo_depth[4]	auto[0]	auto[1]	auto[1]	11601	1			T1	3		T4	26		T5	128
fifo_depth[4]	auto[1]	auto[0]	auto[0]	34367	1			T1	1		T4	20		T5	973
fifo_depth[4]	auto[1]	auto[0]	auto[1]	32416	1			T4	15		T5	751		T7	515
fifo_depth[4]	auto[1]	auto[1]	auto[0]	31459	1			T1	5		T4	18		T5	465
fifo_depth[4]	auto[1]	auto[1]	auto[1]	32847	1			T1	3		T4	6		T5	553
fifo_depth[5]	auto[0]	auto[0]	auto[0]	11490	1			T4	10		T5	130		T7	198
fifo_depth[5]	auto[0]	auto[0]	auto[1]	11874	1			T4	7		T5	486		T7	154
fifo_depth[5]	auto[0]	auto[1]	auto[0]	78346	1			T4	17		T5	2335		T7	1008
fifo_depth[5]	auto[0]	auto[1]	auto[1]	9580	1			T4	8		T5	89		T7	200
fifo_depth[5]	auto[1]	auto[0]	auto[0]	32358	1			T4	7		T5	930		T7	481
fifo_depth[5]	auto[1]	auto[0]	auto[1]	29961	1			T4	4		T5	711		T7	492
fifo_depth[5]	auto[1]	auto[1]	auto[0]	29505	1			T1	1		T4	3		T5	472
fifo_depth[5]	auto[1]	auto[1]	auto[1]	31052	1			T1	1		T4	2		T5	567
fifo_depth[6]	auto[0]	auto[0]	auto[0]	11487	1			T4	1		T5	130		T7	190
fifo_depth[6]	auto[0]	auto[0]	auto[1]	11641	1			T1	1		T5	490		T7	150
fifo_depth[6]	auto[0]	auto[1]	auto[0]	68296	1			T4	5		T5	1875		T7	822
fifo_depth[6]	auto[0]	auto[1]	auto[1]	9805	1			T4	1		T5	101		T7	182
fifo_depth[6]	auto[1]	auto[0]	auto[0]	31615	1			T5	960		T7	467		T24	3
fifo_depth[6]	auto[1]	auto[0]	auto[1]	29328	1			T4	2		T5	682		T7	519
fifo_depth[6]	auto[1]	auto[1]	auto[0]	28817	1			T5	470		T6	1		T7	781
fifo_depth[6]	auto[1]	auto[1]	auto[1]	30301	1			T4	2		T5	534		T7	771
fifo_depth[7]	auto[0]	auto[0]	auto[0]	10481	1			T5	143		T7	182		T25	26
fifo_depth[7]	auto[0]	auto[0]	auto[1]	10823	1			T5	427		T7	139		T15	22
fifo_depth[7]	auto[0]	auto[1]	auto[0]	54749	1			T4	2		T5	1444		T7	674
fifo_depth[7]	auto[0]	auto[1]	auto[1]	8572	1			T4	1		T5	118		T7	182
fifo_depth[7]	auto[1]	auto[0]	auto[0]	28714	1			T1	1		T4	1		T5	875
fifo_depth[7]	auto[1]	auto[0]	auto[1]	26732	1			T5	651		T7	492		T25	24
fifo_depth[7]	auto[1]	auto[1]	auto[0]	26598	1			T5	447		T7	727		T25	34
fifo_depth[7]	auto[1]	auto[1]	auto[1]	27597	1			T5	509		T7	678		T24	2
fifo_depth[8]	auto[0]	auto[0]	auto[0]	10006	1			T5	159		T7	174		T25	30
fifo_depth[8]	auto[0]	auto[0]	auto[1]	11194	1			T5	373		T7	102		T15	56
fifo_depth[8]	auto[0]	auto[1]	auto[0]	42673	1			T5	949		T7	460		T15	65
fifo_depth[8]	auto[0]	auto[1]	auto[1]	8759	1			T5	73		T7	162		T25	8
fifo_depth[8]	auto[1]	auto[0]	auto[0]	25682	1			T5	719		T7	339		T24	2
fifo_depth[8]	auto[1]	auto[0]	auto[1]	24148	1			T5	580		T7	400		T25	19
fifo_depth[8]	auto[1]	auto[1]	auto[0]	22954	1			T5	377		T7	570		T25	36
fifo_depth[8]	auto[1]	auto[1]	auto[1]	24873	1			T5	421		T7	641		T83	138
fifo_depth[9]	auto[0]	auto[0]	auto[0]	7144	1			T5	128		T7	120		T25	16
fifo_depth[9]	auto[0]	auto[0]	auto[1]	7438	1			T5	285		T7	75		T15	10
fifo_depth[9]	auto[0]	auto[1]	auto[0]	28725	1			T5	652		T7	260		T15	19
fifo_depth[9]	auto[0]	auto[1]	auto[1]	5564	1			T4	1		T5	34		T7	138
fifo_depth[9]	auto[1]	auto[0]	auto[0]	18126	1			T5	510		T7	268		T24	1
fifo_depth[9]	auto[1]	auto[0]	auto[1]	17652	1			T5	440		T7	295		T25	18
fifo_depth[9]	auto[1]	auto[1]	auto[0]	17141	1			T5	299		T7	470		T25	27
fifo_depth[9]	auto[1]	auto[1]	auto[1]	17670	1			T5	295		T7	438		T83	83
fifo_depth[10]	auto[0]	auto[0]	auto[0]	6181	1			T5	89		T7	86		T25	8
fifo_depth[10]	auto[0]	auto[0]	auto[1]	6160	1			T5	318		T7	66		T15	6
fifo_depth[10]	auto[0]	auto[1]	auto[0]	19787	1			T5	373		T7	169		T15	16
fifo_depth[10]	auto[0]	auto[1]	auto[1]	5115	1			T5	64		T7	74		T25	5
fifo_depth[10]	auto[1]	auto[0]	auto[0]	13584	1			T5	414		T7	175		T24	2
fifo_depth[10]	auto[1]	auto[0]	auto[1]	12546	1			T5	372		T7	214		T25	14
fifo_depth[10]	auto[1]	auto[1]	auto[0]	12523	1			T5	242		T7	309		T25	18
fifo_depth[10]	auto[1]	auto[1]	auto[1]	12846	1			T5	221		T7	316		T83	60
fifo_depth[11]	auto[0]	auto[0]	auto[0]	3830	1			T5	66		T7	49		T25	6
fifo_depth[11]	auto[0]	auto[0]	auto[1]	3984	1			T5	190		T7	38		T15	1
fifo_depth[11]	auto[0]	auto[1]	auto[0]	11174	1			T5	185		T7	98		T15	5
fifo_depth[11]	auto[0]	auto[1]	auto[1]	3045	1			T5	16		T7	36		T25	7
fifo_depth[11]	auto[1]	auto[0]	auto[0]	7928	1			T5	263		T7	108		T56	58
fifo_depth[11]	auto[1]	auto[0]	auto[1]	7809	1			T5	216		T7	139		T25	8
fifo_depth[11]	auto[1]	auto[1]	auto[0]	7610	1			T5	140		T7	163		T25	9
fifo_depth[11]	auto[1]	auto[1]	auto[1]	8230	1			T5	130		T7	207		T83	36
fifo_depth[12]	auto[0]	auto[0]	auto[0]	3507	1			T5	51		T7	15		T25	7
fifo_depth[12]	auto[0]	auto[0]	auto[1]	4647	1			T5	291		T7	21		T15	1
fifo_depth[12]	auto[0]	auto[1]	auto[0]	8092	1			T5	120		T7	46		T79	2
fifo_depth[12]	auto[0]	auto[1]	auto[1]	4104	1			T5	11		T7	26		T25	1
fifo_depth[12]	auto[1]	auto[0]	auto[0]	6699	1			T5	157		T7	49		T56	22
fifo_depth[12]	auto[1]	auto[0]	auto[1]	6054	1			T5	171		T7	61		T25	5
fifo_depth[12]	auto[1]	auto[1]	auto[0]	5450	1			T5	90		T7	75		T25	6
fifo_depth[12]	auto[1]	auto[1]	auto[1]	6659	1			T5	80		T7	96		T83	19
fifo_depth[13]	auto[0]	auto[0]	auto[0]	2565	1			T5	47		T7	4		T25	1
fifo_depth[13]	auto[0]	auto[0]	auto[1]	2373	1			T5	137		T7	8		T82	9
fifo_depth[13]	auto[0]	auto[1]	auto[0]	4190	1			T5	48		T7	18		T79	2
fifo_depth[13]	auto[0]	auto[1]	auto[1]	1975	1			T5	32		T7	7		T79	2
fifo_depth[13]	auto[1]	auto[0]	auto[0]	3451	1			T5	130		T7	29		T56	14
fifo_depth[13]	auto[1]	auto[0]	auto[1]	3336	1			T5	90		T7	21		T25	1
fifo_depth[13]	auto[1]	auto[1]	auto[0]	3007	1			T5	75		T7	32		T25	5
fifo_depth[13]	auto[1]	auto[1]	auto[1]	3365	1			T5	20		T7	40		T83	12
fifo_depth[14]	auto[0]	auto[0]	auto[0]	3086	1			T5	58		T7	2		T82	4
fifo_depth[14]	auto[0]	auto[0]	auto[1]	3162	1			T5	250		T7	6		T82	4
fifo_depth[14]	auto[0]	auto[1]	auto[0]	4062	1			T5	17		T7	5		T79	1
fifo_depth[14]	auto[0]	auto[1]	auto[1]	3604	1			T5	42		T7	6		T120	1
fifo_depth[14]	auto[1]	auto[0]	auto[0]	3551	1			T5	113		T7	6		T56	4
fifo_depth[14]	auto[1]	auto[0]	auto[1]	3254	1			T5	104		T7	11		T25	2
fifo_depth[14]	auto[1]	auto[1]	auto[0]	3049	1			T5	79		T7	14		T56	3
fifo_depth[14]	auto[1]	auto[1]	auto[1]	3508	1			T5	31		T7	23		T83	3
fifo_depth[15]	auto[0]	auto[0]	auto[0]	2405	1			T5	64		T7	3		T82	2
fifo_depth[15]	auto[0]	auto[0]	auto[1]	2090	1			T5	139		T7	1		T120	1
fifo_depth[15]	auto[0]	auto[1]	auto[0]	2639	1			T5	2		T7	2		T21	43
fifo_depth[15]	auto[0]	auto[1]	auto[1]	2107	1			T5	16		T21	64		T107	40
fifo_depth[15]	auto[1]	auto[0]	auto[0]	2485	1			T5	71		T7	1		T79	1
fifo_depth[15]	auto[1]	auto[0]	auto[1]	2261	1			T5	92		T7	7		T56	3
fifo_depth[15]	auto[1]	auto[1]	auto[0]	1876	1			T5	76		T7	3		T56	5
fifo_depth[15]	auto[1]	auto[1]	auto[1]	2299	1			T5	4		T7	5		T77	4
fifo_depth[16]	auto[0]	auto[0]	auto[0]	12226	1			T5	1448		T7	2		T21	37
fifo_depth[16]	auto[0]	auto[0]	auto[1]	6994	1			T5	199		T7	1		T21	507
fifo_depth[16]	auto[0]	auto[1]	auto[0]	7325	1			T5	8		T7	1		T21	527
fifo_depth[16]	auto[0]	auto[1]	auto[1]	9889	1			T5	43		T21	215		T107	7
fifo_depth[16]	auto[1]	auto[0]	auto[0]	6671	1			T5	443		T7	1		T120	1
fifo_depth[16]	auto[1]	auto[0]	auto[1]	11166	1			T5	342		T7	2		T56	1
fifo_depth[16]	auto[1]	auto[1]	auto[0]	6597	1			T5	202		T7	3		T56	1
fifo_depth[16]	auto[1]	auto[1]	auto[1]	7726	1			T5	45		T7	3		T77	1