Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	14881760	1			T1	3146		T3	7716		T4	123413
all_pins[1]	14881760	1			T1	3146		T3	7716		T4	123413
all_pins[2]	14881760	1			T1	3146		T3	7716		T4	123413

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	42354331	1			T1	9419		T3	15749		T4	338740
values[0x1]	2290949	1			T1	19		T3	7399		T4	31499
transitions[0x0=>0x1]	2290802	1			T1	19		T3	7399		T4	31499
transitions[0x1=>0x0]	2290814	1			T1	19		T3	7399		T4	31499

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	14831142	1			T1	3127		T3	7715		T4	123112
all_pins[0]	values[0x1]	50618	1			T1	19		T3	1		T4	301
all_pins[0]	transitions[0x0=>0x1]	50561	1			T1	19		T3	1		T4	301
all_pins[0]	transitions[0x1=>0x0]	2239780	1			T3	7398		T4	31198		T5	44099
all_pins[1]	values[0x0]	14881254	1			T1	3146		T3	7716		T4	123413
all_pins[1]	values[0x1]	506	1			T5	8		T15	2		T12	5
all_pins[1]	transitions[0x0=>0x1]	468	1			T5	8		T15	2		T12	5
all_pins[1]	transitions[0x1=>0x0]	50580	1			T1	19		T3	1		T4	301
all_pins[2]	values[0x0]	12641935	1			T1	3146		T3	318		T4	92215
all_pins[2]	values[0x1]	2239825	1			T3	7398		T4	31198		T5	44099
all_pins[2]	transitions[0x0=>0x1]	2239773	1			T3	7398		T4	31198		T5	44097
all_pins[2]	transitions[0x1=>0x0]	454	1			T5	6		T15	1		T12	5