Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 960 1 T5 14 T15 17 T12 24
all_values[1] 960 1 T5 14 T15 17 T12 24
all_values[2] 960 1 T5 14 T15 17 T12 24


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1480 1 T5 18 T15 27 T12 46
auto[1] 1400 1 T5 24 T15 24 T12 26


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1028 1 T5 21 T15 17 T12 33
auto[1] 1852 1 T5 21 T15 34 T12 39


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1626 1 T5 28 T15 29 T12 46
auto[1] 1254 1 T5 14 T15 22 T12 26


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 179 1 T5 5 T15 5 T12 5
all_values[0] auto[0] auto[0] auto[1] 88 1 T5 1 T15 1 T12 3
all_values[0] auto[0] auto[1] auto[0] 163 1 T5 5 T15 1 T68 4
all_values[0] auto[0] auto[1] auto[1] 101 1 T15 3 T12 2 T68 1
all_values[0] auto[1] auto[0] auto[1] 219 1 T5 3 T15 5 T12 10
all_values[0] auto[1] auto[1] auto[1] 210 1 T15 2 T12 4 T68 4
all_values[1] auto[0] auto[0] auto[0] 168 1 T5 2 T15 2 T12 5
all_values[1] auto[0] auto[0] auto[1] 116 1 T5 1 T15 2 T12 4
all_values[1] auto[0] auto[1] auto[0] 158 1 T5 4 T15 6 T12 4
all_values[1] auto[0] auto[1] auto[1] 117 1 T5 2 T15 1 T12 3
all_values[1] auto[1] auto[0] auto[1] 192 1 T15 5 T12 4 T68 2
all_values[1] auto[1] auto[1] auto[1] 209 1 T5 5 T15 1 T12 4
all_values[2] auto[0] auto[0] auto[0] 209 1 T5 2 T15 1 T12 12
all_values[2] auto[0] auto[0] auto[1] 84 1 T5 1 T15 2 T12 1
all_values[2] auto[0] auto[1] auto[0] 151 1 T5 3 T15 2 T12 7
all_values[2] auto[0] auto[1] auto[1] 92 1 T5 2 T15 3 T68 4
all_values[2] auto[1] auto[0] auto[1] 225 1 T5 3 T15 4 T12 2
all_values[2] auto[1] auto[1] auto[1] 199 1 T5 3 T15 5 T12 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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