Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.55 92.46 85.17 100.00 73.68 85.93 99.49 69.08


Total test records in report: 733
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html
T534 /workspace/coverage/default/48.hmac_stress_all.3300283921 Apr 15 02:24:36 PM PDT 24 Apr 15 02:39:05 PM PDT 24 137516431936 ps
T535 /workspace/coverage/default/39.hmac_wipe_secret.2527870249 Apr 15 02:23:54 PM PDT 24 Apr 15 02:23:58 PM PDT 24 118492425 ps
T536 /workspace/coverage/default/35.hmac_test_hmac_vectors.2233589183 Apr 15 02:23:38 PM PDT 24 Apr 15 02:23:40 PM PDT 24 62006184 ps
T537 /workspace/coverage/default/37.hmac_wipe_secret.3161590431 Apr 15 02:23:49 PM PDT 24 Apr 15 02:24:43 PM PDT 24 11303238023 ps
T538 /workspace/coverage/default/40.hmac_wipe_secret.3640329271 Apr 15 02:23:58 PM PDT 24 Apr 15 02:24:51 PM PDT 24 2906988630 ps
T539 /workspace/coverage/default/17.hmac_wipe_secret.1921507516 Apr 15 02:22:21 PM PDT 24 Apr 15 02:22:58 PM PDT 24 6668838816 ps
T540 /workspace/coverage/default/10.hmac_test_sha_vectors.1849352844 Apr 15 02:21:59 PM PDT 24 Apr 15 02:30:01 PM PDT 24 36709507192 ps
T541 /workspace/coverage/default/41.hmac_error.2305845926 Apr 15 02:24:01 PM PDT 24 Apr 15 02:25:38 PM PDT 24 12913661735 ps
T542 /workspace/coverage/default/35.hmac_back_pressure.4253872310 Apr 15 02:23:35 PM PDT 24 Apr 15 02:24:24 PM PDT 24 2956937172 ps
T543 /workspace/coverage/default/17.hmac_back_pressure.259563287 Apr 15 02:22:24 PM PDT 24 Apr 15 02:22:28 PM PDT 24 91863018 ps
T544 /workspace/coverage/default/16.hmac_test_sha_vectors.413109657 Apr 15 02:22:19 PM PDT 24 Apr 15 02:30:13 PM PDT 24 25371465904 ps
T75 /workspace/coverage/default/96.hmac_stress_all_with_rand_reset.1603071168 Apr 15 02:24:56 PM PDT 24 Apr 15 02:27:29 PM PDT 24 91239352078 ps
T545 /workspace/coverage/default/22.hmac_datapath_stress.1231731474 Apr 15 02:22:42 PM PDT 24 Apr 15 02:25:20 PM PDT 24 22646258861 ps
T546 /workspace/coverage/default/7.hmac_stress_all.3679982351 Apr 15 02:22:01 PM PDT 24 Apr 15 02:42:13 PM PDT 24 183943390304 ps
T547 /workspace/coverage/default/28.hmac_burst_wr.907595469 Apr 15 02:23:07 PM PDT 24 Apr 15 02:23:29 PM PDT 24 1292089809 ps
T548 /workspace/coverage/default/17.hmac_datapath_stress.4095106498 Apr 15 02:22:20 PM PDT 24 Apr 15 02:22:47 PM PDT 24 827249660 ps
T549 /workspace/coverage/default/11.hmac_burst_wr.3494989864 Apr 15 02:22:02 PM PDT 24 Apr 15 02:22:11 PM PDT 24 176020111 ps
T550 /workspace/coverage/default/44.hmac_long_msg.3481339426 Apr 15 02:24:14 PM PDT 24 Apr 15 02:25:26 PM PDT 24 1897608641 ps
T551 /workspace/coverage/default/20.hmac_back_pressure.283913165 Apr 15 02:22:34 PM PDT 24 Apr 15 02:23:38 PM PDT 24 5952866907 ps
T552 /workspace/coverage/default/36.hmac_burst_wr.3140612841 Apr 15 02:23:41 PM PDT 24 Apr 15 02:23:55 PM PDT 24 2165607468 ps
T553 /workspace/coverage/default/11.hmac_error.144426744 Apr 15 02:22:00 PM PDT 24 Apr 15 02:24:08 PM PDT 24 4755091699 ps
T554 /workspace/coverage/default/40.hmac_datapath_stress.1194169381 Apr 15 02:23:53 PM PDT 24 Apr 15 02:25:42 PM PDT 24 7871219884 ps
T555 /workspace/coverage/default/14.hmac_long_msg.3666975032 Apr 15 02:22:11 PM PDT 24 Apr 15 02:23:28 PM PDT 24 5264876890 ps
T556 /workspace/coverage/default/8.hmac_error.2581175986 Apr 15 02:21:51 PM PDT 24 Apr 15 02:22:12 PM PDT 24 2716328107 ps
T557 /workspace/coverage/default/45.hmac_test_hmac_vectors.721084899 Apr 15 02:24:22 PM PDT 24 Apr 15 02:24:24 PM PDT 24 111901105 ps
T558 /workspace/coverage/default/26.hmac_burst_wr.3892343673 Apr 15 02:23:05 PM PDT 24 Apr 15 02:23:35 PM PDT 24 577135369 ps
T559 /workspace/coverage/default/2.hmac_back_pressure.2434400064 Apr 15 02:21:41 PM PDT 24 Apr 15 02:21:51 PM PDT 24 184478027 ps
T560 /workspace/coverage/default/33.hmac_test_hmac_vectors.2119236444 Apr 15 02:23:25 PM PDT 24 Apr 15 02:23:27 PM PDT 24 555900196 ps
T561 /workspace/coverage/default/26.hmac_test_hmac_vectors.446362588 Apr 15 02:23:01 PM PDT 24 Apr 15 02:23:04 PM PDT 24 198297944 ps
T562 /workspace/coverage/default/13.hmac_wipe_secret.3080995286 Apr 15 02:22:03 PM PDT 24 Apr 15 02:23:32 PM PDT 24 2162892523 ps
T563 /workspace/coverage/default/44.hmac_burst_wr.1408282349 Apr 15 02:24:16 PM PDT 24 Apr 15 02:24:26 PM PDT 24 601087264 ps
T31 /workspace/coverage/default/4.hmac_sec_cm.1460122801 Apr 15 02:21:50 PM PDT 24 Apr 15 02:21:55 PM PDT 24 224225920 ps
T564 /workspace/coverage/default/16.hmac_long_msg.1207097592 Apr 15 02:22:15 PM PDT 24 Apr 15 02:22:34 PM PDT 24 591559991 ps
T565 /workspace/coverage/default/35.hmac_wipe_secret.1686176274 Apr 15 02:23:46 PM PDT 24 Apr 15 02:25:12 PM PDT 24 8729305200 ps
T566 /workspace/coverage/default/25.hmac_burst_wr.3541941646 Apr 15 02:22:56 PM PDT 24 Apr 15 02:23:16 PM PDT 24 4395117898 ps
T567 /workspace/coverage/default/33.hmac_wipe_secret.4013733708 Apr 15 02:23:25 PM PDT 24 Apr 15 02:24:18 PM PDT 24 11448010804 ps
T568 /workspace/coverage/default/39.hmac_back_pressure.953517551 Apr 15 02:23:51 PM PDT 24 Apr 15 02:23:56 PM PDT 24 113030757 ps
T569 /workspace/coverage/default/6.hmac_long_msg.478116594 Apr 15 02:21:53 PM PDT 24 Apr 15 02:22:25 PM PDT 24 2122502259 ps
T570 /workspace/coverage/default/38.hmac_datapath_stress.3562214449 Apr 15 02:23:46 PM PDT 24 Apr 15 02:25:14 PM PDT 24 5933783162 ps
T76 /workspace/coverage/default/186.hmac_stress_all_with_rand_reset.3947683411 Apr 15 02:25:29 PM PDT 24 Apr 15 02:32:16 PM PDT 24 119486529568 ps
T571 /workspace/coverage/default/25.hmac_wipe_secret.3870997508 Apr 15 02:22:54 PM PDT 24 Apr 15 02:23:09 PM PDT 24 777091998 ps
T572 /workspace/coverage/default/37.hmac_burst_wr.1760533447 Apr 15 02:23:41 PM PDT 24 Apr 15 02:24:24 PM PDT 24 2192525274 ps
T573 /workspace/coverage/default/4.hmac_alert_test.3784509815 Apr 15 02:21:41 PM PDT 24 Apr 15 02:21:45 PM PDT 24 43592214 ps
T574 /workspace/coverage/default/48.hmac_test_hmac_vectors.3901157147 Apr 15 02:24:44 PM PDT 24 Apr 15 02:24:46 PM PDT 24 52625812 ps
T575 /workspace/coverage/default/10.hmac_stress_all_with_rand_reset.1239731458 Apr 15 02:22:00 PM PDT 24 Apr 15 02:39:08 PM PDT 24 38210884766 ps
T576 /workspace/coverage/default/36.hmac_test_hmac_vectors.3119158261 Apr 15 02:23:41 PM PDT 24 Apr 15 02:23:42 PM PDT 24 30264668 ps
T577 /workspace/coverage/default/34.hmac_smoke.1169121367 Apr 15 02:23:32 PM PDT 24 Apr 15 02:23:35 PM PDT 24 58443896 ps
T578 /workspace/coverage/default/12.hmac_smoke.258733370 Apr 15 02:22:05 PM PDT 24 Apr 15 02:22:09 PM PDT 24 306578837 ps
T579 /workspace/coverage/default/35.hmac_stress_all.801713001 Apr 15 02:23:37 PM PDT 24 Apr 15 02:24:13 PM PDT 24 1933661399 ps
T580 /workspace/coverage/default/25.hmac_datapath_stress.278730866 Apr 15 02:23:00 PM PDT 24 Apr 15 02:25:18 PM PDT 24 8610117253 ps
T581 /workspace/coverage/default/21.hmac_test_sha_vectors.3739142208 Apr 15 02:22:42 PM PDT 24 Apr 15 02:29:40 PM PDT 24 7625966278 ps
T582 /workspace/coverage/default/37.hmac_long_msg.3549066331 Apr 15 02:23:45 PM PDT 24 Apr 15 02:24:05 PM PDT 24 5856108212 ps
T583 /workspace/coverage/default/45.hmac_error.3005559674 Apr 15 02:24:18 PM PDT 24 Apr 15 02:25:48 PM PDT 24 1616825469 ps
T584 /workspace/coverage/default/13.hmac_test_sha_vectors.4161659697 Apr 15 02:22:07 PM PDT 24 Apr 15 02:29:15 PM PDT 24 60013787773 ps
T585 /workspace/coverage/default/38.hmac_burst_wr.3031612928 Apr 15 02:23:47 PM PDT 24 Apr 15 02:24:25 PM PDT 24 7572808690 ps
T586 /workspace/coverage/default/45.hmac_back_pressure.3102401422 Apr 15 02:24:19 PM PDT 24 Apr 15 02:25:20 PM PDT 24 5763188254 ps
T587 /workspace/coverage/default/21.hmac_datapath_stress.3169239508 Apr 15 02:22:39 PM PDT 24 Apr 15 02:24:14 PM PDT 24 1682851460 ps
T588 /workspace/coverage/default/28.hmac_long_msg.895449495 Apr 15 02:23:04 PM PDT 24 Apr 15 02:24:41 PM PDT 24 6315444771 ps
T589 /workspace/coverage/default/43.hmac_test_hmac_vectors.3924486765 Apr 15 02:24:13 PM PDT 24 Apr 15 02:24:15 PM PDT 24 27631922 ps
T590 /workspace/coverage/default/27.hmac_long_msg.3403753711 Apr 15 02:23:00 PM PDT 24 Apr 15 02:24:38 PM PDT 24 24210231954 ps
T591 /workspace/coverage/default/11.hmac_test_hmac_vectors.3071434759 Apr 15 02:21:58 PM PDT 24 Apr 15 02:22:01 PM PDT 24 48008842 ps
T592 /workspace/coverage/default/35.hmac_long_msg.2210414257 Apr 15 02:23:34 PM PDT 24 Apr 15 02:25:09 PM PDT 24 1690888868 ps
T593 /workspace/coverage/default/34.hmac_long_msg.1319005858 Apr 15 02:23:29 PM PDT 24 Apr 15 02:24:55 PM PDT 24 6354186538 ps
T594 /workspace/coverage/default/21.hmac_smoke.1158853968 Apr 15 02:22:39 PM PDT 24 Apr 15 02:22:41 PM PDT 24 458152096 ps
T595 /workspace/coverage/default/30.hmac_stress_all.301820677 Apr 15 02:23:19 PM PDT 24 Apr 15 02:35:54 PM PDT 24 225809218366 ps
T596 /workspace/coverage/default/6.hmac_wipe_secret.2052878684 Apr 15 02:21:48 PM PDT 24 Apr 15 02:22:31 PM PDT 24 4098464118 ps
T597 /workspace/coverage/default/3.hmac_alert_test.958904488 Apr 15 02:21:42 PM PDT 24 Apr 15 02:21:47 PM PDT 24 12180737 ps
T598 /workspace/coverage/default/41.hmac_test_sha_vectors.3098391727 Apr 15 02:24:01 PM PDT 24 Apr 15 02:32:48 PM PDT 24 38782924191 ps
T62 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1996689562 Apr 15 12:39:33 PM PDT 24 Apr 15 12:39:37 PM PDT 24 441561194 ps
T63 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.477301799 Apr 15 12:39:29 PM PDT 24 Apr 15 12:39:32 PM PDT 24 82142872 ps
T64 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.222991790 Apr 15 12:39:31 PM PDT 24 Apr 15 12:41:42 PM PDT 24 44509244340 ps
T599 /workspace/coverage/cover_reg_top/35.hmac_intr_test.2895854114 Apr 15 12:39:38 PM PDT 24 Apr 15 12:39:40 PM PDT 24 17084890 ps
T600 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3665720687 Apr 15 12:40:48 PM PDT 24 Apr 15 12:40:51 PM PDT 24 175944687 ps
T94 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3186176007 Apr 15 12:39:30 PM PDT 24 Apr 15 12:39:33 PM PDT 24 76087001 ps
T601 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2294644286 Apr 15 12:39:32 PM PDT 24 Apr 15 12:39:34 PM PDT 24 37335639 ps
T602 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.902720889 Apr 15 12:39:29 PM PDT 24 Apr 15 12:39:32 PM PDT 24 104559586 ps
T603 /workspace/coverage/cover_reg_top/34.hmac_intr_test.337332109 Apr 15 12:39:38 PM PDT 24 Apr 15 12:39:40 PM PDT 24 30316557 ps
T604 /workspace/coverage/cover_reg_top/40.hmac_intr_test.2505395779 Apr 15 12:39:35 PM PDT 24 Apr 15 12:39:37 PM PDT 24 17380642 ps
T605 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3195656936 Apr 15 12:39:25 PM PDT 24 Apr 15 12:39:31 PM PDT 24 276111998 ps
T102 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1844505969 Apr 15 12:39:31 PM PDT 24 Apr 15 12:39:38 PM PDT 24 447163268 ps
T606 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2635194992 Apr 15 12:39:27 PM PDT 24 Apr 15 12:39:32 PM PDT 24 36205416 ps
T607 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3685336905 Apr 15 12:39:29 PM PDT 24 Apr 15 12:39:32 PM PDT 24 49537326 ps
T95 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3563467181 Apr 15 12:39:36 PM PDT 24 Apr 15 12:39:39 PM PDT 24 18183348 ps
T608 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2395300229 Apr 15 12:39:23 PM PDT 24 Apr 15 12:39:27 PM PDT 24 271113448 ps
T609 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.698714822 Apr 15 12:39:30 PM PDT 24 Apr 15 12:39:34 PM PDT 24 47508264 ps
T610 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2177944202 Apr 15 12:39:24 PM PDT 24 Apr 15 12:43:50 PM PDT 24 165649840667 ps
T611 /workspace/coverage/cover_reg_top/36.hmac_intr_test.4229326208 Apr 15 12:39:27 PM PDT 24 Apr 15 12:39:30 PM PDT 24 41791480 ps
T96 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3860241830 Apr 15 12:39:29 PM PDT 24 Apr 15 12:39:40 PM PDT 24 2292786426 ps
T612 /workspace/coverage/cover_reg_top/24.hmac_intr_test.286617078 Apr 15 12:39:24 PM PDT 24 Apr 15 12:39:28 PM PDT 24 11461993 ps
T613 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.998742728 Apr 15 12:39:24 PM PDT 24 Apr 15 12:39:30 PM PDT 24 580298800 ps
T59 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2240553785 Apr 15 12:39:24 PM PDT 24 Apr 15 12:39:30 PM PDT 24 52128206 ps
T614 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1926068308 Apr 15 12:39:37 PM PDT 24 Apr 15 12:39:39 PM PDT 24 40087614 ps
T60 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3449476529 Apr 15 12:39:37 PM PDT 24 Apr 15 12:39:43 PM PDT 24 242660065 ps
T615 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2526141335 Apr 15 12:39:28 PM PDT 24 Apr 15 12:39:32 PM PDT 24 2129902625 ps
T616 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2585916906 Apr 15 12:39:31 PM PDT 24 Apr 15 12:39:38 PM PDT 24 20062328 ps
T617 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2912686339 Apr 15 12:39:31 PM PDT 24 Apr 15 12:39:33 PM PDT 24 129234192 ps
T618 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1486369194 Apr 15 12:39:26 PM PDT 24 Apr 15 12:39:37 PM PDT 24 165520463 ps
T619 /workspace/coverage/cover_reg_top/47.hmac_intr_test.1324515873 Apr 15 12:39:35 PM PDT 24 Apr 15 12:39:37 PM PDT 24 11596623 ps
T61 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2194553608 Apr 15 12:39:34 PM PDT 24 Apr 15 12:39:39 PM PDT 24 195450860 ps
T620 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.849192866 Apr 15 12:39:33 PM PDT 24 Apr 15 12:39:38 PM PDT 24 178594843 ps
T621 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2921773550 Apr 15 12:39:31 PM PDT 24 Apr 15 12:39:34 PM PDT 24 104579908 ps
T108 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1493146790 Apr 15 12:39:20 PM PDT 24 Apr 15 12:39:23 PM PDT 24 47146086 ps
T622 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3444164713 Apr 15 12:39:34 PM PDT 24 Apr 15 12:39:38 PM PDT 24 141939006 ps
T623 /workspace/coverage/cover_reg_top/14.hmac_intr_test.867998194 Apr 15 12:39:23 PM PDT 24 Apr 15 12:39:26 PM PDT 24 33660577 ps
T624 /workspace/coverage/cover_reg_top/48.hmac_intr_test.3392437353 Apr 15 12:39:36 PM PDT 24 Apr 15 12:39:38 PM PDT 24 32824786 ps
T625 /workspace/coverage/cover_reg_top/29.hmac_intr_test.3553715236 Apr 15 12:39:25 PM PDT 24 Apr 15 12:39:29 PM PDT 24 16380480 ps
T626 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1703065407 Apr 15 12:39:30 PM PDT 24 Apr 15 12:39:34 PM PDT 24 435228082 ps
T627 /workspace/coverage/cover_reg_top/20.hmac_intr_test.166396483 Apr 15 12:39:25 PM PDT 24 Apr 15 12:39:29 PM PDT 24 42660480 ps
T628 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.383955961 Apr 15 12:39:30 PM PDT 24 Apr 15 12:39:35 PM PDT 24 401768423 ps
T629 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3868163481 Apr 15 12:39:27 PM PDT 24 Apr 15 12:39:33 PM PDT 24 111053754 ps
T115 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3939118699 Apr 15 12:39:21 PM PDT 24 Apr 15 12:39:25 PM PDT 24 190085541 ps
T630 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4177596099 Apr 15 12:39:22 PM PDT 24 Apr 15 12:39:27 PM PDT 24 48640625 ps
T631 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3979640826 Apr 15 12:39:35 PM PDT 24 Apr 15 12:39:37 PM PDT 24 29674782 ps
T109 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1392529550 Apr 15 12:39:23 PM PDT 24 Apr 15 12:39:28 PM PDT 24 169590305 ps
T632 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1032880483 Apr 15 12:39:29 PM PDT 24 Apr 15 12:39:35 PM PDT 24 1069603536 ps
T633 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3511423065 Apr 15 12:40:24 PM PDT 24 Apr 15 12:40:28 PM PDT 24 795886932 ps
T97 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1629480415 Apr 15 12:39:21 PM PDT 24 Apr 15 12:39:23 PM PDT 24 261516066 ps
T634 /workspace/coverage/cover_reg_top/31.hmac_intr_test.4169448764 Apr 15 12:39:35 PM PDT 24 Apr 15 12:39:37 PM PDT 24 13261510 ps
T635 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1697249862 Apr 15 12:39:31 PM PDT 24 Apr 15 12:39:35 PM PDT 24 932861911 ps
T636 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2476361415 Apr 15 12:39:29 PM PDT 24 Apr 15 12:39:34 PM PDT 24 54132859 ps
T637 /workspace/coverage/cover_reg_top/30.hmac_intr_test.3758889373 Apr 15 12:39:35 PM PDT 24 Apr 15 12:39:37 PM PDT 24 12860223 ps
T638 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3936863472 Apr 15 12:39:24 PM PDT 24 Apr 15 12:39:29 PM PDT 24 41491825 ps
T98 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1489565585 Apr 15 12:39:21 PM PDT 24 Apr 15 12:39:37 PM PDT 24 632342241 ps
T99 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3394543722 Apr 15 12:39:30 PM PDT 24 Apr 15 12:39:33 PM PDT 24 47304904 ps
T639 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.598752557 Apr 15 12:39:31 PM PDT 24 Apr 15 12:39:33 PM PDT 24 203332121 ps
T640 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3426275831 Apr 15 12:39:20 PM PDT 24 Apr 15 12:39:22 PM PDT 24 86918936 ps
T100 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1641766024 Apr 15 12:39:28 PM PDT 24 Apr 15 12:39:39 PM PDT 24 465919076 ps
T641 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3822012335 Apr 15 12:39:34 PM PDT 24 Apr 15 12:39:38 PM PDT 24 47067491 ps
T642 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1985959743 Apr 15 12:39:26 PM PDT 24 Apr 15 12:39:31 PM PDT 24 484878343 ps
T643 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.148518189 Apr 15 12:39:25 PM PDT 24 Apr 15 12:39:31 PM PDT 24 37903561 ps
T644 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2010016916 Apr 15 12:39:24 PM PDT 24 Apr 15 12:39:29 PM PDT 24 73276268 ps
T101 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2719520789 Apr 15 12:39:23 PM PDT 24 Apr 15 12:39:27 PM PDT 24 28933321 ps
T110 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2325473263 Apr 15 12:39:34 PM PDT 24 Apr 15 12:39:39 PM PDT 24 260002903 ps
T645 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2140227116 Apr 15 12:39:23 PM PDT 24 Apr 15 12:39:27 PM PDT 24 104392162 ps
T116 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.147295292 Apr 15 12:39:25 PM PDT 24 Apr 15 12:39:32 PM PDT 24 456492109 ps
T646 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.660850172 Apr 15 12:39:33 PM PDT 24 Apr 15 12:39:35 PM PDT 24 41013194 ps
T647 /workspace/coverage/cover_reg_top/9.hmac_intr_test.4161696847 Apr 15 12:40:24 PM PDT 24 Apr 15 12:40:26 PM PDT 24 22315976 ps
T648 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2936766488 Apr 15 12:39:23 PM PDT 24 Apr 15 12:39:27 PM PDT 24 43800953 ps
T103 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2007682201 Apr 15 12:39:26 PM PDT 24 Apr 15 12:39:42 PM PDT 24 2031538672 ps
T649 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2310969894 Apr 15 12:39:35 PM PDT 24 Apr 15 12:39:41 PM PDT 24 466299772 ps
T650 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.681163217 Apr 15 12:39:27 PM PDT 24 Apr 15 12:39:31 PM PDT 24 99509020 ps
T117 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2761356597 Apr 15 12:39:36 PM PDT 24 Apr 15 12:39:40 PM PDT 24 1186409640 ps
T119 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1190286172 Apr 15 12:39:31 PM PDT 24 Apr 15 12:39:36 PM PDT 24 1494384590 ps
T104 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3132530038 Apr 15 12:39:27 PM PDT 24 Apr 15 12:39:31 PM PDT 24 152293319 ps
T651 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.262530695 Apr 15 12:39:34 PM PDT 24 Apr 15 12:39:37 PM PDT 24 33737877 ps
T652 /workspace/coverage/cover_reg_top/7.hmac_intr_test.1044287790 Apr 15 12:39:21 PM PDT 24 Apr 15 12:39:24 PM PDT 24 96045068 ps
T653 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1426302194 Apr 15 12:39:31 PM PDT 24 Apr 15 12:39:34 PM PDT 24 16828910 ps
T105 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2804900378 Apr 15 12:39:20 PM PDT 24 Apr 15 12:39:26 PM PDT 24 111993982 ps
T654 /workspace/coverage/cover_reg_top/46.hmac_intr_test.856870751 Apr 15 12:39:30 PM PDT 24 Apr 15 12:39:32 PM PDT 24 19037562 ps
T655 /workspace/coverage/cover_reg_top/4.hmac_intr_test.1228638955 Apr 15 12:39:27 PM PDT 24 Apr 15 12:39:30 PM PDT 24 52964966 ps
T656 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1775100483 Apr 15 12:39:31 PM PDT 24 Apr 15 12:39:34 PM PDT 24 160365524 ps
T657 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3509838883 Apr 15 12:39:30 PM PDT 24 Apr 15 12:39:34 PM PDT 24 144495157 ps
T658 /workspace/coverage/cover_reg_top/3.hmac_intr_test.3899047757 Apr 15 12:39:19 PM PDT 24 Apr 15 12:39:21 PM PDT 24 16138563 ps
T659 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1508016683 Apr 15 12:39:28 PM PDT 24 Apr 15 12:39:31 PM PDT 24 45634706 ps
T660 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.275980198 Apr 15 12:39:30 PM PDT 24 Apr 15 12:39:33 PM PDT 24 139178334 ps
T661 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2842788104 Apr 15 12:39:32 PM PDT 24 Apr 15 12:39:36 PM PDT 24 127185474 ps
T662 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1772036917 Apr 15 12:39:32 PM PDT 24 Apr 15 12:39:35 PM PDT 24 149661914 ps
T663 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1142573802 Apr 15 12:39:34 PM PDT 24 Apr 15 12:39:36 PM PDT 24 20549888 ps
T664 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2343710241 Apr 15 12:40:49 PM PDT 24 Apr 15 12:40:52 PM PDT 24 48649322 ps
T665 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1406654717 Apr 15 12:39:29 PM PDT 24 Apr 15 12:39:32 PM PDT 24 71502115 ps
T666 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2281204572 Apr 15 12:39:23 PM PDT 24 Apr 15 12:39:27 PM PDT 24 19594472 ps
T667 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2172121452 Apr 15 12:39:38 PM PDT 24 Apr 15 12:39:40 PM PDT 24 56320061 ps
T668 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1490100670 Apr 15 12:39:26 PM PDT 24 Apr 15 12:39:30 PM PDT 24 103737413 ps
T669 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4115504715 Apr 15 12:39:30 PM PDT 24 Apr 15 12:39:34 PM PDT 24 161449960 ps
T670 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2751383172 Apr 15 12:39:19 PM PDT 24 Apr 15 12:39:22 PM PDT 24 98727736 ps
T671 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2691638610 Apr 15 12:39:34 PM PDT 24 Apr 15 12:39:38 PM PDT 24 182054000 ps
T672 /workspace/coverage/cover_reg_top/8.hmac_intr_test.1953779677 Apr 15 12:39:23 PM PDT 24 Apr 15 12:39:26 PM PDT 24 43325213 ps
T673 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2602443385 Apr 15 12:39:30 PM PDT 24 Apr 15 12:39:33 PM PDT 24 29553448 ps
T674 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.559383755 Apr 15 12:39:23 PM PDT 24 Apr 15 12:39:28 PM PDT 24 147938315 ps
T675 /workspace/coverage/cover_reg_top/11.hmac_intr_test.3244974394 Apr 15 12:39:24 PM PDT 24 Apr 15 12:39:27 PM PDT 24 47765906 ps
T676 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1470656364 Apr 15 12:39:22 PM PDT 24 Apr 15 12:39:25 PM PDT 24 19747547 ps
T677 /workspace/coverage/cover_reg_top/44.hmac_intr_test.947450650 Apr 15 12:39:36 PM PDT 24 Apr 15 12:39:38 PM PDT 24 38407621 ps
T678 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.46929588 Apr 15 12:39:35 PM PDT 24 Apr 15 12:39:37 PM PDT 24 24440681 ps
T679 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1707684878 Apr 15 12:39:20 PM PDT 24 Apr 15 12:39:23 PM PDT 24 187323279 ps
T680 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2084560099 Apr 15 12:39:34 PM PDT 24 Apr 15 12:39:38 PM PDT 24 270957243 ps
T681 /workspace/coverage/cover_reg_top/13.hmac_intr_test.955690596 Apr 15 12:39:30 PM PDT 24 Apr 15 12:39:33 PM PDT 24 30889299 ps
T118 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.4193628724 Apr 15 12:39:34 PM PDT 24 Apr 15 12:39:39 PM PDT 24 231612307 ps
T682 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3493480353 Apr 15 12:39:31 PM PDT 24 Apr 15 12:39:36 PM PDT 24 127839470 ps
T111 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.4253611908 Apr 15 12:39:34 PM PDT 24 Apr 15 12:39:39 PM PDT 24 180494331 ps
T683 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2202804419 Apr 15 12:39:25 PM PDT 24 Apr 15 12:39:29 PM PDT 24 59866421 ps
T684 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1911750060 Apr 15 12:39:30 PM PDT 24 Apr 15 12:39:34 PM PDT 24 183089401 ps
T685 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2218147674 Apr 15 12:39:49 PM PDT 24 Apr 15 12:39:52 PM PDT 24 1697428666 ps
T686 /workspace/coverage/cover_reg_top/10.hmac_intr_test.2490275394 Apr 15 12:39:35 PM PDT 24 Apr 15 12:39:37 PM PDT 24 42602654 ps
T687 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1049004585 Apr 15 12:39:34 PM PDT 24 Apr 15 12:39:37 PM PDT 24 23030096 ps
T113 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3779782912 Apr 15 12:39:24 PM PDT 24 Apr 15 12:39:29 PM PDT 24 313372460 ps
T112 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3338183101 Apr 15 12:39:30 PM PDT 24 Apr 15 12:39:34 PM PDT 24 97731225 ps
T688 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.4021999851 Apr 15 12:39:21 PM PDT 24 Apr 15 12:39:24 PM PDT 24 29952345 ps
T689 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2386225411 Apr 15 12:39:35 PM PDT 24 Apr 15 12:39:37 PM PDT 24 58129144 ps
T690 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3514012822 Apr 15 12:39:23 PM PDT 24 Apr 15 12:39:26 PM PDT 24 146565765 ps
T691 /workspace/coverage/cover_reg_top/17.hmac_intr_test.970668358 Apr 15 12:39:28 PM PDT 24 Apr 15 12:39:31 PM PDT 24 23268034 ps
T692 /workspace/coverage/cover_reg_top/26.hmac_intr_test.2251307072 Apr 15 12:39:35 PM PDT 24 Apr 15 12:39:37 PM PDT 24 22164865 ps
T693 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.406729018 Apr 15 12:40:46 PM PDT 24 Apr 15 12:40:48 PM PDT 24 60568586 ps
T694 /workspace/coverage/cover_reg_top/6.hmac_intr_test.10303548 Apr 15 12:39:30 PM PDT 24 Apr 15 12:39:33 PM PDT 24 13800459 ps
T695 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.369366943 Apr 15 12:40:49 PM PDT 24 Apr 15 12:40:51 PM PDT 24 289224065 ps
T696 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1308144086 Apr 15 12:39:27 PM PDT 24 Apr 15 12:39:30 PM PDT 24 13717753 ps
T697 /workspace/coverage/cover_reg_top/18.hmac_intr_test.3346571899 Apr 15 12:39:42 PM PDT 24 Apr 15 12:39:43 PM PDT 24 18087905 ps
T698 /workspace/coverage/cover_reg_top/49.hmac_intr_test.388380788 Apr 15 12:39:33 PM PDT 24 Apr 15 12:39:35 PM PDT 24 18776530 ps
T699 /workspace/coverage/cover_reg_top/33.hmac_intr_test.1298081849 Apr 15 12:39:26 PM PDT 24 Apr 15 12:39:30 PM PDT 24 51212992 ps
T700 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2559051766 Apr 15 12:39:26 PM PDT 24 Apr 15 12:39:31 PM PDT 24 62094779 ps
T701 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2995326105 Apr 15 12:39:28 PM PDT 24 Apr 15 12:39:31 PM PDT 24 47453915 ps
T114 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.576394814 Apr 15 12:39:25 PM PDT 24 Apr 15 12:39:31 PM PDT 24 108996236 ps
T702 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3682647684 Apr 15 12:39:31 PM PDT 24 Apr 15 12:52:26 PM PDT 24 358622725961 ps
T703 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2442722701 Apr 15 12:39:21 PM PDT 24 Apr 15 12:39:24 PM PDT 24 22085225 ps
T704 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1308909864 Apr 15 12:39:30 PM PDT 24 Apr 15 12:39:33 PM PDT 24 58081367 ps
T705 /workspace/coverage/cover_reg_top/45.hmac_intr_test.3270624373 Apr 15 12:39:35 PM PDT 24 Apr 15 12:39:37 PM PDT 24 14428611 ps
T706 /workspace/coverage/cover_reg_top/22.hmac_intr_test.2505250382 Apr 15 12:39:28 PM PDT 24 Apr 15 12:39:31 PM PDT 24 50780757 ps
T707 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3909836334 Apr 15 12:39:39 PM PDT 24 Apr 15 12:39:40 PM PDT 24 28555527 ps
T708 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3737704640 Apr 15 12:39:26 PM PDT 24 Apr 15 12:39:30 PM PDT 24 49666368 ps
T709 /workspace/coverage/cover_reg_top/27.hmac_intr_test.2888469021 Apr 15 12:39:34 PM PDT 24 Apr 15 12:39:35 PM PDT 24 47155853 ps
T710 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3687111039 Apr 15 12:39:30 PM PDT 24 Apr 15 12:39:34 PM PDT 24 85396139 ps
T711 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3802306505 Apr 15 12:39:38 PM PDT 24 Apr 15 12:39:40 PM PDT 24 18765889 ps
T712 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1821088892 Apr 15 12:39:23 PM PDT 24 Apr 15 12:39:26 PM PDT 24 27198706 ps
T713 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2190675717 Apr 15 12:39:31 PM PDT 24 Apr 15 12:39:33 PM PDT 24 12048735 ps
T714 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1276567534 Apr 15 12:39:31 PM PDT 24 Apr 15 12:39:37 PM PDT 24 221088081 ps
T715 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1234593481 Apr 15 12:39:25 PM PDT 24 Apr 15 12:39:28 PM PDT 24 41457235 ps
T716 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2335662812 Apr 15 12:39:33 PM PDT 24 Apr 15 12:39:35 PM PDT 24 20089050 ps
T717 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3792309056 Apr 15 12:39:27 PM PDT 24 Apr 15 12:39:38 PM PDT 24 1638382291 ps
T718 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2289975193 Apr 15 12:39:19 PM PDT 24 Apr 15 12:39:21 PM PDT 24 144537663 ps
T719 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.88256853 Apr 15 12:39:22 PM PDT 24 Apr 15 12:39:31 PM PDT 24 386396236 ps
T720 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1403208942 Apr 15 12:39:35 PM PDT 24 Apr 15 12:39:40 PM PDT 24 651615383 ps
T721 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1714413636 Apr 15 12:39:24 PM PDT 24 Apr 15 12:39:30 PM PDT 24 180596122 ps
T722 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2308440073 Apr 15 12:39:24 PM PDT 24 Apr 15 12:39:28 PM PDT 24 32998223 ps
T723 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3209349570 Apr 15 12:39:28 PM PDT 24 Apr 15 12:39:31 PM PDT 24 83492387 ps
T724 /workspace/coverage/cover_reg_top/0.hmac_intr_test.3025700653 Apr 15 12:39:24 PM PDT 24 Apr 15 12:39:28 PM PDT 24 13012239 ps
T725 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1113513943 Apr 15 12:39:25 PM PDT 24 Apr 15 12:39:29 PM PDT 24 35773137 ps
T726 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1742876570 Apr 15 12:39:27 PM PDT 24 Apr 15 12:39:31 PM PDT 24 56605705 ps
T727 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2025416747 Apr 15 12:39:15 PM PDT 24 Apr 15 12:39:27 PM PDT 24 2798173245 ps
T728 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.4275298841 Apr 15 12:39:26 PM PDT 24 Apr 15 12:39:31 PM PDT 24 186396042 ps
T729 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2830876074 Apr 15 12:39:35 PM PDT 24 Apr 15 12:39:37 PM PDT 24 49819102 ps
T730 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.4074309367 Apr 15 12:39:24 PM PDT 24 Apr 15 12:39:31 PM PDT 24 721037904 ps
T731 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1335781697 Apr 15 12:39:27 PM PDT 24 Apr 15 12:39:30 PM PDT 24 69560022 ps
T732 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.663583507 Apr 15 12:39:26 PM PDT 24 Apr 15 12:39:31 PM PDT 24 79930316 ps
T733 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3949718498 Apr 15 12:39:25 PM PDT 24 Apr 15 12:39:29 PM PDT 24 41078422 ps

Test location /workspace/coverage/default/53.hmac_stress_all_with_rand_reset.3428706212
Short name T5
Test name
Test status
Simulation time 53234264579 ps
CPU time 2424.86 seconds
Started Apr 15 02:24:42 PM PDT 24
Finished Apr 15 03:05:08 PM PDT 24
Peak memory 216128 kb
Host smart-857d8a9e-bf0c-4156-9cf3-8f8477eb6598
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3428706212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.hmac_stress_all_with_rand_reset.3428706212
Directory /workspace/53.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.839540873
Short name T25
Test name
Test status
Simulation time 5800501303 ps
CPU time 11.64 seconds
Started Apr 15 02:22:32 PM PDT 24
Finished Apr 15 02:22:44 PM PDT 24
Peak memory 199704 kb
Host smart-f3ae59c4-aaeb-4d8b-b92c-a4da9db8ebf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839540873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.839540873
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3562266807
Short name T30
Test name
Test status
Simulation time 57056249 ps
CPU time 0.89 seconds
Started Apr 15 02:21:40 PM PDT 24
Finished Apr 15 02:21:44 PM PDT 24
Peak memory 218192 kb
Host smart-ffa02ddb-bef1-4adf-89f8-52826b9acf1c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562266807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3562266807
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/41.hmac_stress_all_with_rand_reset.600140445
Short name T65
Test name
Test status
Simulation time 52430514766 ps
CPU time 2443.64 seconds
Started Apr 15 02:24:04 PM PDT 24
Finished Apr 15 03:04:48 PM PDT 24
Peak memory 257124 kb
Host smart-4597d46f-a830-4a5d-9b43-2b769ebc4327
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=600140445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all_with_rand_reset.600140445
Directory /workspace/41.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.hmac_stress_all_with_rand_reset.2839894621
Short name T22
Test name
Test status
Simulation time 22969223507 ps
CPU time 721.7 seconds
Started Apr 15 02:25:07 PM PDT 24
Finished Apr 15 02:37:10 PM PDT 24
Peak memory 216128 kb
Host smart-17ee7997-1a14-41e8-a8f4-0479177f953d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2839894621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.hmac_stress_all_with_rand_reset.2839894621
Directory /workspace/120.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2194553608
Short name T61
Test name
Test status
Simulation time 195450860 ps
CPU time 3.35 seconds
Started Apr 15 12:39:34 PM PDT 24
Finished Apr 15 12:39:39 PM PDT 24
Peak memory 199088 kb
Host smart-0f8aa8c2-6fd7-4e2b-8693-b801c3d55b3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194553608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2194553608
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/31.hmac_alert_test.805997225
Short name T78
Test name
Test status
Simulation time 19703666 ps
CPU time 0.55 seconds
Started Apr 15 02:23:24 PM PDT 24
Finished Apr 15 02:23:25 PM PDT 24
Peak memory 195064 kb
Host smart-0814ee26-b48c-47c9-a59b-a3b4987858b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805997225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.805997225
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3563467181
Short name T95
Test name
Test status
Simulation time 18183348 ps
CPU time 0.93 seconds
Started Apr 15 12:39:36 PM PDT 24
Finished Apr 15 12:39:39 PM PDT 24
Peak memory 198452 kb
Host smart-85b725d7-ff5d-4fdd-844e-4b1a714ba5e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563467181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3563467181
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/default/43.hmac_error.3626035476
Short name T265
Test name
Test status
Simulation time 39634893276 ps
CPU time 195.73 seconds
Started Apr 15 02:24:10 PM PDT 24
Finished Apr 15 02:27:26 PM PDT 24
Peak memory 199732 kb
Host smart-ffcc9253-b3cb-48e7-a941-40dec18eab62
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626035476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3626035476
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_error.2721131994
Short name T41
Test name
Test status
Simulation time 882739108 ps
CPU time 46.43 seconds
Started Apr 15 02:23:38 PM PDT 24
Finished Apr 15 02:24:26 PM PDT 24
Peak memory 199536 kb
Host smart-dae1cee0-6634-4422-b468-5ddcab607810
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721131994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2721131994
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2761356597
Short name T117
Test name
Test status
Simulation time 1186409640 ps
CPU time 3.11 seconds
Started Apr 15 12:39:36 PM PDT 24
Finished Apr 15 12:39:40 PM PDT 24
Peak memory 198988 kb
Host smart-664363b2-658a-47f8-b2e0-71dc1688f272
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761356597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2761356597
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2325473263
Short name T110
Test name
Test status
Simulation time 260002903 ps
CPU time 4.26 seconds
Started Apr 15 12:39:34 PM PDT 24
Finished Apr 15 12:39:39 PM PDT 24
Peak memory 199068 kb
Host smart-4cd312bd-b3a6-4073-877a-ed155e923210
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325473263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2325473263
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3457865808
Short name T68
Test name
Test status
Simulation time 152999833928 ps
CPU time 1839.12 seconds
Started Apr 15 02:22:06 PM PDT 24
Finished Apr 15 02:52:46 PM PDT 24
Peak memory 232504 kb
Host smart-3b1f4d88-957e-47be-a711-2825cadd16ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457865808 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3457865808
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_error.379442389
Short name T494
Test name
Test status
Simulation time 9809133535 ps
CPU time 54.51 seconds
Started Apr 15 02:22:46 PM PDT 24
Finished Apr 15 02:23:42 PM PDT 24
Peak memory 199672 kb
Host smart-a87fd997-1916-4e00-8620-0219de673f63
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379442389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.379442389
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1641766024
Short name T100
Test name
Test status
Simulation time 465919076 ps
CPU time 8.4 seconds
Started Apr 15 12:39:28 PM PDT 24
Finished Apr 15 12:39:39 PM PDT 24
Peak memory 198456 kb
Host smart-7d30b63e-72e5-4658-a464-89c36b16f922
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641766024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1641766024
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2025416747
Short name T727
Test name
Test status
Simulation time 2798173245 ps
CPU time 11.14 seconds
Started Apr 15 12:39:15 PM PDT 24
Finished Apr 15 12:39:27 PM PDT 24
Peak memory 198136 kb
Host smart-6525cfa8-157b-4de6-b04c-a27c7f051c33
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025416747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2025416747
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1629480415
Short name T97
Test name
Test status
Simulation time 261516066 ps
CPU time 0.96 seconds
Started Apr 15 12:39:21 PM PDT 24
Finished Apr 15 12:39:23 PM PDT 24
Peak memory 198204 kb
Host smart-da8ac219-4737-4d08-8ca0-934e398a0f72
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629480415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1629480415
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1707684878
Short name T679
Test name
Test status
Simulation time 187323279 ps
CPU time 2.11 seconds
Started Apr 15 12:39:20 PM PDT 24
Finished Apr 15 12:39:23 PM PDT 24
Peak memory 199104 kb
Host smart-0541be1c-73bb-4985-9b28-3a057a2aa48b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707684878 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1707684878
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.598752557
Short name T639
Test name
Test status
Simulation time 203332121 ps
CPU time 0.7 seconds
Started Apr 15 12:39:31 PM PDT 24
Finished Apr 15 12:39:33 PM PDT 24
Peak memory 196416 kb
Host smart-f38ed3b4-477f-4319-92a1-8cf6e1419ab0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598752557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.598752557
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.3025700653
Short name T724
Test name
Test status
Simulation time 13012239 ps
CPU time 0.55 seconds
Started Apr 15 12:39:24 PM PDT 24
Finished Apr 15 12:39:28 PM PDT 24
Peak memory 193712 kb
Host smart-c902d874-dadf-45da-a20b-a8693dad307a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025700653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3025700653
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2559051766
Short name T700
Test name
Test status
Simulation time 62094779 ps
CPU time 1.5 seconds
Started Apr 15 12:39:26 PM PDT 24
Finished Apr 15 12:39:31 PM PDT 24
Peak memory 198796 kb
Host smart-10b89736-9ebc-492f-973a-aa6c3e688dbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559051766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2559051766
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.559383755
Short name T674
Test name
Test status
Simulation time 147938315 ps
CPU time 2.05 seconds
Started Apr 15 12:39:23 PM PDT 24
Finished Apr 15 12:39:28 PM PDT 24
Peak memory 199056 kb
Host smart-ebf55683-cc5e-4236-9590-c5e31308abe6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559383755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.559383755
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2751383172
Short name T670
Test name
Test status
Simulation time 98727736 ps
CPU time 1.96 seconds
Started Apr 15 12:39:19 PM PDT 24
Finished Apr 15 12:39:22 PM PDT 24
Peak memory 199056 kb
Host smart-7262931c-8826-4858-a3e9-abe6c80f6da0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751383172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2751383172
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3792309056
Short name T717
Test name
Test status
Simulation time 1638382291 ps
CPU time 8.11 seconds
Started Apr 15 12:39:27 PM PDT 24
Finished Apr 15 12:39:38 PM PDT 24
Peak memory 198148 kb
Host smart-bc3dbc57-bf0e-4711-ac0f-bbb7964d4c53
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792309056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3792309056
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1489565585
Short name T98
Test name
Test status
Simulation time 632342241 ps
CPU time 14.63 seconds
Started Apr 15 12:39:21 PM PDT 24
Finished Apr 15 12:39:37 PM PDT 24
Peak memory 198916 kb
Host smart-597d398c-bb0c-4169-b194-f7e82d2a8314
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489565585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1489565585
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3132530038
Short name T104
Test name
Test status
Simulation time 152293319 ps
CPU time 0.94 seconds
Started Apr 15 12:39:27 PM PDT 24
Finished Apr 15 12:39:31 PM PDT 24
Peak memory 198580 kb
Host smart-024adb7b-f658-4239-ab55-46db5dbf8881
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132530038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3132530038
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2177944202
Short name T610
Test name
Test status
Simulation time 165649840667 ps
CPU time 261.99 seconds
Started Apr 15 12:39:24 PM PDT 24
Finished Apr 15 12:43:50 PM PDT 24
Peak memory 215588 kb
Host smart-74edf00f-2ebf-4eee-b9ed-5b400c2bbdf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177944202 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2177944202
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2202804419
Short name T683
Test name
Test status
Simulation time 59866421 ps
CPU time 0.94 seconds
Started Apr 15 12:39:25 PM PDT 24
Finished Apr 15 12:39:29 PM PDT 24
Peak memory 198392 kb
Host smart-0c23a978-53df-4715-a3f1-0e07982fcdbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202804419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2202804419
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1470656364
Short name T676
Test name
Test status
Simulation time 19747547 ps
CPU time 0.59 seconds
Started Apr 15 12:39:22 PM PDT 24
Finished Apr 15 12:39:25 PM PDT 24
Peak memory 193708 kb
Host smart-2f40de9a-b43b-4670-9b11-ab0e098aabba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470656364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1470656364
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2936766488
Short name T648
Test name
Test status
Simulation time 43800953 ps
CPU time 1.1 seconds
Started Apr 15 12:39:23 PM PDT 24
Finished Apr 15 12:39:27 PM PDT 24
Peak memory 198960 kb
Host smart-73cf0ba3-a8bd-4d22-a0fb-dedfc58e9f08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936766488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2936766488
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.849192866
Short name T620
Test name
Test status
Simulation time 178594843 ps
CPU time 4.03 seconds
Started Apr 15 12:39:33 PM PDT 24
Finished Apr 15 12:39:38 PM PDT 24
Peak memory 199124 kb
Host smart-f6cf99f9-4b55-45af-a635-6f89d7c4c8da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849192866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.849192866
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3665720687
Short name T600
Test name
Test status
Simulation time 175944687 ps
CPU time 2.4 seconds
Started Apr 15 12:40:48 PM PDT 24
Finished Apr 15 12:40:51 PM PDT 24
Peak memory 198880 kb
Host smart-4634d32d-806b-45c3-80bc-43f96786b7fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665720687 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3665720687
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.4021999851
Short name T688
Test name
Test status
Simulation time 29952345 ps
CPU time 0.92 seconds
Started Apr 15 12:39:21 PM PDT 24
Finished Apr 15 12:39:24 PM PDT 24
Peak memory 198060 kb
Host smart-1e4152ec-cf77-404d-a074-41224919dbe5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021999851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.4021999851
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.2490275394
Short name T686
Test name
Test status
Simulation time 42602654 ps
CPU time 0.6 seconds
Started Apr 15 12:39:35 PM PDT 24
Finished Apr 15 12:39:37 PM PDT 24
Peak memory 193736 kb
Host smart-4ae69694-c479-4398-bb78-6c66e5a8731b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490275394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2490275394
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.698714822
Short name T609
Test name
Test status
Simulation time 47508264 ps
CPU time 2.07 seconds
Started Apr 15 12:39:30 PM PDT 24
Finished Apr 15 12:39:34 PM PDT 24
Peak memory 198724 kb
Host smart-22d4c35c-d9c7-4eb5-befd-b51d081cf206
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698714822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr
_outstanding.698714822
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2343710241
Short name T664
Test name
Test status
Simulation time 48649322 ps
CPU time 2.57 seconds
Started Apr 15 12:40:49 PM PDT 24
Finished Apr 15 12:40:52 PM PDT 24
Peak memory 198884 kb
Host smart-824e9aa6-7a88-432a-b6f2-98dd312536cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343710241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2343710241
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3511423065
Short name T633
Test name
Test status
Simulation time 795886932 ps
CPU time 2.9 seconds
Started Apr 15 12:40:24 PM PDT 24
Finished Apr 15 12:40:28 PM PDT 24
Peak memory 197360 kb
Host smart-779d3fc1-58b3-49c6-b24c-15e19c8bb1c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511423065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3511423065
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.262530695
Short name T651
Test name
Test status
Simulation time 33737877 ps
CPU time 1.16 seconds
Started Apr 15 12:39:34 PM PDT 24
Finished Apr 15 12:39:37 PM PDT 24
Peak memory 198984 kb
Host smart-1f4b1772-fe47-4df7-9bb7-d71dc386b4f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262530695 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.262530695
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.3244974394
Short name T675
Test name
Test status
Simulation time 47765906 ps
CPU time 0.58 seconds
Started Apr 15 12:39:24 PM PDT 24
Finished Apr 15 12:39:27 PM PDT 24
Peak memory 193664 kb
Host smart-d28ef7cd-b74d-4fb1-b631-e575555cca98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244974394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3244974394
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3822012335
Short name T641
Test name
Test status
Simulation time 47067491 ps
CPU time 2.39 seconds
Started Apr 15 12:39:34 PM PDT 24
Finished Apr 15 12:39:38 PM PDT 24
Peak memory 198800 kb
Host smart-91d80fcd-fec7-4f4b-a407-965954319149
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822012335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3822012335
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3493480353
Short name T682
Test name
Test status
Simulation time 127839470 ps
CPU time 3.47 seconds
Started Apr 15 12:39:31 PM PDT 24
Finished Apr 15 12:39:36 PM PDT 24
Peak memory 199132 kb
Host smart-72db3e7f-d9a3-4596-993b-ff8fda067e19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493480353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3493480353
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2140227116
Short name T645
Test name
Test status
Simulation time 104392162 ps
CPU time 2.34 seconds
Started Apr 15 12:39:23 PM PDT 24
Finished Apr 15 12:39:27 PM PDT 24
Peak memory 199152 kb
Host smart-e33d4b47-34cb-4ef6-bd49-460e3f600c9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140227116 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.2140227116
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1926068308
Short name T614
Test name
Test status
Simulation time 40087614 ps
CPU time 0.97 seconds
Started Apr 15 12:39:37 PM PDT 24
Finished Apr 15 12:39:39 PM PDT 24
Peak memory 197988 kb
Host smart-12da3e89-3141-4669-bf52-f7a5d7b44a76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926068308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1926068308
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2912686339
Short name T617
Test name
Test status
Simulation time 129234192 ps
CPU time 0.61 seconds
Started Apr 15 12:39:31 PM PDT 24
Finished Apr 15 12:39:33 PM PDT 24
Peak memory 193688 kb
Host smart-e91f6e38-6b71-4879-aa64-1620ee4b3832
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912686339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2912686339
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.663583507
Short name T732
Test name
Test status
Simulation time 79930316 ps
CPU time 1.67 seconds
Started Apr 15 12:39:26 PM PDT 24
Finished Apr 15 12:39:31 PM PDT 24
Peak memory 198704 kb
Host smart-11355f3e-230b-4d5c-a98d-e46f5b0fd835
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663583507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.663583507
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3868163481
Short name T629
Test name
Test status
Simulation time 111053754 ps
CPU time 2.95 seconds
Started Apr 15 12:39:27 PM PDT 24
Finished Apr 15 12:39:33 PM PDT 24
Peak memory 199140 kb
Host smart-1137342d-9305-4c6b-8b5c-ed340a66f096
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868163481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3868163481
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3449476529
Short name T60
Test name
Test status
Simulation time 242660065 ps
CPU time 4.45 seconds
Started Apr 15 12:39:37 PM PDT 24
Finished Apr 15 12:39:43 PM PDT 24
Peak memory 198976 kb
Host smart-ec4a2125-0faf-4b50-ac63-518b19f2b14d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449476529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3449476529
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.275980198
Short name T660
Test name
Test status
Simulation time 139178334 ps
CPU time 1.29 seconds
Started Apr 15 12:39:30 PM PDT 24
Finished Apr 15 12:39:33 PM PDT 24
Peak memory 199128 kb
Host smart-1c3ef4be-4d48-44b2-abae-538235fc5bd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275980198 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.275980198
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2719520789
Short name T101
Test name
Test status
Simulation time 28933321 ps
CPU time 0.82 seconds
Started Apr 15 12:39:23 PM PDT 24
Finished Apr 15 12:39:27 PM PDT 24
Peak memory 197892 kb
Host smart-9cf21427-f746-4b71-8b7a-7e69c6d056f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719520789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2719520789
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.955690596
Short name T681
Test name
Test status
Simulation time 30889299 ps
CPU time 0.6 seconds
Started Apr 15 12:39:30 PM PDT 24
Finished Apr 15 12:39:33 PM PDT 24
Peak memory 193688 kb
Host smart-1e4eb8a2-582a-4a09-a8de-42ce8f6a9849
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955690596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.955690596
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3509838883
Short name T657
Test name
Test status
Simulation time 144495157 ps
CPU time 2.07 seconds
Started Apr 15 12:39:30 PM PDT 24
Finished Apr 15 12:39:34 PM PDT 24
Peak memory 199068 kb
Host smart-e0afb1d6-c13c-4fdd-acd2-7c2875bf89d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509838883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3509838883
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.148518189
Short name T643
Test name
Test status
Simulation time 37903561 ps
CPU time 2.09 seconds
Started Apr 15 12:39:25 PM PDT 24
Finished Apr 15 12:39:31 PM PDT 24
Peak memory 199100 kb
Host smart-6e78218e-c52c-46cd-af24-7c89908b2415
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148518189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.148518189
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2691638610
Short name T671
Test name
Test status
Simulation time 182054000 ps
CPU time 3.17 seconds
Started Apr 15 12:39:34 PM PDT 24
Finished Apr 15 12:39:38 PM PDT 24
Peak memory 199060 kb
Host smart-33e31950-f36c-4d68-8f66-0feb13e5d0e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691638610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2691638610
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1996689562
Short name T62
Test name
Test status
Simulation time 441561194 ps
CPU time 2.44 seconds
Started Apr 15 12:39:33 PM PDT 24
Finished Apr 15 12:39:37 PM PDT 24
Peak memory 199100 kb
Host smart-514b466a-86cb-4eba-91c7-0cc751dbc4c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996689562 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1996689562
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3737704640
Short name T708
Test name
Test status
Simulation time 49666368 ps
CPU time 0.91 seconds
Started Apr 15 12:39:26 PM PDT 24
Finished Apr 15 12:39:30 PM PDT 24
Peak memory 197940 kb
Host smart-c79891c6-d6b2-48d0-89c9-269d3a4f7ed6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737704640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3737704640
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.867998194
Short name T623
Test name
Test status
Simulation time 33660577 ps
CPU time 0.53 seconds
Started Apr 15 12:39:23 PM PDT 24
Finished Apr 15 12:39:26 PM PDT 24
Peak memory 193632 kb
Host smart-7e92d15d-5f09-4bc5-bb04-57145032d1c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867998194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.867998194
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.4275298841
Short name T728
Test name
Test status
Simulation time 186396042 ps
CPU time 2.15 seconds
Started Apr 15 12:39:26 PM PDT 24
Finished Apr 15 12:39:31 PM PDT 24
Peak memory 199028 kb
Host smart-68262396-db34-488b-a31b-e52d1c12394c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275298841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.4275298841
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.998742728
Short name T613
Test name
Test status
Simulation time 580298800 ps
CPU time 2.54 seconds
Started Apr 15 12:39:24 PM PDT 24
Finished Apr 15 12:39:30 PM PDT 24
Peak memory 199100 kb
Host smart-7d574766-3400-4191-92a7-c6cc532e4a08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998742728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.998742728
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3939118699
Short name T115
Test name
Test status
Simulation time 190085541 ps
CPU time 1.97 seconds
Started Apr 15 12:39:21 PM PDT 24
Finished Apr 15 12:39:25 PM PDT 24
Peak memory 199112 kb
Host smart-31220619-bad7-4b21-a290-91972e8e4bb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939118699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3939118699
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3949718498
Short name T733
Test name
Test status
Simulation time 41078422 ps
CPU time 1.15 seconds
Started Apr 15 12:39:25 PM PDT 24
Finished Apr 15 12:39:29 PM PDT 24
Peak memory 198980 kb
Host smart-bd654382-8c7a-4ac9-b158-358ce81527f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949718498 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.3949718498
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1049004585
Short name T687
Test name
Test status
Simulation time 23030096 ps
CPU time 0.82 seconds
Started Apr 15 12:39:34 PM PDT 24
Finished Apr 15 12:39:37 PM PDT 24
Peak memory 198324 kb
Host smart-52b708e5-3525-4565-8537-c524a595e8b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049004585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1049004585
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1406654717
Short name T665
Test name
Test status
Simulation time 71502115 ps
CPU time 0.59 seconds
Started Apr 15 12:39:29 PM PDT 24
Finished Apr 15 12:39:32 PM PDT 24
Peak memory 193920 kb
Host smart-7f91ddb2-a62d-47ec-986a-ba84ddd1ae26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406654717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1406654717
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2526141335
Short name T615
Test name
Test status
Simulation time 2129902625 ps
CPU time 2.24 seconds
Started Apr 15 12:39:28 PM PDT 24
Finished Apr 15 12:39:32 PM PDT 24
Peak memory 199100 kb
Host smart-908a5d12-4b1a-497d-bf1f-1325bc2a588f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526141335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2526141335
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1772036917
Short name T662
Test name
Test status
Simulation time 149661914 ps
CPU time 1.19 seconds
Started Apr 15 12:39:32 PM PDT 24
Finished Apr 15 12:39:35 PM PDT 24
Peak memory 199108 kb
Host smart-81b9d384-0b4f-46f3-b973-f0d4a90382c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772036917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1772036917
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.4253611908
Short name T111
Test name
Test status
Simulation time 180494331 ps
CPU time 2.91 seconds
Started Apr 15 12:39:34 PM PDT 24
Finished Apr 15 12:39:39 PM PDT 24
Peak memory 199104 kb
Host smart-e88b2162-1eb4-42ac-981c-524b526ffc77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253611908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.4253611908
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2010016916
Short name T644
Test name
Test status
Simulation time 73276268 ps
CPU time 1.26 seconds
Started Apr 15 12:39:24 PM PDT 24
Finished Apr 15 12:39:29 PM PDT 24
Peak memory 198900 kb
Host smart-81d6337b-3e1f-41d5-a215-e7f9e39636df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010016916 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2010016916
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2602443385
Short name T673
Test name
Test status
Simulation time 29553448 ps
CPU time 0.89 seconds
Started Apr 15 12:39:30 PM PDT 24
Finished Apr 15 12:39:33 PM PDT 24
Peak memory 198292 kb
Host smart-30535ee5-416f-4fe3-a582-e6f614b16785
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602443385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2602443385
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.1308144086
Short name T696
Test name
Test status
Simulation time 13717753 ps
CPU time 0.61 seconds
Started Apr 15 12:39:27 PM PDT 24
Finished Apr 15 12:39:30 PM PDT 24
Peak memory 193744 kb
Host smart-2ceae88a-0d3b-49d3-8665-f7f308af870f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308144086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1308144086
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2218147674
Short name T685
Test name
Test status
Simulation time 1697428666 ps
CPU time 2.22 seconds
Started Apr 15 12:39:49 PM PDT 24
Finished Apr 15 12:39:52 PM PDT 24
Peak memory 198760 kb
Host smart-fc674ee5-bfae-40f8-a906-ca53f205070f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218147674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.2218147674
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2635194992
Short name T606
Test name
Test status
Simulation time 36205416 ps
CPU time 2.02 seconds
Started Apr 15 12:39:27 PM PDT 24
Finished Apr 15 12:39:32 PM PDT 24
Peak memory 199072 kb
Host smart-e285c4cd-f5f5-41e1-8f06-8d39b7d4c555
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635194992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2635194992
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2476361415
Short name T636
Test name
Test status
Simulation time 54132859 ps
CPU time 2.05 seconds
Started Apr 15 12:39:29 PM PDT 24
Finished Apr 15 12:39:34 PM PDT 24
Peak memory 199120 kb
Host smart-642221cd-cc41-4b77-a9f0-0c4fc4193161
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476361415 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2476361415
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1821088892
Short name T712
Test name
Test status
Simulation time 27198706 ps
CPU time 0.83 seconds
Started Apr 15 12:39:23 PM PDT 24
Finished Apr 15 12:39:26 PM PDT 24
Peak memory 198808 kb
Host smart-9a57408f-238f-470e-b26e-6676873e4e1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821088892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1821088892
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.970668358
Short name T691
Test name
Test status
Simulation time 23268034 ps
CPU time 0.58 seconds
Started Apr 15 12:39:28 PM PDT 24
Finished Apr 15 12:39:31 PM PDT 24
Peak memory 193716 kb
Host smart-ac52555c-f53a-4030-bc50-7eaa7c8caebb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970668358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.970668358
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4115504715
Short name T669
Test name
Test status
Simulation time 161449960 ps
CPU time 2.55 seconds
Started Apr 15 12:39:30 PM PDT 24
Finished Apr 15 12:39:34 PM PDT 24
Peak memory 198832 kb
Host smart-a22ece34-89d4-485e-8c27-cb7316d8fb32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115504715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.4115504715
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.4074309367
Short name T730
Test name
Test status
Simulation time 721037904 ps
CPU time 3.97 seconds
Started Apr 15 12:39:24 PM PDT 24
Finished Apr 15 12:39:31 PM PDT 24
Peak memory 199148 kb
Host smart-78abb46c-dc1e-44f1-8270-6c3427606ab1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074309367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.4074309367
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2310969894
Short name T649
Test name
Test status
Simulation time 466299772 ps
CPU time 4.2 seconds
Started Apr 15 12:39:35 PM PDT 24
Finished Apr 15 12:39:41 PM PDT 24
Peak memory 199060 kb
Host smart-93e742a5-4320-47ae-be3d-1d5c3fc5fdb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310969894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2310969894
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.222991790
Short name T64
Test name
Test status
Simulation time 44509244340 ps
CPU time 128.88 seconds
Started Apr 15 12:39:31 PM PDT 24
Finished Apr 15 12:41:42 PM PDT 24
Peak memory 215536 kb
Host smart-6e396d0c-2441-48b2-9f5b-65045f9cf0fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222991790 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.222991790
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3394543722
Short name T99
Test name
Test status
Simulation time 47304904 ps
CPU time 0.77 seconds
Started Apr 15 12:39:30 PM PDT 24
Finished Apr 15 12:39:33 PM PDT 24
Peak memory 198132 kb
Host smart-3d65a3f1-318d-4d64-9222-530a5d7878f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394543722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3394543722
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3346571899
Short name T697
Test name
Test status
Simulation time 18087905 ps
CPU time 0.61 seconds
Started Apr 15 12:39:42 PM PDT 24
Finished Apr 15 12:39:43 PM PDT 24
Peak memory 193668 kb
Host smart-e6dbc85a-74d6-49c3-b6cf-dc942ad2c7e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346571899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3346571899
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1985959743
Short name T642
Test name
Test status
Simulation time 484878343 ps
CPU time 2.31 seconds
Started Apr 15 12:39:26 PM PDT 24
Finished Apr 15 12:39:31 PM PDT 24
Peak memory 198876 kb
Host smart-14553078-181a-41cb-9dd4-59ebed5fd825
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985959743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.1985959743
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2084560099
Short name T680
Test name
Test status
Simulation time 270957243 ps
CPU time 3.21 seconds
Started Apr 15 12:39:34 PM PDT 24
Finished Apr 15 12:39:38 PM PDT 24
Peak memory 199172 kb
Host smart-4a4aaba7-28e0-4e7f-b3b3-3fbb5a38c338
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084560099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2084560099
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3338183101
Short name T112
Test name
Test status
Simulation time 97731225 ps
CPU time 1.84 seconds
Started Apr 15 12:39:30 PM PDT 24
Finished Apr 15 12:39:34 PM PDT 24
Peak memory 198980 kb
Host smart-58dd0da8-5059-4a37-a264-ad823806a19d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338183101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3338183101
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1113513943
Short name T725
Test name
Test status
Simulation time 35773137 ps
CPU time 1.18 seconds
Started Apr 15 12:39:25 PM PDT 24
Finished Apr 15 12:39:29 PM PDT 24
Peak memory 198964 kb
Host smart-9ffa9836-9905-4442-9ba1-7fa7a6e9d6ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113513943 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1113513943
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.660850172
Short name T646
Test name
Test status
Simulation time 41013194 ps
CPU time 0.84 seconds
Started Apr 15 12:39:33 PM PDT 24
Finished Apr 15 12:39:35 PM PDT 24
Peak memory 197772 kb
Host smart-861f7e04-5ace-40f2-8891-774aa3339160
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660850172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.660850172
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1234593481
Short name T715
Test name
Test status
Simulation time 41457235 ps
CPU time 0.57 seconds
Started Apr 15 12:39:25 PM PDT 24
Finished Apr 15 12:39:28 PM PDT 24
Peak memory 193900 kb
Host smart-7f577563-97b5-4674-907c-8e03790a5472
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234593481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1234593481
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.46929588
Short name T678
Test name
Test status
Simulation time 24440681 ps
CPU time 1.11 seconds
Started Apr 15 12:39:35 PM PDT 24
Finished Apr 15 12:39:37 PM PDT 24
Peak memory 198992 kb
Host smart-7d4b195a-6823-49e9-b710-fb60c0156050
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46929588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr_
outstanding.46929588
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1032880483
Short name T632
Test name
Test status
Simulation time 1069603536 ps
CPU time 4.06 seconds
Started Apr 15 12:39:29 PM PDT 24
Finished Apr 15 12:39:35 PM PDT 24
Peak memory 199132 kb
Host smart-7f7826fa-9301-4265-b568-1dd32a21fed1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032880483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1032880483
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.4193628724
Short name T118
Test name
Test status
Simulation time 231612307 ps
CPU time 4.1 seconds
Started Apr 15 12:39:34 PM PDT 24
Finished Apr 15 12:39:39 PM PDT 24
Peak memory 199056 kb
Host smart-99463b0b-0be3-47da-b15d-8cc64df9e1b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193628724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.4193628724
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.88256853
Short name T719
Test name
Test status
Simulation time 386396236 ps
CPU time 6.28 seconds
Started Apr 15 12:39:22 PM PDT 24
Finished Apr 15 12:39:31 PM PDT 24
Peak memory 198476 kb
Host smart-9556a19c-42e3-41aa-9397-a07d0a480e8b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88256853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.88256853
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2007682201
Short name T103
Test name
Test status
Simulation time 2031538672 ps
CPU time 12.95 seconds
Started Apr 15 12:39:26 PM PDT 24
Finished Apr 15 12:39:42 PM PDT 24
Peak memory 197492 kb
Host smart-28731c72-576b-4c8a-a53e-864e29050191
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007682201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2007682201
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3514012822
Short name T690
Test name
Test status
Simulation time 146565765 ps
CPU time 0.89 seconds
Started Apr 15 12:39:23 PM PDT 24
Finished Apr 15 12:39:26 PM PDT 24
Peak memory 197720 kb
Host smart-5772cd41-df8d-48c3-a264-babb9e06f24d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514012822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3514012822
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3426275831
Short name T640
Test name
Test status
Simulation time 86918936 ps
CPU time 1.49 seconds
Started Apr 15 12:39:20 PM PDT 24
Finished Apr 15 12:39:22 PM PDT 24
Peak memory 199088 kb
Host smart-5817df97-4c25-4b64-9c80-7655114fa0b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426275831 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3426275831
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1335781697
Short name T731
Test name
Test status
Simulation time 69560022 ps
CPU time 0.67 seconds
Started Apr 15 12:39:27 PM PDT 24
Finished Apr 15 12:39:30 PM PDT 24
Peak memory 196440 kb
Host smart-9a991958-6f9d-45a7-a7ff-85403a15b7a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335781697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1335781697
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2281204572
Short name T666
Test name
Test status
Simulation time 19594472 ps
CPU time 0.62 seconds
Started Apr 15 12:39:23 PM PDT 24
Finished Apr 15 12:39:27 PM PDT 24
Peak memory 193716 kb
Host smart-b133b864-629a-4e37-9b14-782afd456ce3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281204572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2281204572
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3936863472
Short name T638
Test name
Test status
Simulation time 41491825 ps
CPU time 1.1 seconds
Started Apr 15 12:39:24 PM PDT 24
Finished Apr 15 12:39:29 PM PDT 24
Peak memory 198388 kb
Host smart-d5fca815-cadc-452a-b5df-7c654581138f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936863472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3936863472
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1508016683
Short name T659
Test name
Test status
Simulation time 45634706 ps
CPU time 1.05 seconds
Started Apr 15 12:39:28 PM PDT 24
Finished Apr 15 12:39:31 PM PDT 24
Peak memory 198900 kb
Host smart-af4a6f44-d306-42e8-987d-3e63535ac0b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508016683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1508016683
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2240553785
Short name T59
Test name
Test status
Simulation time 52128206 ps
CPU time 1.71 seconds
Started Apr 15 12:39:24 PM PDT 24
Finished Apr 15 12:39:30 PM PDT 24
Peak memory 198992 kb
Host smart-ce2656b2-f9b8-46e4-b3d6-055228c0ed46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240553785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2240553785
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.166396483
Short name T627
Test name
Test status
Simulation time 42660480 ps
CPU time 0.61 seconds
Started Apr 15 12:39:25 PM PDT 24
Finished Apr 15 12:39:29 PM PDT 24
Peak memory 193652 kb
Host smart-b3ad57ff-b80a-496a-8931-44b922b2bab4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166396483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.166396483
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3802306505
Short name T711
Test name
Test status
Simulation time 18765889 ps
CPU time 0.6 seconds
Started Apr 15 12:39:38 PM PDT 24
Finished Apr 15 12:39:40 PM PDT 24
Peak memory 193948 kb
Host smart-724040b3-54c6-43e9-8b58-3b69c820d71b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802306505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3802306505
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.2505250382
Short name T706
Test name
Test status
Simulation time 50780757 ps
CPU time 0.58 seconds
Started Apr 15 12:39:28 PM PDT 24
Finished Apr 15 12:39:31 PM PDT 24
Peak memory 193668 kb
Host smart-87011a33-5d88-46b3-8766-5cfdef4ee373
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505250382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.2505250382
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2294644286
Short name T601
Test name
Test status
Simulation time 37335639 ps
CPU time 0.62 seconds
Started Apr 15 12:39:32 PM PDT 24
Finished Apr 15 12:39:34 PM PDT 24
Peak memory 193656 kb
Host smart-2bdce518-99da-430f-9620-20e9724575a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294644286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2294644286
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.286617078
Short name T612
Test name
Test status
Simulation time 11461993 ps
CPU time 0.57 seconds
Started Apr 15 12:39:24 PM PDT 24
Finished Apr 15 12:39:28 PM PDT 24
Peak memory 193680 kb
Host smart-68b90177-ff0d-4b79-a5a0-9e5201cf563f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286617078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.286617078
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2172121452
Short name T667
Test name
Test status
Simulation time 56320061 ps
CPU time 0.61 seconds
Started Apr 15 12:39:38 PM PDT 24
Finished Apr 15 12:39:40 PM PDT 24
Peak memory 193736 kb
Host smart-a58e7600-3f69-40f5-840b-a7ea0a76e04a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172121452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2172121452
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.2251307072
Short name T692
Test name
Test status
Simulation time 22164865 ps
CPU time 0.6 seconds
Started Apr 15 12:39:35 PM PDT 24
Finished Apr 15 12:39:37 PM PDT 24
Peak memory 193940 kb
Host smart-ef4fe070-c3b6-49cc-a7e8-01146192cd1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251307072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2251307072
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2888469021
Short name T709
Test name
Test status
Simulation time 47155853 ps
CPU time 0.58 seconds
Started Apr 15 12:39:34 PM PDT 24
Finished Apr 15 12:39:35 PM PDT 24
Peak memory 193676 kb
Host smart-07a4f833-f6d3-4bcf-9e1b-4bae554d8bf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888469021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2888469021
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2830876074
Short name T729
Test name
Test status
Simulation time 49819102 ps
CPU time 0.62 seconds
Started Apr 15 12:39:35 PM PDT 24
Finished Apr 15 12:39:37 PM PDT 24
Peak memory 193936 kb
Host smart-d43de721-c1ff-4e33-877c-704706caa708
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830876074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2830876074
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3553715236
Short name T625
Test name
Test status
Simulation time 16380480 ps
CPU time 0.56 seconds
Started Apr 15 12:39:25 PM PDT 24
Finished Apr 15 12:39:29 PM PDT 24
Peak memory 193628 kb
Host smart-1d7d9750-04ce-4beb-9ebd-65e66e6c556b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553715236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3553715236
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3860241830
Short name T96
Test name
Test status
Simulation time 2292786426 ps
CPU time 8.57 seconds
Started Apr 15 12:39:29 PM PDT 24
Finished Apr 15 12:39:40 PM PDT 24
Peak memory 198832 kb
Host smart-8498f7ad-0608-40a1-97c3-310f190e9508
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860241830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3860241830
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2804900378
Short name T105
Test name
Test status
Simulation time 111993982 ps
CPU time 5.17 seconds
Started Apr 15 12:39:20 PM PDT 24
Finished Apr 15 12:39:26 PM PDT 24
Peak memory 198924 kb
Host smart-5937259a-9aed-44de-88da-480c29da7bca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804900378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2804900378
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1490100670
Short name T668
Test name
Test status
Simulation time 103737413 ps
CPU time 0.87 seconds
Started Apr 15 12:39:26 PM PDT 24
Finished Apr 15 12:39:30 PM PDT 24
Peak memory 198140 kb
Host smart-6682f278-5e12-4127-9dd5-cfb7cf3ac83f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490100670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1490100670
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.383955961
Short name T628
Test name
Test status
Simulation time 401768423 ps
CPU time 2.74 seconds
Started Apr 15 12:39:30 PM PDT 24
Finished Apr 15 12:39:35 PM PDT 24
Peak memory 199032 kb
Host smart-9e3aded7-e2dc-4cfd-b558-f591b085aa1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383955961 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.383955961
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2442722701
Short name T703
Test name
Test status
Simulation time 22085225 ps
CPU time 0.85 seconds
Started Apr 15 12:39:21 PM PDT 24
Finished Apr 15 12:39:24 PM PDT 24
Peak memory 198864 kb
Host smart-c6eb5dd6-cc7f-4f13-bc5c-c4085d8a3de5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442722701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2442722701
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3899047757
Short name T658
Test name
Test status
Simulation time 16138563 ps
CPU time 0.61 seconds
Started Apr 15 12:39:19 PM PDT 24
Finished Apr 15 12:39:21 PM PDT 24
Peak memory 193684 kb
Host smart-b5e1e9b5-d5b1-4d0a-b503-00e7f6673250
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899047757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3899047757
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.681163217
Short name T650
Test name
Test status
Simulation time 99509020 ps
CPU time 1.67 seconds
Started Apr 15 12:39:27 PM PDT 24
Finished Apr 15 12:39:31 PM PDT 24
Peak memory 198432 kb
Host smart-0b541371-5bcc-403a-91ad-236bae218e91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681163217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.681163217
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2308440073
Short name T722
Test name
Test status
Simulation time 32998223 ps
CPU time 1.58 seconds
Started Apr 15 12:39:24 PM PDT 24
Finished Apr 15 12:39:28 PM PDT 24
Peak memory 199132 kb
Host smart-50658d89-8aed-4cac-862f-05d74b509831
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308440073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2308440073
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1714413636
Short name T721
Test name
Test status
Simulation time 180596122 ps
CPU time 2.83 seconds
Started Apr 15 12:39:24 PM PDT 24
Finished Apr 15 12:39:30 PM PDT 24
Peak memory 199020 kb
Host smart-cd75df82-16b5-4e39-89a1-f31f43a5b48f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714413636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1714413636
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.3758889373
Short name T637
Test name
Test status
Simulation time 12860223 ps
CPU time 0.59 seconds
Started Apr 15 12:39:35 PM PDT 24
Finished Apr 15 12:39:37 PM PDT 24
Peak memory 193620 kb
Host smart-875e92f2-ade8-45cf-a551-5b8ae5fcdeac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758889373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.3758889373
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.4169448764
Short name T634
Test name
Test status
Simulation time 13261510 ps
CPU time 0.6 seconds
Started Apr 15 12:39:35 PM PDT 24
Finished Apr 15 12:39:37 PM PDT 24
Peak memory 193948 kb
Host smart-06828284-5938-4be0-afc7-be3dd27e90e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169448764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.4169448764
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3979640826
Short name T631
Test name
Test status
Simulation time 29674782 ps
CPU time 0.65 seconds
Started Apr 15 12:39:35 PM PDT 24
Finished Apr 15 12:39:37 PM PDT 24
Peak memory 193716 kb
Host smart-2b0b723d-726c-4a4e-984e-0b1072775f23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979640826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3979640826
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.1298081849
Short name T699
Test name
Test status
Simulation time 51212992 ps
CPU time 0.61 seconds
Started Apr 15 12:39:26 PM PDT 24
Finished Apr 15 12:39:30 PM PDT 24
Peak memory 193720 kb
Host smart-bcc95848-c669-4045-a2d1-cf35949cb540
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298081849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1298081849
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.337332109
Short name T603
Test name
Test status
Simulation time 30316557 ps
CPU time 0.63 seconds
Started Apr 15 12:39:38 PM PDT 24
Finished Apr 15 12:39:40 PM PDT 24
Peak memory 193864 kb
Host smart-beacb5b5-bc28-475c-bcf5-b6a81fa6a90a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337332109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.337332109
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2895854114
Short name T599
Test name
Test status
Simulation time 17084890 ps
CPU time 0.67 seconds
Started Apr 15 12:39:38 PM PDT 24
Finished Apr 15 12:39:40 PM PDT 24
Peak memory 193684 kb
Host smart-5114823b-96af-46a2-9147-571b01a0de8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895854114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2895854114
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.4229326208
Short name T611
Test name
Test status
Simulation time 41791480 ps
CPU time 0.64 seconds
Started Apr 15 12:39:27 PM PDT 24
Finished Apr 15 12:39:30 PM PDT 24
Peak memory 193600 kb
Host smart-8ca12eb6-3ad4-4bf8-b175-03dfe207d51f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229326208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.4229326208
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2190675717
Short name T713
Test name
Test status
Simulation time 12048735 ps
CPU time 0.64 seconds
Started Apr 15 12:39:31 PM PDT 24
Finished Apr 15 12:39:33 PM PDT 24
Peak memory 193700 kb
Host smart-6bcf6ee4-e515-4ab5-8666-129af9aee923
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190675717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2190675717
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2995326105
Short name T701
Test name
Test status
Simulation time 47453915 ps
CPU time 0.62 seconds
Started Apr 15 12:39:28 PM PDT 24
Finished Apr 15 12:39:31 PM PDT 24
Peak memory 193880 kb
Host smart-be7b911f-da2b-4ea5-a311-16842e0ee0db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995326105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2995326105
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1426302194
Short name T653
Test name
Test status
Simulation time 16828910 ps
CPU time 0.59 seconds
Started Apr 15 12:39:31 PM PDT 24
Finished Apr 15 12:39:34 PM PDT 24
Peak memory 193724 kb
Host smart-db6e5b31-74c2-4714-91b5-c3a1bf42e718
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426302194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1426302194
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1486369194
Short name T618
Test name
Test status
Simulation time 165520463 ps
CPU time 7.23 seconds
Started Apr 15 12:39:26 PM PDT 24
Finished Apr 15 12:39:37 PM PDT 24
Peak memory 198804 kb
Host smart-c3661172-e13e-49f8-81b5-d7d729128a29
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486369194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1486369194
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1844505969
Short name T102
Test name
Test status
Simulation time 447163268 ps
CPU time 4.99 seconds
Started Apr 15 12:39:31 PM PDT 24
Finished Apr 15 12:39:38 PM PDT 24
Peak memory 197952 kb
Host smart-5d574436-b47c-4ea6-a01d-7f30981ebdd8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844505969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1844505969
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3186176007
Short name T94
Test name
Test status
Simulation time 76087001 ps
CPU time 0.89 seconds
Started Apr 15 12:39:30 PM PDT 24
Finished Apr 15 12:39:33 PM PDT 24
Peak memory 198168 kb
Host smart-0e961d78-0cf2-44cc-bf8a-88eb00bf47c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186176007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3186176007
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1775100483
Short name T656
Test name
Test status
Simulation time 160365524 ps
CPU time 1.27 seconds
Started Apr 15 12:39:31 PM PDT 24
Finished Apr 15 12:39:34 PM PDT 24
Peak memory 198992 kb
Host smart-08335129-7acb-48e5-ac4b-96ed627526d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775100483 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1775100483
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2386225411
Short name T689
Test name
Test status
Simulation time 58129144 ps
CPU time 0.93 seconds
Started Apr 15 12:39:35 PM PDT 24
Finished Apr 15 12:39:37 PM PDT 24
Peak memory 198240 kb
Host smart-72664dfa-d97c-45c8-9be7-2bdf7b07f17a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386225411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2386225411
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.1228638955
Short name T655
Test name
Test status
Simulation time 52964966 ps
CPU time 0.55 seconds
Started Apr 15 12:39:27 PM PDT 24
Finished Apr 15 12:39:30 PM PDT 24
Peak memory 193416 kb
Host smart-ba4905a9-b449-4bf4-a867-5ad092ab76d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228638955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1228638955
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3685336905
Short name T607
Test name
Test status
Simulation time 49537326 ps
CPU time 1.13 seconds
Started Apr 15 12:39:29 PM PDT 24
Finished Apr 15 12:39:32 PM PDT 24
Peak memory 197380 kb
Host smart-cedb1802-6e65-49ea-9795-51301c1a7276
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685336905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3685336905
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1703065407
Short name T626
Test name
Test status
Simulation time 435228082 ps
CPU time 1.24 seconds
Started Apr 15 12:39:30 PM PDT 24
Finished Apr 15 12:39:34 PM PDT 24
Peak memory 198996 kb
Host smart-6c10c65c-2b5e-4a29-b221-8603a20fba86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703065407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1703065407
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.576394814
Short name T114
Test name
Test status
Simulation time 108996236 ps
CPU time 1.86 seconds
Started Apr 15 12:39:25 PM PDT 24
Finished Apr 15 12:39:31 PM PDT 24
Peak memory 199084 kb
Host smart-08b62637-332b-45ca-90d5-6fcc9c594d99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576394814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.576394814
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.2505395779
Short name T604
Test name
Test status
Simulation time 17380642 ps
CPU time 0.61 seconds
Started Apr 15 12:39:35 PM PDT 24
Finished Apr 15 12:39:37 PM PDT 24
Peak memory 193744 kb
Host smart-7d9a73f4-8a20-4805-8f99-e3350bc5983a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505395779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2505395779
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1142573802
Short name T663
Test name
Test status
Simulation time 20549888 ps
CPU time 0.57 seconds
Started Apr 15 12:39:34 PM PDT 24
Finished Apr 15 12:39:36 PM PDT 24
Peak memory 193680 kb
Host smart-7ee0d1c9-33c3-4034-b55e-bf3fdb088ed8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142573802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1142573802
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2335662812
Short name T716
Test name
Test status
Simulation time 20089050 ps
CPU time 0.66 seconds
Started Apr 15 12:39:33 PM PDT 24
Finished Apr 15 12:39:35 PM PDT 24
Peak memory 193732 kb
Host smart-0eb538d3-31a0-4555-ac90-a001828f3a7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335662812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2335662812
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3909836334
Short name T707
Test name
Test status
Simulation time 28555527 ps
CPU time 0.55 seconds
Started Apr 15 12:39:39 PM PDT 24
Finished Apr 15 12:39:40 PM PDT 24
Peak memory 193916 kb
Host smart-59376d08-a97d-470d-a83d-a8b30c57732b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909836334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3909836334
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.947450650
Short name T677
Test name
Test status
Simulation time 38407621 ps
CPU time 0.57 seconds
Started Apr 15 12:39:36 PM PDT 24
Finished Apr 15 12:39:38 PM PDT 24
Peak memory 193704 kb
Host smart-e2503929-9381-40ba-bb73-e1d26e772a1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947450650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.947450650
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3270624373
Short name T705
Test name
Test status
Simulation time 14428611 ps
CPU time 0.64 seconds
Started Apr 15 12:39:35 PM PDT 24
Finished Apr 15 12:39:37 PM PDT 24
Peak memory 193892 kb
Host smart-a699b356-aa6f-4eec-810f-0a8d855c24a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270624373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3270624373
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.856870751
Short name T654
Test name
Test status
Simulation time 19037562 ps
CPU time 0.61 seconds
Started Apr 15 12:39:30 PM PDT 24
Finished Apr 15 12:39:32 PM PDT 24
Peak memory 193912 kb
Host smart-bc401038-1993-4c30-9288-07a3439190fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856870751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.856870751
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.1324515873
Short name T619
Test name
Test status
Simulation time 11596623 ps
CPU time 0.62 seconds
Started Apr 15 12:39:35 PM PDT 24
Finished Apr 15 12:39:37 PM PDT 24
Peak memory 193712 kb
Host smart-56a2e58a-3697-43c1-938d-decc592f7975
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324515873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1324515873
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.3392437353
Short name T624
Test name
Test status
Simulation time 32824786 ps
CPU time 0.56 seconds
Started Apr 15 12:39:36 PM PDT 24
Finished Apr 15 12:39:38 PM PDT 24
Peak memory 193888 kb
Host smart-15798fdd-09ca-48d7-b5e3-2a04b2538728
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392437353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3392437353
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.388380788
Short name T698
Test name
Test status
Simulation time 18776530 ps
CPU time 0.61 seconds
Started Apr 15 12:39:33 PM PDT 24
Finished Apr 15 12:39:35 PM PDT 24
Peak memory 193916 kb
Host smart-c4d7036d-8686-48d3-b4ff-ab3f2061fdb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388380788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.388380788
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4177596099
Short name T630
Test name
Test status
Simulation time 48640625 ps
CPU time 2.93 seconds
Started Apr 15 12:39:22 PM PDT 24
Finished Apr 15 12:39:27 PM PDT 24
Peak memory 199132 kb
Host smart-dbdbb8e2-d9f2-4512-a46e-9d26441ca2fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177596099 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.4177596099
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.477301799
Short name T63
Test name
Test status
Simulation time 82142872 ps
CPU time 0.94 seconds
Started Apr 15 12:39:29 PM PDT 24
Finished Apr 15 12:39:32 PM PDT 24
Peak memory 198252 kb
Host smart-0a2ec3ae-6c31-47d0-91e8-17d1cfd9462d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477301799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.477301799
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2585916906
Short name T616
Test name
Test status
Simulation time 20062328 ps
CPU time 0.56 seconds
Started Apr 15 12:39:31 PM PDT 24
Finished Apr 15 12:39:38 PM PDT 24
Peak memory 193580 kb
Host smart-8e8e05b8-79e1-4555-94fb-f254f3ad3b8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585916906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2585916906
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3687111039
Short name T710
Test name
Test status
Simulation time 85396139 ps
CPU time 2.08 seconds
Started Apr 15 12:39:30 PM PDT 24
Finished Apr 15 12:39:34 PM PDT 24
Peak memory 199008 kb
Host smart-f14997f2-b6fb-4c54-a3fc-8ae9952b8145
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687111039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3687111039
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3444164713
Short name T622
Test name
Test status
Simulation time 141939006 ps
CPU time 2.18 seconds
Started Apr 15 12:39:34 PM PDT 24
Finished Apr 15 12:39:38 PM PDT 24
Peak memory 199132 kb
Host smart-d5a1ed13-ad6c-4fb1-8041-42967c925153
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444164713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3444164713
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1392529550
Short name T109
Test name
Test status
Simulation time 169590305 ps
CPU time 1.72 seconds
Started Apr 15 12:39:23 PM PDT 24
Finished Apr 15 12:39:28 PM PDT 24
Peak memory 199084 kb
Host smart-9175f6f5-6c3e-4306-91f2-053dd8698423
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392529550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1392529550
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3682647684
Short name T702
Test name
Test status
Simulation time 358622725961 ps
CPU time 773.44 seconds
Started Apr 15 12:39:31 PM PDT 24
Finished Apr 15 12:52:26 PM PDT 24
Peak memory 215440 kb
Host smart-c59cf761-087c-491d-a63e-40832f24a08c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682647684 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3682647684
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2289975193
Short name T718
Test name
Test status
Simulation time 144537663 ps
CPU time 0.89 seconds
Started Apr 15 12:39:19 PM PDT 24
Finished Apr 15 12:39:21 PM PDT 24
Peak memory 198564 kb
Host smart-48128e2b-2371-4a2b-8998-5b5213e56a07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289975193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2289975193
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.10303548
Short name T694
Test name
Test status
Simulation time 13800459 ps
CPU time 0.56 seconds
Started Apr 15 12:39:30 PM PDT 24
Finished Apr 15 12:39:33 PM PDT 24
Peak memory 193584 kb
Host smart-74e4bb3d-854c-4648-bc3e-81bc8b2ce573
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10303548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.10303548
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3195656936
Short name T605
Test name
Test status
Simulation time 276111998 ps
CPU time 2.36 seconds
Started Apr 15 12:39:25 PM PDT 24
Finished Apr 15 12:39:31 PM PDT 24
Peak memory 198836 kb
Host smart-4c2cfc8f-0d5a-49d5-b5a8-5c3ce4c2e246
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195656936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.3195656936
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1276567534
Short name T714
Test name
Test status
Simulation time 221088081 ps
CPU time 3.84 seconds
Started Apr 15 12:39:31 PM PDT 24
Finished Apr 15 12:39:37 PM PDT 24
Peak memory 198988 kb
Host smart-29e827cf-56c9-416d-b856-29ba37bac187
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276567534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1276567534
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1190286172
Short name T119
Test name
Test status
Simulation time 1494384590 ps
CPU time 3.86 seconds
Started Apr 15 12:39:31 PM PDT 24
Finished Apr 15 12:39:36 PM PDT 24
Peak memory 199040 kb
Host smart-48d8575c-658d-4b86-8444-b7e1471ec541
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190286172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1190286172
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1697249862
Short name T635
Test name
Test status
Simulation time 932861911 ps
CPU time 1.77 seconds
Started Apr 15 12:39:31 PM PDT 24
Finished Apr 15 12:39:35 PM PDT 24
Peak memory 199140 kb
Host smart-b21aca0c-2be5-47da-920e-32d8ab7d426a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697249862 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1697249862
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2921773550
Short name T621
Test name
Test status
Simulation time 104579908 ps
CPU time 0.91 seconds
Started Apr 15 12:39:31 PM PDT 24
Finished Apr 15 12:39:34 PM PDT 24
Peak memory 198664 kb
Host smart-fa27096d-b1ce-4d63-a806-c1e21bd62246
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921773550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2921773550
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1044287790
Short name T652
Test name
Test status
Simulation time 96045068 ps
CPU time 0.56 seconds
Started Apr 15 12:39:21 PM PDT 24
Finished Apr 15 12:39:24 PM PDT 24
Peak memory 193920 kb
Host smart-adb52ba1-abb7-4902-8f88-593aca4e879b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044287790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1044287790
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2842788104
Short name T661
Test name
Test status
Simulation time 127185474 ps
CPU time 2.28 seconds
Started Apr 15 12:39:32 PM PDT 24
Finished Apr 15 12:39:36 PM PDT 24
Peak memory 198784 kb
Host smart-e213ec47-a99a-4706-8f38-380982d6ec61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842788104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2842788104
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1742876570
Short name T726
Test name
Test status
Simulation time 56605705 ps
CPU time 1.59 seconds
Started Apr 15 12:39:27 PM PDT 24
Finished Apr 15 12:39:31 PM PDT 24
Peak memory 198904 kb
Host smart-27bc7c26-e431-4a3c-bca1-dc06d28c5f0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742876570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1742876570
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.147295292
Short name T116
Test name
Test status
Simulation time 456492109 ps
CPU time 3.91 seconds
Started Apr 15 12:39:25 PM PDT 24
Finished Apr 15 12:39:32 PM PDT 24
Peak memory 199124 kb
Host smart-abab28eb-f9bb-4d97-bc47-7a4e9d8840e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147295292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.147295292
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2395300229
Short name T608
Test name
Test status
Simulation time 271113448 ps
CPU time 1.14 seconds
Started Apr 15 12:39:23 PM PDT 24
Finished Apr 15 12:39:27 PM PDT 24
Peak memory 198960 kb
Host smart-6ef293c9-c282-4a2d-80a1-c87432e5bc2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395300229 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2395300229
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.902720889
Short name T602
Test name
Test status
Simulation time 104559586 ps
CPU time 0.83 seconds
Started Apr 15 12:39:29 PM PDT 24
Finished Apr 15 12:39:32 PM PDT 24
Peak memory 198172 kb
Host smart-4165a8d0-2005-4d06-b2dc-20c3d3920573
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902720889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.902720889
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.1953779677
Short name T672
Test name
Test status
Simulation time 43325213 ps
CPU time 0.63 seconds
Started Apr 15 12:39:23 PM PDT 24
Finished Apr 15 12:39:26 PM PDT 24
Peak memory 193684 kb
Host smart-570c15b2-3da9-4691-9dac-9dbae364ef4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953779677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.1953779677
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1308909864
Short name T704
Test name
Test status
Simulation time 58081367 ps
CPU time 1.12 seconds
Started Apr 15 12:39:30 PM PDT 24
Finished Apr 15 12:39:33 PM PDT 24
Peak memory 197220 kb
Host smart-a584d4ef-8606-41cc-a7f5-b6e3c5edffdb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308909864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1308909864
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.406729018
Short name T693
Test name
Test status
Simulation time 60568586 ps
CPU time 1.52 seconds
Started Apr 15 12:40:46 PM PDT 24
Finished Apr 15 12:40:48 PM PDT 24
Peak memory 198892 kb
Host smart-58798486-763b-4f18-8d3e-43d0b7daa23b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406729018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.406729018
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1493146790
Short name T108
Test name
Test status
Simulation time 47146086 ps
CPU time 1.64 seconds
Started Apr 15 12:39:20 PM PDT 24
Finished Apr 15 12:39:23 PM PDT 24
Peak memory 199068 kb
Host smart-0e2fd157-74a4-435c-ac9e-af95fae02ebc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493146790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1493146790
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.369366943
Short name T695
Test name
Test status
Simulation time 289224065 ps
CPU time 1.51 seconds
Started Apr 15 12:40:49 PM PDT 24
Finished Apr 15 12:40:51 PM PDT 24
Peak memory 198868 kb
Host smart-72b834aa-8465-404c-8e16-1417ae0247e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369366943 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.369366943
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3209349570
Short name T723
Test name
Test status
Simulation time 83492387 ps
CPU time 0.96 seconds
Started Apr 15 12:39:28 PM PDT 24
Finished Apr 15 12:39:31 PM PDT 24
Peak memory 198872 kb
Host smart-169dbbb8-05cb-4fab-a6dc-177ba5745fb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209349570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3209349570
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.4161696847
Short name T647
Test name
Test status
Simulation time 22315976 ps
CPU time 0.61 seconds
Started Apr 15 12:40:24 PM PDT 24
Finished Apr 15 12:40:26 PM PDT 24
Peak memory 191908 kb
Host smart-034d370a-b08d-4934-8f73-741523bbf645
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161696847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.4161696847
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1911750060
Short name T684
Test name
Test status
Simulation time 183089401 ps
CPU time 2.04 seconds
Started Apr 15 12:39:30 PM PDT 24
Finished Apr 15 12:39:34 PM PDT 24
Peak memory 198680 kb
Host smart-1e3a55b4-b1e2-4f03-ac26-5fc42bc07805
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911750060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.1911750060
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1403208942
Short name T720
Test name
Test status
Simulation time 651615383 ps
CPU time 3.55 seconds
Started Apr 15 12:39:35 PM PDT 24
Finished Apr 15 12:39:40 PM PDT 24
Peak memory 199124 kb
Host smart-e091f440-1586-4ece-82b8-260ba6ecf8e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403208942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1403208942
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3779782912
Short name T113
Test name
Test status
Simulation time 313372460 ps
CPU time 1.68 seconds
Started Apr 15 12:39:24 PM PDT 24
Finished Apr 15 12:39:29 PM PDT 24
Peak memory 199068 kb
Host smart-269eff3d-9cdb-43c1-8921-110ac425bdc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779782912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.3779782912
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2353567022
Short name T369
Test name
Test status
Simulation time 11375429 ps
CPU time 0.58 seconds
Started Apr 15 02:21:43 PM PDT 24
Finished Apr 15 02:21:47 PM PDT 24
Peak memory 195148 kb
Host smart-a11074b2-214d-4c29-a080-4a2d5056bb78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353567022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2353567022
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3642019517
Short name T521
Test name
Test status
Simulation time 3846080229 ps
CPU time 31.76 seconds
Started Apr 15 02:21:37 PM PDT 24
Finished Apr 15 02:22:11 PM PDT 24
Peak memory 207936 kb
Host smart-25fd73c9-2f5c-45ca-9812-39f9331ba97d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3642019517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3642019517
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.16425171
Short name T492
Test name
Test status
Simulation time 612579990 ps
CPU time 9.27 seconds
Started Apr 15 02:21:39 PM PDT 24
Finished Apr 15 02:21:50 PM PDT 24
Peak memory 199564 kb
Host smart-f6d89253-4281-4cf7-af11-ecfb66808a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16425171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.16425171
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.4074016542
Short name T77
Test name
Test status
Simulation time 1400920333 ps
CPU time 83.22 seconds
Started Apr 15 02:21:42 PM PDT 24
Finished Apr 15 02:23:09 PM PDT 24
Peak memory 199612 kb
Host smart-edb59b3f-d118-4f9a-b867-864aa355695c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4074016542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.4074016542
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.3522031382
Short name T491
Test name
Test status
Simulation time 22983359774 ps
CPU time 78.83 seconds
Started Apr 15 02:21:39 PM PDT 24
Finished Apr 15 02:23:00 PM PDT 24
Peak memory 199680 kb
Host smart-18086f82-0047-4101-89b6-f67fd042cee7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522031382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.3522031382
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1784362212
Short name T82
Test name
Test status
Simulation time 4413219817 ps
CPU time 61.07 seconds
Started Apr 15 02:21:36 PM PDT 24
Finished Apr 15 02:22:39 PM PDT 24
Peak memory 199728 kb
Host smart-b5786de3-edb0-4e55-abdd-84a9c8b6b512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784362212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1784362212
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.757908323
Short name T149
Test name
Test status
Simulation time 448622323 ps
CPU time 5.42 seconds
Started Apr 15 02:21:34 PM PDT 24
Finished Apr 15 02:21:40 PM PDT 24
Peak memory 199612 kb
Host smart-73f6e995-54db-4e9f-980c-0afe7a958403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757908323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.757908323
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2177202128
Short name T366
Test name
Test status
Simulation time 20988353663 ps
CPU time 290.81 seconds
Started Apr 15 02:21:43 PM PDT 24
Finished Apr 15 02:26:38 PM PDT 24
Peak memory 209472 kb
Host smart-ef5328dc-a334-4802-8c9f-ef025860b85d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177202128 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2177202128
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.1270673021
Short name T154
Test name
Test status
Simulation time 368340148 ps
CPU time 1.02 seconds
Started Apr 15 02:21:39 PM PDT 24
Finished Apr 15 02:21:43 PM PDT 24
Peak memory 198892 kb
Host smart-afea4a88-bfdd-4c20-bcf5-4da83218a666
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270673021 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.1270673021
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.3876707878
Short name T523
Test name
Test status
Simulation time 37287957459 ps
CPU time 394.62 seconds
Started Apr 15 02:21:39 PM PDT 24
Finished Apr 15 02:28:17 PM PDT 24
Peak memory 199716 kb
Host smart-fea98e8a-f4bd-4b0c-a775-fe10a09aabca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876707878 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.3876707878
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1734004660
Short name T226
Test name
Test status
Simulation time 4716482574 ps
CPU time 45.19 seconds
Started Apr 15 02:21:42 PM PDT 24
Finished Apr 15 02:22:31 PM PDT 24
Peak memory 199764 kb
Host smart-c4c0348d-57c3-4d58-9b57-363b3ab301b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734004660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1734004660
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3708929504
Short name T246
Test name
Test status
Simulation time 13710889 ps
CPU time 0.59 seconds
Started Apr 15 02:21:44 PM PDT 24
Finished Apr 15 02:21:49 PM PDT 24
Peak memory 194108 kb
Host smart-f1dff6a9-4aeb-4fa3-9faa-ecd593bbd1f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708929504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3708929504
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.1156409720
Short name T526
Test name
Test status
Simulation time 2829784412 ps
CPU time 31.25 seconds
Started Apr 15 02:21:41 PM PDT 24
Finished Apr 15 02:22:16 PM PDT 24
Peak memory 228988 kb
Host smart-419b2e35-e13a-4202-b725-c10cb56d8a7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1156409720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.1156409720
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.655926658
Short name T172
Test name
Test status
Simulation time 5071202330 ps
CPU time 34.18 seconds
Started Apr 15 02:21:41 PM PDT 24
Finished Apr 15 02:22:18 PM PDT 24
Peak memory 199616 kb
Host smart-3085ba61-fc0c-46da-8c71-3ddf43b1cc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655926658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.655926658
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1961864765
Short name T421
Test name
Test status
Simulation time 56438328787 ps
CPU time 165.92 seconds
Started Apr 15 02:21:39 PM PDT 24
Finished Apr 15 02:24:27 PM PDT 24
Peak memory 199656 kb
Host smart-68890fad-45ff-472a-9dbb-e3667d8fc8d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1961864765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1961864765
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3526568774
Short name T212
Test name
Test status
Simulation time 17618622623 ps
CPU time 234.94 seconds
Started Apr 15 02:21:38 PM PDT 24
Finished Apr 15 02:25:35 PM PDT 24
Peak memory 199724 kb
Host smart-df0858ae-6dfe-4706-b90a-5e1887d74ec2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526568774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3526568774
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.4110010457
Short name T57
Test name
Test status
Simulation time 2511006750 ps
CPU time 36.01 seconds
Started Apr 15 02:21:36 PM PDT 24
Finished Apr 15 02:22:13 PM PDT 24
Peak memory 199724 kb
Host smart-7776ade4-90f5-4b2e-9470-4942d690337a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110010457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.4110010457
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.2144501953
Short name T27
Test name
Test status
Simulation time 612136790 ps
CPU time 1.1 seconds
Started Apr 15 02:21:45 PM PDT 24
Finished Apr 15 02:21:50 PM PDT 24
Peak memory 219244 kb
Host smart-72f4b5d1-32d6-4bbb-a440-d41898ef56e7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144501953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2144501953
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.171993408
Short name T143
Test name
Test status
Simulation time 667219262 ps
CPU time 6.74 seconds
Started Apr 15 02:21:45 PM PDT 24
Finished Apr 15 02:21:55 PM PDT 24
Peak memory 199596 kb
Host smart-190ac1cf-340f-4816-9703-6ee82716620b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171993408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.171993408
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.650237644
Short name T522
Test name
Test status
Simulation time 197467693010 ps
CPU time 880.44 seconds
Started Apr 15 02:21:40 PM PDT 24
Finished Apr 15 02:36:23 PM PDT 24
Peak memory 199720 kb
Host smart-97bb37ef-24c6-44dc-931e-e2273bb20173
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650237644 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.650237644
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.3980158219
Short name T26
Test name
Test status
Simulation time 53721361 ps
CPU time 1.02 seconds
Started Apr 15 02:21:42 PM PDT 24
Finished Apr 15 02:21:46 PM PDT 24
Peak memory 199064 kb
Host smart-1811beca-e465-44c0-85bf-10f84f6cd1fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980158219 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.3980158219
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.2603277717
Short name T282
Test name
Test status
Simulation time 23544275706 ps
CPU time 441.5 seconds
Started Apr 15 02:21:39 PM PDT 24
Finished Apr 15 02:29:02 PM PDT 24
Peak memory 199624 kb
Host smart-0e84796b-16f8-46e9-956c-570bd66a7c39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603277717 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.2603277717
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1875297970
Short name T419
Test name
Test status
Simulation time 4387891491 ps
CPU time 36.63 seconds
Started Apr 15 02:21:45 PM PDT 24
Finished Apr 15 02:22:25 PM PDT 24
Peak memory 199700 kb
Host smart-0d9d27e1-f4b7-4397-8d7d-57a1384e2482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875297970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1875297970
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.1416120961
Short name T164
Test name
Test status
Simulation time 45022725 ps
CPU time 0.55 seconds
Started Apr 15 02:21:58 PM PDT 24
Finished Apr 15 02:22:00 PM PDT 24
Peak memory 195264 kb
Host smart-5e4f2f6b-2e88-4e37-bce8-ed2d172240ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416120961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1416120961
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1732698868
Short name T203
Test name
Test status
Simulation time 478339892 ps
CPU time 14.78 seconds
Started Apr 15 02:22:04 PM PDT 24
Finished Apr 15 02:22:20 PM PDT 24
Peak memory 199632 kb
Host smart-a4327c71-795d-4fdd-ac38-151f184af088
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1732698868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1732698868
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.1819383824
Short name T451
Test name
Test status
Simulation time 4525219599 ps
CPU time 48.15 seconds
Started Apr 15 02:22:02 PM PDT 24
Finished Apr 15 02:22:51 PM PDT 24
Peak memory 199724 kb
Host smart-832e4691-8922-4d1e-b575-bef6e798b964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819383824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1819383824
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1238324162
Short name T507
Test name
Test status
Simulation time 8870898921 ps
CPU time 128.69 seconds
Started Apr 15 02:21:55 PM PDT 24
Finished Apr 15 02:24:06 PM PDT 24
Peak memory 199680 kb
Host smart-03c42064-9518-474d-9e12-d22dd49fc898
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1238324162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1238324162
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.1167504093
Short name T293
Test name
Test status
Simulation time 4859684648 ps
CPU time 38.89 seconds
Started Apr 15 02:22:02 PM PDT 24
Finished Apr 15 02:22:42 PM PDT 24
Peak memory 199676 kb
Host smart-e46b90be-4bd4-4c18-bb5b-d54586a219b3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167504093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1167504093
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.1933967475
Short name T414
Test name
Test status
Simulation time 3254452351 ps
CPU time 16.5 seconds
Started Apr 15 02:22:00 PM PDT 24
Finished Apr 15 02:22:18 PM PDT 24
Peak memory 199728 kb
Host smart-e413a227-85b5-42d8-a9bb-5cd2e3247352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933967475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1933967475
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.658094772
Short name T509
Test name
Test status
Simulation time 724369454 ps
CPU time 2.13 seconds
Started Apr 15 02:21:56 PM PDT 24
Finished Apr 15 02:22:00 PM PDT 24
Peak memory 199568 kb
Host smart-794552e8-6c27-43e1-a3d2-4136b0d7a708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658094772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.658094772
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1981992692
Short name T463
Test name
Test status
Simulation time 1490675708 ps
CPU time 77.48 seconds
Started Apr 15 02:21:59 PM PDT 24
Finished Apr 15 02:23:18 PM PDT 24
Peak memory 199584 kb
Host smart-af6773ec-10f0-4a12-808f-1910fcb0fd52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981992692 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1981992692
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_stress_all_with_rand_reset.1239731458
Short name T575
Test name
Test status
Simulation time 38210884766 ps
CPU time 1026.97 seconds
Started Apr 15 02:22:00 PM PDT 24
Finished Apr 15 02:39:08 PM PDT 24
Peak memory 216188 kb
Host smart-5667e03b-da22-46cc-a179-4a7c64324b98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1239731458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all_with_rand_reset.1239731458
Directory /workspace/10.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.1443269506
Short name T480
Test name
Test status
Simulation time 30868530 ps
CPU time 1.24 seconds
Started Apr 15 02:22:02 PM PDT 24
Finished Apr 15 02:22:04 PM PDT 24
Peak memory 199484 kb
Host smart-62a8538b-6b94-41cd-adf5-b1d7f15afd72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443269506 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.1443269506
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.1849352844
Short name T540
Test name
Test status
Simulation time 36709507192 ps
CPU time 480.7 seconds
Started Apr 15 02:21:59 PM PDT 24
Finished Apr 15 02:30:01 PM PDT 24
Peak memory 199600 kb
Host smart-7f10c0de-272a-4d56-9b4b-cb373c1a6d32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849352844 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.1849352844
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.3413978643
Short name T139
Test name
Test status
Simulation time 3737676935 ps
CPU time 50.33 seconds
Started Apr 15 02:22:01 PM PDT 24
Finished Apr 15 02:22:52 PM PDT 24
Peak memory 199724 kb
Host smart-bb7b4c72-219a-404f-820a-af1e466e7ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413978643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.3413978643
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2414390286
Short name T429
Test name
Test status
Simulation time 16523618 ps
CPU time 0.58 seconds
Started Apr 15 02:21:58 PM PDT 24
Finished Apr 15 02:22:00 PM PDT 24
Peak memory 195184 kb
Host smart-8e6946a3-e523-4bcf-98cc-3b3c78771622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414390286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2414390286
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2697501111
Short name T466
Test name
Test status
Simulation time 4420928148 ps
CPU time 47.18 seconds
Started Apr 15 02:22:04 PM PDT 24
Finished Apr 15 02:22:52 PM PDT 24
Peak memory 207928 kb
Host smart-0021b56e-ca02-4dc6-b044-c65f1ea59191
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2697501111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2697501111
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3494989864
Short name T549
Test name
Test status
Simulation time 176020111 ps
CPU time 8.23 seconds
Started Apr 15 02:22:02 PM PDT 24
Finished Apr 15 02:22:11 PM PDT 24
Peak memory 199600 kb
Host smart-af98f7b4-38dc-4d05-9c46-10ae34fc5a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494989864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3494989864
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.2728045417
Short name T472
Test name
Test status
Simulation time 507897967 ps
CPU time 30.54 seconds
Started Apr 15 02:22:05 PM PDT 24
Finished Apr 15 02:22:36 PM PDT 24
Peak memory 199612 kb
Host smart-522b8698-cf40-4759-bce0-d800ca41f896
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2728045417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2728045417
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.144426744
Short name T553
Test name
Test status
Simulation time 4755091699 ps
CPU time 126.98 seconds
Started Apr 15 02:22:00 PM PDT 24
Finished Apr 15 02:24:08 PM PDT 24
Peak memory 199676 kb
Host smart-7d975d9c-aa52-4f0e-8997-73247b60fd64
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144426744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.144426744
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2508252841
Short name T106
Test name
Test status
Simulation time 28363244906 ps
CPU time 94.54 seconds
Started Apr 15 02:21:59 PM PDT 24
Finished Apr 15 02:23:35 PM PDT 24
Peak memory 199756 kb
Host smart-ac696e1a-fef7-448c-8326-1b4292810302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508252841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2508252841
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.3939479083
Short name T175
Test name
Test status
Simulation time 56469044 ps
CPU time 1.26 seconds
Started Apr 15 02:21:58 PM PDT 24
Finished Apr 15 02:22:01 PM PDT 24
Peak memory 199584 kb
Host smart-30d929f0-512f-4622-988e-bdb1970c2993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939479083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3939479083
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3585891045
Short name T220
Test name
Test status
Simulation time 1856805787 ps
CPU time 19.46 seconds
Started Apr 15 02:22:06 PM PDT 24
Finished Apr 15 02:22:26 PM PDT 24
Peak memory 199556 kb
Host smart-e932f52f-6843-4336-bdc4-3bb2ed5ad773
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585891045 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3585891045
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.3071434759
Short name T591
Test name
Test status
Simulation time 48008842 ps
CPU time 1 seconds
Started Apr 15 02:21:58 PM PDT 24
Finished Apr 15 02:22:01 PM PDT 24
Peak memory 198948 kb
Host smart-2cd30ae3-7afb-443c-a9d9-497673d2b38a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071434759 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.3071434759
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.3967658736
Short name T356
Test name
Test status
Simulation time 35292329499 ps
CPU time 457.31 seconds
Started Apr 15 02:22:01 PM PDT 24
Finished Apr 15 02:29:40 PM PDT 24
Peak memory 199632 kb
Host smart-9c9d23b5-fbf7-43f9-8a68-131d32205d6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967658736 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.3967658736
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.740211434
Short name T530
Test name
Test status
Simulation time 5614103208 ps
CPU time 72.69 seconds
Started Apr 15 02:22:00 PM PDT 24
Finished Apr 15 02:23:14 PM PDT 24
Peak memory 199708 kb
Host smart-b603dbd2-6aa1-4687-ba8a-cf163c0ccec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740211434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.740211434
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.3595987922
Short name T39
Test name
Test status
Simulation time 12130279 ps
CPU time 0.59 seconds
Started Apr 15 02:22:04 PM PDT 24
Finished Apr 15 02:22:06 PM PDT 24
Peak memory 195152 kb
Host smart-4147efd9-d1f3-422e-9320-1f10fd233c7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595987922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3595987922
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1442623080
Short name T514
Test name
Test status
Simulation time 2516503205 ps
CPU time 23.3 seconds
Started Apr 15 02:22:06 PM PDT 24
Finished Apr 15 02:22:31 PM PDT 24
Peak memory 219184 kb
Host smart-8d1711e3-9caa-4486-ade0-16ddadad388d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1442623080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1442623080
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.730510642
Short name T215
Test name
Test status
Simulation time 1301237028 ps
CPU time 6.52 seconds
Started Apr 15 02:22:04 PM PDT 24
Finished Apr 15 02:22:11 PM PDT 24
Peak memory 199536 kb
Host smart-940a735f-92ea-4b97-8ce1-f312263749cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730510642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.730510642
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3498675272
Short name T138
Test name
Test status
Simulation time 733945510 ps
CPU time 40.33 seconds
Started Apr 15 02:22:04 PM PDT 24
Finished Apr 15 02:22:46 PM PDT 24
Peak memory 199512 kb
Host smart-eee5ac69-845f-4a1e-839b-9333cb4d9324
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3498675272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3498675272
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.4187681823
Short name T504
Test name
Test status
Simulation time 7151762744 ps
CPU time 33.72 seconds
Started Apr 15 02:22:04 PM PDT 24
Finished Apr 15 02:22:39 PM PDT 24
Peak memory 199716 kb
Host smart-cd8d1bc9-4e35-4f97-bcc0-d1b12e51ea07
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187681823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.4187681823
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.967164645
Short name T272
Test name
Test status
Simulation time 1140597918 ps
CPU time 28.41 seconds
Started Apr 15 02:22:07 PM PDT 24
Finished Apr 15 02:22:37 PM PDT 24
Peak memory 199524 kb
Host smart-b7d0a242-b934-4b1e-b052-c8aa16cfa972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967164645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.967164645
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.258733370
Short name T578
Test name
Test status
Simulation time 306578837 ps
CPU time 3.93 seconds
Started Apr 15 02:22:05 PM PDT 24
Finished Apr 15 02:22:09 PM PDT 24
Peak memory 199620 kb
Host smart-dfba9a01-90cc-4df0-b7e6-e74f351b9086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258733370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.258733370
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.4196595899
Short name T190
Test name
Test status
Simulation time 188007734 ps
CPU time 1.05 seconds
Started Apr 15 02:22:06 PM PDT 24
Finished Apr 15 02:22:08 PM PDT 24
Peak memory 199448 kb
Host smart-cfb17a67-d963-490a-9e59-c7a0112b6e4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196595899 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.4196595899
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.3389541124
Short name T306
Test name
Test status
Simulation time 220129040629 ps
CPU time 455.78 seconds
Started Apr 15 02:22:08 PM PDT 24
Finished Apr 15 02:29:46 PM PDT 24
Peak memory 199644 kb
Host smart-aba28a88-0859-4ef5-b60a-773846b2a318
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389541124 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.3389541124
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.4019741082
Short name T242
Test name
Test status
Simulation time 7811169830 ps
CPU time 73.92 seconds
Started Apr 15 02:22:07 PM PDT 24
Finished Apr 15 02:23:22 PM PDT 24
Peak memory 199732 kb
Host smart-8a363597-0a49-4b3c-8202-55c7f3489203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019741082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.4019741082
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.4016376509
Short name T455
Test name
Test status
Simulation time 37519862 ps
CPU time 0.56 seconds
Started Apr 15 02:22:09 PM PDT 24
Finished Apr 15 02:22:11 PM PDT 24
Peak memory 194012 kb
Host smart-679cbed1-7fbb-4d4c-ad78-8b59364d0b88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016376509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.4016376509
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3855517435
Short name T385
Test name
Test status
Simulation time 1138849947 ps
CPU time 44.51 seconds
Started Apr 15 02:22:06 PM PDT 24
Finished Apr 15 02:22:51 PM PDT 24
Peak memory 227344 kb
Host smart-754ec3a4-92d8-43d2-8ff8-f00f6ca47551
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3855517435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3855517435
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2417589126
Short name T140
Test name
Test status
Simulation time 1076571965 ps
CPU time 51.49 seconds
Started Apr 15 02:22:03 PM PDT 24
Finished Apr 15 02:22:55 PM PDT 24
Peak memory 199560 kb
Host smart-68ed2c3c-1af9-4465-b153-26cbaae86fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417589126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2417589126
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.4083507875
Short name T186
Test name
Test status
Simulation time 3103758501 ps
CPU time 85.72 seconds
Started Apr 15 02:22:03 PM PDT 24
Finished Apr 15 02:23:29 PM PDT 24
Peak memory 199680 kb
Host smart-9355967d-210d-4ce3-9d21-e7cd98eed437
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4083507875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.4083507875
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.3303436467
Short name T251
Test name
Test status
Simulation time 48366947921 ps
CPU time 220.93 seconds
Started Apr 15 02:22:08 PM PDT 24
Finished Apr 15 02:25:50 PM PDT 24
Peak memory 199632 kb
Host smart-2e44565f-fdd8-4c24-995a-4ac331a7ff33
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303436467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3303436467
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1608057619
Short name T167
Test name
Test status
Simulation time 4499295289 ps
CPU time 66.32 seconds
Started Apr 15 02:22:06 PM PDT 24
Finished Apr 15 02:23:13 PM PDT 24
Peak memory 199724 kb
Host smart-3da406df-1add-42fc-ac5d-5828445ca400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608057619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1608057619
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1782943052
Short name T181
Test name
Test status
Simulation time 435258401 ps
CPU time 5.1 seconds
Started Apr 15 02:22:01 PM PDT 24
Finished Apr 15 02:22:08 PM PDT 24
Peak memory 199608 kb
Host smart-e96624a4-454f-4ca2-b7ae-af49b3b2556f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782943052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1782943052
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.665923968
Short name T54
Test name
Test status
Simulation time 2004501631 ps
CPU time 64.47 seconds
Started Apr 15 02:22:06 PM PDT 24
Finished Apr 15 02:23:12 PM PDT 24
Peak memory 207796 kb
Host smart-a55e2e8d-10e2-4f82-9766-a5395ad37afb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665923968 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.665923968
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.669431536
Short name T259
Test name
Test status
Simulation time 28298486 ps
CPU time 0.97 seconds
Started Apr 15 02:22:06 PM PDT 24
Finished Apr 15 02:22:08 PM PDT 24
Peak memory 198896 kb
Host smart-43551780-9355-4641-81b8-b8bb6dbe077f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669431536 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_hmac_vectors.669431536
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.4161659697
Short name T584
Test name
Test status
Simulation time 60013787773 ps
CPU time 426.99 seconds
Started Apr 15 02:22:07 PM PDT 24
Finished Apr 15 02:29:15 PM PDT 24
Peak memory 199612 kb
Host smart-d35e6fca-5428-4607-b2a4-6fef675d61c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161659697 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.4161659697
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3080995286
Short name T562
Test name
Test status
Simulation time 2162892523 ps
CPU time 88.28 seconds
Started Apr 15 02:22:03 PM PDT 24
Finished Apr 15 02:23:32 PM PDT 24
Peak memory 199672 kb
Host smart-a3e4ade1-0ced-4f4c-b7f5-2df4f36e7695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080995286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3080995286
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1844094500
Short name T256
Test name
Test status
Simulation time 30010489 ps
CPU time 0.57 seconds
Started Apr 15 02:22:08 PM PDT 24
Finished Apr 15 02:22:10 PM PDT 24
Peak memory 194852 kb
Host smart-a3a98c27-9858-49cc-b32e-f95a4b9c1317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844094500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1844094500
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.587692386
Short name T53
Test name
Test status
Simulation time 292005711 ps
CPU time 10.11 seconds
Started Apr 15 02:22:10 PM PDT 24
Finished Apr 15 02:22:21 PM PDT 24
Peak memory 207764 kb
Host smart-7b932ecf-8f70-4705-9831-9c948e818df5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=587692386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.587692386
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2803130575
Short name T488
Test name
Test status
Simulation time 1042153081 ps
CPU time 21.6 seconds
Started Apr 15 02:22:12 PM PDT 24
Finished Apr 15 02:22:34 PM PDT 24
Peak memory 199512 kb
Host smart-841db7b4-1785-4604-95ad-8526066b4271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803130575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2803130575
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.2405679536
Short name T210
Test name
Test status
Simulation time 828566659 ps
CPU time 12.24 seconds
Started Apr 15 02:22:09 PM PDT 24
Finished Apr 15 02:22:22 PM PDT 24
Peak memory 199604 kb
Host smart-38e00c3b-3d87-421b-a1c6-c7b454364a23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2405679536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2405679536
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.1364811933
Short name T440
Test name
Test status
Simulation time 4670718081 ps
CPU time 45.72 seconds
Started Apr 15 02:22:07 PM PDT 24
Finished Apr 15 02:22:54 PM PDT 24
Peak memory 199712 kb
Host smart-967537db-7ba4-46c0-8284-f4f58982ea77
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364811933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1364811933
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.3666975032
Short name T555
Test name
Test status
Simulation time 5264876890 ps
CPU time 76.68 seconds
Started Apr 15 02:22:11 PM PDT 24
Finished Apr 15 02:23:28 PM PDT 24
Peak memory 199660 kb
Host smart-4bcb1876-5226-422e-ab91-8794263cc942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666975032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3666975032
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3347882046
Short name T320
Test name
Test status
Simulation time 18912866 ps
CPU time 0.76 seconds
Started Apr 15 02:22:07 PM PDT 24
Finished Apr 15 02:22:09 PM PDT 24
Peak memory 196840 kb
Host smart-67fd1253-eed0-4373-979f-b0baf332e742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347882046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3347882046
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.3357687291
Short name T473
Test name
Test status
Simulation time 24671784044 ps
CPU time 1273.49 seconds
Started Apr 15 02:22:10 PM PDT 24
Finished Apr 15 02:43:25 PM PDT 24
Peak memory 231588 kb
Host smart-39a184dc-9999-4822-87b8-638ca2f62938
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357687291 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3357687291
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.447483073
Short name T123
Test name
Test status
Simulation time 58324196 ps
CPU time 1.27 seconds
Started Apr 15 02:22:07 PM PDT 24
Finished Apr 15 02:22:10 PM PDT 24
Peak memory 199488 kb
Host smart-2b8b74c5-8523-41fd-9de5-c0ddc7724870
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447483073 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_test_hmac_vectors.447483073
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.2893733435
Short name T487
Test name
Test status
Simulation time 75611130744 ps
CPU time 479.76 seconds
Started Apr 15 02:22:12 PM PDT 24
Finished Apr 15 02:30:13 PM PDT 24
Peak memory 199644 kb
Host smart-a188bc4c-19ab-41b9-9827-d4553328afd8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893733435 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.2893733435
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2325179877
Short name T511
Test name
Test status
Simulation time 654662799 ps
CPU time 12.39 seconds
Started Apr 15 02:22:09 PM PDT 24
Finished Apr 15 02:22:23 PM PDT 24
Peak memory 199540 kb
Host smart-3d3af3c3-6b2d-4068-8674-e6a1a40713c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325179877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2325179877
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.1408062151
Short name T209
Test name
Test status
Simulation time 13614577 ps
CPU time 0.59 seconds
Started Apr 15 02:22:14 PM PDT 24
Finished Apr 15 02:22:15 PM PDT 24
Peak memory 194816 kb
Host smart-b6517ad8-49de-47ec-a747-7c1bf268f77c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408062151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1408062151
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.921646508
Short name T371
Test name
Test status
Simulation time 2143570068 ps
CPU time 23.16 seconds
Started Apr 15 02:22:09 PM PDT 24
Finished Apr 15 02:22:33 PM PDT 24
Peak memory 231360 kb
Host smart-561dc173-24f1-4bde-94fd-8cfde61c6088
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=921646508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.921646508
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2515956529
Short name T308
Test name
Test status
Simulation time 3462066411 ps
CPU time 18.8 seconds
Started Apr 15 02:22:09 PM PDT 24
Finished Apr 15 02:22:29 PM PDT 24
Peak memory 199608 kb
Host smart-8a1fc313-4c86-447b-a986-e53b230ef4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515956529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2515956529
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.750142054
Short name T518
Test name
Test status
Simulation time 12616441168 ps
CPU time 103.82 seconds
Started Apr 15 02:22:09 PM PDT 24
Finished Apr 15 02:23:54 PM PDT 24
Peak memory 199720 kb
Host smart-6ba8308c-7159-456f-975d-7ed507c0b119
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=750142054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.750142054
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.1961778864
Short name T296
Test name
Test status
Simulation time 20447829523 ps
CPU time 95.03 seconds
Started Apr 15 02:22:12 PM PDT 24
Finished Apr 15 02:23:48 PM PDT 24
Peak memory 199684 kb
Host smart-049c6b93-b86b-4727-adfb-fde6531db358
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961778864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1961778864
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.4125904189
Short name T474
Test name
Test status
Simulation time 2148098530 ps
CPU time 40 seconds
Started Apr 15 02:22:10 PM PDT 24
Finished Apr 15 02:22:51 PM PDT 24
Peak memory 199664 kb
Host smart-32eec768-41b5-4732-8cd1-50959863851b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125904189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.4125904189
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2069264150
Short name T469
Test name
Test status
Simulation time 591995602 ps
CPU time 6.83 seconds
Started Apr 15 02:22:08 PM PDT 24
Finished Apr 15 02:22:16 PM PDT 24
Peak memory 199604 kb
Host smart-72d4a69b-87f8-4045-b6c5-5329352d794d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069264150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2069264150
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.659202646
Short name T528
Test name
Test status
Simulation time 11351548797 ps
CPU time 486.83 seconds
Started Apr 15 02:22:13 PM PDT 24
Finished Apr 15 02:30:21 PM PDT 24
Peak memory 240712 kb
Host smart-cf58ce10-b7dc-4d23-aa2e-4814704b3b41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659202646 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.659202646
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.2241706694
Short name T179
Test name
Test status
Simulation time 261269312 ps
CPU time 1.27 seconds
Started Apr 15 02:22:12 PM PDT 24
Finished Apr 15 02:22:15 PM PDT 24
Peak memory 199592 kb
Host smart-1b959ca2-f5ed-4272-8f2b-4b403b24c0fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241706694 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.2241706694
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.1264888531
Short name T324
Test name
Test status
Simulation time 14630570002 ps
CPU time 404.93 seconds
Started Apr 15 02:22:13 PM PDT 24
Finished Apr 15 02:28:59 PM PDT 24
Peak memory 199640 kb
Host smart-98f9cf2f-ccf8-40cd-acb1-7f2abb60d027
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264888531 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.1264888531
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.2690516120
Short name T358
Test name
Test status
Simulation time 33014989031 ps
CPU time 65.49 seconds
Started Apr 15 02:22:09 PM PDT 24
Finished Apr 15 02:23:15 PM PDT 24
Peak memory 199676 kb
Host smart-0a958aee-14ee-41e3-96f7-3bdd265b0970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690516120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.2690516120
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.4277015950
Short name T216
Test name
Test status
Simulation time 40794156 ps
CPU time 0.54 seconds
Started Apr 15 02:22:20 PM PDT 24
Finished Apr 15 02:22:21 PM PDT 24
Peak memory 194136 kb
Host smart-384b873e-1a63-4f64-a052-11e2ed02a8d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277015950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.4277015950
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2229486340
Short name T40
Test name
Test status
Simulation time 235673944 ps
CPU time 8.73 seconds
Started Apr 15 02:22:22 PM PDT 24
Finished Apr 15 02:22:32 PM PDT 24
Peak memory 207756 kb
Host smart-8dbf3da3-e38c-4c8d-96fa-93022f2b1225
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2229486340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2229486340
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.3147481152
Short name T155
Test name
Test status
Simulation time 1194281062 ps
CPU time 18.74 seconds
Started Apr 15 02:22:32 PM PDT 24
Finished Apr 15 02:22:52 PM PDT 24
Peak memory 199604 kb
Host smart-e07cda1c-6fd6-4e40-a943-97bd6bebb8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147481152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.3147481152
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.4246276200
Short name T230
Test name
Test status
Simulation time 2823947072 ps
CPU time 36.31 seconds
Started Apr 15 02:22:18 PM PDT 24
Finished Apr 15 02:22:55 PM PDT 24
Peak memory 199664 kb
Host smart-a961d3b4-c725-4f19-9449-8fb0c3e44f7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4246276200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.4246276200
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.3379291217
Short name T170
Test name
Test status
Simulation time 4257175816 ps
CPU time 57.62 seconds
Started Apr 15 02:22:19 PM PDT 24
Finished Apr 15 02:23:17 PM PDT 24
Peak memory 199732 kb
Host smart-f9bd9017-25da-415c-8a26-53ae0239f92b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379291217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3379291217
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1207097592
Short name T564
Test name
Test status
Simulation time 591559991 ps
CPU time 17.91 seconds
Started Apr 15 02:22:15 PM PDT 24
Finished Apr 15 02:22:34 PM PDT 24
Peak memory 199616 kb
Host smart-f5fc34f6-9100-49cc-86cc-666cefbc7fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207097592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1207097592
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.3597107646
Short name T254
Test name
Test status
Simulation time 1107334584 ps
CPU time 4.5 seconds
Started Apr 15 02:22:14 PM PDT 24
Finished Apr 15 02:22:19 PM PDT 24
Peak memory 199608 kb
Host smart-2e1967c4-2aaf-4fe0-b731-54594e07f51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597107646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.3597107646
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.4131221677
Short name T248
Test name
Test status
Simulation time 60071179418 ps
CPU time 2034.6 seconds
Started Apr 15 02:22:20 PM PDT 24
Finished Apr 15 02:56:15 PM PDT 24
Peak memory 232416 kb
Host smart-55eb39a6-15fb-494d-b674-0732692494bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131221677 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.4131221677
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.806098117
Short name T312
Test name
Test status
Simulation time 216781981 ps
CPU time 1.23 seconds
Started Apr 15 02:22:20 PM PDT 24
Finished Apr 15 02:22:22 PM PDT 24
Peak memory 199576 kb
Host smart-76277af7-f9f7-4218-a919-0e2f98dce761
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806098117 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.hmac_test_hmac_vectors.806098117
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.413109657
Short name T544
Test name
Test status
Simulation time 25371465904 ps
CPU time 472.98 seconds
Started Apr 15 02:22:19 PM PDT 24
Finished Apr 15 02:30:13 PM PDT 24
Peak memory 199704 kb
Host smart-10eaed64-025e-4c51-a588-7d8dd8af9dd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413109657 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.413109657
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2367611218
Short name T258
Test name
Test status
Simulation time 9911713496 ps
CPU time 82.44 seconds
Started Apr 15 02:22:19 PM PDT 24
Finished Apr 15 02:23:42 PM PDT 24
Peak memory 199724 kb
Host smart-00359493-e3f4-40b4-902d-bf2ccf46e802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367611218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2367611218
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3209524000
Short name T182
Test name
Test status
Simulation time 17710349 ps
CPU time 0.57 seconds
Started Apr 15 02:22:25 PM PDT 24
Finished Apr 15 02:22:26 PM PDT 24
Peak memory 195136 kb
Host smart-0f487770-3e81-4b42-899c-ee992a42fc68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209524000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3209524000
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.259563287
Short name T543
Test name
Test status
Simulation time 91863018 ps
CPU time 3.41 seconds
Started Apr 15 02:22:24 PM PDT 24
Finished Apr 15 02:22:28 PM PDT 24
Peak memory 199556 kb
Host smart-b78de71c-52d8-47a6-80b4-6f06a1ad129c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=259563287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.259563287
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.868419703
Short name T38
Test name
Test status
Simulation time 5732355239 ps
CPU time 50.57 seconds
Started Apr 15 02:22:22 PM PDT 24
Finished Apr 15 02:23:14 PM PDT 24
Peak memory 199728 kb
Host smart-9a9b6fb2-bf37-4a39-b02a-9101cc60f70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868419703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.868419703
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.4095106498
Short name T548
Test name
Test status
Simulation time 827249660 ps
CPU time 25.54 seconds
Started Apr 15 02:22:20 PM PDT 24
Finished Apr 15 02:22:47 PM PDT 24
Peak memory 199560 kb
Host smart-34951d83-024f-44a8-93b9-d19fcf19f7a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4095106498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.4095106498
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.2061170286
Short name T188
Test name
Test status
Simulation time 3046614994 ps
CPU time 41.67 seconds
Started Apr 15 02:22:21 PM PDT 24
Finished Apr 15 02:23:04 PM PDT 24
Peak memory 199912 kb
Host smart-8d934a1a-be1b-4e0f-aa7a-92e18e717fee
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061170286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2061170286
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3990687522
Short name T289
Test name
Test status
Simulation time 83445589 ps
CPU time 1.89 seconds
Started Apr 15 02:22:20 PM PDT 24
Finished Apr 15 02:22:23 PM PDT 24
Peak memory 199544 kb
Host smart-890e6c3e-eb51-4ebb-828e-e2df068a571e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990687522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3990687522
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.286603802
Short name T236
Test name
Test status
Simulation time 1137904880 ps
CPU time 3.9 seconds
Started Apr 15 02:22:22 PM PDT 24
Finished Apr 15 02:22:26 PM PDT 24
Peak memory 199580 kb
Host smart-0f64f8f1-cae4-4f58-90bc-ff1fd66b017c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286603802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.286603802
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.1525518630
Short name T4
Test name
Test status
Simulation time 84593444382 ps
CPU time 810.2 seconds
Started Apr 15 02:22:22 PM PDT 24
Finished Apr 15 02:35:53 PM PDT 24
Peak memory 207928 kb
Host smart-d41d9f49-547f-4db8-81b9-f44c1b9b61dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525518630 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.1525518630
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.3778875248
Short name T291
Test name
Test status
Simulation time 178408099 ps
CPU time 1.26 seconds
Started Apr 15 02:22:21 PM PDT 24
Finished Apr 15 02:22:23 PM PDT 24
Peak memory 199560 kb
Host smart-5e0d440c-d0fb-426e-82b9-4c96269d31a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778875248 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.3778875248
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.2495832962
Short name T336
Test name
Test status
Simulation time 74200984296 ps
CPU time 499.79 seconds
Started Apr 15 02:22:23 PM PDT 24
Finished Apr 15 02:30:43 PM PDT 24
Peak memory 199728 kb
Host smart-19aa896e-f717-4d33-b49b-bfd301ef5ac8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495832962 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.2495832962
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1921507516
Short name T539
Test name
Test status
Simulation time 6668838816 ps
CPU time 35.71 seconds
Started Apr 15 02:22:21 PM PDT 24
Finished Apr 15 02:22:58 PM PDT 24
Peak memory 199724 kb
Host smart-d22e61e5-40c0-4cbe-aa3b-309f40e90e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921507516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1921507516
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1338723089
Short name T300
Test name
Test status
Simulation time 17927660 ps
CPU time 0.61 seconds
Started Apr 15 02:22:32 PM PDT 24
Finished Apr 15 02:22:34 PM PDT 24
Peak memory 194120 kb
Host smart-cd237b9b-ec85-449c-8e19-c7a355936437
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338723089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1338723089
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.804687874
Short name T422
Test name
Test status
Simulation time 653362060 ps
CPU time 24.18 seconds
Started Apr 15 02:22:27 PM PDT 24
Finished Apr 15 02:22:52 PM PDT 24
Peak memory 207784 kb
Host smart-ac49022b-dbb8-4d94-8dc3-8bcf9a3be4cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=804687874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.804687874
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.2700057231
Short name T493
Test name
Test status
Simulation time 1387722335 ps
CPU time 3.97 seconds
Started Apr 15 02:22:24 PM PDT 24
Finished Apr 15 02:22:29 PM PDT 24
Peak memory 199568 kb
Host smart-7e279e04-8495-4f80-b173-3c3afe5f0d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700057231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.2700057231
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3648855422
Short name T418
Test name
Test status
Simulation time 6531831564 ps
CPU time 97.27 seconds
Started Apr 15 02:22:23 PM PDT 24
Finished Apr 15 02:24:02 PM PDT 24
Peak memory 199728 kb
Host smart-638c0bd1-864c-410c-8dbe-be7420a747bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3648855422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3648855422
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.1925941932
Short name T42
Test name
Test status
Simulation time 35100773370 ps
CPU time 275.98 seconds
Started Apr 15 02:22:23 PM PDT 24
Finished Apr 15 02:27:00 PM PDT 24
Peak memory 199696 kb
Host smart-14d9825f-12d9-4a1a-9dac-fcb898f85e29
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925941932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1925941932
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.4092026460
Short name T133
Test name
Test status
Simulation time 18052274476 ps
CPU time 66.99 seconds
Started Apr 15 02:22:25 PM PDT 24
Finished Apr 15 02:23:33 PM PDT 24
Peak memory 199692 kb
Host smart-2e2d210c-f240-4f3a-92a7-bb52c79a8e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092026460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.4092026460
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2816932576
Short name T24
Test name
Test status
Simulation time 515831517 ps
CPU time 4.28 seconds
Started Apr 15 02:22:27 PM PDT 24
Finished Apr 15 02:22:32 PM PDT 24
Peak memory 199568 kb
Host smart-5cf4a3f2-cc6b-428f-a2ac-2019810144ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816932576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2816932576
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3411515639
Short name T12
Test name
Test status
Simulation time 87724049435 ps
CPU time 647.54 seconds
Started Apr 15 02:22:35 PM PDT 24
Finished Apr 15 02:33:24 PM PDT 24
Peak memory 216124 kb
Host smart-d9fe697b-2959-43a1-ac46-48deeb60b993
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411515639 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3411515639
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.4082321774
Short name T349
Test name
Test status
Simulation time 56086111 ps
CPU time 1.17 seconds
Started Apr 15 02:22:30 PM PDT 24
Finished Apr 15 02:22:32 PM PDT 24
Peak memory 198496 kb
Host smart-6471f793-2731-42de-85a0-5732b1d09c50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082321774 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.4082321774
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.2513654712
Short name T458
Test name
Test status
Simulation time 44253719613 ps
CPU time 553.87 seconds
Started Apr 15 02:22:28 PM PDT 24
Finished Apr 15 02:31:43 PM PDT 24
Peak memory 199740 kb
Host smart-3dddb9c4-e172-4618-afd4-5ddc83435dc4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513654712 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.2513654712
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/186.hmac_stress_all_with_rand_reset.3947683411
Short name T76
Test name
Test status
Simulation time 119486529568 ps
CPU time 406.55 seconds
Started Apr 15 02:25:29 PM PDT 24
Finished Apr 15 02:32:16 PM PDT 24
Peak memory 215324 kb
Host smart-c97bc257-5df9-4956-9a94-bf6debf5bd06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3947683411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.hmac_stress_all_with_rand_reset.3947683411
Directory /workspace/186.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1952370161
Short name T286
Test name
Test status
Simulation time 45780513 ps
CPU time 0.55 seconds
Started Apr 15 02:22:33 PM PDT 24
Finished Apr 15 02:22:34 PM PDT 24
Peak memory 195076 kb
Host smart-e468dbb7-cd86-41e8-a500-9bdab8d748f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952370161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1952370161
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.101117494
Short name T517
Test name
Test status
Simulation time 2567615954 ps
CPU time 24.64 seconds
Started Apr 15 02:22:31 PM PDT 24
Finished Apr 15 02:22:57 PM PDT 24
Peak memory 229684 kb
Host smart-8ef10992-1108-4ca3-86aa-d813d10cb621
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=101117494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.101117494
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2895163807
Short name T481
Test name
Test status
Simulation time 2079522079 ps
CPU time 30.04 seconds
Started Apr 15 02:22:29 PM PDT 24
Finished Apr 15 02:23:00 PM PDT 24
Peak memory 199576 kb
Host smart-ae734e9a-9fa0-4a9f-bbe1-a041ab5c50bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895163807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2895163807
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.4104263696
Short name T294
Test name
Test status
Simulation time 5241022385 ps
CPU time 76.08 seconds
Started Apr 15 02:22:34 PM PDT 24
Finished Apr 15 02:23:52 PM PDT 24
Peak memory 199700 kb
Host smart-5b0a023f-eebf-4450-b9be-7d4f1aabccbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4104263696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.4104263696
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3061339878
Short name T420
Test name
Test status
Simulation time 9238311805 ps
CPU time 35.52 seconds
Started Apr 15 02:22:28 PM PDT 24
Finished Apr 15 02:23:04 PM PDT 24
Peak memory 199672 kb
Host smart-569a5f41-906c-40dc-934b-799f2a33d117
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061339878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3061339878
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.839954952
Short name T341
Test name
Test status
Simulation time 186386242 ps
CPU time 4 seconds
Started Apr 15 02:22:30 PM PDT 24
Finished Apr 15 02:22:35 PM PDT 24
Peak memory 199608 kb
Host smart-bd240e76-aeb4-468c-9f9d-14915114b062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839954952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.839954952
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1847176831
Short name T311
Test name
Test status
Simulation time 22131566 ps
CPU time 0.82 seconds
Started Apr 15 02:22:34 PM PDT 24
Finished Apr 15 02:22:36 PM PDT 24
Peak memory 196860 kb
Host smart-a5fa6b05-c92d-4aec-8198-4974e6569fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847176831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1847176831
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.2463647064
Short name T412
Test name
Test status
Simulation time 270478658391 ps
CPU time 1295.57 seconds
Started Apr 15 02:22:29 PM PDT 24
Finished Apr 15 02:44:06 PM PDT 24
Peak memory 240864 kb
Host smart-26f490ed-f0c0-45de-8eb0-bbd5f051fdae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463647064 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2463647064
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.3853138003
Short name T450
Test name
Test status
Simulation time 54702923 ps
CPU time 1.08 seconds
Started Apr 15 02:22:35 PM PDT 24
Finished Apr 15 02:22:37 PM PDT 24
Peak memory 199084 kb
Host smart-1243615a-c16c-49a8-95eb-0c27e66d2d38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853138003 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.3853138003
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.3033964302
Short name T516
Test name
Test status
Simulation time 128008913543 ps
CPU time 493.62 seconds
Started Apr 15 02:22:35 PM PDT 24
Finished Apr 15 02:30:50 PM PDT 24
Peak memory 199704 kb
Host smart-e3397b49-cedb-4cfe-820e-8e4135a21440
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033964302 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.3033964302
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.924873971
Short name T1
Test name
Test status
Simulation time 2476484539 ps
CPU time 24.1 seconds
Started Apr 15 02:22:34 PM PDT 24
Finished Apr 15 02:22:59 PM PDT 24
Peak memory 199708 kb
Host smart-047917be-5b50-465d-bf3d-3c7bac93d560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924873971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.924873971
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/195.hmac_stress_all_with_rand_reset.141949659
Short name T8
Test name
Test status
Simulation time 68440210386 ps
CPU time 654.61 seconds
Started Apr 15 02:25:40 PM PDT 24
Finished Apr 15 02:36:36 PM PDT 24
Peak memory 248916 kb
Host smart-8d024a4b-c4f2-4075-83fb-b2d7ef333804
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=141949659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.hmac_stress_all_with_rand_reset.141949659
Directory /workspace/195.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1879465594
Short name T508
Test name
Test status
Simulation time 14663975 ps
CPU time 0.56 seconds
Started Apr 15 02:21:42 PM PDT 24
Finished Apr 15 02:21:46 PM PDT 24
Peak memory 195168 kb
Host smart-1697bd54-0898-44f6-89ec-c662d2108ec8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879465594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1879465594
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.2434400064
Short name T559
Test name
Test status
Simulation time 184478027 ps
CPU time 6.18 seconds
Started Apr 15 02:21:41 PM PDT 24
Finished Apr 15 02:21:51 PM PDT 24
Peak memory 199596 kb
Host smart-514ec5ab-9f65-42da-bcc5-77029e1abfc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2434400064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.2434400064
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1016324996
Short name T273
Test name
Test status
Simulation time 2004707970 ps
CPU time 40.03 seconds
Started Apr 15 02:21:42 PM PDT 24
Finished Apr 15 02:22:26 PM PDT 24
Peak memory 199608 kb
Host smart-6dd46c46-0df1-48bc-991b-323ce839cb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016324996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1016324996
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3279019593
Short name T237
Test name
Test status
Simulation time 22971765305 ps
CPU time 85.25 seconds
Started Apr 15 02:21:40 PM PDT 24
Finished Apr 15 02:23:09 PM PDT 24
Peak memory 199724 kb
Host smart-2fed5026-c907-431d-a98a-7cd431fa794e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3279019593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3279019593
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.1750866096
Short name T23
Test name
Test status
Simulation time 70365427003 ps
CPU time 125.96 seconds
Started Apr 15 02:21:45 PM PDT 24
Finished Apr 15 02:23:56 PM PDT 24
Peak memory 199720 kb
Host smart-49a547a4-cf25-477e-aa06-31215eddb52b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750866096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.1750866096
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3031950505
Short name T392
Test name
Test status
Simulation time 1164710469 ps
CPU time 66.11 seconds
Started Apr 15 02:21:41 PM PDT 24
Finished Apr 15 02:22:50 PM PDT 24
Peak memory 199608 kb
Host smart-8c1bb7d8-77f8-41eb-8594-7c61e3f9e22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031950505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3031950505
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2235649410
Short name T28
Test name
Test status
Simulation time 122654936 ps
CPU time 0.81 seconds
Started Apr 15 02:21:43 PM PDT 24
Finished Apr 15 02:21:48 PM PDT 24
Peak memory 218180 kb
Host smart-4f5d9770-3d8b-48c8-839d-eff9c79c78f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235649410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2235649410
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.60089661
Short name T152
Test name
Test status
Simulation time 752853801 ps
CPU time 5.91 seconds
Started Apr 15 02:21:43 PM PDT 24
Finished Apr 15 02:21:54 PM PDT 24
Peak memory 199584 kb
Host smart-129b3d78-7e10-487d-93be-6b4b381f1895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60089661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.60089661
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.1459332205
Short name T72
Test name
Test status
Simulation time 528465325595 ps
CPU time 1565.4 seconds
Started Apr 15 02:21:43 PM PDT 24
Finished Apr 15 02:47:52 PM PDT 24
Peak memory 232124 kb
Host smart-031eafcf-aa64-47cf-be0d-0ffe1694b706
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459332205 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.1459332205
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.2403479203
Short name T499
Test name
Test status
Simulation time 56661033 ps
CPU time 1.02 seconds
Started Apr 15 02:21:43 PM PDT 24
Finished Apr 15 02:21:48 PM PDT 24
Peak memory 199096 kb
Host smart-a0bd8ac9-d536-4420-bad1-c6cf429f3c89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403479203 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.2403479203
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.3797548500
Short name T191
Test name
Test status
Simulation time 8358251738 ps
CPU time 450.04 seconds
Started Apr 15 02:21:39 PM PDT 24
Finished Apr 15 02:29:11 PM PDT 24
Peak memory 199684 kb
Host smart-a610b616-22db-4c3d-9d91-a749e6c9e4b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797548500 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.3797548500
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2075449370
Short name T234
Test name
Test status
Simulation time 1001453262 ps
CPU time 26.12 seconds
Started Apr 15 02:21:43 PM PDT 24
Finished Apr 15 02:22:13 PM PDT 24
Peak memory 199556 kb
Host smart-0644ca66-3a90-4aef-8c65-f58fd2549a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075449370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2075449370
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2893583063
Short name T302
Test name
Test status
Simulation time 24200668 ps
CPU time 0.56 seconds
Started Apr 15 02:22:37 PM PDT 24
Finished Apr 15 02:22:39 PM PDT 24
Peak memory 195144 kb
Host smart-94e20a50-21ff-410d-b4cc-711788cf3b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893583063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2893583063
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.283913165
Short name T551
Test name
Test status
Simulation time 5952866907 ps
CPU time 61.9 seconds
Started Apr 15 02:22:34 PM PDT 24
Finished Apr 15 02:23:38 PM PDT 24
Peak memory 248408 kb
Host smart-af1782d8-fbea-4041-a934-37a506e73fef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=283913165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.283913165
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.1833002492
Short name T441
Test name
Test status
Simulation time 992074674 ps
CPU time 5.68 seconds
Started Apr 15 02:22:34 PM PDT 24
Finished Apr 15 02:22:41 PM PDT 24
Peak memory 199596 kb
Host smart-51ee2723-9d76-4719-8a2b-f5da91391479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833002492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1833002492
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.2543300609
Short name T384
Test name
Test status
Simulation time 323737022 ps
CPU time 18.13 seconds
Started Apr 15 02:22:34 PM PDT 24
Finished Apr 15 02:22:53 PM PDT 24
Peak memory 199612 kb
Host smart-3a28bb8b-10e1-45e5-8fcc-097d0bf8f0c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2543300609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2543300609
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3602859504
Short name T3
Test name
Test status
Simulation time 8879665956 ps
CPU time 39.59 seconds
Started Apr 15 02:22:34 PM PDT 24
Finished Apr 15 02:23:14 PM PDT 24
Peak memory 199760 kb
Host smart-b2b418a6-5161-4063-a9ae-37dd1f9c3141
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602859504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3602859504
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1612846508
Short name T519
Test name
Test status
Simulation time 1136541941 ps
CPU time 65.33 seconds
Started Apr 15 02:22:35 PM PDT 24
Finished Apr 15 02:23:41 PM PDT 24
Peak memory 199576 kb
Host smart-dea54a1e-97c8-455e-a139-ac93f32fe97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612846508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1612846508
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.3022764571
Short name T442
Test name
Test status
Simulation time 410488354 ps
CPU time 5.91 seconds
Started Apr 15 02:22:33 PM PDT 24
Finished Apr 15 02:22:40 PM PDT 24
Peak memory 199376 kb
Host smart-307cce87-3410-43dc-9da1-b2c3678c5a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022764571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3022764571
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.1534966721
Short name T271
Test name
Test status
Simulation time 121999019235 ps
CPU time 2290.46 seconds
Started Apr 15 02:22:33 PM PDT 24
Finished Apr 15 03:00:44 PM PDT 24
Peak memory 232524 kb
Host smart-28c4a07d-b401-44c9-b209-8a46823387cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534966721 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1534966721
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_stress_all_with_rand_reset.3815714739
Short name T66
Test name
Test status
Simulation time 35256666774 ps
CPU time 1171.5 seconds
Started Apr 15 02:22:35 PM PDT 24
Finished Apr 15 02:42:08 PM PDT 24
Peak memory 248144 kb
Host smart-c2bc4a38-648d-43e4-afd8-c326f4dcace8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3815714739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all_with_rand_reset.3815714739
Directory /workspace/20.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.580886300
Short name T176
Test name
Test status
Simulation time 57124128 ps
CPU time 1.21 seconds
Started Apr 15 02:22:33 PM PDT 24
Finished Apr 15 02:22:36 PM PDT 24
Peak memory 199596 kb
Host smart-e2b59091-eadf-418e-96b1-6e3c6d8e1a21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580886300 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_hmac_vectors.580886300
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.2892030813
Short name T288
Test name
Test status
Simulation time 30225894690 ps
CPU time 444.81 seconds
Started Apr 15 02:22:36 PM PDT 24
Finished Apr 15 02:30:02 PM PDT 24
Peak memory 199656 kb
Host smart-5a8790b8-c473-4825-9bbc-c6f573822b27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892030813 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.2892030813
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.2906630634
Short name T426
Test name
Test status
Simulation time 4759168756 ps
CPU time 61.14 seconds
Started Apr 15 02:22:33 PM PDT 24
Finished Apr 15 02:23:35 PM PDT 24
Peak memory 199628 kb
Host smart-f33db5ba-3963-4399-998b-9c1dee0ddf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906630634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2906630634
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1485954199
Short name T505
Test name
Test status
Simulation time 33058598 ps
CPU time 0.58 seconds
Started Apr 15 02:22:47 PM PDT 24
Finished Apr 15 02:22:48 PM PDT 24
Peak memory 195112 kb
Host smart-674c9cc9-d513-4188-ab1c-0391b1eac748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485954199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1485954199
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1933800458
Short name T233
Test name
Test status
Simulation time 2199508541 ps
CPU time 45.07 seconds
Started Apr 15 02:22:37 PM PDT 24
Finished Apr 15 02:23:23 PM PDT 24
Peak memory 222320 kb
Host smart-59038258-e5ce-464d-817c-bb9e87f74c72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1933800458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1933800458
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2922781642
Short name T348
Test name
Test status
Simulation time 356175643 ps
CPU time 7.17 seconds
Started Apr 15 02:22:44 PM PDT 24
Finished Apr 15 02:22:52 PM PDT 24
Peak memory 199584 kb
Host smart-90bb6b90-f20a-4186-9c36-8a223ded2f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922781642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2922781642
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.3169239508
Short name T587
Test name
Test status
Simulation time 1682851460 ps
CPU time 94.83 seconds
Started Apr 15 02:22:39 PM PDT 24
Finished Apr 15 02:24:14 PM PDT 24
Peak memory 199608 kb
Host smart-633ee529-c9fc-4a06-af02-3c69f753f1d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3169239508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3169239508
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.925726166
Short name T44
Test name
Test status
Simulation time 560876759 ps
CPU time 5.59 seconds
Started Apr 15 02:22:42 PM PDT 24
Finished Apr 15 02:22:48 PM PDT 24
Peak memory 199596 kb
Host smart-2091fa50-f3e0-437a-bb80-a955884725aa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925726166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.925726166
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.435292199
Short name T437
Test name
Test status
Simulation time 33507733857 ps
CPU time 117.15 seconds
Started Apr 15 02:22:38 PM PDT 24
Finished Apr 15 02:24:35 PM PDT 24
Peak memory 199744 kb
Host smart-43a81e9e-fb59-4adc-8686-77741da260d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435292199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.435292199
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.1158853968
Short name T594
Test name
Test status
Simulation time 458152096 ps
CPU time 1.2 seconds
Started Apr 15 02:22:39 PM PDT 24
Finished Apr 15 02:22:41 PM PDT 24
Peak memory 199604 kb
Host smart-183cc200-8893-435c-9c64-9c8229516f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158853968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.1158853968
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1209289839
Short name T69
Test name
Test status
Simulation time 12438721421 ps
CPU time 194.2 seconds
Started Apr 15 02:22:47 PM PDT 24
Finished Apr 15 02:26:02 PM PDT 24
Peak memory 214092 kb
Host smart-b3b21957-0689-43c4-9b9d-dffbec9648a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209289839 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1209289839
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.2005416547
Short name T183
Test name
Test status
Simulation time 31489789 ps
CPU time 1.2 seconds
Started Apr 15 02:22:43 PM PDT 24
Finished Apr 15 02:22:45 PM PDT 24
Peak memory 199544 kb
Host smart-6d6a7181-b875-4bda-8530-dba488aa6ef6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005416547 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.2005416547
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.3739142208
Short name T581
Test name
Test status
Simulation time 7625966278 ps
CPU time 417.29 seconds
Started Apr 15 02:22:42 PM PDT 24
Finished Apr 15 02:29:40 PM PDT 24
Peak memory 199708 kb
Host smart-dff326b9-af50-4b3a-b3ae-2f409bff03ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739142208 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.3739142208
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.1563094277
Short name T313
Test name
Test status
Simulation time 4268503478 ps
CPU time 58.38 seconds
Started Apr 15 02:22:42 PM PDT 24
Finished Apr 15 02:23:42 PM PDT 24
Peak memory 199728 kb
Host smart-b8d60052-716c-4ad7-892c-673858ff06ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563094277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1563094277
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.526967781
Short name T344
Test name
Test status
Simulation time 11117222 ps
CPU time 0.55 seconds
Started Apr 15 02:22:46 PM PDT 24
Finished Apr 15 02:22:47 PM PDT 24
Peak memory 194060 kb
Host smart-f465f70a-3173-4ac7-be3a-7a70efce8fc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526967781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.526967781
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.1618271871
Short name T51
Test name
Test status
Simulation time 4819018974 ps
CPU time 43.72 seconds
Started Apr 15 02:22:44 PM PDT 24
Finished Apr 15 02:23:28 PM PDT 24
Peak memory 216136 kb
Host smart-f454470e-2801-496b-9725-6913104e98cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1618271871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.1618271871
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.3947960508
Short name T359
Test name
Test status
Simulation time 4614958827 ps
CPU time 45.98 seconds
Started Apr 15 02:22:43 PM PDT 24
Finished Apr 15 02:23:30 PM PDT 24
Peak memory 199672 kb
Host smart-c922d083-f2c1-42e9-bc4b-118561d74b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947960508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.3947960508
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1231731474
Short name T545
Test name
Test status
Simulation time 22646258861 ps
CPU time 157.14 seconds
Started Apr 15 02:22:42 PM PDT 24
Finished Apr 15 02:25:20 PM PDT 24
Peak memory 199716 kb
Host smart-380ed73f-6de3-46dc-a0c5-55d02479982e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1231731474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1231731474
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.352977584
Short name T36
Test name
Test status
Simulation time 8984693212 ps
CPU time 92.03 seconds
Started Apr 15 02:22:43 PM PDT 24
Finished Apr 15 02:24:15 PM PDT 24
Peak memory 199740 kb
Host smart-eab7b769-049a-4ec2-8551-3d4c06603750
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352977584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.352977584
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1915535588
Short name T506
Test name
Test status
Simulation time 5639608263 ps
CPU time 92.56 seconds
Started Apr 15 02:22:43 PM PDT 24
Finished Apr 15 02:24:17 PM PDT 24
Peak memory 199764 kb
Host smart-86259ef2-a943-422c-81fa-2372bc810f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915535588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1915535588
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2419105553
Short name T84
Test name
Test status
Simulation time 601067956 ps
CPU time 4.84 seconds
Started Apr 15 02:22:47 PM PDT 24
Finished Apr 15 02:22:52 PM PDT 24
Peak memory 199624 kb
Host smart-a2400597-87b5-4620-8965-f28c96a6b2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419105553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2419105553
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.1869961116
Short name T45
Test name
Test status
Simulation time 123666388997 ps
CPU time 2086.13 seconds
Started Apr 15 02:22:46 PM PDT 24
Finished Apr 15 02:57:33 PM PDT 24
Peak memory 240704 kb
Host smart-dce10645-f501-49a9-a525-8e07e6c222d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869961116 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1869961116
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.1254327443
Short name T402
Test name
Test status
Simulation time 470191789 ps
CPU time 1.3 seconds
Started Apr 15 02:22:48 PM PDT 24
Finished Apr 15 02:22:50 PM PDT 24
Peak memory 199488 kb
Host smart-72d1100e-5bd2-42c5-96c9-372d18add97f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254327443 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.1254327443
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.1872919870
Short name T198
Test name
Test status
Simulation time 97002479944 ps
CPU time 505.76 seconds
Started Apr 15 02:22:47 PM PDT 24
Finished Apr 15 02:31:14 PM PDT 24
Peak memory 199380 kb
Host smart-ddd50fd3-83fb-4de7-b6b3-7f2f84c0cf89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872919870 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.1872919870
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2842924103
Short name T137
Test name
Test status
Simulation time 6160189539 ps
CPU time 83.41 seconds
Started Apr 15 02:22:44 PM PDT 24
Finished Apr 15 02:24:08 PM PDT 24
Peak memory 199732 kb
Host smart-5e19f0d8-ceaa-43f0-808b-52b78036af24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842924103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2842924103
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.3061837181
Short name T270
Test name
Test status
Simulation time 43775770 ps
CPU time 0.6 seconds
Started Apr 15 02:22:48 PM PDT 24
Finished Apr 15 02:22:49 PM PDT 24
Peak memory 195164 kb
Host smart-25f50a9a-802d-4c1e-be35-c097dad33824
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061837181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3061837181
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.3689348575
Short name T479
Test name
Test status
Simulation time 1333990718 ps
CPU time 17.62 seconds
Started Apr 15 02:22:48 PM PDT 24
Finished Apr 15 02:23:07 PM PDT 24
Peak memory 215980 kb
Host smart-4696ce17-00a1-40b4-93cd-3d31947bb840
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3689348575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3689348575
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1164859963
Short name T471
Test name
Test status
Simulation time 560692107 ps
CPU time 27.64 seconds
Started Apr 15 02:22:46 PM PDT 24
Finished Apr 15 02:23:15 PM PDT 24
Peak memory 199600 kb
Host smart-a244192b-d563-44f6-8793-bf83dad19e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164859963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1164859963
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1625856948
Short name T158
Test name
Test status
Simulation time 6429280265 ps
CPU time 86.3 seconds
Started Apr 15 02:22:49 PM PDT 24
Finished Apr 15 02:24:16 PM PDT 24
Peak memory 199712 kb
Host smart-4439cffc-0d9f-4055-906a-ac820a4b2ff4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1625856948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1625856948
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1098646927
Short name T489
Test name
Test status
Simulation time 168316450 ps
CPU time 8.87 seconds
Started Apr 15 02:22:47 PM PDT 24
Finished Apr 15 02:22:57 PM PDT 24
Peak memory 199600 kb
Host smart-0af0494f-b7fc-43ca-bf58-1e6a4545b65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098646927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1098646927
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1773919901
Short name T477
Test name
Test status
Simulation time 88940850 ps
CPU time 0.82 seconds
Started Apr 15 02:22:48 PM PDT 24
Finished Apr 15 02:22:49 PM PDT 24
Peak memory 197936 kb
Host smart-c1e04e0b-73d0-493c-b51c-c52609f00ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773919901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1773919901
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.721629044
Short name T235
Test name
Test status
Simulation time 4546062397 ps
CPU time 196.42 seconds
Started Apr 15 02:22:50 PM PDT 24
Finished Apr 15 02:26:07 PM PDT 24
Peak memory 215600 kb
Host smart-1cc76d28-906a-4973-8956-7065daaa9294
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721629044 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.721629044
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.2192688899
Short name T464
Test name
Test status
Simulation time 99195315 ps
CPU time 0.91 seconds
Started Apr 15 02:22:47 PM PDT 24
Finished Apr 15 02:22:48 PM PDT 24
Peak memory 197604 kb
Host smart-5a4e5ac3-8805-48c7-a3da-1c8eb13827c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192688899 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.2192688899
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.1591405743
Short name T332
Test name
Test status
Simulation time 116938390977 ps
CPU time 567.29 seconds
Started Apr 15 02:22:48 PM PDT 24
Finished Apr 15 02:32:16 PM PDT 24
Peak memory 199648 kb
Host smart-d407639c-009c-4448-a975-1c2ea1a03461
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591405743 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.1591405743
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3737927691
Short name T406
Test name
Test status
Simulation time 1890883956 ps
CPU time 25.62 seconds
Started Apr 15 02:22:46 PM PDT 24
Finished Apr 15 02:23:13 PM PDT 24
Peak memory 199600 kb
Host smart-78630304-80dc-4f43-8a80-808f4ceff204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737927691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3737927691
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.1163673521
Short name T227
Test name
Test status
Simulation time 11178668 ps
CPU time 0.57 seconds
Started Apr 15 02:22:55 PM PDT 24
Finished Apr 15 02:22:56 PM PDT 24
Peak memory 195172 kb
Host smart-aa7e35a2-5a32-4c25-95ed-533796073ec9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163673521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.1163673521
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.4292328703
Short name T347
Test name
Test status
Simulation time 899487800 ps
CPU time 34.24 seconds
Started Apr 15 02:22:52 PM PDT 24
Finished Apr 15 02:23:28 PM PDT 24
Peak memory 207808 kb
Host smart-73813ec0-0aff-4de1-b2ce-058a45b46206
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4292328703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.4292328703
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3830968033
Short name T490
Test name
Test status
Simulation time 1993796093 ps
CPU time 41.3 seconds
Started Apr 15 02:22:52 PM PDT 24
Finished Apr 15 02:23:35 PM PDT 24
Peak memory 199604 kb
Host smart-a1b75c71-49ec-4df5-ba00-4738ea8b1b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830968033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3830968033
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.4089700769
Short name T432
Test name
Test status
Simulation time 19526069670 ps
CPU time 127.7 seconds
Started Apr 15 02:22:51 PM PDT 24
Finished Apr 15 02:24:59 PM PDT 24
Peak memory 199732 kb
Host smart-4cd98fca-a19a-436b-bb48-a6764ca569fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4089700769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.4089700769
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.948535827
Short name T178
Test name
Test status
Simulation time 38587397186 ps
CPU time 121.77 seconds
Started Apr 15 02:22:53 PM PDT 24
Finished Apr 15 02:24:55 PM PDT 24
Peak memory 199628 kb
Host smart-bf2223db-46d4-4bf0-b590-e223c3727cd5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948535827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.948535827
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2945237385
Short name T87
Test name
Test status
Simulation time 1368061332 ps
CPU time 84.96 seconds
Started Apr 15 02:22:52 PM PDT 24
Finished Apr 15 02:24:18 PM PDT 24
Peak memory 199540 kb
Host smart-a84cedad-989a-4122-b999-bb78c3d4aef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945237385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2945237385
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1751423906
Short name T497
Test name
Test status
Simulation time 2168207182 ps
CPU time 4.52 seconds
Started Apr 15 02:22:50 PM PDT 24
Finished Apr 15 02:22:55 PM PDT 24
Peak memory 199680 kb
Host smart-e4cfbdcc-0fb8-4112-b244-501ea2b2af4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751423906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1751423906
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3949739037
Short name T74
Test name
Test status
Simulation time 535807295424 ps
CPU time 1107.79 seconds
Started Apr 15 02:22:52 PM PDT 24
Finished Apr 15 02:41:21 PM PDT 24
Peak memory 226156 kb
Host smart-73799fae-cbc3-4ead-bf43-c4f5798b5c37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949739037 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3949739037
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.3544470664
Short name T475
Test name
Test status
Simulation time 32356366 ps
CPU time 1.17 seconds
Started Apr 15 02:22:50 PM PDT 24
Finished Apr 15 02:22:52 PM PDT 24
Peak memory 199560 kb
Host smart-64546d49-703d-42f9-9a27-e4e415ef7458
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544470664 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.3544470664
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.4252537553
Short name T153
Test name
Test status
Simulation time 168292721810 ps
CPU time 432.36 seconds
Started Apr 15 02:22:53 PM PDT 24
Finished Apr 15 02:30:06 PM PDT 24
Peak memory 199720 kb
Host smart-b7c04404-6341-4e96-ace0-a1ee869ba76d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252537553 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.4252537553
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.1996896383
Short name T180
Test name
Test status
Simulation time 4360003739 ps
CPU time 16.07 seconds
Started Apr 15 02:22:50 PM PDT 24
Finished Apr 15 02:23:07 PM PDT 24
Peak memory 199744 kb
Host smart-e1d3d9da-6143-4888-b17b-995d094034dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996896383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1996896383
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2916266365
Short name T321
Test name
Test status
Simulation time 65655532 ps
CPU time 0.62 seconds
Started Apr 15 02:23:02 PM PDT 24
Finished Apr 15 02:23:04 PM PDT 24
Peak memory 194088 kb
Host smart-680433ad-cdf0-47e9-b89b-00e77f8d484d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916266365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2916266365
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.726134709
Short name T252
Test name
Test status
Simulation time 265006225 ps
CPU time 2.5 seconds
Started Apr 15 02:22:56 PM PDT 24
Finished Apr 15 02:22:59 PM PDT 24
Peak memory 199504 kb
Host smart-75ac2631-e54d-452d-b8a9-823fa593b12e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=726134709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.726134709
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3541941646
Short name T566
Test name
Test status
Simulation time 4395117898 ps
CPU time 19.21 seconds
Started Apr 15 02:22:56 PM PDT 24
Finished Apr 15 02:23:16 PM PDT 24
Peak memory 199696 kb
Host smart-f229f3f3-c482-4734-a257-04ac261bc661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541941646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3541941646
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.278730866
Short name T580
Test name
Test status
Simulation time 8610117253 ps
CPU time 137.47 seconds
Started Apr 15 02:23:00 PM PDT 24
Finished Apr 15 02:25:18 PM PDT 24
Peak memory 199696 kb
Host smart-8225921a-a704-4910-bab4-bc8ce5201478
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=278730866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.278730866
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.668864832
Short name T532
Test name
Test status
Simulation time 34412562744 ps
CPU time 136.57 seconds
Started Apr 15 02:22:56 PM PDT 24
Finished Apr 15 02:25:14 PM PDT 24
Peak memory 199744 kb
Host smart-41e1bbe9-7547-4539-ade5-23da8003d2e6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668864832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.668864832
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.933272373
Short name T527
Test name
Test status
Simulation time 10823011305 ps
CPU time 52.31 seconds
Started Apr 15 02:22:57 PM PDT 24
Finished Apr 15 02:23:50 PM PDT 24
Peak memory 199696 kb
Host smart-832bc78f-0966-4bc0-93ec-ecdc174db1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933272373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.933272373
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2597526641
Short name T375
Test name
Test status
Simulation time 533392154 ps
CPU time 6.2 seconds
Started Apr 15 02:22:56 PM PDT 24
Finished Apr 15 02:23:03 PM PDT 24
Peak memory 199600 kb
Host smart-aa180f40-c426-49e4-bad3-d82d03ae2820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597526641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2597526641
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.3712595769
Short name T71
Test name
Test status
Simulation time 377356615046 ps
CPU time 1195.49 seconds
Started Apr 15 02:22:57 PM PDT 24
Finished Apr 15 02:42:53 PM PDT 24
Peak memory 199672 kb
Host smart-c0a6121e-5e28-42e8-b029-22eb92b9478d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712595769 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.3712595769
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.1477158638
Short name T379
Test name
Test status
Simulation time 75914166 ps
CPU time 1.05 seconds
Started Apr 15 02:22:58 PM PDT 24
Finished Apr 15 02:22:59 PM PDT 24
Peak memory 197956 kb
Host smart-7796c3af-3e93-4286-9697-f98fadc45da0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477158638 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.1477158638
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.2390974641
Short name T443
Test name
Test status
Simulation time 137692071533 ps
CPU time 441.74 seconds
Started Apr 15 02:23:02 PM PDT 24
Finished Apr 15 02:30:25 PM PDT 24
Peak memory 199684 kb
Host smart-51f5b3e4-8125-41e4-9e05-c8a3f44ae2f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390974641 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.2390974641
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3870997508
Short name T571
Test name
Test status
Simulation time 777091998 ps
CPU time 13.84 seconds
Started Apr 15 02:22:54 PM PDT 24
Finished Apr 15 02:23:09 PM PDT 24
Peak memory 199620 kb
Host smart-11310643-f65f-4b77-998b-0fda9de6ff00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870997508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3870997508
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.280358238
Short name T283
Test name
Test status
Simulation time 55649395 ps
CPU time 0.57 seconds
Started Apr 15 02:23:05 PM PDT 24
Finished Apr 15 02:23:07 PM PDT 24
Peak memory 195104 kb
Host smart-a5a90c53-5825-4e37-bcf0-4cbcf941c9d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280358238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.280358238
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.231200978
Short name T445
Test name
Test status
Simulation time 8736468075 ps
CPU time 22.77 seconds
Started Apr 15 02:23:01 PM PDT 24
Finished Apr 15 02:23:24 PM PDT 24
Peak memory 199728 kb
Host smart-ddf12a87-33f3-4912-83f9-e75518c44202
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=231200978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.231200978
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.3892343673
Short name T558
Test name
Test status
Simulation time 577135369 ps
CPU time 28.75 seconds
Started Apr 15 02:23:05 PM PDT 24
Finished Apr 15 02:23:35 PM PDT 24
Peak memory 199556 kb
Host smart-5465ebd4-ffb6-421d-8b8f-b29b15fe16b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892343673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.3892343673
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.405133193
Short name T303
Test name
Test status
Simulation time 60176166 ps
CPU time 0.69 seconds
Started Apr 15 02:23:00 PM PDT 24
Finished Apr 15 02:23:01 PM PDT 24
Peak memory 196828 kb
Host smart-61111165-9f45-47de-8db0-66a1c2e4e0bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=405133193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.405133193
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.1392812753
Short name T295
Test name
Test status
Simulation time 24291661590 ps
CPU time 181.89 seconds
Started Apr 15 02:23:00 PM PDT 24
Finished Apr 15 02:26:02 PM PDT 24
Peak memory 199736 kb
Host smart-7dab78bb-aa39-4a4b-8385-99073103aa25
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392812753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1392812753
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2364237541
Short name T470
Test name
Test status
Simulation time 1989791703 ps
CPU time 77.55 seconds
Started Apr 15 02:23:02 PM PDT 24
Finished Apr 15 02:24:21 PM PDT 24
Peak memory 199612 kb
Host smart-b1452011-a241-404b-84db-92f3e5cff885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364237541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2364237541
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3148100656
Short name T193
Test name
Test status
Simulation time 227452813 ps
CPU time 2.93 seconds
Started Apr 15 02:23:05 PM PDT 24
Finished Apr 15 02:23:09 PM PDT 24
Peak memory 199552 kb
Host smart-3e08221c-a1b9-49a6-872d-243424a6fff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148100656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3148100656
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3221679910
Short name T91
Test name
Test status
Simulation time 60637559217 ps
CPU time 1696.48 seconds
Started Apr 15 02:23:01 PM PDT 24
Finished Apr 15 02:51:19 PM PDT 24
Peak memory 199652 kb
Host smart-4ca01ef8-9e72-4ed8-b8e1-46c40e3bd8dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221679910 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3221679910
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.446362588
Short name T561
Test name
Test status
Simulation time 198297944 ps
CPU time 1.39 seconds
Started Apr 15 02:23:01 PM PDT 24
Finished Apr 15 02:23:04 PM PDT 24
Peak memory 199540 kb
Host smart-9362554a-7658-488c-84e2-3b4fc4855a58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446362588 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_hmac_vectors.446362588
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.1851407759
Short name T319
Test name
Test status
Simulation time 124390069570 ps
CPU time 497.69 seconds
Started Apr 15 02:23:07 PM PDT 24
Finished Apr 15 02:31:26 PM PDT 24
Peak memory 199552 kb
Host smart-ec2c1e23-94bd-45f0-941e-503a0d1e03ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851407759 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.1851407759
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.111274552
Short name T315
Test name
Test status
Simulation time 5694508765 ps
CPU time 53.97 seconds
Started Apr 15 02:23:04 PM PDT 24
Finished Apr 15 02:23:59 PM PDT 24
Peak memory 199596 kb
Host smart-805257e1-02e8-40ad-b08b-4df582ff90eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111274552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.111274552
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.3849047313
Short name T453
Test name
Test status
Simulation time 31329169 ps
CPU time 0.54 seconds
Started Apr 15 02:23:07 PM PDT 24
Finished Apr 15 02:23:09 PM PDT 24
Peak memory 194012 kb
Host smart-d16da823-8445-466a-aa75-3b89a60aac7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849047313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3849047313
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1754958183
Short name T161
Test name
Test status
Simulation time 445932349 ps
CPU time 15.79 seconds
Started Apr 15 02:23:01 PM PDT 24
Finished Apr 15 02:23:18 PM PDT 24
Peak memory 207744 kb
Host smart-22374250-fe1f-4ac9-9131-aa2d9159a1f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1754958183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1754958183
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.407793612
Short name T380
Test name
Test status
Simulation time 4491411079 ps
CPU time 13.69 seconds
Started Apr 15 02:23:05 PM PDT 24
Finished Apr 15 02:23:20 PM PDT 24
Peak memory 199700 kb
Host smart-db474d65-9b69-46cb-ba96-050e64b671ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407793612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.407793612
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1334786699
Short name T452
Test name
Test status
Simulation time 6314615738 ps
CPU time 89.56 seconds
Started Apr 15 02:23:02 PM PDT 24
Finished Apr 15 02:24:33 PM PDT 24
Peak memory 199716 kb
Host smart-05875048-74f0-4add-89b8-2fa259ea0628
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1334786699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1334786699
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3357594364
Short name T146
Test name
Test status
Simulation time 12659571025 ps
CPU time 165.19 seconds
Started Apr 15 02:23:04 PM PDT 24
Finished Apr 15 02:25:50 PM PDT 24
Peak memory 199732 kb
Host smart-2eb81ee9-054f-4aeb-9236-8d2fffaf3207
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357594364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3357594364
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3403753711
Short name T590
Test name
Test status
Simulation time 24210231954 ps
CPU time 97.35 seconds
Started Apr 15 02:23:00 PM PDT 24
Finished Apr 15 02:24:38 PM PDT 24
Peak memory 199732 kb
Host smart-ac3b4083-b680-47f7-8cb4-0ca5d8c4b5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403753711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3403753711
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.3454785012
Short name T372
Test name
Test status
Simulation time 425644066 ps
CPU time 3.34 seconds
Started Apr 15 02:23:05 PM PDT 24
Finished Apr 15 02:23:09 PM PDT 24
Peak memory 199532 kb
Host smart-6d401dc8-273e-41fb-8e05-70d4eb53209a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454785012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3454785012
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3970012323
Short name T404
Test name
Test status
Simulation time 20408426732 ps
CPU time 95.7 seconds
Started Apr 15 02:23:07 PM PDT 24
Finished Apr 15 02:24:43 PM PDT 24
Peak memory 199724 kb
Host smart-ddcc611a-1663-4cf6-a062-727677300bb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970012323 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3970012323
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.3479942835
Short name T370
Test name
Test status
Simulation time 57230616 ps
CPU time 1.07 seconds
Started Apr 15 02:23:07 PM PDT 24
Finished Apr 15 02:23:09 PM PDT 24
Peak memory 197888 kb
Host smart-f2f8b0f4-8791-4bd4-a1d0-d32980b3a532
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479942835 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.3479942835
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.4073806537
Short name T338
Test name
Test status
Simulation time 11614390112 ps
CPU time 446.08 seconds
Started Apr 15 02:23:08 PM PDT 24
Finished Apr 15 02:30:34 PM PDT 24
Peak memory 199740 kb
Host smart-eefb625d-8c36-4166-8457-1b273b83a4f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073806537 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.4073806537
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.683632084
Short name T430
Test name
Test status
Simulation time 2347593175 ps
CPU time 30.58 seconds
Started Apr 15 02:23:07 PM PDT 24
Finished Apr 15 02:23:38 PM PDT 24
Peak memory 199728 kb
Host smart-7a55bddf-84d0-4a54-91a7-d914f94095ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683632084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.683632084
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1332396520
Short name T173
Test name
Test status
Simulation time 21612135 ps
CPU time 0.6 seconds
Started Apr 15 02:23:11 PM PDT 24
Finished Apr 15 02:23:12 PM PDT 24
Peak memory 194120 kb
Host smart-b698fb2e-413a-459e-a744-b080590dd77d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332396520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1332396520
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1235867037
Short name T355
Test name
Test status
Simulation time 838542809 ps
CPU time 14.41 seconds
Started Apr 15 02:23:04 PM PDT 24
Finished Apr 15 02:23:20 PM PDT 24
Peak memory 207820 kb
Host smart-e92e5504-0b7b-42f2-b840-b3271d436f27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1235867037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1235867037
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.907595469
Short name T547
Test name
Test status
Simulation time 1292089809 ps
CPU time 20.21 seconds
Started Apr 15 02:23:07 PM PDT 24
Finished Apr 15 02:23:29 PM PDT 24
Peak memory 199544 kb
Host smart-e3e7b40b-261b-4736-978c-19d8fc5b24be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907595469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.907595469
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.1303787349
Short name T382
Test name
Test status
Simulation time 4604596930 ps
CPU time 43.43 seconds
Started Apr 15 02:23:04 PM PDT 24
Finished Apr 15 02:23:49 PM PDT 24
Peak memory 199624 kb
Host smart-72d6e2f9-6069-40e7-a8db-8d7873f4862e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1303787349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1303787349
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1498132555
Short name T34
Test name
Test status
Simulation time 2155842500 ps
CPU time 12.6 seconds
Started Apr 15 02:23:09 PM PDT 24
Finished Apr 15 02:23:22 PM PDT 24
Peak memory 199676 kb
Host smart-7a92b5e6-6f3e-4c28-89fc-544dc1472d2b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498132555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1498132555
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.895449495
Short name T588
Test name
Test status
Simulation time 6315444771 ps
CPU time 96 seconds
Started Apr 15 02:23:04 PM PDT 24
Finished Apr 15 02:24:41 PM PDT 24
Peak memory 199728 kb
Host smart-7f8c0d71-66df-47e5-9a66-883b4f207ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895449495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.895449495
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.2427367526
Short name T345
Test name
Test status
Simulation time 492484703 ps
CPU time 1.64 seconds
Started Apr 15 02:23:03 PM PDT 24
Finished Apr 15 02:23:06 PM PDT 24
Peak memory 199544 kb
Host smart-b4a9acf8-e3de-4dd2-965e-b44d2b25058a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427367526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2427367526
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3592360480
Short name T70
Test name
Test status
Simulation time 298689571498 ps
CPU time 1449.46 seconds
Started Apr 15 02:23:08 PM PDT 24
Finished Apr 15 02:47:19 PM PDT 24
Peak memory 248220 kb
Host smart-d575e4f8-ea6a-4a6d-b023-19f4bae4993f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592360480 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3592360480
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.2766750370
Short name T513
Test name
Test status
Simulation time 311861009 ps
CPU time 1.01 seconds
Started Apr 15 02:23:11 PM PDT 24
Finished Apr 15 02:23:13 PM PDT 24
Peak memory 198988 kb
Host smart-97540387-a8e5-49cd-8e88-a1517b2dc4e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766750370 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.2766750370
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.2126061304
Short name T467
Test name
Test status
Simulation time 134955536166 ps
CPU time 427.78 seconds
Started Apr 15 02:23:09 PM PDT 24
Finished Apr 15 02:30:17 PM PDT 24
Peak memory 199740 kb
Host smart-17a416fd-7efb-4901-a6ae-12cfc617cbae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126061304 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.2126061304
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.2628862792
Short name T354
Test name
Test status
Simulation time 1951826997 ps
CPU time 39 seconds
Started Apr 15 02:23:08 PM PDT 24
Finished Apr 15 02:23:49 PM PDT 24
Peak memory 199572 kb
Host smart-baeaff2b-9be7-47b0-b088-0a996be66ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628862792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2628862792
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.524570736
Short name T20
Test name
Test status
Simulation time 20742865 ps
CPU time 0.55 seconds
Started Apr 15 02:23:13 PM PDT 24
Finished Apr 15 02:23:14 PM PDT 24
Peak memory 194072 kb
Host smart-0e7a6047-2d22-4607-922b-f1ff0f37e6ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524570736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.524570736
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1554665668
Short name T512
Test name
Test status
Simulation time 1185241595 ps
CPU time 30.74 seconds
Started Apr 15 02:23:08 PM PDT 24
Finished Apr 15 02:23:40 PM PDT 24
Peak memory 215208 kb
Host smart-8665b208-9d90-40f0-9ed1-f738fa72ef57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1554665668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1554665668
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2041984414
Short name T314
Test name
Test status
Simulation time 562852098 ps
CPU time 9.77 seconds
Started Apr 15 02:23:09 PM PDT 24
Finished Apr 15 02:23:20 PM PDT 24
Peak memory 199620 kb
Host smart-c6bf9ff0-38c2-408e-9813-a52ebc5ae01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041984414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2041984414
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.2167041689
Short name T478
Test name
Test status
Simulation time 3587922597 ps
CPU time 52.27 seconds
Started Apr 15 02:23:09 PM PDT 24
Finished Apr 15 02:24:02 PM PDT 24
Peak memory 199768 kb
Host smart-896a19d4-e7a8-44e8-8bca-b1f6e134aaa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2167041689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2167041689
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.761091110
Short name T323
Test name
Test status
Simulation time 27843920746 ps
CPU time 120.49 seconds
Started Apr 15 02:23:12 PM PDT 24
Finished Apr 15 02:25:14 PM PDT 24
Peak memory 199692 kb
Host smart-951cdac9-6325-4c76-a358-3e6d11a65d86
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761091110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.761091110
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.895745906
Short name T415
Test name
Test status
Simulation time 7729243084 ps
CPU time 105.88 seconds
Started Apr 15 02:23:08 PM PDT 24
Finished Apr 15 02:24:55 PM PDT 24
Peak memory 199724 kb
Host smart-ca506327-c006-4771-871d-b20edbe06e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895745906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.895745906
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.753583925
Short name T387
Test name
Test status
Simulation time 265372510 ps
CPU time 1.4 seconds
Started Apr 15 02:23:09 PM PDT 24
Finished Apr 15 02:23:11 PM PDT 24
Peak memory 199612 kb
Host smart-025bd145-5852-4efe-9379-c134976efa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753583925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.753583925
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.855279253
Short name T427
Test name
Test status
Simulation time 409482151706 ps
CPU time 3558.64 seconds
Started Apr 15 02:23:17 PM PDT 24
Finished Apr 15 03:22:37 PM PDT 24
Peak memory 199612 kb
Host smart-48df8230-3084-4cbf-9237-9620db5b98f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855279253 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.855279253
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.2408380942
Short name T465
Test name
Test status
Simulation time 29682843 ps
CPU time 1.01 seconds
Started Apr 15 02:23:13 PM PDT 24
Finished Apr 15 02:23:15 PM PDT 24
Peak memory 198892 kb
Host smart-6b6e156d-c1b3-48fc-afaf-f8e960f75ad2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408380942 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.2408380942
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.3050091224
Short name T269
Test name
Test status
Simulation time 58206817612 ps
CPU time 517.88 seconds
Started Apr 15 02:23:12 PM PDT 24
Finished Apr 15 02:31:51 PM PDT 24
Peak memory 199640 kb
Host smart-7861efef-5cc8-4998-b0ce-9c9f71eca845
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050091224 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.3050091224
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.3444434285
Short name T339
Test name
Test status
Simulation time 5126865079 ps
CPU time 63.98 seconds
Started Apr 15 02:23:14 PM PDT 24
Finished Apr 15 02:24:19 PM PDT 24
Peak memory 199676 kb
Host smart-17ef1181-38b7-4880-90aa-5fb561cdef78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444434285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3444434285
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.958904488
Short name T597
Test name
Test status
Simulation time 12180737 ps
CPU time 0.56 seconds
Started Apr 15 02:21:42 PM PDT 24
Finished Apr 15 02:21:47 PM PDT 24
Peak memory 195140 kb
Host smart-3f05b62c-e5a6-4387-b0f3-9222e88f9d66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958904488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.958904488
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.1656645211
Short name T224
Test name
Test status
Simulation time 4323555116 ps
CPU time 43.68 seconds
Started Apr 15 02:21:40 PM PDT 24
Finished Apr 15 02:22:26 PM PDT 24
Peak memory 231592 kb
Host smart-1aac85cf-3da2-46af-97e2-0ce8deeb5a46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1656645211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1656645211
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3218463964
Short name T86
Test name
Test status
Simulation time 17234539020 ps
CPU time 64.52 seconds
Started Apr 15 02:21:49 PM PDT 24
Finished Apr 15 02:22:58 PM PDT 24
Peak memory 199672 kb
Host smart-2e93b91f-30d8-4db1-a66f-248f022d8068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218463964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3218463964
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3205412925
Short name T285
Test name
Test status
Simulation time 1123807804 ps
CPU time 68.93 seconds
Started Apr 15 02:21:40 PM PDT 24
Finished Apr 15 02:22:52 PM PDT 24
Peak memory 199788 kb
Host smart-07c96414-5523-4386-abe8-3c829b0c619f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3205412925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3205412925
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.223221729
Short name T46
Test name
Test status
Simulation time 72926343230 ps
CPU time 247.33 seconds
Started Apr 15 02:21:45 PM PDT 24
Finished Apr 15 02:25:57 PM PDT 24
Peak memory 199724 kb
Host smart-ccbf2c7d-4361-4cf4-8079-27d0d979915c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223221729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.223221729
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.1904759850
Short name T326
Test name
Test status
Simulation time 457370612 ps
CPU time 25.04 seconds
Started Apr 15 02:21:39 PM PDT 24
Finished Apr 15 02:22:07 PM PDT 24
Peak memory 199600 kb
Host smart-cb407bae-9d37-49a8-8999-c1fe9e0ee25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904759850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1904759850
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1338537536
Short name T29
Test name
Test status
Simulation time 83906356 ps
CPU time 0.96 seconds
Started Apr 15 02:21:42 PM PDT 24
Finished Apr 15 02:21:47 PM PDT 24
Peak memory 219224 kb
Host smart-1f73012e-b699-437c-8dd1-0149070f907e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338537536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1338537536
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.1549464360
Short name T407
Test name
Test status
Simulation time 51667107 ps
CPU time 1.58 seconds
Started Apr 15 02:21:40 PM PDT 24
Finished Apr 15 02:21:44 PM PDT 24
Peak memory 199516 kb
Host smart-234c31a3-999f-4fda-a6fb-9758bc966b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549464360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1549464360
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3146578597
Short name T459
Test name
Test status
Simulation time 59549438861 ps
CPU time 1558.78 seconds
Started Apr 15 02:21:45 PM PDT 24
Finished Apr 15 02:47:49 PM PDT 24
Peak memory 237588 kb
Host smart-cd92abc6-d9b9-4b3b-a633-c7a3ad986663
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146578597 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3146578597
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.2697675863
Short name T122
Test name
Test status
Simulation time 58855440 ps
CPU time 1.18 seconds
Started Apr 15 02:21:43 PM PDT 24
Finished Apr 15 02:21:49 PM PDT 24
Peak memory 199524 kb
Host smart-6df6fde3-fcfb-4574-8f85-de4bcb90840a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697675863 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.2697675863
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.1447775577
Short name T325
Test name
Test status
Simulation time 30116622140 ps
CPU time 402.91 seconds
Started Apr 15 02:21:44 PM PDT 24
Finished Apr 15 02:28:31 PM PDT 24
Peak memory 199740 kb
Host smart-4c81db23-3b81-4c7b-9856-2edb0136072f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447775577 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.1447775577
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.2426865596
Short name T496
Test name
Test status
Simulation time 7215404355 ps
CPU time 37.52 seconds
Started Apr 15 02:21:43 PM PDT 24
Finished Apr 15 02:22:25 PM PDT 24
Peak memory 199728 kb
Host smart-c77d7bbc-d8e6-4564-9f18-325646a676ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426865596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2426865596
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1466331580
Short name T278
Test name
Test status
Simulation time 12949276 ps
CPU time 0.56 seconds
Started Apr 15 02:23:17 PM PDT 24
Finished Apr 15 02:23:18 PM PDT 24
Peak memory 194088 kb
Host smart-37e88c17-a26b-4699-a4c0-afc47e79b31e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466331580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1466331580
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.3447042282
Short name T88
Test name
Test status
Simulation time 1525365904 ps
CPU time 54.5 seconds
Started Apr 15 02:23:14 PM PDT 24
Finished Apr 15 02:24:09 PM PDT 24
Peak memory 211312 kb
Host smart-854a51d4-8f75-4243-89d0-a8c64b4d2291
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3447042282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3447042282
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3322454661
Short name T460
Test name
Test status
Simulation time 6640517309 ps
CPU time 45.56 seconds
Started Apr 15 02:23:13 PM PDT 24
Finished Apr 15 02:24:00 PM PDT 24
Peak memory 199648 kb
Host smart-fb46214a-2687-4198-a85f-3251acaf76d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322454661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3322454661
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2743532382
Short name T187
Test name
Test status
Simulation time 7383118126 ps
CPU time 120.95 seconds
Started Apr 15 02:23:15 PM PDT 24
Finished Apr 15 02:25:17 PM PDT 24
Peak memory 199740 kb
Host smart-1c048a57-35af-4e3a-b532-2629c2e09db1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2743532382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2743532382
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.2945971178
Short name T189
Test name
Test status
Simulation time 3038838811 ps
CPU time 172.46 seconds
Started Apr 15 02:23:13 PM PDT 24
Finished Apr 15 02:26:07 PM PDT 24
Peak memory 199760 kb
Host smart-8984b75f-1bd8-481d-92c9-bd4b57425e90
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945971178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2945971178
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.660136333
Short name T434
Test name
Test status
Simulation time 3326641073 ps
CPU time 64.93 seconds
Started Apr 15 02:23:15 PM PDT 24
Finished Apr 15 02:24:21 PM PDT 24
Peak memory 199736 kb
Host smart-77f85710-e69b-42af-8e07-ee18b94230dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660136333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.660136333
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.880775363
Short name T495
Test name
Test status
Simulation time 84106435 ps
CPU time 2.74 seconds
Started Apr 15 02:23:12 PM PDT 24
Finished Apr 15 02:23:16 PM PDT 24
Peak memory 199604 kb
Host smart-82b8671a-1f3f-4fb4-ab7d-b46fd6a862f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880775363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.880775363
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.301820677
Short name T595
Test name
Test status
Simulation time 225809218366 ps
CPU time 754.99 seconds
Started Apr 15 02:23:19 PM PDT 24
Finished Apr 15 02:35:54 PM PDT 24
Peak memory 199632 kb
Host smart-1f8eabe2-4345-4dc4-b581-d7037d42c962
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301820677 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.301820677
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.4014191163
Short name T33
Test name
Test status
Simulation time 457541985 ps
CPU time 1.23 seconds
Started Apr 15 02:23:18 PM PDT 24
Finished Apr 15 02:23:20 PM PDT 24
Peak memory 199468 kb
Host smart-24393cca-8383-4f1b-a007-f07acc0ce5fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014191163 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.4014191163
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.3790627850
Short name T136
Test name
Test status
Simulation time 517622170477 ps
CPU time 545.16 seconds
Started Apr 15 02:23:18 PM PDT 24
Finished Apr 15 02:32:24 PM PDT 24
Peak memory 199708 kb
Host smart-84033e0b-1701-4c19-9a8b-703d504b458c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790627850 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.3790627850
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3575220933
Short name T150
Test name
Test status
Simulation time 9820683610 ps
CPU time 92.09 seconds
Started Apr 15 02:23:15 PM PDT 24
Finished Apr 15 02:24:48 PM PDT 24
Peak memory 199676 kb
Host smart-8231d3dd-a5dd-4ef5-b89d-af76eca68dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575220933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3575220933
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2301088411
Short name T279
Test name
Test status
Simulation time 1460906514 ps
CPU time 20.93 seconds
Started Apr 15 02:23:22 PM PDT 24
Finished Apr 15 02:23:43 PM PDT 24
Peak memory 240560 kb
Host smart-c9f7ee0e-6cff-4e4b-9dd7-8dd4a92368e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2301088411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2301088411
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.530782063
Short name T171
Test name
Test status
Simulation time 2561515858 ps
CPU time 63.38 seconds
Started Apr 15 02:23:33 PM PDT 24
Finished Apr 15 02:24:37 PM PDT 24
Peak memory 199708 kb
Host smart-b4e61320-6e3a-479a-86be-8d4203722f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530782063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.530782063
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2364073025
Short name T409
Test name
Test status
Simulation time 1922781247 ps
CPU time 117.5 seconds
Started Apr 15 02:23:21 PM PDT 24
Finished Apr 15 02:25:19 PM PDT 24
Peak memory 199544 kb
Host smart-84890df0-ce06-4427-a3f3-e8e0bf3a7d5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2364073025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2364073025
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.1052476196
Short name T211
Test name
Test status
Simulation time 42853260374 ps
CPU time 191.54 seconds
Started Apr 15 02:23:33 PM PDT 24
Finished Apr 15 02:26:45 PM PDT 24
Peak memory 199708 kb
Host smart-9a5f113e-8ef9-48f2-a904-781c16f0f1c5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052476196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1052476196
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.933533748
Short name T386
Test name
Test status
Simulation time 6288078716 ps
CPU time 23.34 seconds
Started Apr 15 02:23:32 PM PDT 24
Finished Apr 15 02:23:56 PM PDT 24
Peak memory 199700 kb
Host smart-4807cbcb-25cd-4b86-ba3a-675ebac95fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933533748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.933533748
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.4103090125
Short name T334
Test name
Test status
Simulation time 133597031 ps
CPU time 1.34 seconds
Started Apr 15 02:23:23 PM PDT 24
Finished Apr 15 02:23:25 PM PDT 24
Peak memory 199556 kb
Host smart-2798c85e-cbb3-4012-bd95-843d6cf6da44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103090125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.4103090125
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2009551731
Short name T376
Test name
Test status
Simulation time 40453357618 ps
CPU time 529.96 seconds
Started Apr 15 02:23:33 PM PDT 24
Finished Apr 15 02:32:24 PM PDT 24
Peak memory 215728 kb
Host smart-565a114a-01a9-494a-a5e1-b118ac9f93c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009551731 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2009551731
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.898364997
Short name T405
Test name
Test status
Simulation time 31680553 ps
CPU time 1.16 seconds
Started Apr 15 02:23:21 PM PDT 24
Finished Apr 15 02:23:23 PM PDT 24
Peak memory 199104 kb
Host smart-7834f029-7032-493a-995a-365510c16f71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898364997 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_hmac_vectors.898364997
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.2491495518
Short name T241
Test name
Test status
Simulation time 8119620900 ps
CPU time 455.57 seconds
Started Apr 15 02:23:23 PM PDT 24
Finished Apr 15 02:30:59 PM PDT 24
Peak memory 199700 kb
Host smart-15ac0501-9564-4e0c-af23-3880c6173695
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491495518 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.2491495518
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.4075537348
Short name T449
Test name
Test status
Simulation time 14946920042 ps
CPU time 27.56 seconds
Started Apr 15 02:23:19 PM PDT 24
Finished Apr 15 02:23:48 PM PDT 24
Peak memory 199628 kb
Host smart-8296c43a-c4d2-4eb9-a3aa-9aafa2331c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075537348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.4075537348
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1365906072
Short name T276
Test name
Test status
Simulation time 38368023 ps
CPU time 0.57 seconds
Started Apr 15 02:23:26 PM PDT 24
Finished Apr 15 02:23:27 PM PDT 24
Peak memory 195108 kb
Host smart-6247d6f0-9d25-4e62-bdfe-1046f9fd0196
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365906072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1365906072
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3624818917
Short name T223
Test name
Test status
Simulation time 634575718 ps
CPU time 23.09 seconds
Started Apr 15 02:23:21 PM PDT 24
Finished Apr 15 02:23:45 PM PDT 24
Peak memory 215432 kb
Host smart-19a4acb2-3054-41b5-a880-0e4d01a1324b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3624818917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3624818917
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.331822928
Short name T107
Test name
Test status
Simulation time 3960395273 ps
CPU time 18.76 seconds
Started Apr 15 02:23:27 PM PDT 24
Finished Apr 15 02:23:46 PM PDT 24
Peak memory 199704 kb
Host smart-eb334c00-80f7-4732-a7a0-8765ddfe5ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331822928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.331822928
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.734718976
Short name T483
Test name
Test status
Simulation time 6385685891 ps
CPU time 102.68 seconds
Started Apr 15 02:23:33 PM PDT 24
Finished Apr 15 02:25:16 PM PDT 24
Peak memory 199704 kb
Host smart-06f95648-074c-4a47-b7c9-f7006dd17b24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=734718976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.734718976
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.910073311
Short name T383
Test name
Test status
Simulation time 6070838105 ps
CPU time 85.6 seconds
Started Apr 15 02:23:25 PM PDT 24
Finished Apr 15 02:24:51 PM PDT 24
Peak memory 199736 kb
Host smart-4d5bba5c-a4dd-44ec-96ea-cccb6cea390d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910073311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.910073311
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2598962033
Short name T428
Test name
Test status
Simulation time 4167853119 ps
CPU time 22.65 seconds
Started Apr 15 02:23:33 PM PDT 24
Finished Apr 15 02:23:56 PM PDT 24
Peak memory 199704 kb
Host smart-3a021043-7663-41ea-9b2f-db5948991489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598962033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2598962033
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.4026163268
Short name T374
Test name
Test status
Simulation time 348784700 ps
CPU time 4.17 seconds
Started Apr 15 02:23:33 PM PDT 24
Finished Apr 15 02:23:38 PM PDT 24
Peak memory 199576 kb
Host smart-beac61f2-6434-48b0-8804-237ec1f48263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026163268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.4026163268
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1251442763
Short name T281
Test name
Test status
Simulation time 198556255 ps
CPU time 3.15 seconds
Started Apr 15 02:23:26 PM PDT 24
Finished Apr 15 02:23:30 PM PDT 24
Peak memory 199548 kb
Host smart-d62961b3-b53b-4a76-9afd-0aaef96ff8e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251442763 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1251442763
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.4029469253
Short name T266
Test name
Test status
Simulation time 411627752 ps
CPU time 1.35 seconds
Started Apr 15 02:23:30 PM PDT 24
Finished Apr 15 02:23:32 PM PDT 24
Peak memory 199608 kb
Host smart-ed1b859e-6f66-4315-b55b-30cf2fda93fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029469253 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.4029469253
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.4182517133
Short name T503
Test name
Test status
Simulation time 29919090632 ps
CPU time 545.4 seconds
Started Apr 15 02:23:29 PM PDT 24
Finished Apr 15 02:32:35 PM PDT 24
Peak memory 199716 kb
Host smart-5e843b54-3fa9-4765-88e5-646b7855721a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182517133 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.4182517133
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.4118432103
Short name T217
Test name
Test status
Simulation time 1016339533 ps
CPU time 12.4 seconds
Started Apr 15 02:23:25 PM PDT 24
Finished Apr 15 02:23:38 PM PDT 24
Peak memory 199616 kb
Host smart-bb2f928e-574e-47cb-8dfa-a49d174f059d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118432103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.4118432103
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.4246139003
Short name T515
Test name
Test status
Simulation time 22399980 ps
CPU time 0.53 seconds
Started Apr 15 02:23:29 PM PDT 24
Finished Apr 15 02:23:30 PM PDT 24
Peak memory 194132 kb
Host smart-86c3ca10-b53c-41d2-9866-e3a8981a5976
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246139003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.4246139003
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.4045392709
Short name T52
Test name
Test status
Simulation time 4829003633 ps
CPU time 45.64 seconds
Started Apr 15 02:23:27 PM PDT 24
Finished Apr 15 02:24:13 PM PDT 24
Peak memory 216088 kb
Host smart-35e5eb87-13ce-4198-bfc0-edd0ebf6a58a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4045392709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.4045392709
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3361230679
Short name T448
Test name
Test status
Simulation time 482730246 ps
CPU time 21.89 seconds
Started Apr 15 02:23:30 PM PDT 24
Finished Apr 15 02:23:52 PM PDT 24
Peak memory 199820 kb
Host smart-9cf1861c-bf1c-48bd-acfc-f570b620ba82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361230679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3361230679
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1098902465
Short name T142
Test name
Test status
Simulation time 23987960 ps
CPU time 0.82 seconds
Started Apr 15 02:23:26 PM PDT 24
Finished Apr 15 02:23:27 PM PDT 24
Peak memory 197848 kb
Host smart-30a58b33-312c-4e5c-a483-0090b6ba7bc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1098902465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1098902465
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.3853195711
Short name T317
Test name
Test status
Simulation time 20675909803 ps
CPU time 142.22 seconds
Started Apr 15 02:23:25 PM PDT 24
Finished Apr 15 02:25:48 PM PDT 24
Peak memory 199724 kb
Host smart-20ab78b9-614a-4137-931e-e22cb064e615
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853195711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.3853195711
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3422090504
Short name T400
Test name
Test status
Simulation time 23636270153 ps
CPU time 83.69 seconds
Started Apr 15 02:23:25 PM PDT 24
Finished Apr 15 02:24:50 PM PDT 24
Peak memory 199716 kb
Host smart-bb5d6868-129c-469f-9f41-e88c67e11ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422090504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3422090504
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1972686296
Short name T80
Test name
Test status
Simulation time 87013647 ps
CPU time 2.64 seconds
Started Apr 15 02:23:29 PM PDT 24
Finished Apr 15 02:23:32 PM PDT 24
Peak memory 199112 kb
Host smart-efb173f0-de99-4999-b981-b9b2e38d0233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972686296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1972686296
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2248430779
Short name T73
Test name
Test status
Simulation time 35089407443 ps
CPU time 462.63 seconds
Started Apr 15 02:23:28 PM PDT 24
Finished Apr 15 02:31:11 PM PDT 24
Peak memory 223812 kb
Host smart-b5c5f799-31cb-4e88-a5e7-01a672cff1f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248430779 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2248430779
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.2119236444
Short name T560
Test name
Test status
Simulation time 555900196 ps
CPU time 0.98 seconds
Started Apr 15 02:23:25 PM PDT 24
Finished Apr 15 02:23:27 PM PDT 24
Peak memory 198104 kb
Host smart-ba30e40e-be80-4b98-a6a6-acedd6c28b51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119236444 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.2119236444
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.1865081708
Short name T290
Test name
Test status
Simulation time 61866274578 ps
CPU time 399.93 seconds
Started Apr 15 02:23:30 PM PDT 24
Finished Apr 15 02:30:11 PM PDT 24
Peak memory 199728 kb
Host smart-c5cfe5b8-888f-4d8f-a3bd-7567813918fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865081708 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.1865081708
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.4013733708
Short name T567
Test name
Test status
Simulation time 11448010804 ps
CPU time 52.37 seconds
Started Apr 15 02:23:25 PM PDT 24
Finished Apr 15 02:24:18 PM PDT 24
Peak memory 199652 kb
Host smart-b61e8927-7a29-48b0-bed9-5e16e91a15c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013733708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.4013733708
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2001785122
Short name T229
Test name
Test status
Simulation time 26427698 ps
CPU time 0.62 seconds
Started Apr 15 02:23:33 PM PDT 24
Finished Apr 15 02:23:34 PM PDT 24
Peak memory 195212 kb
Host smart-675a9c03-9cb6-4135-8cc0-e12f3a91b5ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001785122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2001785122
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.1463239481
Short name T17
Test name
Test status
Simulation time 799389329 ps
CPU time 32.59 seconds
Started Apr 15 02:23:29 PM PDT 24
Finished Apr 15 02:24:02 PM PDT 24
Peak memory 215964 kb
Host smart-02362b6e-3893-49de-ae9d-304d2ba1800d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1463239481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1463239481
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.212936409
Short name T388
Test name
Test status
Simulation time 437959445 ps
CPU time 20.65 seconds
Started Apr 15 02:23:29 PM PDT 24
Finished Apr 15 02:23:51 PM PDT 24
Peak memory 199576 kb
Host smart-82727e43-345c-46fc-9b11-a7d4b53778c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212936409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.212936409
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.1462547013
Short name T168
Test name
Test status
Simulation time 804832287 ps
CPU time 51.21 seconds
Started Apr 15 02:23:29 PM PDT 24
Finished Apr 15 02:24:21 PM PDT 24
Peak memory 199544 kb
Host smart-830bc26e-1e74-43c3-bfda-594a7ce8b568
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1462547013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1462547013
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.4260481747
Short name T435
Test name
Test status
Simulation time 1161977068 ps
CPU time 32.53 seconds
Started Apr 15 02:23:31 PM PDT 24
Finished Apr 15 02:24:04 PM PDT 24
Peak memory 199636 kb
Host smart-d8ba634c-b27d-444e-954c-846f31a76293
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260481747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.4260481747
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1319005858
Short name T593
Test name
Test status
Simulation time 6354186538 ps
CPU time 85.22 seconds
Started Apr 15 02:23:29 PM PDT 24
Finished Apr 15 02:24:55 PM PDT 24
Peak memory 199748 kb
Host smart-08bfd0be-458c-46b5-8beb-0f0aed4ccaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319005858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1319005858
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1169121367
Short name T577
Test name
Test status
Simulation time 58443896 ps
CPU time 1.98 seconds
Started Apr 15 02:23:32 PM PDT 24
Finished Apr 15 02:23:35 PM PDT 24
Peak memory 199640 kb
Host smart-80aae87f-13b8-4c8e-a047-09d132e3a46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169121367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1169121367
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.1506968010
Short name T14
Test name
Test status
Simulation time 134633911061 ps
CPU time 1590.48 seconds
Started Apr 15 02:23:32 PM PDT 24
Finished Apr 15 02:50:04 PM PDT 24
Peak memory 199688 kb
Host smart-3411d45f-1b08-4fb7-b38b-322f596a0451
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506968010 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1506968010
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.1840386044
Short name T243
Test name
Test status
Simulation time 141163824 ps
CPU time 1.02 seconds
Started Apr 15 02:23:33 PM PDT 24
Finished Apr 15 02:23:34 PM PDT 24
Peak memory 198704 kb
Host smart-8d37d56e-d2f5-4356-bd23-4b6a986982c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840386044 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.1840386044
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.1595497285
Short name T417
Test name
Test status
Simulation time 39084270284 ps
CPU time 521.79 seconds
Started Apr 15 02:23:31 PM PDT 24
Finished Apr 15 02:32:13 PM PDT 24
Peak memory 199700 kb
Host smart-37746d35-167f-4d2a-9c25-4b2dc28cc60e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595497285 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.1595497285
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2612130731
Short name T184
Test name
Test status
Simulation time 6327179687 ps
CPU time 74.7 seconds
Started Apr 15 02:23:31 PM PDT 24
Finished Apr 15 02:24:46 PM PDT 24
Peak memory 199928 kb
Host smart-1759ed01-bf37-4602-88bd-09fcb9c881a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612130731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2612130731
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.4287411501
Short name T214
Test name
Test status
Simulation time 57817092 ps
CPU time 0.61 seconds
Started Apr 15 02:23:43 PM PDT 24
Finished Apr 15 02:23:45 PM PDT 24
Peak memory 195224 kb
Host smart-d2337d9b-35d1-4a6e-be6c-5e4163af8eab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287411501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.4287411501
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.4253872310
Short name T542
Test name
Test status
Simulation time 2956937172 ps
CPU time 48.62 seconds
Started Apr 15 02:23:35 PM PDT 24
Finished Apr 15 02:24:24 PM PDT 24
Peak memory 222156 kb
Host smart-24f5d6af-6e3b-4475-965c-0b180f9ee465
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4253872310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.4253872310
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.657585930
Short name T351
Test name
Test status
Simulation time 5125973324 ps
CPU time 28.09 seconds
Started Apr 15 02:23:35 PM PDT 24
Finished Apr 15 02:24:04 PM PDT 24
Peak memory 199740 kb
Host smart-b1bb9081-d4fb-40a6-8c41-ad265df2f16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657585930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.657585930
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2700397810
Short name T403
Test name
Test status
Simulation time 610085714 ps
CPU time 36.45 seconds
Started Apr 15 02:23:35 PM PDT 24
Finished Apr 15 02:24:12 PM PDT 24
Peak memory 199632 kb
Host smart-cd923ebb-6855-4ff1-bf05-f2e2125ca573
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2700397810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2700397810
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_long_msg.2210414257
Short name T592
Test name
Test status
Simulation time 1690888868 ps
CPU time 95.22 seconds
Started Apr 15 02:23:34 PM PDT 24
Finished Apr 15 02:25:09 PM PDT 24
Peak memory 199608 kb
Host smart-b037341e-844d-4558-93c2-dc27eab25bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210414257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.2210414257
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.3078105660
Short name T373
Test name
Test status
Simulation time 203100293 ps
CPU time 6.19 seconds
Started Apr 15 02:23:31 PM PDT 24
Finished Apr 15 02:23:38 PM PDT 24
Peak memory 199592 kb
Host smart-647e79c2-523b-401f-88d1-5db8dbd14fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078105660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3078105660
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.801713001
Short name T579
Test name
Test status
Simulation time 1933661399 ps
CPU time 35.83 seconds
Started Apr 15 02:23:37 PM PDT 24
Finished Apr 15 02:24:13 PM PDT 24
Peak memory 207828 kb
Host smart-f8c2a669-b513-47f4-aba5-e3c49e860fa2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801713001 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.801713001
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.2233589183
Short name T536
Test name
Test status
Simulation time 62006184 ps
CPU time 1.19 seconds
Started Apr 15 02:23:38 PM PDT 24
Finished Apr 15 02:23:40 PM PDT 24
Peak memory 199256 kb
Host smart-eea245c6-185f-41a6-b02c-1def8910e011
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233589183 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.2233589183
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.2449819202
Short name T363
Test name
Test status
Simulation time 43639388926 ps
CPU time 564.71 seconds
Started Apr 15 02:23:38 PM PDT 24
Finished Apr 15 02:33:04 PM PDT 24
Peak memory 199644 kb
Host smart-2e9a2c05-87ca-498a-8506-d66361eba0a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449819202 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.2449819202
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.1686176274
Short name T565
Test name
Test status
Simulation time 8729305200 ps
CPU time 85.85 seconds
Started Apr 15 02:23:46 PM PDT 24
Finished Apr 15 02:25:12 PM PDT 24
Peak memory 199724 kb
Host smart-99e72840-6a6f-4bd4-a619-fe260150e687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686176274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.1686176274
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.290241304
Short name T257
Test name
Test status
Simulation time 25975049 ps
CPU time 0.59 seconds
Started Apr 15 02:23:41 PM PDT 24
Finished Apr 15 02:23:43 PM PDT 24
Peak memory 195148 kb
Host smart-f34cdee0-f62b-497b-bf35-83942d977148
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290241304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.290241304
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.2850019251
Short name T201
Test name
Test status
Simulation time 1296117229 ps
CPU time 44.15 seconds
Started Apr 15 02:23:39 PM PDT 24
Finished Apr 15 02:24:24 PM PDT 24
Peak memory 221096 kb
Host smart-bd5f59ad-7e12-4819-91ce-22f27418cdc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2850019251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2850019251
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.3140612841
Short name T552
Test name
Test status
Simulation time 2165607468 ps
CPU time 13.22 seconds
Started Apr 15 02:23:41 PM PDT 24
Finished Apr 15 02:23:55 PM PDT 24
Peak memory 199652 kb
Host smart-b42ecf98-9ec6-4de2-a84b-82ed19b6bf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140612841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3140612841
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3612625072
Short name T157
Test name
Test status
Simulation time 2160746369 ps
CPU time 124.99 seconds
Started Apr 15 02:23:40 PM PDT 24
Finished Apr 15 02:25:46 PM PDT 24
Peak memory 199672 kb
Host smart-495a10fd-5dbf-44d0-91e8-abe898efa648
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3612625072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3612625072
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1766102118
Short name T305
Test name
Test status
Simulation time 11606231088 ps
CPU time 155.04 seconds
Started Apr 15 02:23:43 PM PDT 24
Finished Apr 15 02:26:19 PM PDT 24
Peak memory 199728 kb
Host smart-a636bcf8-2534-49fd-8008-8f56503062a8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766102118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1766102118
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3349088401
Short name T485
Test name
Test status
Simulation time 10839155185 ps
CPU time 52.95 seconds
Started Apr 15 02:23:40 PM PDT 24
Finished Apr 15 02:24:33 PM PDT 24
Peak memory 199732 kb
Host smart-e230210b-6f07-42f2-990e-40ee2fa9b4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349088401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3349088401
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2696054600
Short name T126
Test name
Test status
Simulation time 1826045708 ps
CPU time 6.88 seconds
Started Apr 15 02:23:40 PM PDT 24
Finished Apr 15 02:23:48 PM PDT 24
Peak memory 199572 kb
Host smart-2e838523-a6e2-4927-b631-23b2c0896207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696054600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2696054600
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.3973948456
Short name T7
Test name
Test status
Simulation time 15989884315 ps
CPU time 847.06 seconds
Started Apr 15 02:23:45 PM PDT 24
Finished Apr 15 02:37:53 PM PDT 24
Peak memory 224296 kb
Host smart-008f5249-e50a-4809-b10f-0e9eb43f87d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973948456 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.3973948456
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.3119158261
Short name T576
Test name
Test status
Simulation time 30264668 ps
CPU time 1.01 seconds
Started Apr 15 02:23:41 PM PDT 24
Finished Apr 15 02:23:42 PM PDT 24
Peak memory 199460 kb
Host smart-d3b84fa1-4110-49f7-8b69-35a0d7881c26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119158261 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.3119158261
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.2967024843
Short name T468
Test name
Test status
Simulation time 113223217415 ps
CPU time 505.6 seconds
Started Apr 15 02:23:44 PM PDT 24
Finished Apr 15 02:32:11 PM PDT 24
Peak memory 199900 kb
Host smart-55942f07-b937-47d7-ad8c-8d72fdcd4928
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967024843 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.2967024843
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1765805066
Short name T331
Test name
Test status
Simulation time 933075139 ps
CPU time 37.15 seconds
Started Apr 15 02:23:43 PM PDT 24
Finished Apr 15 02:24:20 PM PDT 24
Peak memory 199556 kb
Host smart-dde5b36c-17e4-4be7-aba4-a7a12165b102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765805066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1765805066
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.2253899799
Short name T32
Test name
Test status
Simulation time 24000419 ps
CPU time 0.58 seconds
Started Apr 15 02:23:50 PM PDT 24
Finished Apr 15 02:23:51 PM PDT 24
Peak memory 194132 kb
Host smart-6b1962e7-d391-4be6-bc76-a27fbbb2b31c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253899799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2253899799
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.3394557018
Short name T18
Test name
Test status
Simulation time 651416623 ps
CPU time 23.31 seconds
Started Apr 15 02:23:42 PM PDT 24
Finished Apr 15 02:24:06 PM PDT 24
Peak memory 207804 kb
Host smart-a637c76a-7f3e-47fa-a394-ad27e35d5412
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3394557018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3394557018
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1760533447
Short name T572
Test name
Test status
Simulation time 2192525274 ps
CPU time 42.59 seconds
Started Apr 15 02:23:41 PM PDT 24
Finished Apr 15 02:24:24 PM PDT 24
Peak memory 199620 kb
Host smart-42dc9b72-f92d-42db-96d5-015b1d78e032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760533447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1760533447
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3813837709
Short name T352
Test name
Test status
Simulation time 6723836323 ps
CPU time 106.16 seconds
Started Apr 15 02:23:43 PM PDT 24
Finished Apr 15 02:25:30 PM PDT 24
Peak memory 199704 kb
Host smart-1417a6d7-7733-46fe-bbbc-7105f3db0b7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3813837709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3813837709
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3728750826
Short name T205
Test name
Test status
Simulation time 4230903228 ps
CPU time 53.3 seconds
Started Apr 15 02:23:46 PM PDT 24
Finished Apr 15 02:24:40 PM PDT 24
Peak memory 199728 kb
Host smart-98bd0037-0509-45ac-a91f-d4787eaf8093
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728750826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3728750826
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3549066331
Short name T582
Test name
Test status
Simulation time 5856108212 ps
CPU time 19.65 seconds
Started Apr 15 02:23:45 PM PDT 24
Finished Apr 15 02:24:05 PM PDT 24
Peak memory 199720 kb
Host smart-567311ae-7360-4141-8432-b776eb0d1afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549066331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3549066331
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.1869914562
Short name T163
Test name
Test status
Simulation time 872656412 ps
CPU time 2.57 seconds
Started Apr 15 02:23:44 PM PDT 24
Finished Apr 15 02:23:48 PM PDT 24
Peak memory 199604 kb
Host smart-f7648850-5a1b-4aa9-a766-2a9343655ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869914562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1869914562
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.3914375236
Short name T90
Test name
Test status
Simulation time 30081328062 ps
CPU time 726.66 seconds
Started Apr 15 02:23:45 PM PDT 24
Finished Apr 15 02:35:52 PM PDT 24
Peak memory 240728 kb
Host smart-0c23ac61-d870-48f0-a236-0006e22ff939
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914375236 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3914375236
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.961192225
Short name T298
Test name
Test status
Simulation time 69735133 ps
CPU time 0.96 seconds
Started Apr 15 02:23:50 PM PDT 24
Finished Apr 15 02:23:52 PM PDT 24
Peak memory 197944 kb
Host smart-646f03e1-0435-411a-a14f-97be34d56b7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961192225 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_hmac_vectors.961192225
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.965235876
Short name T397
Test name
Test status
Simulation time 28546790656 ps
CPU time 492.58 seconds
Started Apr 15 02:23:46 PM PDT 24
Finished Apr 15 02:32:00 PM PDT 24
Peak memory 199716 kb
Host smart-29400084-ede8-42c5-85d2-313e45d70898
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965235876 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.965235876
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3161590431
Short name T537
Test name
Test status
Simulation time 11303238023 ps
CPU time 53.05 seconds
Started Apr 15 02:23:49 PM PDT 24
Finished Apr 15 02:24:43 PM PDT 24
Peak memory 199704 kb
Host smart-c91c133c-c0ab-4a20-8970-df7745ec4c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161590431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3161590431
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.1598017041
Short name T297
Test name
Test status
Simulation time 85913429 ps
CPU time 0.58 seconds
Started Apr 15 02:23:52 PM PDT 24
Finished Apr 15 02:23:53 PM PDT 24
Peak memory 195164 kb
Host smart-7f56d3df-d22d-4c0c-a066-4d13ffc08010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598017041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1598017041
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2967905565
Short name T393
Test name
Test status
Simulation time 688211300 ps
CPU time 27.9 seconds
Started Apr 15 02:23:47 PM PDT 24
Finished Apr 15 02:24:16 PM PDT 24
Peak memory 210708 kb
Host smart-d37a38f3-9018-4413-a228-45524e982906
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2967905565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2967905565
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3031612928
Short name T585
Test name
Test status
Simulation time 7572808690 ps
CPU time 37.74 seconds
Started Apr 15 02:23:47 PM PDT 24
Finished Apr 15 02:24:25 PM PDT 24
Peak memory 199720 kb
Host smart-3942b32a-f508-497a-86f2-db7eebd97e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031612928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3031612928
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3562214449
Short name T570
Test name
Test status
Simulation time 5933783162 ps
CPU time 87.78 seconds
Started Apr 15 02:23:46 PM PDT 24
Finished Apr 15 02:25:14 PM PDT 24
Peak memory 199668 kb
Host smart-c4a28824-6ffc-434b-ac43-cbe889c90dbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3562214449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3562214449
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.708252158
Short name T208
Test name
Test status
Simulation time 7530710000 ps
CPU time 73.78 seconds
Started Apr 15 02:23:47 PM PDT 24
Finished Apr 15 02:25:01 PM PDT 24
Peak memory 199732 kb
Host smart-c1a8adc9-76e5-4430-a66e-3dc5ff133cce
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708252158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.708252158
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.517067482
Short name T333
Test name
Test status
Simulation time 20408290392 ps
CPU time 127.54 seconds
Started Apr 15 02:23:46 PM PDT 24
Finished Apr 15 02:25:54 PM PDT 24
Peak memory 199732 kb
Host smart-8013f92a-ec2e-464d-b003-34c4d7ce4796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517067482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.517067482
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1151960461
Short name T221
Test name
Test status
Simulation time 323702795 ps
CPU time 5.06 seconds
Started Apr 15 02:23:50 PM PDT 24
Finished Apr 15 02:23:56 PM PDT 24
Peak memory 199580 kb
Host smart-7666f1e5-5843-4b88-a02e-fd0c147099c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151960461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1151960461
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.417314301
Short name T360
Test name
Test status
Simulation time 536936241034 ps
CPU time 1003.37 seconds
Started Apr 15 02:23:48 PM PDT 24
Finished Apr 15 02:40:32 PM PDT 24
Peak memory 240772 kb
Host smart-0f58b368-f953-4959-b9cf-03665789aa6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417314301 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.417314301
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.3011895956
Short name T194
Test name
Test status
Simulation time 32486286 ps
CPU time 1.1 seconds
Started Apr 15 02:23:48 PM PDT 24
Finished Apr 15 02:23:50 PM PDT 24
Peak memory 198908 kb
Host smart-4f41b2b2-e346-43c6-b6ee-180b009f5ae4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011895956 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.3011895956
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.553337532
Short name T58
Test name
Test status
Simulation time 308016621050 ps
CPU time 444.54 seconds
Started Apr 15 02:23:50 PM PDT 24
Finished Apr 15 02:31:15 PM PDT 24
Peak memory 199704 kb
Host smart-595b2cf5-0493-48cc-aece-ca76507d3f6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553337532 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.553337532
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.607569257
Short name T318
Test name
Test status
Simulation time 3276059804 ps
CPU time 63.53 seconds
Started Apr 15 02:23:49 PM PDT 24
Finished Apr 15 02:24:53 PM PDT 24
Peak memory 199680 kb
Host smart-3123e8bc-ed55-45aa-ba9f-9ea9023d93e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607569257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.607569257
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.805959026
Short name T525
Test name
Test status
Simulation time 16785188 ps
CPU time 0.6 seconds
Started Apr 15 02:23:53 PM PDT 24
Finished Apr 15 02:23:54 PM PDT 24
Peak memory 195120 kb
Host smart-f12c5aa0-dcca-419f-bd52-68590a9a53af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805959026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.805959026
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.953517551
Short name T568
Test name
Test status
Simulation time 113030757 ps
CPU time 4.1 seconds
Started Apr 15 02:23:51 PM PDT 24
Finished Apr 15 02:23:56 PM PDT 24
Peak memory 199588 kb
Host smart-b8d67039-ec3e-4cff-a162-09dff974144a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=953517551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.953517551
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.2041925458
Short name T232
Test name
Test status
Simulation time 1579886001 ps
CPU time 40.19 seconds
Started Apr 15 02:23:50 PM PDT 24
Finished Apr 15 02:24:31 PM PDT 24
Peak memory 199596 kb
Host smart-e16b1082-3168-4d7d-b48f-ce20bedfb99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041925458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2041925458
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2694277370
Short name T310
Test name
Test status
Simulation time 2320395243 ps
CPU time 119.02 seconds
Started Apr 15 02:23:51 PM PDT 24
Finished Apr 15 02:25:51 PM PDT 24
Peak memory 199684 kb
Host smart-6f248112-6b4e-4826-89c4-6c02ab112533
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2694277370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2694277370
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.2085581482
Short name T253
Test name
Test status
Simulation time 5754556614 ps
CPU time 100.24 seconds
Started Apr 15 02:23:56 PM PDT 24
Finished Apr 15 02:25:37 PM PDT 24
Peak memory 199728 kb
Host smart-d10265bc-b782-43d2-85df-a7184ec197d8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085581482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.2085581482
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3765215838
Short name T207
Test name
Test status
Simulation time 1457079588 ps
CPU time 22.88 seconds
Started Apr 15 02:23:49 PM PDT 24
Finished Apr 15 02:24:12 PM PDT 24
Peak memory 199552 kb
Host smart-079494c6-d327-4f30-bf92-83e9b84294fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765215838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3765215838
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.651640822
Short name T148
Test name
Test status
Simulation time 33622856 ps
CPU time 0.89 seconds
Started Apr 15 02:23:50 PM PDT 24
Finished Apr 15 02:23:52 PM PDT 24
Peak memory 198564 kb
Host smart-b0c8649b-c7e9-48b7-aef7-faf81365c0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651640822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.651640822
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.2695082231
Short name T129
Test name
Test status
Simulation time 479867006309 ps
CPU time 2252.64 seconds
Started Apr 15 02:23:55 PM PDT 24
Finished Apr 15 03:01:29 PM PDT 24
Peak memory 199728 kb
Host smart-ff588cdb-045d-4da8-83c0-23f3a8890ef0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695082231 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2695082231
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.3443532298
Short name T89
Test name
Test status
Simulation time 392209241 ps
CPU time 1.06 seconds
Started Apr 15 02:23:53 PM PDT 24
Finished Apr 15 02:23:55 PM PDT 24
Peak memory 199076 kb
Host smart-cbf2f6b1-b401-471a-b7f6-73fc83c67cfd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443532298 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.3443532298
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.269070379
Short name T228
Test name
Test status
Simulation time 37214151112 ps
CPU time 492.52 seconds
Started Apr 15 02:23:53 PM PDT 24
Finished Apr 15 02:32:06 PM PDT 24
Peak memory 199700 kb
Host smart-f8440ee1-b589-45fd-bc1a-0be44ad2ce72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269070379 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.269070379
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.2527870249
Short name T535
Test name
Test status
Simulation time 118492425 ps
CPU time 2.83 seconds
Started Apr 15 02:23:54 PM PDT 24
Finished Apr 15 02:23:58 PM PDT 24
Peak memory 199540 kb
Host smart-3001f8c3-04e4-4e9a-938d-6a8281becec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527870249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2527870249
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3784509815
Short name T573
Test name
Test status
Simulation time 43592214 ps
CPU time 0.55 seconds
Started Apr 15 02:21:41 PM PDT 24
Finished Apr 15 02:21:45 PM PDT 24
Peak memory 195100 kb
Host smart-b9a12e95-1da5-4469-bf67-5ff40d32828f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784509815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3784509815
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3365402293
Short name T364
Test name
Test status
Simulation time 1843017456 ps
CPU time 13.34 seconds
Started Apr 15 02:21:45 PM PDT 24
Finished Apr 15 02:22:02 PM PDT 24
Peak memory 199536 kb
Host smart-02a9ced5-1a10-498a-a333-f9cf50b69bf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3365402293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3365402293
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.1740875916
Short name T255
Test name
Test status
Simulation time 1044271913 ps
CPU time 53.5 seconds
Started Apr 15 02:21:43 PM PDT 24
Finished Apr 15 02:22:41 PM PDT 24
Peak memory 199556 kb
Host smart-e9534170-39f3-4b40-b3ed-db16107fbb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740875916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.1740875916
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.3528142984
Short name T196
Test name
Test status
Simulation time 1982417658 ps
CPU time 115.87 seconds
Started Apr 15 02:21:43 PM PDT 24
Finished Apr 15 02:23:43 PM PDT 24
Peak memory 199544 kb
Host smart-6d76f2d1-5d9f-495c-8379-2d36c44ae41c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3528142984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.3528142984
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.3572620285
Short name T454
Test name
Test status
Simulation time 1215524224 ps
CPU time 61.76 seconds
Started Apr 15 02:21:50 PM PDT 24
Finished Apr 15 02:22:56 PM PDT 24
Peak memory 199540 kb
Host smart-b7a3288b-cc21-45a1-95bc-4ac6eff2270e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572620285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3572620285
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1843988057
Short name T410
Test name
Test status
Simulation time 16478921638 ps
CPU time 60.58 seconds
Started Apr 15 02:21:45 PM PDT 24
Finished Apr 15 02:22:50 PM PDT 24
Peak memory 199720 kb
Host smart-c8fcbdfb-e032-4679-a32c-71f3f5182666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843988057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1843988057
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1460122801
Short name T31
Test name
Test status
Simulation time 224225920 ps
CPU time 0.9 seconds
Started Apr 15 02:21:50 PM PDT 24
Finished Apr 15 02:21:55 PM PDT 24
Peak memory 219164 kb
Host smart-3445ad96-344d-42e2-9a5c-1a0c83e6dea4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460122801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1460122801
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.2887668942
Short name T361
Test name
Test status
Simulation time 498531127 ps
CPU time 3.61 seconds
Started Apr 15 02:21:43 PM PDT 24
Finished Apr 15 02:21:51 PM PDT 24
Peak memory 199604 kb
Host smart-8aa80c3d-04e4-4268-8fcf-51d511c20dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887668942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2887668942
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2500985380
Short name T340
Test name
Test status
Simulation time 2868238394 ps
CPU time 54.34 seconds
Started Apr 15 02:21:42 PM PDT 24
Finished Apr 15 02:22:39 PM PDT 24
Peak memory 199676 kb
Host smart-a2112992-b699-473d-877c-3c98aeedc747
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500985380 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2500985380
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.2909879016
Short name T35
Test name
Test status
Simulation time 274207900 ps
CPU time 1.29 seconds
Started Apr 15 02:21:45 PM PDT 24
Finished Apr 15 02:21:51 PM PDT 24
Peak memory 198228 kb
Host smart-693a98cc-d1ff-4f3d-a01e-add3551c165a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909879016 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.2909879016
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.1724965717
Short name T299
Test name
Test status
Simulation time 14538906835 ps
CPU time 429.29 seconds
Started Apr 15 02:21:43 PM PDT 24
Finished Apr 15 02:28:56 PM PDT 24
Peak memory 199716 kb
Host smart-1423b6de-6ecd-4bfb-8e27-88550ffd3f50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724965717 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.1724965717
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.3198334545
Short name T381
Test name
Test status
Simulation time 4765034120 ps
CPU time 28.65 seconds
Started Apr 15 02:21:43 PM PDT 24
Finished Apr 15 02:22:15 PM PDT 24
Peak memory 199732 kb
Host smart-48dca00f-dfa3-4bc6-8906-0bdccd37a7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198334545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3198334545
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2674311946
Short name T262
Test name
Test status
Simulation time 15452302 ps
CPU time 0.59 seconds
Started Apr 15 02:23:59 PM PDT 24
Finished Apr 15 02:24:00 PM PDT 24
Peak memory 195072 kb
Host smart-4eeba2a2-dda0-47b8-81ad-1d679014b1a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674311946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2674311946
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.2991526771
Short name T501
Test name
Test status
Simulation time 621333150 ps
CPU time 19.66 seconds
Started Apr 15 02:23:56 PM PDT 24
Finished Apr 15 02:24:16 PM PDT 24
Peak memory 207804 kb
Host smart-4ae19af4-d96c-4e42-b992-84169c7a37d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2991526771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2991526771
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.4226758104
Short name T389
Test name
Test status
Simulation time 1817175416 ps
CPU time 17.89 seconds
Started Apr 15 02:23:55 PM PDT 24
Finished Apr 15 02:24:13 PM PDT 24
Peak memory 199504 kb
Host smart-289bc12f-9989-40ff-9fed-5178343ed1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226758104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.4226758104
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1194169381
Short name T554
Test name
Test status
Simulation time 7871219884 ps
CPU time 108.79 seconds
Started Apr 15 02:23:53 PM PDT 24
Finished Apr 15 02:25:42 PM PDT 24
Peak memory 199724 kb
Host smart-f1d0d15d-0ef4-4ebd-8975-37a6140ba0f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1194169381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1194169381
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2260455242
Short name T16
Test name
Test status
Simulation time 7774600566 ps
CPU time 99.76 seconds
Started Apr 15 02:23:57 PM PDT 24
Finished Apr 15 02:25:37 PM PDT 24
Peak memory 199704 kb
Host smart-a8263168-4219-49fb-90f8-ff0fc07d7a6b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260455242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2260455242
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3497589678
Short name T125
Test name
Test status
Simulation time 17196885029 ps
CPU time 61.82 seconds
Started Apr 15 02:23:53 PM PDT 24
Finished Apr 15 02:24:55 PM PDT 24
Peak memory 199688 kb
Host smart-5881c76d-4d1c-4f73-92a1-2e9cacbad0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497589678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3497589678
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2932232354
Short name T438
Test name
Test status
Simulation time 3344761606 ps
CPU time 5.17 seconds
Started Apr 15 02:23:52 PM PDT 24
Finished Apr 15 02:23:58 PM PDT 24
Peak memory 199704 kb
Host smart-6380ad78-21fe-4ab7-b89b-8778f2b54bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932232354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2932232354
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2087027500
Short name T240
Test name
Test status
Simulation time 1746682566 ps
CPU time 20.86 seconds
Started Apr 15 02:23:59 PM PDT 24
Finished Apr 15 02:24:20 PM PDT 24
Peak memory 217544 kb
Host smart-dcd7d4de-4fe3-41d1-b69e-9b4950688ac6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087027500 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2087027500
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.2781368293
Short name T367
Test name
Test status
Simulation time 216794610 ps
CPU time 1.04 seconds
Started Apr 15 02:23:58 PM PDT 24
Finished Apr 15 02:24:00 PM PDT 24
Peak memory 198364 kb
Host smart-bcf9aaff-3f84-4624-90eb-588a5d51484b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781368293 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.2781368293
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.321913725
Short name T396
Test name
Test status
Simulation time 235803304314 ps
CPU time 455.59 seconds
Started Apr 15 02:23:59 PM PDT 24
Finished Apr 15 02:31:35 PM PDT 24
Peak memory 199628 kb
Host smart-d4df0d6f-f856-4564-be72-196209a70177
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321913725 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.321913725
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.3640329271
Short name T538
Test name
Test status
Simulation time 2906988630 ps
CPU time 52.6 seconds
Started Apr 15 02:23:58 PM PDT 24
Finished Apr 15 02:24:51 PM PDT 24
Peak memory 199732 kb
Host smart-4b218147-f6c4-4d16-ac44-d2caf37fe4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640329271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.3640329271
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2761498428
Short name T128
Test name
Test status
Simulation time 13568093 ps
CPU time 0.63 seconds
Started Apr 15 02:24:04 PM PDT 24
Finished Apr 15 02:24:05 PM PDT 24
Peak memory 195260 kb
Host smart-9a4e44a7-ee1f-4fe1-8fb9-6c48a63e0a86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761498428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2761498428
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1718334456
Short name T457
Test name
Test status
Simulation time 4131696704 ps
CPU time 41.73 seconds
Started Apr 15 02:24:01 PM PDT 24
Finished Apr 15 02:24:43 PM PDT 24
Peak memory 240080 kb
Host smart-d404690c-81f7-46e8-a5c5-e11491d4897d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1718334456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1718334456
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3791341124
Short name T238
Test name
Test status
Simulation time 763410917 ps
CPU time 18.64 seconds
Started Apr 15 02:24:10 PM PDT 24
Finished Apr 15 02:24:29 PM PDT 24
Peak memory 199608 kb
Host smart-2df971b1-d0eb-4889-a33e-e1268cb68f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791341124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3791341124
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2314445388
Short name T444
Test name
Test status
Simulation time 4971348570 ps
CPU time 45.76 seconds
Started Apr 15 02:24:01 PM PDT 24
Finished Apr 15 02:24:48 PM PDT 24
Peak memory 199732 kb
Host smart-97264a7a-5043-410b-a796-e3b91fe922b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2314445388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2314445388
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2305845926
Short name T541
Test name
Test status
Simulation time 12913661735 ps
CPU time 96.73 seconds
Started Apr 15 02:24:01 PM PDT 24
Finished Apr 15 02:25:38 PM PDT 24
Peak memory 199660 kb
Host smart-0e149533-f4d8-4c49-9498-8cae28be22ff
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305845926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2305845926
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3348338826
Short name T529
Test name
Test status
Simulation time 13324132428 ps
CPU time 33.78 seconds
Started Apr 15 02:24:00 PM PDT 24
Finished Apr 15 02:24:34 PM PDT 24
Peak memory 199676 kb
Host smart-df8d9b9a-1fce-4a60-9ef9-710af1ce207f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348338826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3348338826
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.3739987556
Short name T408
Test name
Test status
Simulation time 1381117967 ps
CPU time 6.79 seconds
Started Apr 15 02:23:58 PM PDT 24
Finished Apr 15 02:24:06 PM PDT 24
Peak memory 199592 kb
Host smart-f95d99c2-d59a-4aad-aa08-0915c6c624ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739987556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3739987556
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.3749823839
Short name T185
Test name
Test status
Simulation time 6037403623 ps
CPU time 32.54 seconds
Started Apr 15 02:24:02 PM PDT 24
Finished Apr 15 02:24:35 PM PDT 24
Peak memory 199740 kb
Host smart-2695e80b-d561-4c1c-b0a3-d2367b3b26ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749823839 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3749823839
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.3787857629
Short name T378
Test name
Test status
Simulation time 393860326 ps
CPU time 1.01 seconds
Started Apr 15 02:24:04 PM PDT 24
Finished Apr 15 02:24:06 PM PDT 24
Peak memory 199168 kb
Host smart-830895cf-9f69-4ca8-b22e-0777aa815ccb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787857629 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.3787857629
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.3098391727
Short name T598
Test name
Test status
Simulation time 38782924191 ps
CPU time 526.33 seconds
Started Apr 15 02:24:01 PM PDT 24
Finished Apr 15 02:32:48 PM PDT 24
Peak memory 199684 kb
Host smart-dbdf8fb6-f87d-4e8d-81a4-feafff2b3310
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098391727 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.3098391727
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.1751508904
Short name T120
Test name
Test status
Simulation time 1899951262 ps
CPU time 82.77 seconds
Started Apr 15 02:24:02 PM PDT 24
Finished Apr 15 02:25:25 PM PDT 24
Peak memory 199584 kb
Host smart-d144ddef-655f-4ba9-9874-eac62c396011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751508904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1751508904
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2869208583
Short name T274
Test name
Test status
Simulation time 36173393 ps
CPU time 0.58 seconds
Started Apr 15 02:24:06 PM PDT 24
Finished Apr 15 02:24:08 PM PDT 24
Peak memory 195108 kb
Host smart-0c48c2dd-1f1b-499a-bbbd-e03202be4cbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869208583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2869208583
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.3347726652
Short name T50
Test name
Test status
Simulation time 3709899519 ps
CPU time 31.68 seconds
Started Apr 15 02:24:07 PM PDT 24
Finished Apr 15 02:24:39 PM PDT 24
Peak memory 212652 kb
Host smart-ec427a84-4ae2-4783-a062-bea4025ef055
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3347726652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3347726652
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1719612040
Short name T482
Test name
Test status
Simulation time 3569610811 ps
CPU time 34.49 seconds
Started Apr 15 02:24:07 PM PDT 24
Finished Apr 15 02:24:42 PM PDT 24
Peak memory 199732 kb
Host smart-03db1630-3a9d-483f-a049-65606fc9e5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719612040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1719612040
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.3958010049
Short name T316
Test name
Test status
Simulation time 4941576018 ps
CPU time 110.09 seconds
Started Apr 15 02:24:08 PM PDT 24
Finished Apr 15 02:25:59 PM PDT 24
Peak memory 199708 kb
Host smart-814cf487-9d08-4aa9-b3ec-6c4879bfd85b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3958010049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3958010049
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.496925275
Short name T218
Test name
Test status
Simulation time 12142279909 ps
CPU time 155.6 seconds
Started Apr 15 02:24:06 PM PDT 24
Finished Apr 15 02:26:42 PM PDT 24
Peak memory 199676 kb
Host smart-33dd73ce-63ff-4b0c-8379-a20d4f6a2ac6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496925275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.496925275
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.267963392
Short name T280
Test name
Test status
Simulation time 532112872 ps
CPU time 7.85 seconds
Started Apr 15 02:24:07 PM PDT 24
Finished Apr 15 02:24:16 PM PDT 24
Peak memory 199556 kb
Host smart-0b9a80e5-b193-49ab-a6a1-0d7658a88b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267963392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.267963392
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.533628923
Short name T368
Test name
Test status
Simulation time 698989991 ps
CPU time 2.45 seconds
Started Apr 15 02:24:06 PM PDT 24
Finished Apr 15 02:24:09 PM PDT 24
Peak memory 199552 kb
Host smart-faf040e8-4325-4ae7-a593-bd626433bf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533628923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.533628923
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3510824803
Short name T15
Test name
Test status
Simulation time 486089213564 ps
CPU time 2039.45 seconds
Started Apr 15 02:24:07 PM PDT 24
Finished Apr 15 02:58:07 PM PDT 24
Peak memory 199664 kb
Host smart-8b00f640-51f0-4ae3-b46c-fa46c7499333
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510824803 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3510824803
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_stress_all_with_rand_reset.2923694380
Short name T10
Test name
Test status
Simulation time 39258000334 ps
CPU time 1956.31 seconds
Started Apr 15 02:24:07 PM PDT 24
Finished Apr 15 02:56:44 PM PDT 24
Peak memory 248632 kb
Host smart-5873fd68-9d7f-43dd-98c7-97de42db24fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2923694380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all_with_rand_reset.2923694380
Directory /workspace/42.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.1179009043
Short name T250
Test name
Test status
Simulation time 259977857 ps
CPU time 1.19 seconds
Started Apr 15 02:24:06 PM PDT 24
Finished Apr 15 02:24:08 PM PDT 24
Peak memory 199448 kb
Host smart-e4383fd9-ea43-4cf6-9f6c-38f054ebfa60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179009043 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.1179009043
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.1525902927
Short name T524
Test name
Test status
Simulation time 69161658315 ps
CPU time 479.47 seconds
Started Apr 15 02:24:07 PM PDT 24
Finished Apr 15 02:32:08 PM PDT 24
Peak memory 199740 kb
Host smart-247f8ef5-e704-43a9-b594-380a2b427b4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525902927 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.1525902927
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.1831851808
Short name T92
Test name
Test status
Simulation time 4828455150 ps
CPU time 35.79 seconds
Started Apr 15 02:24:06 PM PDT 24
Finished Apr 15 02:24:43 PM PDT 24
Peak memory 199748 kb
Host smart-0db54ede-d4f0-4f33-a923-b19f18a096db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831851808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1831851808
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.4294317082
Short name T206
Test name
Test status
Simulation time 29242370 ps
CPU time 0.57 seconds
Started Apr 15 02:24:15 PM PDT 24
Finished Apr 15 02:24:16 PM PDT 24
Peak memory 195020 kb
Host smart-2b787945-a310-40be-a48d-973ecd65141b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294317082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.4294317082
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.945266696
Short name T353
Test name
Test status
Simulation time 6909777425 ps
CPU time 75.13 seconds
Started Apr 15 02:24:07 PM PDT 24
Finished Apr 15 02:25:23 PM PDT 24
Peak memory 232480 kb
Host smart-ca86f8d6-68af-48b8-84a6-2e61e5455788
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=945266696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.945266696
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2877558766
Short name T222
Test name
Test status
Simulation time 9566750307 ps
CPU time 38.72 seconds
Started Apr 15 02:24:09 PM PDT 24
Finished Apr 15 02:24:48 PM PDT 24
Peak memory 199732 kb
Host smart-af0dcd0c-7dc0-43e1-9a92-aaf5eb7c048a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877558766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2877558766
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.3089882649
Short name T447
Test name
Test status
Simulation time 4838976715 ps
CPU time 66.77 seconds
Started Apr 15 02:24:09 PM PDT 24
Finished Apr 15 02:25:17 PM PDT 24
Peak memory 199704 kb
Host smart-09fef0e7-cb37-48ea-9279-16231d3fe7ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3089882649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.3089882649
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_long_msg.551701780
Short name T510
Test name
Test status
Simulation time 1531271042 ps
CPU time 21.88 seconds
Started Apr 15 02:24:07 PM PDT 24
Finished Apr 15 02:24:29 PM PDT 24
Peak memory 199588 kb
Host smart-33260641-2331-4541-bcfa-ca8e7c9cb8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551701780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.551701780
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2348265190
Short name T145
Test name
Test status
Simulation time 414774324 ps
CPU time 6.45 seconds
Started Apr 15 02:24:07 PM PDT 24
Finished Apr 15 02:24:14 PM PDT 24
Peak memory 199564 kb
Host smart-ca97d525-a30c-436e-a473-8e46deda67ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348265190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2348265190
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1022476507
Short name T520
Test name
Test status
Simulation time 34770086830 ps
CPU time 1762.89 seconds
Started Apr 15 02:24:16 PM PDT 24
Finished Apr 15 02:53:40 PM PDT 24
Peak memory 239868 kb
Host smart-84655beb-5c3b-41ba-87f2-a0716a84ebab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022476507 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1022476507
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.3924486765
Short name T589
Test name
Test status
Simulation time 27631922 ps
CPU time 1.02 seconds
Started Apr 15 02:24:13 PM PDT 24
Finished Apr 15 02:24:15 PM PDT 24
Peak memory 199104 kb
Host smart-d77af4df-e9f2-41f2-b67e-5e9fc812b073
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924486765 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.3924486765
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.2506055139
Short name T327
Test name
Test status
Simulation time 39098123501 ps
CPU time 477.04 seconds
Started Apr 15 02:24:09 PM PDT 24
Finished Apr 15 02:32:07 PM PDT 24
Peak memory 199700 kb
Host smart-acd8e4a4-2a2a-40c9-947c-10b6aa279f23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506055139 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.2506055139
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1035905620
Short name T350
Test name
Test status
Simulation time 3577106238 ps
CPU time 66.58 seconds
Started Apr 15 02:24:12 PM PDT 24
Finished Apr 15 02:25:19 PM PDT 24
Peak memory 199700 kb
Host smart-23e23900-055e-4599-b3b0-4c72b141aaa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035905620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1035905620
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.321131180
Short name T130
Test name
Test status
Simulation time 13142181 ps
CPU time 0.57 seconds
Started Apr 15 02:24:18 PM PDT 24
Finished Apr 15 02:24:19 PM PDT 24
Peak memory 195144 kb
Host smart-77db3049-b1b4-4847-bc6f-c103a1e3fee6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321131180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.321131180
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.611129539
Short name T304
Test name
Test status
Simulation time 1497194315 ps
CPU time 14.24 seconds
Started Apr 15 02:24:13 PM PDT 24
Finished Apr 15 02:24:27 PM PDT 24
Peak memory 220084 kb
Host smart-3df459e8-8b5a-4bd9-b80b-2a2d66538442
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=611129539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.611129539
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1408282349
Short name T563
Test name
Test status
Simulation time 601087264 ps
CPU time 9.08 seconds
Started Apr 15 02:24:16 PM PDT 24
Finished Apr 15 02:24:26 PM PDT 24
Peak memory 199532 kb
Host smart-4ed3c61c-b7d6-4378-a730-5c9813ae96ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408282349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1408282349
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.563364792
Short name T424
Test name
Test status
Simulation time 134880518 ps
CPU time 6.64 seconds
Started Apr 15 02:24:14 PM PDT 24
Finished Apr 15 02:24:21 PM PDT 24
Peak memory 199628 kb
Host smart-58b49ce7-1fa6-4b02-b551-ed1d6b98c576
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=563364792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.563364792
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3838522949
Short name T169
Test name
Test status
Simulation time 3626356400 ps
CPU time 43.48 seconds
Started Apr 15 02:24:13 PM PDT 24
Finished Apr 15 02:24:57 PM PDT 24
Peak memory 199684 kb
Host smart-1981c9f2-8d69-45f0-b77e-e424f5a97f59
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838522949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3838522949
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.3481339426
Short name T550
Test name
Test status
Simulation time 1897608641 ps
CPU time 70.81 seconds
Started Apr 15 02:24:14 PM PDT 24
Finished Apr 15 02:25:26 PM PDT 24
Peak memory 199584 kb
Host smart-5967be5f-3cb0-4338-8ee6-52eb812e226e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481339426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3481339426
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2366845347
Short name T165
Test name
Test status
Simulation time 184418234 ps
CPU time 1.6 seconds
Started Apr 15 02:24:13 PM PDT 24
Finished Apr 15 02:24:15 PM PDT 24
Peak memory 199612 kb
Host smart-cadc1227-66d8-4117-b66a-3df382586543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366845347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2366845347
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.1797567703
Short name T204
Test name
Test status
Simulation time 28160367420 ps
CPU time 1561.62 seconds
Started Apr 15 02:24:14 PM PDT 24
Finished Apr 15 02:50:17 PM PDT 24
Peak memory 199744 kb
Host smart-8f27d9f7-8047-4125-901f-c936d78d2a4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797567703 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1797567703
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.2077711428
Short name T6
Test name
Test status
Simulation time 120495407 ps
CPU time 1.12 seconds
Started Apr 15 02:24:14 PM PDT 24
Finished Apr 15 02:24:16 PM PDT 24
Peak memory 199548 kb
Host smart-d8fa6e2b-9614-4151-8d29-f29538a6b5fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077711428 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.2077711428
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.1795163319
Short name T486
Test name
Test status
Simulation time 121282561248 ps
CPU time 515.06 seconds
Started Apr 15 02:24:16 PM PDT 24
Finished Apr 15 02:32:52 PM PDT 24
Peak memory 199740 kb
Host smart-86d728c6-2e79-48aa-9b15-fd592efafd4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795163319 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.1795163319
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.3376701406
Short name T93
Test name
Test status
Simulation time 7981228258 ps
CPU time 56.84 seconds
Started Apr 15 02:24:14 PM PDT 24
Finished Apr 15 02:25:12 PM PDT 24
Peak memory 199648 kb
Host smart-72c767e1-12c7-488f-a902-11f06fdae8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376701406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.3376701406
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.3142493808
Short name T131
Test name
Test status
Simulation time 11548833 ps
CPU time 0.57 seconds
Started Apr 15 02:24:21 PM PDT 24
Finished Apr 15 02:24:22 PM PDT 24
Peak memory 195040 kb
Host smart-bc3bf046-c8bb-4fb4-ae90-a15af9bea0f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142493808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3142493808
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3102401422
Short name T586
Test name
Test status
Simulation time 5763188254 ps
CPU time 60.64 seconds
Started Apr 15 02:24:19 PM PDT 24
Finished Apr 15 02:25:20 PM PDT 24
Peak memory 224220 kb
Host smart-1707e4b3-6dec-4459-8ceb-3e45c1c925bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3102401422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3102401422
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.741053885
Short name T268
Test name
Test status
Simulation time 528578585 ps
CPU time 26.01 seconds
Started Apr 15 02:24:19 PM PDT 24
Finished Apr 15 02:24:46 PM PDT 24
Peak memory 199560 kb
Host smart-bd084082-3419-47b7-bdec-7908472d9200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741053885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.741053885
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.975287445
Short name T56
Test name
Test status
Simulation time 11362942752 ps
CPU time 76.36 seconds
Started Apr 15 02:24:19 PM PDT 24
Finished Apr 15 02:25:36 PM PDT 24
Peak memory 199724 kb
Host smart-418778ff-bee5-48db-a411-52bcb7ec4d05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=975287445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.975287445
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.3005559674
Short name T583
Test name
Test status
Simulation time 1616825469 ps
CPU time 88.68 seconds
Started Apr 15 02:24:18 PM PDT 24
Finished Apr 15 02:25:48 PM PDT 24
Peak memory 199548 kb
Host smart-7ecc3682-abbe-4682-8902-f0d1916f9c6f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005559674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.3005559674
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.4226552874
Short name T322
Test name
Test status
Simulation time 4484003003 ps
CPU time 81.45 seconds
Started Apr 15 02:24:17 PM PDT 24
Finished Apr 15 02:25:39 PM PDT 24
Peak memory 199728 kb
Host smart-18e1dff4-5ce5-4a2d-b35f-64245d234a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226552874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.4226552874
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1804066736
Short name T425
Test name
Test status
Simulation time 189499909 ps
CPU time 5.74 seconds
Started Apr 15 02:24:20 PM PDT 24
Finished Apr 15 02:24:26 PM PDT 24
Peak memory 199600 kb
Host smart-e102174f-fe2d-4f78-b8b5-1cf281e6dd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804066736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1804066736
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.1210574061
Short name T446
Test name
Test status
Simulation time 52746467439 ps
CPU time 584.6 seconds
Started Apr 15 02:24:22 PM PDT 24
Finished Apr 15 02:34:08 PM PDT 24
Peak memory 199680 kb
Host smart-c60e59b8-bc5d-4aae-86e8-6cea59239a6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210574061 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1210574061
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.721084899
Short name T557
Test name
Test status
Simulation time 111901105 ps
CPU time 1.21 seconds
Started Apr 15 02:24:22 PM PDT 24
Finished Apr 15 02:24:24 PM PDT 24
Peak memory 199220 kb
Host smart-3bbc18dc-7c01-4f24-891e-846977e4c80b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721084899 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_hmac_vectors.721084899
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.1652161417
Short name T277
Test name
Test status
Simulation time 56336967068 ps
CPU time 515.69 seconds
Started Apr 15 02:24:21 PM PDT 24
Finished Apr 15 02:32:58 PM PDT 24
Peak memory 199744 kb
Host smart-0e3d4c73-fe09-4f88-846d-e9ef9f7635df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652161417 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.1652161417
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3174868914
Short name T330
Test name
Test status
Simulation time 2845673684 ps
CPU time 37.55 seconds
Started Apr 15 02:24:22 PM PDT 24
Finished Apr 15 02:25:00 PM PDT 24
Peak memory 199728 kb
Host smart-d8831bd4-c87e-423d-b148-cbe52088cdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174868914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3174868914
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.601012112
Short name T292
Test name
Test status
Simulation time 38360171 ps
CPU time 0.58 seconds
Started Apr 15 02:24:27 PM PDT 24
Finished Apr 15 02:24:29 PM PDT 24
Peak memory 195124 kb
Host smart-ea577d99-b219-4dc1-a509-65f2f88ee587
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601012112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.601012112
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.597529564
Short name T399
Test name
Test status
Simulation time 1111500688 ps
CPU time 27.79 seconds
Started Apr 15 02:24:22 PM PDT 24
Finished Apr 15 02:24:51 PM PDT 24
Peak memory 207820 kb
Host smart-1c9a35a4-3614-4efc-9627-dca719005385
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=597529564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.597529564
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1420002314
Short name T476
Test name
Test status
Simulation time 50043195 ps
CPU time 1.43 seconds
Started Apr 15 02:24:21 PM PDT 24
Finished Apr 15 02:24:24 PM PDT 24
Peak memory 199544 kb
Host smart-749d32dd-7a37-4512-a785-2d9d7eb5e249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420002314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1420002314
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3873370927
Short name T83
Test name
Test status
Simulation time 651304802 ps
CPU time 42.19 seconds
Started Apr 15 02:24:24 PM PDT 24
Finished Apr 15 02:25:06 PM PDT 24
Peak memory 199788 kb
Host smart-dfe34e42-4f8b-454a-b3cd-6fba3a4cf5bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3873370927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3873370927
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.1180587792
Short name T43
Test name
Test status
Simulation time 10025309960 ps
CPU time 134.89 seconds
Started Apr 15 02:24:22 PM PDT 24
Finished Apr 15 02:26:38 PM PDT 24
Peak memory 199708 kb
Host smart-36763815-8a1d-4a38-85c6-b8c3e68b1e7f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180587792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1180587792
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.3601548451
Short name T239
Test name
Test status
Simulation time 3533967783 ps
CPU time 45.53 seconds
Started Apr 15 02:24:23 PM PDT 24
Finished Apr 15 02:25:10 PM PDT 24
Peak memory 199684 kb
Host smart-54f66047-fd00-40c3-8df8-068982e8be76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601548451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.3601548451
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.2062325563
Short name T147
Test name
Test status
Simulation time 291894830 ps
CPU time 4.08 seconds
Started Apr 15 02:24:24 PM PDT 24
Finished Apr 15 02:24:29 PM PDT 24
Peak memory 199616 kb
Host smart-cd54ed5f-bede-43c3-92a9-4e4bb24ed3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062325563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.2062325563
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3257442285
Short name T134
Test name
Test status
Simulation time 3912640074 ps
CPU time 185.59 seconds
Started Apr 15 02:24:27 PM PDT 24
Finished Apr 15 02:27:34 PM PDT 24
Peak memory 199708 kb
Host smart-73061f16-5d04-42f1-ba22-9d67ab6e7e76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257442285 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3257442285
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.2550304534
Short name T401
Test name
Test status
Simulation time 120941461 ps
CPU time 1.25 seconds
Started Apr 15 02:24:25 PM PDT 24
Finished Apr 15 02:24:27 PM PDT 24
Peak memory 199548 kb
Host smart-6871046b-2687-472c-9a1f-efe1ed2676b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550304534 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.2550304534
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.3509250776
Short name T249
Test name
Test status
Simulation time 40987769053 ps
CPU time 475.73 seconds
Started Apr 15 02:24:25 PM PDT 24
Finished Apr 15 02:32:22 PM PDT 24
Peak memory 199724 kb
Host smart-ce06d4d8-8fb9-4f45-99a2-de0e9d7f2f4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509250776 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.3509250776
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.477503452
Short name T156
Test name
Test status
Simulation time 1735021267 ps
CPU time 12.38 seconds
Started Apr 15 02:24:22 PM PDT 24
Finished Apr 15 02:24:35 PM PDT 24
Peak memory 199508 kb
Host smart-c6054869-d14c-45d2-9cdc-69b51428f789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477503452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.477503452
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1194471555
Short name T19
Test name
Test status
Simulation time 45816316 ps
CPU time 0.56 seconds
Started Apr 15 02:24:29 PM PDT 24
Finished Apr 15 02:24:31 PM PDT 24
Peak memory 195000 kb
Host smart-8024922a-563b-4fc3-83ce-db09487403f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194471555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1194471555
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.447139020
Short name T362
Test name
Test status
Simulation time 45529109 ps
CPU time 2.03 seconds
Started Apr 15 02:24:25 PM PDT 24
Finished Apr 15 02:24:28 PM PDT 24
Peak memory 207808 kb
Host smart-54991302-822e-4b79-9d51-98fcfc315d9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=447139020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.447139020
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1256730078
Short name T174
Test name
Test status
Simulation time 351242424 ps
CPU time 16.68 seconds
Started Apr 15 02:24:28 PM PDT 24
Finished Apr 15 02:24:45 PM PDT 24
Peak memory 199544 kb
Host smart-f588f1f3-0ba8-4cee-b9fc-72716e1f7d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256730078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1256730078
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2605113060
Short name T267
Test name
Test status
Simulation time 222144039 ps
CPU time 11.53 seconds
Started Apr 15 02:24:26 PM PDT 24
Finished Apr 15 02:24:38 PM PDT 24
Peak memory 199536 kb
Host smart-179cc944-de48-4876-a4aa-a5af2401af9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2605113060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2605113060
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2014151239
Short name T13
Test name
Test status
Simulation time 26958561677 ps
CPU time 119.65 seconds
Started Apr 15 02:24:26 PM PDT 24
Finished Apr 15 02:26:26 PM PDT 24
Peak memory 199736 kb
Host smart-91ba9afb-eac3-41c9-a811-076710f00576
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014151239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2014151239
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1090749942
Short name T37
Test name
Test status
Simulation time 30151445409 ps
CPU time 84.87 seconds
Started Apr 15 02:24:27 PM PDT 24
Finished Apr 15 02:25:53 PM PDT 24
Peak memory 199644 kb
Host smart-2dec182b-d226-45e0-a9ee-bb884b43905c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090749942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1090749942
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.443165999
Short name T413
Test name
Test status
Simulation time 224260239 ps
CPU time 3.53 seconds
Started Apr 15 02:24:26 PM PDT 24
Finished Apr 15 02:24:31 PM PDT 24
Peak memory 199556 kb
Host smart-ab2e619b-2e0b-4418-9a62-ea60b1ffee8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443165999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.443165999
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.603747538
Short name T49
Test name
Test status
Simulation time 429707809592 ps
CPU time 2347.27 seconds
Started Apr 15 02:24:28 PM PDT 24
Finished Apr 15 03:03:36 PM PDT 24
Peak memory 199720 kb
Host smart-38ecb753-00dd-4f36-8ef5-75e58412c5f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603747538 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.603747538
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.2406695825
Short name T329
Test name
Test status
Simulation time 103431264 ps
CPU time 1.16 seconds
Started Apr 15 02:24:27 PM PDT 24
Finished Apr 15 02:24:29 PM PDT 24
Peak memory 199488 kb
Host smart-7f56b1bd-41dd-4412-b6b2-638e5b8477dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406695825 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.2406695825
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.2495802516
Short name T264
Test name
Test status
Simulation time 9028353024 ps
CPU time 475.08 seconds
Started Apr 15 02:24:25 PM PDT 24
Finished Apr 15 02:32:21 PM PDT 24
Peak memory 199716 kb
Host smart-989d3b3f-ef42-4a52-968d-7aad9866966d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495802516 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.2495802516
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1326645762
Short name T431
Test name
Test status
Simulation time 1853019622 ps
CPU time 27.21 seconds
Started Apr 15 02:24:25 PM PDT 24
Finished Apr 15 02:24:54 PM PDT 24
Peak memory 199604 kb
Host smart-f358f150-811a-4278-91ec-c41186e0be51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326645762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1326645762
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1471699947
Short name T416
Test name
Test status
Simulation time 14964460 ps
CPU time 0.61 seconds
Started Apr 15 02:24:34 PM PDT 24
Finished Apr 15 02:24:36 PM PDT 24
Peak memory 195040 kb
Host smart-ff3be6ab-7981-494d-8471-e1f9f0a4857b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471699947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1471699947
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.4031335218
Short name T151
Test name
Test status
Simulation time 1545941434 ps
CPU time 15.6 seconds
Started Apr 15 02:24:29 PM PDT 24
Finished Apr 15 02:24:46 PM PDT 24
Peak memory 207792 kb
Host smart-07e73ad2-b008-474a-ac05-b52cee568a88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4031335218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.4031335218
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3125985184
Short name T160
Test name
Test status
Simulation time 121253516 ps
CPU time 2.32 seconds
Started Apr 15 02:24:28 PM PDT 24
Finished Apr 15 02:24:31 PM PDT 24
Peak memory 199592 kb
Host smart-23c216d8-75d7-476e-bc40-a6043224b9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125985184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3125985184
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.896664767
Short name T365
Test name
Test status
Simulation time 1833328480 ps
CPU time 59.48 seconds
Started Apr 15 02:24:31 PM PDT 24
Finished Apr 15 02:25:31 PM PDT 24
Peak memory 199788 kb
Host smart-4954c92f-fc32-48d7-a664-9c2e43090a57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=896664767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.896664767
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.344008388
Short name T500
Test name
Test status
Simulation time 24109464200 ps
CPU time 27.74 seconds
Started Apr 15 02:24:29 PM PDT 24
Finished Apr 15 02:24:57 PM PDT 24
Peak memory 199640 kb
Host smart-ec1752f5-0a27-4ef6-9ba1-aef2bee5a8db
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344008388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.344008388
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.964055870
Short name T244
Test name
Test status
Simulation time 5376725514 ps
CPU time 75.7 seconds
Started Apr 15 02:24:29 PM PDT 24
Finished Apr 15 02:25:45 PM PDT 24
Peak memory 199728 kb
Host smart-e754a10d-cb2a-4d9d-b80c-231c0ca726cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964055870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.964055870
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3304942704
Short name T335
Test name
Test status
Simulation time 559395839 ps
CPU time 2.52 seconds
Started Apr 15 02:24:30 PM PDT 24
Finished Apr 15 02:24:33 PM PDT 24
Peak memory 199596 kb
Host smart-34804d9b-4b5e-41ea-b683-949045329f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304942704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3304942704
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.3300283921
Short name T534
Test name
Test status
Simulation time 137516431936 ps
CPU time 867.86 seconds
Started Apr 15 02:24:36 PM PDT 24
Finished Apr 15 02:39:05 PM PDT 24
Peak memory 243756 kb
Host smart-63a77794-b21f-42f9-99c1-f6d375e11761
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300283921 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3300283921
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.3901157147
Short name T574
Test name
Test status
Simulation time 52625812 ps
CPU time 1.07 seconds
Started Apr 15 02:24:44 PM PDT 24
Finished Apr 15 02:24:46 PM PDT 24
Peak memory 199484 kb
Host smart-68ed55d1-d5a8-4a5f-b1a0-52b364e8cbaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901157147 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.3901157147
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.2640454382
Short name T192
Test name
Test status
Simulation time 29917286902 ps
CPU time 508.61 seconds
Started Apr 15 02:24:35 PM PDT 24
Finished Apr 15 02:33:04 PM PDT 24
Peak memory 199676 kb
Host smart-348ac18a-a2a4-4034-beb8-5e1299108bd4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640454382 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.2640454382
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.89515273
Short name T144
Test name
Test status
Simulation time 9028315540 ps
CPU time 62.74 seconds
Started Apr 15 02:24:30 PM PDT 24
Finished Apr 15 02:25:33 PM PDT 24
Peak memory 199728 kb
Host smart-27570ddb-323c-4ac7-8edc-2fb48a3060c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89515273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.89515273
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3385987052
Short name T436
Test name
Test status
Simulation time 12665336 ps
CPU time 0.57 seconds
Started Apr 15 02:24:39 PM PDT 24
Finished Apr 15 02:24:40 PM PDT 24
Peak memory 195088 kb
Host smart-ff4cc6dd-7234-4c4a-9661-c240a52b3099
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385987052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3385987052
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.585927404
Short name T346
Test name
Test status
Simulation time 4627808682 ps
CPU time 25.74 seconds
Started Apr 15 02:24:40 PM PDT 24
Finished Apr 15 02:25:07 PM PDT 24
Peak memory 207916 kb
Host smart-c51910a5-fca7-4a4c-b56a-db346c983806
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=585927404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.585927404
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.4174258427
Short name T219
Test name
Test status
Simulation time 4905775754 ps
CPU time 47.22 seconds
Started Apr 15 02:24:39 PM PDT 24
Finished Apr 15 02:25:28 PM PDT 24
Peak memory 199672 kb
Host smart-ed5a6629-4d8a-401d-bd4b-d7365b16a6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174258427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.4174258427
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.1035074865
Short name T135
Test name
Test status
Simulation time 10618805126 ps
CPU time 76.59 seconds
Started Apr 15 02:24:37 PM PDT 24
Finished Apr 15 02:25:54 PM PDT 24
Peak memory 199748 kb
Host smart-5da2d8e4-33f4-4ef8-af8e-12352faf538f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1035074865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1035074865
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.884364222
Short name T48
Test name
Test status
Simulation time 11172176013 ps
CPU time 84.23 seconds
Started Apr 15 02:24:38 PM PDT 24
Finished Apr 15 02:26:03 PM PDT 24
Peak memory 199668 kb
Host smart-854d8891-c4f8-4e9e-a8d2-d9b1de8d5680
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884364222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.884364222
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.353166515
Short name T533
Test name
Test status
Simulation time 905357265 ps
CPU time 51.52 seconds
Started Apr 15 02:24:34 PM PDT 24
Finished Apr 15 02:25:27 PM PDT 24
Peak memory 199620 kb
Host smart-21e2b894-30d3-4c30-ad38-2c813652e805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353166515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.353166515
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2035623161
Short name T275
Test name
Test status
Simulation time 206923942 ps
CPU time 3.44 seconds
Started Apr 15 02:24:34 PM PDT 24
Finished Apr 15 02:24:38 PM PDT 24
Peak memory 199556 kb
Host smart-3c8585c9-81f9-4511-a8cc-ad28fc4591e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035623161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2035623161
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2309167225
Short name T394
Test name
Test status
Simulation time 253914296238 ps
CPU time 703.63 seconds
Started Apr 15 02:24:37 PM PDT 24
Finished Apr 15 02:36:22 PM PDT 24
Peak memory 231900 kb
Host smart-b04a3aad-21e2-4218-879d-c1f6c9b4892d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309167225 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2309167225
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.3262576817
Short name T124
Test name
Test status
Simulation time 61008334 ps
CPU time 1.3 seconds
Started Apr 15 02:24:39 PM PDT 24
Finished Apr 15 02:24:41 PM PDT 24
Peak memory 199176 kb
Host smart-fd0114ac-53fb-4c90-8a07-5f1dd7987d41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262576817 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.3262576817
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.3028671196
Short name T328
Test name
Test status
Simulation time 168840429221 ps
CPU time 537.25 seconds
Started Apr 15 02:24:38 PM PDT 24
Finished Apr 15 02:33:37 PM PDT 24
Peak memory 199720 kb
Host smart-e6e23646-3c80-4ad3-a727-38f8dada44b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028671196 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.3028671196
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.75151497
Short name T287
Test name
Test status
Simulation time 25426564224 ps
CPU time 86.21 seconds
Started Apr 15 02:24:37 PM PDT 24
Finished Apr 15 02:26:04 PM PDT 24
Peak memory 199728 kb
Host smart-6243dcb1-5b28-4215-bba2-b9aa5fa3251d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75151497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.75151497
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.643185899
Short name T197
Test name
Test status
Simulation time 14457932 ps
CPU time 0.56 seconds
Started Apr 15 02:21:50 PM PDT 24
Finished Apr 15 02:21:55 PM PDT 24
Peak memory 195108 kb
Host smart-2f0d12c4-af7a-4823-a657-2e52bb5348b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643185899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.643185899
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2830589854
Short name T343
Test name
Test status
Simulation time 8998022808 ps
CPU time 25.61 seconds
Started Apr 15 02:21:57 PM PDT 24
Finished Apr 15 02:22:25 PM PDT 24
Peak memory 224328 kb
Host smart-37ca1b83-07d8-4701-80b7-669854d65fbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2830589854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2830589854
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1085407308
Short name T307
Test name
Test status
Simulation time 4101710851 ps
CPU time 19.6 seconds
Started Apr 15 02:21:49 PM PDT 24
Finished Apr 15 02:22:13 PM PDT 24
Peak memory 199632 kb
Host smart-bb666521-74b0-4281-8f81-f2d459803f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085407308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1085407308
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2823549464
Short name T439
Test name
Test status
Simulation time 180468614 ps
CPU time 10.6 seconds
Started Apr 15 02:21:56 PM PDT 24
Finished Apr 15 02:22:09 PM PDT 24
Peak memory 199612 kb
Host smart-01f15b1f-db41-4f4c-830e-73f74afd8cd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2823549464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2823549464
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1893745999
Short name T47
Test name
Test status
Simulation time 3365264777 ps
CPU time 51.53 seconds
Started Apr 15 02:21:56 PM PDT 24
Finished Apr 15 02:22:50 PM PDT 24
Peak memory 199760 kb
Host smart-8ad55264-a091-4521-9137-46cab32210c7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893745999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1893745999
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.1205860778
Short name T231
Test name
Test status
Simulation time 3790429209 ps
CPU time 51.52 seconds
Started Apr 15 02:21:42 PM PDT 24
Finished Apr 15 02:22:37 PM PDT 24
Peak memory 199688 kb
Host smart-54707d69-4234-4941-be33-c92b13e62425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205860778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1205860778
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3906331127
Short name T85
Test name
Test status
Simulation time 1408423820 ps
CPU time 5.18 seconds
Started Apr 15 02:21:45 PM PDT 24
Finished Apr 15 02:21:55 PM PDT 24
Peak memory 199608 kb
Host smart-b0405bad-b0a1-4745-bb28-b58bccf50214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906331127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3906331127
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.351076085
Short name T411
Test name
Test status
Simulation time 238494272417 ps
CPU time 1091.91 seconds
Started Apr 15 02:21:52 PM PDT 24
Finished Apr 15 02:40:08 PM PDT 24
Peak memory 231916 kb
Host smart-09d7863a-c729-46a2-ada3-fbb027b5bb1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351076085 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.351076085
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.1462925809
Short name T213
Test name
Test status
Simulation time 60208632 ps
CPU time 1.13 seconds
Started Apr 15 02:21:47 PM PDT 24
Finished Apr 15 02:21:53 PM PDT 24
Peak memory 199612 kb
Host smart-b76deab7-2444-484d-ab89-b253eb831562
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462925809 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.1462925809
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.3270346423
Short name T162
Test name
Test status
Simulation time 6944333830 ps
CPU time 386.9 seconds
Started Apr 15 02:21:48 PM PDT 24
Finished Apr 15 02:28:19 PM PDT 24
Peak memory 199732 kb
Host smart-1fc62996-428f-44a6-83c3-6d30683584f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270346423 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.3270346423
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3299669748
Short name T202
Test name
Test status
Simulation time 3558302703 ps
CPU time 55.9 seconds
Started Apr 15 02:21:48 PM PDT 24
Finished Apr 15 02:22:48 PM PDT 24
Peak memory 199736 kb
Host smart-89b7e15f-66ca-42ed-abb2-32db3d5d454b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299669748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3299669748
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/57.hmac_stress_all_with_rand_reset.2055508781
Short name T11
Test name
Test status
Simulation time 8646296953 ps
CPU time 107.63 seconds
Started Apr 15 02:24:52 PM PDT 24
Finished Apr 15 02:26:40 PM PDT 24
Peak memory 212300 kb
Host smart-9d08840b-54a1-4aac-b8e9-38537868d9cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2055508781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.hmac_stress_all_with_rand_reset.2055508781
Directory /workspace/57.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2181009918
Short name T263
Test name
Test status
Simulation time 53489936 ps
CPU time 0.6 seconds
Started Apr 15 02:21:57 PM PDT 24
Finished Apr 15 02:22:00 PM PDT 24
Peak memory 195200 kb
Host smart-1aac1590-c110-4916-8370-0e35c70c368a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181009918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2181009918
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.2634954915
Short name T391
Test name
Test status
Simulation time 1956588744 ps
CPU time 18.69 seconds
Started Apr 15 02:21:46 PM PDT 24
Finished Apr 15 02:22:09 PM PDT 24
Peak memory 223644 kb
Host smart-ab381923-f604-42b4-b454-16e08468db10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2634954915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2634954915
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1687304508
Short name T199
Test name
Test status
Simulation time 9230634019 ps
CPU time 44.48 seconds
Started Apr 15 02:21:49 PM PDT 24
Finished Apr 15 02:22:38 PM PDT 24
Peak memory 199376 kb
Host smart-e35da8d2-210d-4c4d-8d4f-68d3f98c3248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687304508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1687304508
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3432595070
Short name T177
Test name
Test status
Simulation time 440893781 ps
CPU time 7.7 seconds
Started Apr 15 02:21:49 PM PDT 24
Finished Apr 15 02:22:01 PM PDT 24
Peak memory 199280 kb
Host smart-b172ec19-7d9d-4894-b000-82ddc0558242
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3432595070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3432595070
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3885608733
Short name T390
Test name
Test status
Simulation time 980491417 ps
CPU time 53.11 seconds
Started Apr 15 02:21:47 PM PDT 24
Finished Apr 15 02:22:44 PM PDT 24
Peak memory 199592 kb
Host smart-2b9af6a6-da3e-4990-a00c-8ddeca635301
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885608733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3885608733
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.478116594
Short name T569
Test name
Test status
Simulation time 2122502259 ps
CPU time 29.01 seconds
Started Apr 15 02:21:53 PM PDT 24
Finished Apr 15 02:22:25 PM PDT 24
Peak memory 199472 kb
Host smart-c981ef2e-d8d9-47f9-a020-a1760b8986be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478116594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.478116594
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.17600175
Short name T395
Test name
Test status
Simulation time 276544605 ps
CPU time 1.06 seconds
Started Apr 15 02:21:47 PM PDT 24
Finished Apr 15 02:21:52 PM PDT 24
Peak memory 199488 kb
Host smart-4e42e795-d9f1-4605-b8b4-cbf0b1e72259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17600175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.17600175
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.1592940015
Short name T284
Test name
Test status
Simulation time 39627977524 ps
CPU time 574.65 seconds
Started Apr 15 02:21:47 PM PDT 24
Finished Apr 15 02:31:25 PM PDT 24
Peak memory 241328 kb
Host smart-34c910a1-c057-4406-b383-92dd3267823a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592940015 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1592940015
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.1286106724
Short name T398
Test name
Test status
Simulation time 105974857 ps
CPU time 1.18 seconds
Started Apr 15 02:21:57 PM PDT 24
Finished Apr 15 02:22:00 PM PDT 24
Peak memory 199564 kb
Host smart-623749a9-675c-4fd6-97c2-59916f790915
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286106724 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.1286106724
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.2923710610
Short name T141
Test name
Test status
Simulation time 175867661151 ps
CPU time 513.97 seconds
Started Apr 15 02:21:57 PM PDT 24
Finished Apr 15 02:30:33 PM PDT 24
Peak memory 199708 kb
Host smart-b7b4e2a9-9895-40b7-beed-8d418cc7ee7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923710610 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.2923710610
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2052878684
Short name T596
Test name
Test status
Simulation time 4098464118 ps
CPU time 38.85 seconds
Started Apr 15 02:21:48 PM PDT 24
Finished Apr 15 02:22:31 PM PDT 24
Peak memory 199732 kb
Host smart-53c611c6-2b38-4054-b572-5bfc3c75f65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052878684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2052878684
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.966795681
Short name T2
Test name
Test status
Simulation time 50209698 ps
CPU time 0.54 seconds
Started Apr 15 02:21:50 PM PDT 24
Finished Apr 15 02:21:54 PM PDT 24
Peak memory 194116 kb
Host smart-c6f8990b-a11f-436f-9387-e1855d7e374b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966795681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.966795681
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1323388788
Short name T261
Test name
Test status
Simulation time 3672841664 ps
CPU time 73.87 seconds
Started Apr 15 02:21:47 PM PDT 24
Finished Apr 15 02:23:06 PM PDT 24
Peak memory 226340 kb
Host smart-2a8631ff-7ec7-4691-8ffa-ae324fabda8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1323388788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1323388788
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1992269297
Short name T498
Test name
Test status
Simulation time 1999849825 ps
CPU time 38.95 seconds
Started Apr 15 02:21:53 PM PDT 24
Finished Apr 15 02:22:35 PM PDT 24
Peak memory 199492 kb
Host smart-05fef372-77e7-4666-92e3-90d3b8d9fa11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992269297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1992269297
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.3435824927
Short name T127
Test name
Test status
Simulation time 1281743635 ps
CPU time 74.09 seconds
Started Apr 15 02:21:50 PM PDT 24
Finished Apr 15 02:23:08 PM PDT 24
Peak memory 199508 kb
Host smart-b8383229-25af-4d77-a059-1b63850a7efc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3435824927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3435824927
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.3738851757
Short name T462
Test name
Test status
Simulation time 8454624128 ps
CPU time 200.34 seconds
Started Apr 15 02:21:50 PM PDT 24
Finished Apr 15 02:25:15 PM PDT 24
Peak memory 199692 kb
Host smart-32fc5d0c-0b57-4f90-b981-6bc290aa8ab2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738851757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3738851757
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.4252189828
Short name T456
Test name
Test status
Simulation time 1954938692 ps
CPU time 26.74 seconds
Started Apr 15 02:21:47 PM PDT 24
Finished Apr 15 02:22:18 PM PDT 24
Peak memory 199620 kb
Host smart-18e98952-364b-47bb-a0b2-1d3c17293023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252189828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.4252189828
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1767171932
Short name T159
Test name
Test status
Simulation time 603487401 ps
CPU time 2.69 seconds
Started Apr 15 02:21:50 PM PDT 24
Finished Apr 15 02:21:57 PM PDT 24
Peak memory 199512 kb
Host smart-043661b9-cb81-4917-876a-f4f2351ce41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767171932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1767171932
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.3679982351
Short name T546
Test name
Test status
Simulation time 183943390304 ps
CPU time 1210.63 seconds
Started Apr 15 02:22:01 PM PDT 24
Finished Apr 15 02:42:13 PM PDT 24
Peak memory 216112 kb
Host smart-f1db881f-7840-4ef6-b76f-e8c125e5a9da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679982351 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.3679982351
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.1102462267
Short name T81
Test name
Test status
Simulation time 158033279 ps
CPU time 1.08 seconds
Started Apr 15 02:21:50 PM PDT 24
Finished Apr 15 02:21:56 PM PDT 24
Peak memory 199436 kb
Host smart-14064431-a44f-4ce2-ba7a-044e680b4cc4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102462267 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.1102462267
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.385993366
Short name T247
Test name
Test status
Simulation time 56954628624 ps
CPU time 483.02 seconds
Started Apr 15 02:21:48 PM PDT 24
Finished Apr 15 02:29:56 PM PDT 24
Peak memory 199704 kb
Host smart-cd5251ae-0337-4364-9481-7fa287fe4486
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385993366 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.385993366
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1563853489
Short name T79
Test name
Test status
Simulation time 644574748 ps
CPU time 26.72 seconds
Started Apr 15 02:21:47 PM PDT 24
Finished Apr 15 02:22:19 PM PDT 24
Peak memory 199608 kb
Host smart-734a5522-544d-45ff-a2c1-8bfcf3f2ea95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563853489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1563853489
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/75.hmac_stress_all_with_rand_reset.303957721
Short name T21
Test name
Test status
Simulation time 83689533607 ps
CPU time 2319.63 seconds
Started Apr 15 02:24:49 PM PDT 24
Finished Apr 15 03:03:29 PM PDT 24
Peak memory 232552 kb
Host smart-0e089be2-a2ce-45ae-b08f-323274a0e7db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=303957721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.hmac_stress_all_with_rand_reset.303957721
Directory /workspace/75.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.hmac_stress_all_with_rand_reset.3498930467
Short name T67
Test name
Test status
Simulation time 4393606695 ps
CPU time 90.18 seconds
Started Apr 15 02:24:47 PM PDT 24
Finished Apr 15 02:26:17 PM PDT 24
Peak memory 216116 kb
Host smart-e66ff5c5-e14f-4e8d-9c08-c7d617f73905
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3498930467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.hmac_stress_all_with_rand_reset.3498930467
Directory /workspace/77.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3178871042
Short name T260
Test name
Test status
Simulation time 35175139 ps
CPU time 0.54 seconds
Started Apr 15 02:21:51 PM PDT 24
Finished Apr 15 02:21:56 PM PDT 24
Peak memory 194112 kb
Host smart-10145758-bcd8-4762-b4b1-b47831a9d6ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178871042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3178871042
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3638597446
Short name T301
Test name
Test status
Simulation time 2796866181 ps
CPU time 56.9 seconds
Started Apr 15 02:21:56 PM PDT 24
Finished Apr 15 02:22:55 PM PDT 24
Peak memory 240168 kb
Host smart-107d0d14-4d72-470c-8df4-132bd291220b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3638597446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3638597446
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3083501190
Short name T461
Test name
Test status
Simulation time 2141000578 ps
CPU time 21.92 seconds
Started Apr 15 02:21:52 PM PDT 24
Finished Apr 15 02:22:18 PM PDT 24
Peak memory 199512 kb
Host smart-9b440c14-a615-48ae-b0a6-5a93ebb1feec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083501190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3083501190
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3694269022
Short name T484
Test name
Test status
Simulation time 6356030185 ps
CPU time 91.3 seconds
Started Apr 15 02:21:52 PM PDT 24
Finished Apr 15 02:23:27 PM PDT 24
Peak memory 199724 kb
Host smart-93ba8887-2fe1-4018-bc09-ac0a004793f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3694269022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3694269022
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.2581175986
Short name T556
Test name
Test status
Simulation time 2716328107 ps
CPU time 17.39 seconds
Started Apr 15 02:21:51 PM PDT 24
Finished Apr 15 02:22:12 PM PDT 24
Peak memory 199716 kb
Host smart-2db97035-a682-4cfc-9710-e4a0f384d4a4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581175986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2581175986
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3331046141
Short name T337
Test name
Test status
Simulation time 994698711 ps
CPU time 55.43 seconds
Started Apr 15 02:21:52 PM PDT 24
Finished Apr 15 02:22:51 PM PDT 24
Peak memory 199552 kb
Host smart-8d6f7a78-293a-44bc-9949-950de8975007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331046141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3331046141
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.4034631930
Short name T200
Test name
Test status
Simulation time 1471592519 ps
CPU time 6.46 seconds
Started Apr 15 02:21:52 PM PDT 24
Finished Apr 15 02:22:02 PM PDT 24
Peak memory 199536 kb
Host smart-f3e0acfe-a554-4ae7-a6d6-3bfb64a5a3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034631930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.4034631930
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2692532103
Short name T377
Test name
Test status
Simulation time 76032840123 ps
CPU time 1010.82 seconds
Started Apr 15 02:21:53 PM PDT 24
Finished Apr 15 02:38:47 PM PDT 24
Peak memory 199724 kb
Host smart-42f5d2a6-e2c7-4300-ac8c-5392a85bb60f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692532103 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2692532103
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.1670144333
Short name T166
Test name
Test status
Simulation time 27997791 ps
CPU time 0.94 seconds
Started Apr 15 02:21:52 PM PDT 24
Finished Apr 15 02:21:57 PM PDT 24
Peak memory 198992 kb
Host smart-bad3842e-3f61-4243-b683-8df07c7a450b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670144333 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.1670144333
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.1132427533
Short name T195
Test name
Test status
Simulation time 42871030834 ps
CPU time 536.17 seconds
Started Apr 15 02:21:50 PM PDT 24
Finished Apr 15 02:30:51 PM PDT 24
Peak memory 199728 kb
Host smart-73423ab2-47cc-4f54-9e3e-1b2064a65f9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132427533 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.1132427533
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2840207683
Short name T531
Test name
Test status
Simulation time 1640932446 ps
CPU time 28.36 seconds
Started Apr 15 02:21:50 PM PDT 24
Finished Apr 15 02:22:23 PM PDT 24
Peak memory 199608 kb
Host smart-9214f4ea-9269-4811-b3d4-7fe7601f8a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840207683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2840207683
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1685580318
Short name T433
Test name
Test status
Simulation time 13607754 ps
CPU time 0.56 seconds
Started Apr 15 02:21:54 PM PDT 24
Finished Apr 15 02:21:58 PM PDT 24
Peak memory 195064 kb
Host smart-7617954c-6798-4a89-abcc-22f5c86d9f44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685580318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1685580318
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2272255229
Short name T245
Test name
Test status
Simulation time 2410271614 ps
CPU time 42.83 seconds
Started Apr 15 02:21:54 PM PDT 24
Finished Apr 15 02:22:40 PM PDT 24
Peak memory 215504 kb
Host smart-623feb6f-2894-40f2-aff6-baba5ba7003a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2272255229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2272255229
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2622521195
Short name T309
Test name
Test status
Simulation time 2339632788 ps
CPU time 28 seconds
Started Apr 15 02:21:51 PM PDT 24
Finished Apr 15 02:22:23 PM PDT 24
Peak memory 199760 kb
Host smart-2142c28e-bac2-4da4-865c-a318f218306c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622521195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2622521195
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3246392628
Short name T502
Test name
Test status
Simulation time 589605722 ps
CPU time 32.39 seconds
Started Apr 15 02:21:50 PM PDT 24
Finished Apr 15 02:22:27 PM PDT 24
Peak memory 199588 kb
Host smart-a7956293-a159-4d6b-bc50-cb07bc95d8ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3246392628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3246392628
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.1864796148
Short name T342
Test name
Test status
Simulation time 2129851731 ps
CPU time 27.09 seconds
Started Apr 15 02:21:57 PM PDT 24
Finished Apr 15 02:22:26 PM PDT 24
Peak memory 199624 kb
Host smart-501a9910-2e21-490c-8771-a39d434d38de
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864796148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1864796148
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3053917895
Short name T225
Test name
Test status
Simulation time 1394420471 ps
CPU time 46.26 seconds
Started Apr 15 02:21:51 PM PDT 24
Finished Apr 15 02:22:41 PM PDT 24
Peak memory 199612 kb
Host smart-3deb2c17-fd28-4a2d-974d-5dc1a8431f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053917895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3053917895
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.907891090
Short name T132
Test name
Test status
Simulation time 64772109 ps
CPU time 0.87 seconds
Started Apr 15 02:21:52 PM PDT 24
Finished Apr 15 02:21:57 PM PDT 24
Peak memory 198004 kb
Host smart-fc2b4e0d-f928-44d4-b7ee-79b07bd5caf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907891090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.907891090
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1677525840
Short name T423
Test name
Test status
Simulation time 11231400731 ps
CPU time 598.2 seconds
Started Apr 15 02:21:56 PM PDT 24
Finished Apr 15 02:31:57 PM PDT 24
Peak memory 207944 kb
Host smart-af4ec1aa-7354-44a7-8334-2d3f8d8b6d4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677525840 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1677525840
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.3647321836
Short name T55
Test name
Test status
Simulation time 30091182 ps
CPU time 1.26 seconds
Started Apr 15 02:21:54 PM PDT 24
Finished Apr 15 02:21:59 PM PDT 24
Peak memory 199584 kb
Host smart-08c93c18-dc95-4388-950b-1986359547eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647321836 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.3647321836
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.992366490
Short name T121
Test name
Test status
Simulation time 41054354266 ps
CPU time 528.61 seconds
Started Apr 15 02:21:55 PM PDT 24
Finished Apr 15 02:30:47 PM PDT 24
Peak memory 199696 kb
Host smart-4e3d4832-f894-426e-9126-e57ea5f007a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992366490 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.992366490
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.4118211647
Short name T357
Test name
Test status
Simulation time 4259941612 ps
CPU time 33.58 seconds
Started Apr 15 02:22:00 PM PDT 24
Finished Apr 15 02:22:35 PM PDT 24
Peak memory 199740 kb
Host smart-031627fc-e435-4a55-a9bb-69f4ee075309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118211647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.4118211647
Directory /workspace/9.hmac_wipe_secret/latest

Test location /workspace/coverage/default/92.hmac_stress_all_with_rand_reset.969263465
Short name T9
Test name
Test status
Simulation time 89682167865 ps
CPU time 2871.71 seconds
Started Apr 15 02:24:55 PM PDT 24
Finished Apr 15 03:12:47 PM PDT 24
Peak memory 246716 kb
Host smart-c0bb6b7e-fc45-489d-b7c9-161ca57735a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=969263465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.hmac_stress_all_with_rand_reset.969263465
Directory /workspace/92.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.hmac_stress_all_with_rand_reset.1603071168
Short name T75
Test name
Test status
Simulation time 91239352078 ps
CPU time 153.17 seconds
Started Apr 15 02:24:56 PM PDT 24
Finished Apr 15 02:27:29 PM PDT 24
Peak memory 210592 kb
Host smart-aa7a7e20-5ab5-4c5e-a402-f5ff250281fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1603071168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.hmac_stress_all_with_rand_reset.1603071168
Directory /workspace/96.hmac_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%