Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15140722	1			T1	8886		T2	11668		T3	35
all_values[1]	15140722	1			T1	8886		T2	11668		T3	35
all_values[2]	15140722	1			T1	8886		T2	11668		T3	35

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

98451

1

T2

696

T5

1426

T4

40

auto[1]

45323715

1

T1

26658

T2

34308

T3

105

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42867371

1

T1

22852

T2

34954

T3

101

auto[1]

2554795

1

T1

3806

T2

50

T3

4

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	38377	1			T4	9		T6	1		T93	319
all_values[0]	auto[0]	auto[1]	473	1			T4	2		T6	6		T33	2
all_values[0]	auto[1]	auto[0]	15050664	1			T1	8876		T2	11618		T3	31
all_values[0]	auto[1]	auto[1]	51208	1			T1	10		T2	50		T3	4
all_values[1]	auto[0]	auto[0]	34169	1			T2	696		T5	1426		T4	10
all_values[1]	auto[0]	auto[1]	212	1			T4	1		T6	2		T33	1
all_values[1]	auto[1]	auto[0]	15105645	1			T1	8886		T2	10972		T3	35
all_values[1]	auto[1]	auto[1]	696	1			T4	5		T6	3		T28	1
all_values[2]	auto[0]	auto[0]	20588	1			T4	17		T29	23		T33	2
all_values[2]	auto[0]	auto[1]	4632	1			T4	1		T6	1		T28	3
all_values[2]	auto[1]	auto[0]	12617928	1			T1	5090		T2	11668		T3	35
all_values[2]	auto[1]	auto[1]	2497574	1			T1	3796		T26	15		T5	2594