Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7349767

1

T1

1132

T2

5563

T3

30

auto[1]

2959270

1

T1

2438

T2

5892

T5

883

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2942461

1

T1

1045

T2

6040

T5

916

auto[1]

7366576

1

T1

2525

T2

5415

T3

30

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6580913

1

T1

2558

T2

6452

T5

916

auto[1]

3728124

1

T1

1012

T2

5003

T3

30

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6447926	1			T1	3288		T2	4000		T3	3
fifo_depth[1]	474439	1			T1	163		T2	874		T3	4
fifo_depth[2]	395752	1			T1	80		T2	840		T3	5
fifo_depth[3]	329697	1			T1	32		T2	817		T3	2
fifo_depth[4]	292527	1			T1	5		T2	773		T3	2
fifo_depth[5]	263307	1			T1	1		T2	823		T3	1
fifo_depth[6]	253478	1			T1	1		T2	809		T3	2
fifo_depth[7]	223814	1			T2	761		T3	2		T4	3
fifo_depth[8]	209328	1			T2	649		T3	2		T4	4
fifo_depth[9]	141201	1			T2	461		T3	3		T6	1301
fifo_depth[10]	113193	1			T2	279		T3	2		T6	826
fifo_depth[11]	68242	1			T2	199		T3	1		T6	441
fifo_depth[12]	74328	1			T2	101		T3	1		T6	244
fifo_depth[13]	37411	1			T2	41		T6	98		T29	31
fifo_depth[14]	51711	1			T2	20		T6	51		T29	12
fifo_depth[15]	32724	1			T2	3		T6	20		T29	2
fifo_depth[16]	126428	1			T2	1		T6	9		T29	1

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4019517

1

T1

282

T2

7455

T3

27

auto[1]

6289520

1

T1

3288

T2

4000

T3

3

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10150631

1

T1

3570

T2

11455

T3

30

auto[1]

158406

1

T17

320

T18

1318

T19

2061

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

288532

1

T2

508

T5

29

T4

221

auto[0]

auto[0]

auto[0]

auto[1]

305744

1

T1

94

T2

1655

T4

522

auto[0]

auto[0]

auto[1]

auto[0]

1092601

1

T1

15

T2

1005

T4

753

auto[0]

auto[0]

auto[1]

auto[1]

277823

1

T1

85

T2

972

T4

343

auto[0]

auto[1]

auto[0]

auto[0]

519366

1

T2

1350

T4

259

T6

1939

auto[0]

auto[1]

auto[0]

auto[1]

513251

1

T2

405

T4

492

T6

1701

auto[0]

auto[1]

auto[1]

auto[0]

511528

1

T1

44

T2

758

T3

27

auto[0]

auto[1]

auto[1]

auto[1]

510672

1

T1

44

T2

802

T5

107

auto[1]

auto[0]

auto[0]

auto[0]

232257

1

T1

1

T2

334

T5

886

auto[1]

auto[0]

auto[0]

auto[1]

265225

1

T1

950

T2

914

T4

6906

auto[1]

auto[0]

auto[1]

auto[0]

3867599

1

T1

494

T2

539

T5

1

auto[1]

auto[0]

auto[1]

auto[1]

251132

1

T1

919

T2

525

T4

3146

auto[1]

auto[1]

auto[0]

auto[0]

407043

1

T2

669

T4

3963

T6

2269

auto[1]

auto[1]

auto[0]

auto[1]

411043

1

T2

205

T5

1

T4

6428

auto[1]

auto[1]

auto[1]

auto[0]

430841

1

T1

578

T2

400

T3

3

auto[1]

auto[1]

auto[1]

auto[1]

424380

1

T1

346

T2

414

T5

775

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

502775

1

T1

1

T2

842

T5

915

auto[0]

auto[0]

auto[0]

auto[1]

549968

1

T1

1044

T2

2569

T4

7428

auto[0]

auto[0]

auto[1]

auto[0]

4935632

1

T1

509

T2

1544

T5

1

auto[0]

auto[0]

auto[1]

auto[1]

511407

1

T1

1004

T2

1497

T4

3489

auto[0]

auto[1]

auto[0]

auto[0]

907169

1

T2

2019

T4

4222

T6

4208

auto[0]

auto[1]

auto[0]

auto[1]

905440

1

T2

610

T5

1

T4

6920

auto[0]

auto[1]

auto[1]

auto[0]

918711

1

T1

622

T2

1158

T3

30

auto[0]

auto[1]

auto[1]

auto[1]

919529

1

T1

390

T2

1216

T5

882

auto[1]

auto[0]

auto[0]

auto[0]

18014

1

T17

28

T18

27

T19

225

auto[1]

auto[0]

auto[0]

auto[1]

21001

1

T18

162

T19

1345

T20

1

auto[1]

auto[0]

auto[1]

auto[0]

24568

1

T18

149

T19

20

T20

1

auto[1]

auto[0]

auto[1]

auto[1]

17548

1

T18

45

T19

275

T21

184

auto[1]

auto[1]

auto[0]

auto[0]

19240

1

T21

79

T80

718

T22

3

auto[1]

auto[1]

auto[0]

auto[1]

18854

1

T17

292

T18

700

T19

151

auto[1]

auto[1]

auto[1]

auto[0]

23658

1

T18

224

T19

40

T21

273

auto[1]

auto[1]

auto[1]

auto[1]

15523

1

T18

11

T19

5

T20

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	250271	1			T1	1		T2	334		T5	886
fifo_depth[0]	auto[0]	auto[0]	auto[1]	286226	1			T1	950		T2	914		T4	6906
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3892167	1			T1	494		T2	539		T5	1
fifo_depth[0]	auto[0]	auto[1]	auto[1]	268680	1			T1	919		T2	525		T4	3146
fifo_depth[0]	auto[1]	auto[0]	auto[0]	426283	1			T2	669		T4	3963		T6	2269
fifo_depth[0]	auto[1]	auto[0]	auto[1]	429897	1			T2	205		T5	1		T4	6428
fifo_depth[0]	auto[1]	auto[1]	auto[0]	454499	1			T1	578		T2	400		T3	3
fifo_depth[0]	auto[1]	auto[1]	auto[1]	439903	1			T1	346		T2	414		T5	775
fifo_depth[1]	auto[0]	auto[0]	auto[0]	19646	1			T2	66		T5	27		T4	133
fifo_depth[1]	auto[0]	auto[0]	auto[1]	22487	1			T1	45		T2	178		T4	246
fifo_depth[1]	auto[0]	auto[1]	auto[0]	218655	1			T1	14		T2	128		T4	426
fifo_depth[1]	auto[0]	auto[1]	auto[1]	20048	1			T1	59		T2	112		T4	164
fifo_depth[1]	auto[1]	auto[0]	auto[0]	47684	1			T2	159		T4	157		T6	267
fifo_depth[1]	auto[1]	auto[0]	auto[1]	47695	1			T2	41		T4	299		T6	181
fifo_depth[1]	auto[1]	auto[1]	auto[0]	48754	1			T1	25		T2	98		T3	4
fifo_depth[1]	auto[1]	auto[1]	auto[1]	49470	1			T1	20		T2	92		T5	45
fifo_depth[2]	auto[0]	auto[0]	auto[0]	17452	1			T2	54		T5	2		T4	42
fifo_depth[2]	auto[0]	auto[0]	auto[1]	19487	1			T1	30		T2	185		T4	133
fifo_depth[2]	auto[0]	auto[1]	auto[0]	165618	1			T1	1		T2	111		T4	213
fifo_depth[2]	auto[0]	auto[1]	auto[1]	16951	1			T1	19		T2	103		T4	93
fifo_depth[2]	auto[1]	auto[0]	auto[0]	44233	1			T2	152		T4	66		T6	262
fifo_depth[2]	auto[1]	auto[0]	auto[1]	43259	1			T2	46		T4	132		T6	185
fifo_depth[2]	auto[1]	auto[1]	auto[0]	43858	1			T1	13		T2	87		T3	5
fifo_depth[2]	auto[1]	auto[1]	auto[1]	44894	1			T1	17		T2	102		T5	40
fifo_depth[3]	auto[0]	auto[0]	auto[0]	14602	1			T2	60		T4	22		T6	148
fifo_depth[3]	auto[0]	auto[0]	auto[1]	16488	1			T1	16		T2	187		T4	70
fifo_depth[3]	auto[0]	auto[1]	auto[0]	124725	1			T2	110		T4	63		T6	2387
fifo_depth[3]	auto[0]	auto[1]	auto[1]	14023	1			T1	7		T2	91		T4	33
fifo_depth[3]	auto[1]	auto[0]	auto[0]	40175	1			T2	154		T4	20		T6	239
fifo_depth[3]	auto[1]	auto[0]	auto[1]	38861	1			T2	50		T4	35		T6	175
fifo_depth[3]	auto[1]	auto[1]	auto[0]	39725	1			T1	6		T2	80		T3	2
fifo_depth[3]	auto[1]	auto[1]	auto[1]	41098	1			T1	3		T2	85		T5	14
fifo_depth[4]	auto[0]	auto[0]	auto[0]	14831	1			T2	52		T4	21		T6	181
fifo_depth[4]	auto[0]	auto[0]	auto[1]	16586	1			T1	2		T2	180		T4	49
fifo_depth[4]	auto[0]	auto[1]	auto[0]	93104	1			T2	100		T4	35		T6	2129
fifo_depth[4]	auto[0]	auto[1]	auto[1]	13467	1			T2	108		T4	39		T6	244
fifo_depth[4]	auto[1]	auto[0]	auto[0]	39108	1			T2	145		T4	13		T6	187
fifo_depth[4]	auto[1]	auto[0]	auto[1]	37111	1			T2	37		T4	20		T6	165
fifo_depth[4]	auto[1]	auto[1]	auto[0]	38577	1			T2	74		T3	2		T4	19
fifo_depth[4]	auto[1]	auto[1]	auto[1]	39743	1			T1	3		T2	77		T5	5
fifo_depth[5]	auto[0]	auto[0]	auto[0]	12837	1			T2	60		T4	2		T6	162
fifo_depth[5]	auto[0]	auto[0]	auto[1]	14267	1			T2	179		T4	13		T6	135
fifo_depth[5]	auto[0]	auto[1]	auto[0]	77071	1			T2	118		T4	9		T6	1831
fifo_depth[5]	auto[0]	auto[1]	auto[1]	12025	1			T2	98		T4	7		T6	246
fifo_depth[5]	auto[1]	auto[0]	auto[0]	37214	1			T2	141		T4	1		T6	187
fifo_depth[5]	auto[1]	auto[0]	auto[1]	35361	1			T2	44		T4	3		T6	180
fifo_depth[5]	auto[1]	auto[1]	auto[0]	36730	1			T2	81		T3	1		T4	7
fifo_depth[5]	auto[1]	auto[1]	auto[1]	37802	1			T1	1		T2	102		T5	2
fifo_depth[6]	auto[0]	auto[0]	auto[0]	13768	1			T2	59		T4	1		T6	176
fifo_depth[6]	auto[0]	auto[0]	auto[1]	14685	1			T1	1		T2	188		T4	7
fifo_depth[6]	auto[0]	auto[1]	auto[0]	67813	1			T2	101		T4	6		T6	1617
fifo_depth[6]	auto[0]	auto[1]	auto[1]	12060	1			T2	112		T4	7		T6	244
fifo_depth[6]	auto[1]	auto[0]	auto[0]	37157	1			T2	143		T4	2		T6	189
fifo_depth[6]	auto[1]	auto[0]	auto[1]	34668	1			T2	44		T4	1		T6	207
fifo_depth[6]	auto[1]	auto[1]	auto[0]	36091	1			T2	73		T3	2		T4	4
fifo_depth[6]	auto[1]	auto[1]	auto[1]	37236	1			T2	89		T5	1		T4	2
fifo_depth[7]	auto[0]	auto[0]	auto[0]	11990	1			T2	43		T6	150		T29	15
fifo_depth[7]	auto[0]	auto[0]	auto[1]	12857	1			T2	167		T4	2		T6	143
fifo_depth[7]	auto[0]	auto[1]	auto[0]	54102	1			T2	111		T6	1198		T29	159
fifo_depth[7]	auto[0]	auto[1]	auto[1]	10787	1			T2	101		T6	181		T29	143
fifo_depth[7]	auto[1]	auto[0]	auto[0]	34041	1			T2	133		T6	177		T29	14
fifo_depth[7]	auto[1]	auto[0]	auto[1]	32065	1			T2	42		T4	1		T6	170
fifo_depth[7]	auto[1]	auto[1]	auto[0]	33497	1			T2	83		T3	2		T6	117
fifo_depth[7]	auto[1]	auto[1]	auto[1]	34475	1			T2	81		T6	327		T29	81
fifo_depth[8]	auto[0]	auto[0]	auto[0]	13827	1			T2	44		T6	117		T29	14
fifo_depth[8]	auto[0]	auto[0]	auto[1]	13965	1			T2	141		T4	2		T6	84
fifo_depth[8]	auto[0]	auto[1]	auto[0]	43892	1			T2	79		T4	1		T6	888
fifo_depth[8]	auto[0]	auto[1]	auto[1]	11660	1			T2	89		T6	149		T29	124
fifo_depth[8]	auto[1]	auto[0]	auto[0]	32570	1			T2	111		T6	132		T29	18
fifo_depth[8]	auto[1]	auto[0]	auto[1]	30601	1			T2	45		T4	1		T6	150
fifo_depth[8]	auto[1]	auto[1]	auto[0]	31198	1			T2	82		T3	2		T6	78
fifo_depth[8]	auto[1]	auto[1]	auto[1]	31615	1			T2	58		T6	236		T29	70
fifo_depth[9]	auto[0]	auto[0]	auto[0]	8378	1			T2	34		T6	80		T29	6
fifo_depth[9]	auto[0]	auto[0]	auto[1]	8641	1			T2	107		T6	71		T29	109
fifo_depth[9]	auto[0]	auto[1]	auto[0]	28804	1			T2	60		T6	552		T29	106
fifo_depth[9]	auto[0]	auto[1]	auto[1]	7378	1			T2	65		T6	126		T29	92
fifo_depth[9]	auto[1]	auto[0]	auto[0]	22457	1			T2	77		T6	131		T29	12
fifo_depth[9]	auto[1]	auto[0]	auto[1]	20866	1			T2	24		T6	113		T29	100
fifo_depth[9]	auto[1]	auto[1]	auto[0]	21893	1			T2	44		T3	3		T6	55
fifo_depth[9]	auto[1]	auto[1]	auto[1]	22784	1			T2	50		T6	173		T29	63
fifo_depth[10]	auto[0]	auto[0]	auto[0]	8300	1			T2	16		T6	56		T29	4
fifo_depth[10]	auto[0]	auto[0]	auto[1]	8296	1			T2	61		T6	38		T29	50
fifo_depth[10]	auto[0]	auto[1]	auto[0]	20282	1			T2	34		T6	335		T29	61
fifo_depth[10]	auto[0]	auto[1]	auto[1]	7428	1			T2	46		T6	78		T29	59
fifo_depth[10]	auto[1]	auto[0]	auto[0]	17597	1			T2	51		T6	75		T29	14
fifo_depth[10]	auto[1]	auto[0]	auto[1]	16105	1			T2	16		T6	84		T29	83
fifo_depth[10]	auto[1]	auto[1]	auto[0]	17201	1			T2	24		T3	2		T6	38
fifo_depth[10]	auto[1]	auto[1]	auto[1]	17984	1			T2	31		T6	122		T29	28
fifo_depth[11]	auto[0]	auto[0]	auto[0]	5043	1			T2	14		T6	30		T29	3
fifo_depth[11]	auto[0]	auto[0]	auto[1]	4718	1			T2	48		T6	23		T29	21
fifo_depth[11]	auto[0]	auto[1]	auto[0]	12416	1			T2	31		T6	182		T29	37
fifo_depth[11]	auto[0]	auto[1]	auto[1]	4574	1			T2	15		T6	41		T29	34
fifo_depth[11]	auto[1]	auto[0]	auto[0]	10887	1			T2	41		T6	38		T29	8
fifo_depth[11]	auto[1]	auto[0]	auto[1]	9709	1			T2	11		T6	43		T29	41
fifo_depth[11]	auto[1]	auto[1]	auto[0]	10148	1			T2	15		T3	1		T6	24
fifo_depth[11]	auto[1]	auto[1]	auto[1]	10747	1			T2	24		T6	60		T29	15
fifo_depth[12]	auto[0]	auto[0]	auto[0]	7281	1			T2	5		T6	15		T29	1
fifo_depth[12]	auto[0]	auto[0]	auto[1]	7390	1			T2	20		T6	12		T29	12
fifo_depth[12]	auto[0]	auto[1]	auto[0]	11460	1			T2	13		T6	111		T29	15
fifo_depth[12]	auto[0]	auto[1]	auto[1]	6896	1			T2	18		T6	10		T29	19
fifo_depth[12]	auto[1]	auto[0]	auto[0]	10650	1			T2	26		T6	36		T29	3
fifo_depth[12]	auto[1]	auto[0]	auto[1]	10580	1			T2	4		T6	25		T29	14
fifo_depth[12]	auto[1]	auto[1]	auto[0]	10539	1			T2	6		T3	1		T6	11
fifo_depth[12]	auto[1]	auto[1]	auto[1]	9532	1			T2	9		T6	24		T29	11
fifo_depth[13]	auto[0]	auto[0]	auto[0]	3579	1			T6	7		T29	1		T17	1
fifo_depth[13]	auto[0]	auto[0]	auto[1]	3439	1			T2	10		T6	4		T29	3
fifo_depth[13]	auto[0]	auto[1]	auto[0]	5807	1			T2	6		T6	36		T29	5
fifo_depth[13]	auto[0]	auto[1]	auto[1]	3385	1			T2	4		T6	7		T29	9
fifo_depth[13]	auto[1]	auto[0]	auto[0]	5918	1			T2	12		T6	10		T29	1
fifo_depth[13]	auto[1]	auto[0]	auto[1]	4917	1			T2	1		T6	16		T29	10
fifo_depth[13]	auto[1]	auto[1]	auto[0]	4910	1			T2	6		T6	4		T89	34
fifo_depth[13]	auto[1]	auto[1]	auto[1]	5456	1			T2	2		T6	14		T29	2
fifo_depth[14]	auto[0]	auto[0]	auto[0]	5915	1			T2	1		T6	5		T17	15
fifo_depth[14]	auto[0]	auto[0]	auto[1]	5749	1			T2	2		T6	6		T29	2
fifo_depth[14]	auto[0]	auto[1]	auto[0]	7047	1			T2	3		T6	22		T29	2
fifo_depth[14]	auto[0]	auto[1]	auto[1]	5636	1			T2	5		T6	4		T29	1
fifo_depth[14]	auto[1]	auto[0]	auto[0]	7070	1			T2	5		T6	5		T29	2
fifo_depth[14]	auto[1]	auto[0]	auto[1]	6629	1			T6	4		T29	5		T89	2
fifo_depth[14]	auto[1]	auto[1]	auto[0]	7013	1			T2	4		T6	1		T89	14
fifo_depth[14]	auto[1]	auto[1]	auto[1]	6652	1			T6	4		T89	6		T92	1
fifo_depth[15]	auto[0]	auto[0]	auto[0]	3709	1			T6	2		T17	26		T92	1
fifo_depth[15]	auto[0]	auto[0]	auto[1]	3643	1			T2	1		T29	1		T18	43
fifo_depth[15]	auto[0]	auto[1]	auto[0]	4790	1			T6	8		T127	6		T18	110
fifo_depth[15]	auto[0]	auto[1]	auto[1]	3350	1			T2	2		T6	2		T18	40
fifo_depth[15]	auto[1]	auto[0]	auto[0]	4812	1			T6	2		T89	7		T18	40
fifo_depth[15]	auto[1]	auto[0]	auto[1]	4425	1			T6	2		T29	1		T14	1
fifo_depth[15]	auto[1]	auto[1]	auto[0]	3658	1			T6	2		T89	8		T18	266
fifo_depth[15]	auto[1]	auto[1]	auto[1]	4337	1			T6	2		T89	2		T18	52
fifo_depth[16]	auto[0]	auto[0]	auto[0]	15940	1			T17	82		T18	40		T94	1
fifo_depth[16]	auto[0]	auto[0]	auto[1]	13743	1			T2	1		T18	46		T19	472
fifo_depth[16]	auto[0]	auto[1]	auto[0]	16508	1			T6	5		T18	359		T128	1
fifo_depth[16]	auto[0]	auto[1]	auto[1]	15735	1			T18	42		T19	386		T21	609
fifo_depth[16]	auto[1]	auto[0]	auto[0]	16648	1			T6	2		T29	1		T89	2
fifo_depth[16]	auto[1]	auto[0]	auto[1]	16245	1			T6	1		T17	1		T18	2
fifo_depth[16]	auto[1]	auto[1]	auto[0]	13929	1			T89	1		T18	388		T19	1
fifo_depth[16]	auto[1]	auto[1]	auto[1]	17680	1			T6	1		T18	113		T94	1