Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	15140722	1			T1	8886		T2	11668		T3	35
all_pins[1]	15140722	1			T1	8886		T2	11668		T3	35
all_pins[2]	15140722	1			T1	8886		T2	11668		T3	35

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	42871270	1			T1	22852		T2	34953		T3	101
values[0x1]	2550896	1			T1	3806		T2	51		T3	4
transitions[0x0=>0x1]	2550659	1			T1	3806		T2	51		T3	4
transitions[0x1=>0x0]	2550683	1			T1	3806		T2	51		T3	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	15088122	1			T1	8876		T2	11617		T3	31
all_pins[0]	values[0x1]	52600	1			T1	10		T2	51		T3	4
all_pins[0]	transitions[0x0=>0x1]	52502	1			T1	10		T2	51		T3	4
all_pins[0]	transitions[0x1=>0x0]	2497500	1			T1	3796		T26	15		T5	2594
all_pins[1]	values[0x0]	15140000	1			T1	8886		T2	11668		T3	35
all_pins[1]	values[0x1]	722	1			T4	5		T6	3		T28	1
all_pins[1]	transitions[0x0=>0x1]	646	1			T4	5		T6	3		T18	2
all_pins[1]	transitions[0x1=>0x0]	52524	1			T1	10		T2	51		T3	4
all_pins[2]	values[0x0]	12643148	1			T1	5090		T2	11668		T3	35
all_pins[2]	values[0x1]	2497574	1			T1	3796		T26	15		T5	2594
all_pins[2]	transitions[0x0=>0x1]	2497511	1			T1	3796		T26	15		T5	2594
all_pins[2]	transitions[0x1=>0x0]	659	1			T4	4		T6	3		T28	1