Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	18	0	18	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	18	0	18	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1083	1			T4	14		T6	7		T33	4
all_values[1]	1083	1			T4	14		T6	7		T33	4
all_values[2]	1083	1			T4	14		T6	7		T33	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1625

1

T4

14

T6

10

T33

8

auto[1]

1624

1

T4

28

T6

11

T33

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1052

1

T4

21

T6

3

T33

7

auto[1]

2197

1

T4

21

T6

18

T33

5

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1827

1

T4

28

T6

8

T33

9

auto[1]

1422

1

T4

14

T6

13

T33

3

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	18	0	18	100.00
Automatically Generated Cross Bins	18	0	18	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

181

1

T4

3

T28

2

T118

6

all_values[0]

auto[0]

auto[0]

auto[1]

107

1

T4

1

T6

2

T33

1

all_values[0]

auto[0]

auto[1]

auto[0]

196

1

T4

6

T6

1

T33

1

all_values[0]

auto[0]

auto[1]

auto[1]

120

1

T4

1

T28

1

T21

2

all_values[0]

auto[1]

auto[0]

auto[1]

250

1

T4

1

T6

4

T33

2

all_values[0]

auto[1]

auto[1]

auto[1]

229

1

T4

2

T28

4

T21

3

all_values[1]

auto[0]

auto[0]

auto[0]

161

1

T28

3

T118

2

T81

1

all_values[1]

auto[0]

auto[0]

auto[1]

133

1

T6

1

T33

1

T28

2

all_values[1]

auto[0]

auto[1]

auto[0]

153

1

T4

4

T6

1

T33

2

all_values[1]

auto[0]

auto[1]

auto[1]

150

1

T4

4

T21

1

T118

3

all_values[1]

auto[1]

auto[0]

auto[1]

230

1

T4

4

T6

1

T33

1

all_values[1]

auto[1]

auto[1]

auto[1]

256

1

T4

2

T6

4

T21

2

all_values[2]

auto[0]

auto[0]

auto[0]

207

1

T4

3

T33

3

T28

4

all_values[2]

auto[0]

auto[0]

auto[1]

135

1

T6

1

T28

1

T8

1

all_values[2]

auto[0]

auto[1]

auto[0]

154

1

T4

5

T6

1

T33

1

all_values[2]

auto[0]

auto[1]

auto[1]

130

1

T4

1

T6

1

T28

1

all_values[2]

auto[1]

auto[0]

auto[1]

221

1

T4

2

T6

1

T28

2

all_values[2]

auto[1]

auto[1]

auto[1]

236

1

T4

3

T6

3

T28

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal