SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
86.55 | 92.46 | 85.19 | 100.00 | 73.68 | 85.93 | 99.49 | 69.08 |
T541 | /workspace/coverage/default/24.hmac_error.3837251225 | Apr 16 02:04:19 PM PDT 24 | Apr 16 02:06:50 PM PDT 24 | 52138550786 ps | ||
T49 | /workspace/coverage/default/4.hmac_stress_all.4249320482 | Apr 16 02:03:40 PM PDT 24 | Apr 16 02:07:49 PM PDT 24 | 36169937823 ps | ||
T542 | /workspace/coverage/default/43.hmac_datapath_stress.2311536244 | Apr 16 02:05:05 PM PDT 24 | Apr 16 02:06:03 PM PDT 24 | 1963310508 ps | ||
T543 | /workspace/coverage/default/20.hmac_back_pressure.2733279230 | Apr 16 02:04:13 PM PDT 24 | Apr 16 02:04:51 PM PDT 24 | 4437150512 ps | ||
T544 | /workspace/coverage/default/27.hmac_smoke.1473204528 | Apr 16 02:04:20 PM PDT 24 | Apr 16 02:04:23 PM PDT 24 | 220353233 ps | ||
T545 | /workspace/coverage/default/46.hmac_back_pressure.598172722 | Apr 16 02:05:12 PM PDT 24 | Apr 16 02:05:17 PM PDT 24 | 227156694 ps | ||
T546 | /workspace/coverage/default/29.hmac_error.505620824 | Apr 16 02:04:26 PM PDT 24 | Apr 16 02:06:05 PM PDT 24 | 1632191751 ps | ||
T547 | /workspace/coverage/default/34.hmac_alert_test.1628091545 | Apr 16 02:04:39 PM PDT 24 | Apr 16 02:04:41 PM PDT 24 | 43996743 ps | ||
T548 | /workspace/coverage/default/11.hmac_burst_wr.1262971174 | Apr 16 02:03:52 PM PDT 24 | Apr 16 02:04:09 PM PDT 24 | 975889984 ps | ||
T549 | /workspace/coverage/default/31.hmac_error.1263155132 | Apr 16 02:04:33 PM PDT 24 | Apr 16 02:06:07 PM PDT 24 | 24663140124 ps | ||
T550 | /workspace/coverage/default/27.hmac_back_pressure.2167302754 | Apr 16 02:04:30 PM PDT 24 | Apr 16 02:04:34 PM PDT 24 | 376358114 ps | ||
T551 | /workspace/coverage/default/35.hmac_test_hmac_vectors.1172276173 | Apr 16 02:04:50 PM PDT 24 | Apr 16 02:04:52 PM PDT 24 | 112136849 ps | ||
T552 | /workspace/coverage/default/13.hmac_smoke.3849140765 | Apr 16 02:03:52 PM PDT 24 | Apr 16 02:03:55 PM PDT 24 | 241947239 ps | ||
T553 | /workspace/coverage/default/0.hmac_test_hmac_vectors.3754308920 | Apr 16 02:03:27 PM PDT 24 | Apr 16 02:03:30 PM PDT 24 | 156867722 ps | ||
T88 | /workspace/coverage/default/17.hmac_stress_all.2302988837 | Apr 16 02:04:11 PM PDT 24 | Apr 16 02:43:54 PM PDT 24 | 712658057468 ps | ||
T554 | /workspace/coverage/default/26.hmac_stress_all.515238991 | Apr 16 02:04:19 PM PDT 24 | Apr 16 02:09:38 PM PDT 24 | 23786250244 ps | ||
T555 | /workspace/coverage/default/23.hmac_test_hmac_vectors.1651690462 | Apr 16 02:04:22 PM PDT 24 | Apr 16 02:04:24 PM PDT 24 | 59030607 ps | ||
T556 | /workspace/coverage/default/37.hmac_error.4243823815 | Apr 16 02:04:53 PM PDT 24 | Apr 16 02:06:10 PM PDT 24 | 26820938412 ps | ||
T557 | /workspace/coverage/default/45.hmac_datapath_stress.1439152977 | Apr 16 02:05:06 PM PDT 24 | Apr 16 02:07:29 PM PDT 24 | 10793134610 ps | ||
T558 | /workspace/coverage/default/27.hmac_test_hmac_vectors.1900828556 | Apr 16 02:04:28 PM PDT 24 | Apr 16 02:04:30 PM PDT 24 | 106616645 ps | ||
T559 | /workspace/coverage/default/4.hmac_test_sha_vectors.3367125023 | Apr 16 02:03:29 PM PDT 24 | Apr 16 02:11:19 PM PDT 24 | 159480698957 ps | ||
T560 | /workspace/coverage/default/14.hmac_alert_test.2464496799 | Apr 16 02:03:58 PM PDT 24 | Apr 16 02:04:00 PM PDT 24 | 13019887 ps | ||
T561 | /workspace/coverage/default/38.hmac_back_pressure.2562039147 | Apr 16 02:04:52 PM PDT 24 | Apr 16 02:04:58 PM PDT 24 | 160386605 ps | ||
T562 | /workspace/coverage/default/17.hmac_test_hmac_vectors.3054761110 | Apr 16 02:04:13 PM PDT 24 | Apr 16 02:04:15 PM PDT 24 | 256507290 ps | ||
T563 | /workspace/coverage/default/25.hmac_smoke.3190316877 | Apr 16 02:04:22 PM PDT 24 | Apr 16 02:04:28 PM PDT 24 | 1439384548 ps | ||
T564 | /workspace/coverage/default/35.hmac_burst_wr.3293908967 | Apr 16 02:04:40 PM PDT 24 | Apr 16 02:05:46 PM PDT 24 | 3091075589 ps | ||
T565 | /workspace/coverage/default/41.hmac_error.4174100226 | Apr 16 02:05:00 PM PDT 24 | Apr 16 02:08:20 PM PDT 24 | 61483592739 ps | ||
T566 | /workspace/coverage/default/19.hmac_error.2543562141 | Apr 16 02:04:11 PM PDT 24 | Apr 16 02:05:43 PM PDT 24 | 6784814637 ps | ||
T567 | /workspace/coverage/default/17.hmac_burst_wr.272660204 | Apr 16 02:04:08 PM PDT 24 | Apr 16 02:04:34 PM PDT 24 | 542547800 ps | ||
T568 | /workspace/coverage/default/23.hmac_long_msg.3116644141 | Apr 16 02:04:19 PM PDT 24 | Apr 16 02:06:16 PM PDT 24 | 27816869273 ps | ||
T569 | /workspace/coverage/default/6.hmac_test_hmac_vectors.3859684963 | Apr 16 02:03:37 PM PDT 24 | Apr 16 02:03:39 PM PDT 24 | 53916795 ps | ||
T570 | /workspace/coverage/default/2.hmac_stress_all.2043678423 | Apr 16 02:03:28 PM PDT 24 | Apr 16 02:11:39 PM PDT 24 | 25735697450 ps | ||
T571 | /workspace/coverage/default/14.hmac_error.633520549 | Apr 16 02:03:59 PM PDT 24 | Apr 16 02:04:28 PM PDT 24 | 2127716783 ps | ||
T572 | /workspace/coverage/default/34.hmac_long_msg.3668964414 | Apr 16 02:04:38 PM PDT 24 | Apr 16 02:05:42 PM PDT 24 | 4603356195 ps | ||
T573 | /workspace/coverage/default/48.hmac_back_pressure.331809150 | Apr 16 02:05:22 PM PDT 24 | Apr 16 02:05:54 PM PDT 24 | 3607109671 ps | ||
T574 | /workspace/coverage/default/35.hmac_datapath_stress.3701965015 | Apr 16 02:04:37 PM PDT 24 | Apr 16 02:05:20 PM PDT 24 | 700647845 ps | ||
T575 | /workspace/coverage/default/43.hmac_alert_test.1577118473 | Apr 16 02:05:03 PM PDT 24 | Apr 16 02:05:05 PM PDT 24 | 118821500 ps | ||
T576 | /workspace/coverage/default/21.hmac_back_pressure.3785199169 | Apr 16 02:04:15 PM PDT 24 | Apr 16 02:05:01 PM PDT 24 | 5806139385 ps | ||
T577 | /workspace/coverage/default/15.hmac_datapath_stress.678476517 | Apr 16 02:03:57 PM PDT 24 | Apr 16 02:04:19 PM PDT 24 | 918701503 ps | ||
T578 | /workspace/coverage/default/22.hmac_alert_test.855041603 | Apr 16 02:04:21 PM PDT 24 | Apr 16 02:04:23 PM PDT 24 | 31920979 ps | ||
T579 | /workspace/coverage/default/38.hmac_alert_test.4162233569 | Apr 16 02:04:54 PM PDT 24 | Apr 16 02:04:56 PM PDT 24 | 23169893 ps | ||
T580 | /workspace/coverage/default/24.hmac_wipe_secret.1254086191 | Apr 16 02:04:19 PM PDT 24 | Apr 16 02:04:44 PM PDT 24 | 1652010493 ps | ||
T581 | /workspace/coverage/default/48.hmac_alert_test.1024351190 | Apr 16 02:05:20 PM PDT 24 | Apr 16 02:05:21 PM PDT 24 | 12511644 ps | ||
T582 | /workspace/coverage/default/26.hmac_alert_test.1790195279 | Apr 16 02:05:34 PM PDT 24 | Apr 16 02:05:36 PM PDT 24 | 18786413 ps | ||
T583 | /workspace/coverage/default/6.hmac_burst_wr.956010832 | Apr 16 02:03:39 PM PDT 24 | Apr 16 02:04:04 PM PDT 24 | 429358305 ps | ||
T584 | /workspace/coverage/default/26.hmac_long_msg.2242045302 | Apr 16 02:04:19 PM PDT 24 | Apr 16 02:06:04 PM PDT 24 | 39280337850 ps | ||
T585 | /workspace/coverage/default/42.hmac_smoke.920371057 | Apr 16 02:05:04 PM PDT 24 | Apr 16 02:05:10 PM PDT 24 | 1575270044 ps | ||
T586 | /workspace/coverage/default/46.hmac_smoke.4248855166 | Apr 16 02:05:06 PM PDT 24 | Apr 16 02:05:09 PM PDT 24 | 194326213 ps | ||
T587 | /workspace/coverage/default/31.hmac_datapath_stress.3985965184 | Apr 16 02:04:33 PM PDT 24 | Apr 16 02:05:46 PM PDT 24 | 1200439989 ps | ||
T588 | /workspace/coverage/default/43.hmac_back_pressure.2563774119 | Apr 16 02:05:04 PM PDT 24 | Apr 16 02:05:32 PM PDT 24 | 7297033294 ps | ||
T95 | /workspace/coverage/default/191.hmac_stress_all_with_rand_reset.3815834593 | Apr 16 02:06:00 PM PDT 24 | Apr 16 03:00:32 PM PDT 24 | 60308569829 ps | ||
T96 | /workspace/coverage/default/28.hmac_long_msg.3804350014 | Apr 16 02:04:31 PM PDT 24 | Apr 16 02:06:23 PM PDT 24 | 1907800255 ps | ||
T97 | /workspace/coverage/default/33.hmac_test_hmac_vectors.4215889848 | Apr 16 02:04:40 PM PDT 24 | Apr 16 02:04:43 PM PDT 24 | 35345563 ps | ||
T13 | /workspace/coverage/default/41.hmac_stress_all_with_rand_reset.1174448715 | Apr 16 02:05:07 PM PDT 24 | Apr 16 02:40:00 PM PDT 24 | 38754897071 ps | ||
T98 | /workspace/coverage/default/40.hmac_alert_test.3808257168 | Apr 16 02:04:56 PM PDT 24 | Apr 16 02:04:58 PM PDT 24 | 16721397 ps | ||
T99 | /workspace/coverage/default/11.hmac_back_pressure.2816496810 | Apr 16 02:03:48 PM PDT 24 | Apr 16 02:04:18 PM PDT 24 | 1663790159 ps | ||
T100 | /workspace/coverage/default/10.hmac_long_msg.2915740665 | Apr 16 02:03:43 PM PDT 24 | Apr 16 02:05:24 PM PDT 24 | 5183066889 ps | ||
T101 | /workspace/coverage/default/35.hmac_alert_test.2584559267 | Apr 16 02:04:52 PM PDT 24 | Apr 16 02:04:53 PM PDT 24 | 30743221 ps | ||
T102 | /workspace/coverage/default/11.hmac_stress_all_with_rand_reset.2710667880 | Apr 16 02:03:52 PM PDT 24 | Apr 16 02:07:41 PM PDT 24 | 48948770646 ps | ||
T103 | /workspace/coverage/default/47.hmac_wipe_secret.1772991062 | Apr 16 02:05:13 PM PDT 24 | Apr 16 02:06:50 PM PDT 24 | 12998829683 ps | ||
T589 | /workspace/coverage/default/0.hmac_smoke.1500219033 | Apr 16 02:03:39 PM PDT 24 | Apr 16 02:03:42 PM PDT 24 | 2335628447 ps | ||
T590 | /workspace/coverage/default/41.hmac_back_pressure.2118746059 | Apr 16 02:05:01 PM PDT 24 | Apr 16 02:05:08 PM PDT 24 | 291544108 ps | ||
T591 | /workspace/coverage/default/48.hmac_smoke.1954557372 | Apr 16 02:05:13 PM PDT 24 | Apr 16 02:05:21 PM PDT 24 | 418365768 ps | ||
T592 | /workspace/coverage/default/16.hmac_test_sha_vectors.2538973620 | Apr 16 02:04:03 PM PDT 24 | Apr 16 02:11:24 PM PDT 24 | 7564643091 ps | ||
T593 | /workspace/coverage/default/44.hmac_stress_all.1459924630 | Apr 16 02:05:08 PM PDT 24 | Apr 16 02:11:19 PM PDT 24 | 6960517704 ps | ||
T594 | /workspace/coverage/default/1.hmac_test_hmac_vectors.2693457579 | Apr 16 02:03:32 PM PDT 24 | Apr 16 02:03:35 PM PDT 24 | 33502242 ps | ||
T595 | /workspace/coverage/default/9.hmac_test_sha_vectors.503533689 | Apr 16 02:03:43 PM PDT 24 | Apr 16 02:11:57 PM PDT 24 | 51386565340 ps | ||
T596 | /workspace/coverage/default/18.hmac_stress_all.1685575343 | Apr 16 02:04:20 PM PDT 24 | Apr 16 02:16:07 PM PDT 24 | 105087104728 ps | ||
T597 | /workspace/coverage/default/4.hmac_wipe_secret.495388663 | Apr 16 02:03:31 PM PDT 24 | Apr 16 02:04:50 PM PDT 24 | 3736259513 ps | ||
T66 | /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.4145158203 | Apr 16 02:20:33 PM PDT 24 | Apr 16 02:27:02 PM PDT 24 | 25248899389 ps | ||
T598 | /workspace/coverage/cover_reg_top/31.hmac_intr_test.2872073533 | Apr 16 02:20:36 PM PDT 24 | Apr 16 02:20:38 PM PDT 24 | 24197503 ps | ||
T599 | /workspace/coverage/cover_reg_top/22.hmac_intr_test.1932445866 | Apr 16 02:20:41 PM PDT 24 | Apr 16 02:20:43 PM PDT 24 | 21851338 ps | ||
T600 | /workspace/coverage/cover_reg_top/30.hmac_intr_test.4133970367 | Apr 16 02:20:34 PM PDT 24 | Apr 16 02:20:36 PM PDT 24 | 12849307 ps | ||
T601 | /workspace/coverage/cover_reg_top/49.hmac_intr_test.177447766 | Apr 16 02:20:46 PM PDT 24 | Apr 16 02:20:47 PM PDT 24 | 14490760 ps | ||
T602 | /workspace/coverage/cover_reg_top/18.hmac_intr_test.4060168835 | Apr 16 02:20:34 PM PDT 24 | Apr 16 02:20:36 PM PDT 24 | 22667351 ps | ||
T603 | /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3514447837 | Apr 16 02:20:14 PM PDT 24 | Apr 16 02:20:16 PM PDT 24 | 102626513 ps | ||
T67 | /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3258518736 | Apr 16 02:19:58 PM PDT 24 | Apr 16 02:20:00 PM PDT 24 | 231110663 ps | ||
T604 | /workspace/coverage/cover_reg_top/14.hmac_intr_test.2055172472 | Apr 16 02:20:31 PM PDT 24 | Apr 16 02:20:33 PM PDT 24 | 40199633 ps | ||
T68 | /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3767752410 | Apr 16 02:19:57 PM PDT 24 | Apr 16 02:19:59 PM PDT 24 | 28623449 ps | ||
T104 | /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1836691474 | Apr 16 02:20:30 PM PDT 24 | Apr 16 02:20:32 PM PDT 24 | 45778406 ps | ||
T605 | /workspace/coverage/cover_reg_top/32.hmac_intr_test.3324950021 | Apr 16 02:20:34 PM PDT 24 | Apr 16 02:20:36 PM PDT 24 | 68967243 ps | ||
T606 | /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1091604155 | Apr 16 02:20:18 PM PDT 24 | Apr 16 02:20:21 PM PDT 24 | 249739694 ps | ||
T607 | /workspace/coverage/cover_reg_top/5.hmac_intr_test.2120117504 | Apr 16 02:20:02 PM PDT 24 | Apr 16 02:20:04 PM PDT 24 | 33176879 ps | ||
T608 | /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2253865964 | Apr 16 02:20:30 PM PDT 24 | Apr 16 02:20:32 PM PDT 24 | 360481437 ps | ||
T609 | /workspace/coverage/cover_reg_top/15.hmac_tl_errors.106764297 | Apr 16 02:20:26 PM PDT 24 | Apr 16 02:20:28 PM PDT 24 | 75510976 ps | ||
T610 | /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2791156151 | Apr 16 02:19:56 PM PDT 24 | Apr 16 02:19:58 PM PDT 24 | 158320491 ps | ||
T105 | /workspace/coverage/cover_reg_top/1.hmac_csr_rw.932318341 | Apr 16 02:19:56 PM PDT 24 | Apr 16 02:19:58 PM PDT 24 | 62520779 ps | ||
T611 | /workspace/coverage/cover_reg_top/29.hmac_intr_test.3755060192 | Apr 16 02:20:35 PM PDT 24 | Apr 16 02:20:37 PM PDT 24 | 14292838 ps | ||
T612 | /workspace/coverage/cover_reg_top/16.hmac_tl_errors.4180750301 | Apr 16 02:20:29 PM PDT 24 | Apr 16 02:20:32 PM PDT 24 | 451503864 ps | ||
T613 | /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1693608171 | Apr 16 02:20:36 PM PDT 24 | Apr 16 02:20:40 PM PDT 24 | 817480804 ps | ||
T614 | /workspace/coverage/cover_reg_top/41.hmac_intr_test.1219022845 | Apr 16 02:20:35 PM PDT 24 | Apr 16 02:20:37 PM PDT 24 | 14638878 ps | ||
T615 | /workspace/coverage/cover_reg_top/10.hmac_intr_test.2490796924 | Apr 16 02:20:25 PM PDT 24 | Apr 16 02:20:27 PM PDT 24 | 13140123 ps | ||
T616 | /workspace/coverage/cover_reg_top/2.hmac_tl_errors.257311025 | Apr 16 02:19:55 PM PDT 24 | Apr 16 02:19:59 PM PDT 24 | 347520364 ps | ||
T617 | /workspace/coverage/cover_reg_top/27.hmac_intr_test.2034873895 | Apr 16 02:20:41 PM PDT 24 | Apr 16 02:20:43 PM PDT 24 | 140281281 ps | ||
T618 | /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1338314779 | Apr 16 02:20:35 PM PDT 24 | Apr 16 02:20:40 PM PDT 24 | 785479752 ps | ||
T619 | /workspace/coverage/cover_reg_top/26.hmac_intr_test.2135177276 | Apr 16 02:20:40 PM PDT 24 | Apr 16 02:20:41 PM PDT 24 | 16315028 ps | ||
T620 | /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3127691224 | Apr 16 02:20:30 PM PDT 24 | Apr 16 02:20:34 PM PDT 24 | 248730827 ps | ||
T621 | /workspace/coverage/cover_reg_top/39.hmac_intr_test.836336269 | Apr 16 02:20:37 PM PDT 24 | Apr 16 02:20:38 PM PDT 24 | 24003207 ps | ||
T622 | /workspace/coverage/cover_reg_top/19.hmac_intr_test.777481847 | Apr 16 02:20:34 PM PDT 24 | Apr 16 02:20:35 PM PDT 24 | 13487260 ps | ||
T623 | /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2939494306 | Apr 16 02:20:36 PM PDT 24 | Apr 16 02:20:38 PM PDT 24 | 32971844 ps | ||
T63 | /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2869013085 | Apr 16 02:20:06 PM PDT 24 | Apr 16 02:20:09 PM PDT 24 | 177526911 ps | ||
T106 | /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3066058887 | Apr 16 02:20:36 PM PDT 24 | Apr 16 02:20:38 PM PDT 24 | 17121211 ps | ||
T64 | /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2366159283 | Apr 16 02:19:55 PM PDT 24 | Apr 16 02:19:59 PM PDT 24 | 783102274 ps | ||
T624 | /workspace/coverage/cover_reg_top/2.hmac_intr_test.3442816364 | Apr 16 02:19:53 PM PDT 24 | Apr 16 02:19:55 PM PDT 24 | 27644409 ps | ||
T625 | /workspace/coverage/cover_reg_top/15.hmac_intr_test.4168488250 | Apr 16 02:20:30 PM PDT 24 | Apr 16 02:20:31 PM PDT 24 | 50630715 ps | ||
T626 | /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2923143480 | Apr 16 02:19:55 PM PDT 24 | Apr 16 02:19:58 PM PDT 24 | 507421328 ps | ||
T627 | /workspace/coverage/cover_reg_top/13.hmac_intr_test.2713705877 | Apr 16 02:20:29 PM PDT 24 | Apr 16 02:20:30 PM PDT 24 | 42038342 ps | ||
T107 | /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2645166637 | Apr 16 02:19:51 PM PDT 24 | Apr 16 02:20:09 PM PDT 24 | 6540818123 ps | ||
T628 | /workspace/coverage/cover_reg_top/35.hmac_intr_test.3609672092 | Apr 16 02:20:34 PM PDT 24 | Apr 16 02:20:36 PM PDT 24 | 14235960 ps | ||
T629 | /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.4049213160 | Apr 16 02:20:08 PM PDT 24 | Apr 16 02:20:10 PM PDT 24 | 110473698 ps | ||
T630 | /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.4054389426 | Apr 16 02:19:57 PM PDT 24 | Apr 16 02:19:59 PM PDT 24 | 39327171 ps | ||
T631 | /workspace/coverage/cover_reg_top/42.hmac_intr_test.2328365544 | Apr 16 02:20:41 PM PDT 24 | Apr 16 02:20:43 PM PDT 24 | 44794900 ps | ||
T632 | /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3613103953 | Apr 16 02:19:49 PM PDT 24 | Apr 16 02:19:53 PM PDT 24 | 100848176 ps | ||
T633 | /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.970586639 | Apr 16 02:20:28 PM PDT 24 | Apr 16 02:20:30 PM PDT 24 | 109034935 ps | ||
T634 | /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2734667559 | Apr 16 02:20:24 PM PDT 24 | Apr 16 02:20:26 PM PDT 24 | 43105079 ps | ||
T635 | /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.326133737 | Apr 16 02:20:07 PM PDT 24 | Apr 16 02:20:10 PM PDT 24 | 711816184 ps | ||
T636 | /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3071683544 | Apr 16 02:20:35 PM PDT 24 | Apr 16 02:20:38 PM PDT 24 | 116919972 ps | ||
T637 | /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3437266670 | Apr 16 02:20:03 PM PDT 24 | Apr 16 02:20:06 PM PDT 24 | 169001332 ps | ||
T638 | /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.914575301 | Apr 16 02:20:30 PM PDT 24 | Apr 16 02:20:32 PM PDT 24 | 40115229 ps | ||
T639 | /workspace/coverage/cover_reg_top/1.hmac_intr_test.1634998844 | Apr 16 02:19:57 PM PDT 24 | Apr 16 02:19:59 PM PDT 24 | 60262363 ps | ||
T640 | /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3817295389 | Apr 16 02:20:30 PM PDT 24 | Apr 16 02:20:32 PM PDT 24 | 17761934 ps | ||
T65 | /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3426178713 | Apr 16 02:19:58 PM PDT 24 | Apr 16 02:20:02 PM PDT 24 | 97769523 ps | ||
T641 | /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1359116477 | Apr 16 02:20:19 PM PDT 24 | Apr 16 02:20:22 PM PDT 24 | 455728536 ps | ||
T642 | /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2517840093 | Apr 16 02:20:31 PM PDT 24 | Apr 16 02:20:34 PM PDT 24 | 761645205 ps | ||
T121 | /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1574010539 | Apr 16 02:20:13 PM PDT 24 | Apr 16 02:20:17 PM PDT 24 | 714617348 ps | ||
T643 | /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2156889977 | Apr 16 02:20:31 PM PDT 24 | Apr 16 02:20:34 PM PDT 24 | 153661576 ps | ||
T644 | /workspace/coverage/cover_reg_top/43.hmac_intr_test.555497480 | Apr 16 02:20:34 PM PDT 24 | Apr 16 02:20:36 PM PDT 24 | 29021864 ps | ||
T645 | /workspace/coverage/cover_reg_top/24.hmac_intr_test.570837457 | Apr 16 02:20:34 PM PDT 24 | Apr 16 02:20:35 PM PDT 24 | 13142143 ps | ||
T646 | /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.645088408 | Apr 16 02:20:13 PM PDT 24 | Apr 16 02:20:16 PM PDT 24 | 537474868 ps | ||
T119 | /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.664385630 | Apr 16 02:20:23 PM PDT 24 | Apr 16 02:20:27 PM PDT 24 | 3575424246 ps | ||
T647 | /workspace/coverage/cover_reg_top/17.hmac_intr_test.3153731681 | Apr 16 02:20:31 PM PDT 24 | Apr 16 02:20:33 PM PDT 24 | 27062092 ps | ||
T124 | /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1757063614 | Apr 16 02:20:26 PM PDT 24 | Apr 16 02:20:28 PM PDT 24 | 261960772 ps | ||
T120 | /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3828349224 | Apr 16 02:20:03 PM PDT 24 | Apr 16 02:20:08 PM PDT 24 | 272171118 ps | ||
T108 | /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2284829571 | Apr 16 02:20:28 PM PDT 24 | Apr 16 02:20:29 PM PDT 24 | 16548701 ps | ||
T648 | /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.477390141 | Apr 16 02:19:56 PM PDT 24 | Apr 16 02:20:01 PM PDT 24 | 420221058 ps | ||
T649 | /workspace/coverage/cover_reg_top/33.hmac_intr_test.120412068 | Apr 16 02:20:34 PM PDT 24 | Apr 16 02:20:36 PM PDT 24 | 29909255 ps | ||
T650 | /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2223924358 | Apr 16 02:20:13 PM PDT 24 | Apr 16 02:20:15 PM PDT 24 | 119975133 ps | ||
T651 | /workspace/coverage/cover_reg_top/7.hmac_intr_test.693255268 | Apr 16 02:20:14 PM PDT 24 | Apr 16 02:20:15 PM PDT 24 | 17510546 ps | ||
T652 | /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.289299718 | Apr 16 02:19:54 PM PDT 24 | Apr 16 02:19:56 PM PDT 24 | 55895232 ps | ||
T653 | /workspace/coverage/cover_reg_top/4.hmac_intr_test.4215185972 | Apr 16 02:19:54 PM PDT 24 | Apr 16 02:19:55 PM PDT 24 | 38543899 ps | ||
T654 | /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3222784106 | Apr 16 02:20:15 PM PDT 24 | Apr 16 02:20:18 PM PDT 24 | 262965267 ps | ||
T655 | /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1248304038 | Apr 16 02:20:24 PM PDT 24 | Apr 16 02:20:26 PM PDT 24 | 49998763 ps | ||
T122 | /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.866686628 | Apr 16 02:19:55 PM PDT 24 | Apr 16 02:20:01 PM PDT 24 | 2545770960 ps | ||
T656 | /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.838246260 | Apr 16 02:20:13 PM PDT 24 | Apr 16 02:20:16 PM PDT 24 | 467532045 ps | ||
T109 | /workspace/coverage/cover_reg_top/8.hmac_csr_rw.4202141360 | Apr 16 02:20:20 PM PDT 24 | Apr 16 02:20:22 PM PDT 24 | 26742306 ps | ||
T123 | /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2951559115 | Apr 16 02:19:56 PM PDT 24 | Apr 16 02:20:01 PM PDT 24 | 162946221 ps | ||
T657 | /workspace/coverage/cover_reg_top/47.hmac_intr_test.1683166210 | Apr 16 02:20:42 PM PDT 24 | Apr 16 02:20:44 PM PDT 24 | 45265687 ps | ||
T110 | /workspace/coverage/cover_reg_top/14.hmac_csr_rw.120122188 | Apr 16 02:20:34 PM PDT 24 | Apr 16 02:20:36 PM PDT 24 | 30506101 ps | ||
T658 | /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2109549751 | Apr 16 02:19:49 PM PDT 24 | Apr 16 02:19:53 PM PDT 24 | 234663180 ps | ||
T659 | /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1202933996 | Apr 16 02:20:32 PM PDT 24 | Apr 16 02:20:34 PM PDT 24 | 59484608 ps | ||
T660 | /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3882534115 | Apr 16 02:19:49 PM PDT 24 | Apr 16 02:19:56 PM PDT 24 | 884430755 ps | ||
T661 | /workspace/coverage/cover_reg_top/37.hmac_intr_test.277159839 | Apr 16 02:20:37 PM PDT 24 | Apr 16 02:20:38 PM PDT 24 | 49588201 ps | ||
T662 | /workspace/coverage/cover_reg_top/45.hmac_intr_test.3857346026 | Apr 16 02:20:36 PM PDT 24 | Apr 16 02:20:38 PM PDT 24 | 36269901 ps | ||
T663 | /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3995362871 | Apr 16 02:20:20 PM PDT 24 | Apr 16 02:20:22 PM PDT 24 | 32384493 ps | ||
T664 | /workspace/coverage/cover_reg_top/6.hmac_intr_test.3494793975 | Apr 16 02:20:06 PM PDT 24 | Apr 16 02:20:07 PM PDT 24 | 19723626 ps | ||
T665 | /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2330503989 | Apr 16 02:20:29 PM PDT 24 | Apr 16 02:20:31 PM PDT 24 | 27109840 ps | ||
T125 | /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1667360603 | Apr 16 02:20:36 PM PDT 24 | Apr 16 02:20:41 PM PDT 24 | 227006191 ps | ||
T666 | /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3068786826 | Apr 16 02:20:24 PM PDT 24 | Apr 16 02:20:25 PM PDT 24 | 31416467 ps | ||
T113 | /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.4231926858 | Apr 16 02:19:49 PM PDT 24 | Apr 16 02:20:07 PM PDT 24 | 4382254145 ps | ||
T667 | /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1342569022 | Apr 16 02:20:35 PM PDT 24 | Apr 16 02:20:38 PM PDT 24 | 132185624 ps | ||
T668 | /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.223838857 | Apr 16 02:19:58 PM PDT 24 | Apr 16 02:20:02 PM PDT 24 | 57213055 ps | ||
T669 | /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1143746820 | Apr 16 02:20:30 PM PDT 24 | Apr 16 02:20:33 PM PDT 24 | 357631610 ps | ||
T670 | /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1151020296 | Apr 16 02:19:55 PM PDT 24 | Apr 16 02:19:59 PM PDT 24 | 63375607 ps | ||
T671 | /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1354561121 | Apr 16 02:19:47 PM PDT 24 | Apr 16 02:19:49 PM PDT 24 | 57761251 ps | ||
T672 | /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2267903497 | Apr 16 02:19:58 PM PDT 24 | Apr 16 02:20:05 PM PDT 24 | 533840765 ps | ||
T673 | /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1771303468 | Apr 16 02:19:53 PM PDT 24 | Apr 16 02:19:58 PM PDT 24 | 228647036 ps | ||
T126 | /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3802102645 | Apr 16 02:20:30 PM PDT 24 | Apr 16 02:20:34 PM PDT 24 | 164346401 ps | ||
T674 | /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.818308527 | Apr 16 02:20:23 PM PDT 24 | Apr 16 02:20:26 PM PDT 24 | 70334372 ps | ||
T675 | /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2792304187 | Apr 16 02:20:31 PM PDT 24 | Apr 16 02:20:34 PM PDT 24 | 415368678 ps | ||
T111 | /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3269508012 | Apr 16 02:20:07 PM PDT 24 | Apr 16 02:20:08 PM PDT 24 | 28707058 ps | ||
T676 | /workspace/coverage/cover_reg_top/28.hmac_intr_test.49101554 | Apr 16 02:20:35 PM PDT 24 | Apr 16 02:20:37 PM PDT 24 | 10873711 ps | ||
T677 | /workspace/coverage/cover_reg_top/12.hmac_intr_test.1077031728 | Apr 16 02:20:29 PM PDT 24 | Apr 16 02:20:31 PM PDT 24 | 31793647 ps | ||
T678 | /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.219905139 | Apr 16 02:20:34 PM PDT 24 | Apr 16 02:20:39 PM PDT 24 | 967295503 ps | ||
T679 | /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.590654759 | Apr 16 02:20:12 PM PDT 24 | Apr 16 02:20:13 PM PDT 24 | 38755982 ps | ||
T680 | /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3947187349 | Apr 16 02:20:36 PM PDT 24 | Apr 16 02:23:15 PM PDT 24 | 119320109632 ps | ||
T112 | /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1696511822 | Apr 16 02:19:54 PM PDT 24 | Apr 16 02:19:56 PM PDT 24 | 35195629 ps | ||
T681 | /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1322139014 | Apr 16 02:20:34 PM PDT 24 | Apr 16 02:20:37 PM PDT 24 | 311063420 ps | ||
T682 | /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3223140044 | Apr 16 02:20:03 PM PDT 24 | Apr 16 02:20:08 PM PDT 24 | 232364364 ps | ||
T683 | /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.127149747 | Apr 16 02:20:30 PM PDT 24 | Apr 16 02:20:33 PM PDT 24 | 175139491 ps | ||
T684 | /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.274898112 | Apr 16 02:20:24 PM PDT 24 | Apr 16 02:20:26 PM PDT 24 | 439177810 ps | ||
T685 | /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3966970648 | Apr 16 02:20:02 PM PDT 24 | Apr 16 02:20:04 PM PDT 24 | 29081071 ps | ||
T686 | /workspace/coverage/cover_reg_top/36.hmac_intr_test.933805476 | Apr 16 02:20:35 PM PDT 24 | Apr 16 02:20:36 PM PDT 24 | 28979906 ps | ||
T687 | /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3150886117 | Apr 16 02:19:58 PM PDT 24 | Apr 16 02:24:41 PM PDT 24 | 37039059613 ps | ||
T688 | /workspace/coverage/cover_reg_top/38.hmac_intr_test.2906460632 | Apr 16 02:20:38 PM PDT 24 | Apr 16 02:20:39 PM PDT 24 | 13553058 ps | ||
T689 | /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1768885526 | Apr 16 02:20:28 PM PDT 24 | Apr 16 02:20:32 PM PDT 24 | 85904615 ps | ||
T690 | /workspace/coverage/cover_reg_top/34.hmac_intr_test.1450921641 | Apr 16 02:20:35 PM PDT 24 | Apr 16 02:20:37 PM PDT 24 | 17050392 ps | ||
T114 | /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2173938055 | Apr 16 02:19:52 PM PDT 24 | Apr 16 02:19:53 PM PDT 24 | 418967496 ps | ||
T691 | /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2907473120 | Apr 16 02:19:51 PM PDT 24 | Apr 16 02:19:55 PM PDT 24 | 96937799 ps | ||
T115 | /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3495044871 | Apr 16 02:19:53 PM PDT 24 | Apr 16 02:20:11 PM PDT 24 | 5961299175 ps | ||
T692 | /workspace/coverage/cover_reg_top/23.hmac_intr_test.1050621661 | Apr 16 02:20:35 PM PDT 24 | Apr 16 02:20:37 PM PDT 24 | 18164481 ps | ||
T693 | /workspace/coverage/cover_reg_top/21.hmac_intr_test.1203209370 | Apr 16 02:20:36 PM PDT 24 | Apr 16 02:20:37 PM PDT 24 | 14826030 ps | ||
T694 | /workspace/coverage/cover_reg_top/40.hmac_intr_test.4211223213 | Apr 16 02:20:34 PM PDT 24 | Apr 16 02:20:36 PM PDT 24 | 17765764 ps | ||
T695 | /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3916861259 | Apr 16 02:20:23 PM PDT 24 | Apr 16 02:20:26 PM PDT 24 | 93383260 ps | ||
T116 | /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.451794842 | Apr 16 02:19:55 PM PDT 24 | Apr 16 02:19:57 PM PDT 24 | 20030972 ps | ||
T117 | /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2871624233 | Apr 16 02:19:57 PM PDT 24 | Apr 16 02:20:10 PM PDT 24 | 1165006441 ps | ||
T696 | /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3694141918 | Apr 16 02:20:25 PM PDT 24 | Apr 16 02:20:27 PM PDT 24 | 28901949 ps | ||
T697 | /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2907661599 | Apr 16 02:20:12 PM PDT 24 | Apr 16 02:20:15 PM PDT 24 | 81917224 ps | ||
T698 | /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3346226562 | Apr 16 02:20:07 PM PDT 24 | Apr 16 02:20:08 PM PDT 24 | 64178648 ps | ||
T699 | /workspace/coverage/cover_reg_top/25.hmac_intr_test.714686291 | Apr 16 02:20:40 PM PDT 24 | Apr 16 02:20:41 PM PDT 24 | 42281616 ps | ||
T700 | /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2344557723 | Apr 16 02:19:52 PM PDT 24 | Apr 16 02:19:54 PM PDT 24 | 102422899 ps | ||
T701 | /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3195204700 | Apr 16 02:20:24 PM PDT 24 | Apr 16 02:20:27 PM PDT 24 | 115233001 ps | ||
T702 | /workspace/coverage/cover_reg_top/20.hmac_intr_test.1147354074 | Apr 16 02:20:33 PM PDT 24 | Apr 16 02:20:34 PM PDT 24 | 43060766 ps | ||
T703 | /workspace/coverage/cover_reg_top/3.hmac_intr_test.2494874743 | Apr 16 02:19:54 PM PDT 24 | Apr 16 02:19:56 PM PDT 24 | 25160987 ps | ||
T704 | /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2040184529 | Apr 16 02:20:34 PM PDT 24 | Apr 16 02:20:36 PM PDT 24 | 29088413 ps | ||
T705 | /workspace/coverage/cover_reg_top/6.hmac_tl_errors.840382032 | Apr 16 02:20:07 PM PDT 24 | Apr 16 02:20:12 PM PDT 24 | 615177850 ps | ||
T706 | /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.509872380 | Apr 16 02:20:28 PM PDT 24 | Apr 16 02:20:32 PM PDT 24 | 161458678 ps | ||
T707 | /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3691511773 | Apr 16 02:20:29 PM PDT 24 | Apr 16 02:20:33 PM PDT 24 | 294383056 ps | ||
T708 | /workspace/coverage/cover_reg_top/8.hmac_intr_test.765752339 | Apr 16 02:20:12 PM PDT 24 | Apr 16 02:20:14 PM PDT 24 | 11699949 ps | ||
T709 | /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2531773177 | Apr 16 02:20:24 PM PDT 24 | Apr 16 02:20:27 PM PDT 24 | 938801232 ps | ||
T710 | /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2576202748 | Apr 16 02:19:55 PM PDT 24 | Apr 16 02:19:57 PM PDT 24 | 79389401 ps | ||
T711 | /workspace/coverage/cover_reg_top/46.hmac_intr_test.341897960 | Apr 16 02:20:36 PM PDT 24 | Apr 16 02:20:37 PM PDT 24 | 26384043 ps | ||
T712 | /workspace/coverage/cover_reg_top/0.hmac_intr_test.2643148749 | Apr 16 02:19:47 PM PDT 24 | Apr 16 02:19:48 PM PDT 24 | 30389994 ps | ||
T713 | /workspace/coverage/cover_reg_top/16.hmac_intr_test.3844112857 | Apr 16 02:20:31 PM PDT 24 | Apr 16 02:20:33 PM PDT 24 | 15169597 ps | ||
T714 | /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.962708702 | Apr 16 02:20:40 PM PDT 24 | Apr 16 02:20:45 PM PDT 24 | 1095861503 ps | ||
T715 | /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2226520433 | Apr 16 02:20:25 PM PDT 24 | Apr 16 02:20:27 PM PDT 24 | 20472475 ps | ||
T716 | /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2832700321 | Apr 16 02:19:54 PM PDT 24 | Apr 16 02:20:03 PM PDT 24 | 163283746 ps | ||
T717 | /workspace/coverage/cover_reg_top/48.hmac_intr_test.197585691 | Apr 16 02:20:41 PM PDT 24 | Apr 16 02:20:42 PM PDT 24 | 31269900 ps | ||
T718 | /workspace/coverage/cover_reg_top/9.hmac_intr_test.3880261962 | Apr 16 02:20:18 PM PDT 24 | Apr 16 02:20:19 PM PDT 24 | 15161539 ps | ||
T719 | /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3269229467 | Apr 16 02:19:49 PM PDT 24 | Apr 16 02:19:51 PM PDT 24 | 54275648 ps | ||
T720 | /workspace/coverage/cover_reg_top/12.hmac_tl_errors.617146546 | Apr 16 02:20:28 PM PDT 24 | Apr 16 02:20:32 PM PDT 24 | 384618411 ps | ||
T721 | /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1374453318 | Apr 16 02:20:13 PM PDT 24 | Apr 16 02:20:17 PM PDT 24 | 188371556 ps | ||
T722 | /workspace/coverage/cover_reg_top/11.hmac_intr_test.1709196551 | Apr 16 02:20:25 PM PDT 24 | Apr 16 02:20:26 PM PDT 24 | 10553462 ps | ||
T723 | /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1013372304 | Apr 16 02:20:30 PM PDT 24 | Apr 16 02:20:31 PM PDT 24 | 25378179 ps | ||
T724 | /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.945759132 | Apr 16 02:20:32 PM PDT 24 | Apr 16 02:20:34 PM PDT 24 | 207781572 ps | ||
T725 | /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2099673232 | Apr 16 02:20:09 PM PDT 24 | Apr 16 02:20:10 PM PDT 24 | 122907708 ps | ||
T726 | /workspace/coverage/cover_reg_top/44.hmac_intr_test.1656849131 | Apr 16 02:20:41 PM PDT 24 | Apr 16 02:20:43 PM PDT 24 | 34320475 ps | ||
T727 | /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3985760964 | Apr 16 02:19:58 PM PDT 24 | Apr 16 02:20:01 PM PDT 24 | 101569221 ps | ||
T728 | /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2536367156 | Apr 16 02:20:29 PM PDT 24 | Apr 16 02:20:30 PM PDT 24 | 38598214 ps | ||
T729 | /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2973305318 | Apr 16 02:19:58 PM PDT 24 | Apr 16 02:20:04 PM PDT 24 | 112626368 ps | ||
T730 | /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2501557136 | Apr 16 02:20:26 PM PDT 24 | Apr 16 02:20:28 PM PDT 24 | 229455627 ps | ||
T731 | /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3336376162 | Apr 16 02:19:54 PM PDT 24 | Apr 16 02:19:56 PM PDT 24 | 16348040 ps | ||
T732 | /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.794902875 | Apr 16 02:20:23 PM PDT 24 | Apr 16 02:20:26 PM PDT 24 | 518121090 ps | ||
T733 | /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2151941095 | Apr 16 02:20:31 PM PDT 24 | Apr 16 02:20:34 PM PDT 24 | 76978810 ps | ||
T734 | /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.407442259 | Apr 16 02:20:20 PM PDT 24 | Apr 16 02:20:23 PM PDT 24 | 187975858 ps |
Test location | /workspace/coverage/default/43.hmac_long_msg.3799162830 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 1382288863 ps |
CPU time | 75.42 seconds |
Started | Apr 16 02:05:00 PM PDT 24 |
Finished | Apr 16 02:06:17 PM PDT 24 |
Peak memory | 199548 kb |
Host | smart-dddc9420-3c58-4622-b99d-447da6ccf6e5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3799162830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3799162830 |
Directory | /workspace/43.hmac_long_msg/latest |
Test location | /workspace/coverage/default/145.hmac_stress_all_with_rand_reset.4174305723 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 40140385730 ps |
CPU time | 387.97 seconds |
Started | Apr 16 02:05:44 PM PDT 24 |
Finished | Apr 16 02:12:12 PM PDT 24 |
Peak memory | 232524 kb |
Host | smart-f46e2d25-75e0-47fc-b9a1-45479a37fbd6 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4174305723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.hmac_stress_all_with_rand_reset.4174305723 |
Directory | /workspace/145.hmac_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/36.hmac_stress_all.2389151856 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 208779041161 ps |
CPU time | 734.91 seconds |
Started | Apr 16 02:04:54 PM PDT 24 |
Finished | Apr 16 02:17:10 PM PDT 24 |
Peak memory | 227368 kb |
Host | smart-4f678cfc-50cf-4080-aac5-d1c1637743c8 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389151856 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2389151856 |
Directory | /workspace/36.hmac_stress_all/latest |
Test location | /workspace/coverage/default/3.hmac_sec_cm.414086749 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 1028782413 ps |
CPU time | 0.94 seconds |
Started | Apr 16 02:03:32 PM PDT 24 |
Finished | Apr 16 02:03:35 PM PDT 24 |
Peak memory | 219428 kb |
Host | smart-12c90292-e2b6-4b3f-b2d9-b6650aff2b14 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414086749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.414086749 |
Directory | /workspace/3.hmac_sec_cm/latest |
Test location | /workspace/coverage/default/153.hmac_stress_all_with_rand_reset.1532330607 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 266252504385 ps |
CPU time | 2997.58 seconds |
Started | Apr 16 02:05:47 PM PDT 24 |
Finished | Apr 16 02:55:46 PM PDT 24 |
Peak memory | 240748 kb |
Host | smart-d7032af9-adf2-4ecb-be72-737f8f16da8f |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1532330607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.hmac_stress_all_with_rand_reset.1532330607 |
Directory | /workspace/153.hmac_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2869013085 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 177526911 ps |
CPU time | 1.89 seconds |
Started | Apr 16 02:20:06 PM PDT 24 |
Finished | Apr 16 02:20:09 PM PDT 24 |
Peak memory | 199252 kb |
Host | smart-82275e0b-c279-4373-ae70-b6ff82771c5d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869013085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2869013085 |
Directory | /workspace/6.hmac_tl_intg_err/latest |
Test location | /workspace/coverage/default/16.hmac_burst_wr.1137111181 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 1863570905 ps |
CPU time | 46.1 seconds |
Started | Apr 16 02:04:03 PM PDT 24 |
Finished | Apr 16 02:04:51 PM PDT 24 |
Peak memory | 199640 kb |
Host | smart-8919e819-b16d-4780-a741-d933ceba7c1e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1137111181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1137111181 |
Directory | /workspace/16.hmac_burst_wr/latest |
Test location | /workspace/coverage/cover_reg_top/14.hmac_csr_rw.120122188 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 30506101 ps |
CPU time | 0.93 seconds |
Started | Apr 16 02:20:34 PM PDT 24 |
Finished | Apr 16 02:20:36 PM PDT 24 |
Peak memory | 198152 kb |
Host | smart-afd951db-853c-44fa-b1d5-4dd6efbf1f7f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120122188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.120122188 |
Directory | /workspace/14.hmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.866686628 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 2545770960 ps |
CPU time | 4.52 seconds |
Started | Apr 16 02:19:55 PM PDT 24 |
Finished | Apr 16 02:20:01 PM PDT 24 |
Peak memory | 199344 kb |
Host | smart-52f95f8b-bf35-4f46-a65c-be6eb485ff9b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866686628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.866686628 |
Directory | /workspace/3.hmac_tl_intg_err/latest |
Test location | /workspace/coverage/default/16.hmac_alert_test.3466770073 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 16089946 ps |
CPU time | 0.64 seconds |
Started | Apr 16 02:04:03 PM PDT 24 |
Finished | Apr 16 02:04:05 PM PDT 24 |
Peak memory | 195188 kb |
Host | smart-0fcbc4e0-60a5-478f-9c63-312a52081448 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466770073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3466770073 |
Directory | /workspace/16.hmac_alert_test/latest |
Test location | /workspace/coverage/default/0.hmac_stress_all.610760200 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 106048941200 ps |
CPU time | 1841.44 seconds |
Started | Apr 16 02:03:28 PM PDT 24 |
Finished | Apr 16 02:34:12 PM PDT 24 |
Peak memory | 207932 kb |
Host | smart-180deb0c-7228-4674-be82-4727e4f6f43a |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610760200 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.610760200 |
Directory | /workspace/0.hmac_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2366159283 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 783102274 ps |
CPU time | 3.14 seconds |
Started | Apr 16 02:19:55 PM PDT 24 |
Finished | Apr 16 02:19:59 PM PDT 24 |
Peak memory | 199228 kb |
Host | smart-56ec6047-13d8-49ac-b186-c6c7b2bd1b6b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366159283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2366159283 |
Directory | /workspace/0.hmac_tl_intg_err/latest |
Test location | /workspace/coverage/default/27.hmac_wipe_secret.1972667796 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 4426379257 ps |
CPU time | 85.27 seconds |
Started | Apr 16 02:04:28 PM PDT 24 |
Finished | Apr 16 02:05:54 PM PDT 24 |
Peak memory | 199696 kb |
Host | smart-7a85fbcc-ec0d-4bff-b620-6f81aabd2840 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1972667796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1972667796 |
Directory | /workspace/27.hmac_wipe_secret/latest |
Test location | /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3802102645 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 164346401 ps |
CPU time | 3.01 seconds |
Started | Apr 16 02:20:30 PM PDT 24 |
Finished | Apr 16 02:20:34 PM PDT 24 |
Peak memory | 199196 kb |
Host | smart-b1822f18-356b-452a-9eb0-694ed27a3148 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802102645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3802102645 |
Directory | /workspace/15.hmac_tl_intg_err/latest |
Test location | /workspace/coverage/default/18.hmac_error.2758288515 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 9798681289 ps |
CPU time | 121.37 seconds |
Started | Apr 16 02:04:12 PM PDT 24 |
Finished | Apr 16 02:06:15 PM PDT 24 |
Peak memory | 199712 kb |
Host | smart-b78de9cd-7ddf-4866-a227-81365eb2544a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758288515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2758288515 |
Directory | /workspace/18.hmac_error/latest |
Test location | /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3882534115 |
Short name | T660 |
Test name | |
Test status | |
Simulation time | 884430755 ps |
CPU time | 5.75 seconds |
Started | Apr 16 02:19:49 PM PDT 24 |
Finished | Apr 16 02:19:56 PM PDT 24 |
Peak memory | 198812 kb |
Host | smart-4f99f765-8da8-4e3d-bd8c-f72b31610c64 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882534115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3882534115 |
Directory | /workspace/0.hmac_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2645166637 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 6540818123 ps |
CPU time | 17.11 seconds |
Started | Apr 16 02:19:51 PM PDT 24 |
Finished | Apr 16 02:20:09 PM PDT 24 |
Peak memory | 198212 kb |
Host | smart-68ebf471-b98a-44f7-8dc9-a7fac48ed72c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645166637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2645166637 |
Directory | /workspace/0.hmac_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.451794842 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 20030972 ps |
CPU time | 0.7 seconds |
Started | Apr 16 02:19:55 PM PDT 24 |
Finished | Apr 16 02:19:57 PM PDT 24 |
Peak memory | 196636 kb |
Host | smart-d5bd2bb0-0567-40b6-a5cd-e6dd1270d5f6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451794842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.451794842 |
Directory | /workspace/0.hmac_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.223838857 |
Short name | T668 |
Test name | |
Test status | |
Simulation time | 57213055 ps |
CPU time | 2.7 seconds |
Started | Apr 16 02:19:58 PM PDT 24 |
Finished | Apr 16 02:20:02 PM PDT 24 |
Peak memory | 199480 kb |
Host | smart-0c8c4f68-dd0d-4924-9542-d78af2d097ce |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223838857 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.223838857 |
Directory | /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3269229467 |
Short name | T719 |
Test name | |
Test status | |
Simulation time | 54275648 ps |
CPU time | 0.88 seconds |
Started | Apr 16 02:19:49 PM PDT 24 |
Finished | Apr 16 02:19:51 PM PDT 24 |
Peak memory | 198616 kb |
Host | smart-e14ea046-053b-4001-921e-c3c232fc963e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269229467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3269229467 |
Directory | /workspace/0.hmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.hmac_intr_test.2643148749 |
Short name | T712 |
Test name | |
Test status | |
Simulation time | 30389994 ps |
CPU time | 0.57 seconds |
Started | Apr 16 02:19:47 PM PDT 24 |
Finished | Apr 16 02:19:48 PM PDT 24 |
Peak memory | 193924 kb |
Host | smart-e221cb16-a4ab-4af4-87a4-d7b2fe5ae1ff |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643148749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2643148749 |
Directory | /workspace/0.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1354561121 |
Short name | T671 |
Test name | |
Test status | |
Simulation time | 57761251 ps |
CPU time | 1.62 seconds |
Started | Apr 16 02:19:47 PM PDT 24 |
Finished | Apr 16 02:19:49 PM PDT 24 |
Peak memory | 199196 kb |
Host | smart-5d82b8e4-90e8-48d7-aef7-9dc2de50b627 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354561121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr _outstanding.1354561121 |
Directory | /workspace/0.hmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2907473120 |
Short name | T691 |
Test name | |
Test status | |
Simulation time | 96937799 ps |
CPU time | 2.87 seconds |
Started | Apr 16 02:19:51 PM PDT 24 |
Finished | Apr 16 02:19:55 PM PDT 24 |
Peak memory | 199328 kb |
Host | smart-685e8b8b-da62-4223-b0ff-e1c94222a489 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907473120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2907473120 |
Directory | /workspace/0.hmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2109549751 |
Short name | T658 |
Test name | |
Test status | |
Simulation time | 234663180 ps |
CPU time | 3.07 seconds |
Started | Apr 16 02:19:49 PM PDT 24 |
Finished | Apr 16 02:19:53 PM PDT 24 |
Peak memory | 198276 kb |
Host | smart-a6472ce8-b4f4-48a4-bc3b-5229d799887e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109549751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.2109549751 |
Directory | /workspace/1.hmac_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.4231926858 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 4382254145 ps |
CPU time | 17.77 seconds |
Started | Apr 16 02:19:49 PM PDT 24 |
Finished | Apr 16 02:20:07 PM PDT 24 |
Peak memory | 199208 kb |
Host | smart-f885060d-4cdd-49df-9053-f7a3bfa95c64 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231926858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.4231926858 |
Directory | /workspace/1.hmac_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.4054389426 |
Short name | T630 |
Test name | |
Test status | |
Simulation time | 39327171 ps |
CPU time | 1.02 seconds |
Started | Apr 16 02:19:57 PM PDT 24 |
Finished | Apr 16 02:19:59 PM PDT 24 |
Peak memory | 199284 kb |
Host | smart-905eb2a6-267c-4b2f-9c65-b1d1ecb4531d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054389426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.4054389426 |
Directory | /workspace/1.hmac_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2791156151 |
Short name | T610 |
Test name | |
Test status | |
Simulation time | 158320491 ps |
CPU time | 1.34 seconds |
Started | Apr 16 02:19:56 PM PDT 24 |
Finished | Apr 16 02:19:58 PM PDT 24 |
Peak memory | 199236 kb |
Host | smart-09d1e797-8d42-44c7-9510-a3f3e224a053 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791156151 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2791156151 |
Directory | /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.hmac_csr_rw.932318341 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 62520779 ps |
CPU time | 0.67 seconds |
Started | Apr 16 02:19:56 PM PDT 24 |
Finished | Apr 16 02:19:58 PM PDT 24 |
Peak memory | 196512 kb |
Host | smart-275d9c39-21ea-4e5c-bf1d-1963c1a2efb7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932318341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.932318341 |
Directory | /workspace/1.hmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.hmac_intr_test.1634998844 |
Short name | T639 |
Test name | |
Test status | |
Simulation time | 60262363 ps |
CPU time | 0.64 seconds |
Started | Apr 16 02:19:57 PM PDT 24 |
Finished | Apr 16 02:19:59 PM PDT 24 |
Peak memory | 194140 kb |
Host | smart-c508f1be-0371-4b8d-83e0-8832edec6714 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634998844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1634998844 |
Directory | /workspace/1.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3258518736 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 231110663 ps |
CPU time | 1.79 seconds |
Started | Apr 16 02:19:58 PM PDT 24 |
Finished | Apr 16 02:20:00 PM PDT 24 |
Peak memory | 199420 kb |
Host | smart-653f646b-610e-40a4-b168-c6395ba2aa93 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258518736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr _outstanding.3258518736 |
Directory | /workspace/1.hmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3613103953 |
Short name | T632 |
Test name | |
Test status | |
Simulation time | 100848176 ps |
CPU time | 3.09 seconds |
Started | Apr 16 02:19:49 PM PDT 24 |
Finished | Apr 16 02:19:53 PM PDT 24 |
Peak memory | 199216 kb |
Host | smart-2957f735-3023-47c3-bf72-5010c5067daf |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613103953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3613103953 |
Directory | /workspace/1.hmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3426178713 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 97769523 ps |
CPU time | 2.13 seconds |
Started | Apr 16 02:19:58 PM PDT 24 |
Finished | Apr 16 02:20:02 PM PDT 24 |
Peak memory | 199464 kb |
Host | smart-fc2ed0c8-d288-48e4-9ab9-f9bf2c8bcbd0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426178713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3426178713 |
Directory | /workspace/1.hmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2734667559 |
Short name | T634 |
Test name | |
Test status | |
Simulation time | 43105079 ps |
CPU time | 1.23 seconds |
Started | Apr 16 02:20:24 PM PDT 24 |
Finished | Apr 16 02:20:26 PM PDT 24 |
Peak memory | 199196 kb |
Host | smart-ec6e98e8-a71f-4883-8650-d55cbbfee0ef |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734667559 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2734667559 |
Directory | /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2226520433 |
Short name | T715 |
Test name | |
Test status | |
Simulation time | 20472475 ps |
CPU time | 0.68 seconds |
Started | Apr 16 02:20:25 PM PDT 24 |
Finished | Apr 16 02:20:27 PM PDT 24 |
Peak memory | 196524 kb |
Host | smart-a5d00372-629b-45a6-9419-c972d2bbb28f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226520433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2226520433 |
Directory | /workspace/10.hmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.hmac_intr_test.2490796924 |
Short name | T615 |
Test name | |
Test status | |
Simulation time | 13140123 ps |
CPU time | 0.59 seconds |
Started | Apr 16 02:20:25 PM PDT 24 |
Finished | Apr 16 02:20:27 PM PDT 24 |
Peak memory | 193856 kb |
Host | smart-559b2e7c-12e1-486c-b08b-6cc369662f48 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490796924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2490796924 |
Directory | /workspace/10.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.794902875 |
Short name | T732 |
Test name | |
Test status | |
Simulation time | 518121090 ps |
CPU time | 2.27 seconds |
Started | Apr 16 02:20:23 PM PDT 24 |
Finished | Apr 16 02:20:26 PM PDT 24 |
Peak memory | 198988 kb |
Host | smart-6532252e-c95d-4a37-95a7-4ea6d2f0885a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794902875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr _outstanding.794902875 |
Directory | /workspace/10.hmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1248304038 |
Short name | T655 |
Test name | |
Test status | |
Simulation time | 49998763 ps |
CPU time | 1.57 seconds |
Started | Apr 16 02:20:24 PM PDT 24 |
Finished | Apr 16 02:20:26 PM PDT 24 |
Peak memory | 199276 kb |
Host | smart-16644072-95c3-4870-bbe7-e4b06b0c04ec |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248304038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1248304038 |
Directory | /workspace/10.hmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.274898112 |
Short name | T684 |
Test name | |
Test status | |
Simulation time | 439177810 ps |
CPU time | 1.89 seconds |
Started | Apr 16 02:20:24 PM PDT 24 |
Finished | Apr 16 02:20:26 PM PDT 24 |
Peak memory | 199208 kb |
Host | smart-5e3e684c-b516-40bc-904f-11c2aca99239 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274898112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.274898112 |
Directory | /workspace/10.hmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2501557136 |
Short name | T730 |
Test name | |
Test status | |
Simulation time | 229455627 ps |
CPU time | 1.82 seconds |
Started | Apr 16 02:20:26 PM PDT 24 |
Finished | Apr 16 02:20:28 PM PDT 24 |
Peak memory | 199304 kb |
Host | smart-050076a3-2ad6-4353-9ab9-14f55a439c55 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501557136 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.2501557136 |
Directory | /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3068786826 |
Short name | T666 |
Test name | |
Test status | |
Simulation time | 31416467 ps |
CPU time | 0.71 seconds |
Started | Apr 16 02:20:24 PM PDT 24 |
Finished | Apr 16 02:20:25 PM PDT 24 |
Peak memory | 196724 kb |
Host | smart-3dfda47c-6845-491f-8bcf-46cde220c6e9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068786826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3068786826 |
Directory | /workspace/11.hmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.hmac_intr_test.1709196551 |
Short name | T722 |
Test name | |
Test status | |
Simulation time | 10553462 ps |
CPU time | 0.57 seconds |
Started | Apr 16 02:20:25 PM PDT 24 |
Finished | Apr 16 02:20:26 PM PDT 24 |
Peak memory | 193864 kb |
Host | smart-edd3b6bd-3392-44f8-bd69-50a46ae02ca2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709196551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1709196551 |
Directory | /workspace/11.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2531773177 |
Short name | T709 |
Test name | |
Test status | |
Simulation time | 938801232 ps |
CPU time | 2.67 seconds |
Started | Apr 16 02:20:24 PM PDT 24 |
Finished | Apr 16 02:20:27 PM PDT 24 |
Peak memory | 199056 kb |
Host | smart-7b42c14f-c378-4f75-a180-58857a1b5752 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531773177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs r_outstanding.2531773177 |
Directory | /workspace/11.hmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3691511773 |
Short name | T707 |
Test name | |
Test status | |
Simulation time | 294383056 ps |
CPU time | 2.83 seconds |
Started | Apr 16 02:20:29 PM PDT 24 |
Finished | Apr 16 02:20:33 PM PDT 24 |
Peak memory | 199328 kb |
Host | smart-c73ce7ff-661c-4422-b1f1-2089d1910bcf |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691511773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3691511773 |
Directory | /workspace/11.hmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.509872380 |
Short name | T706 |
Test name | |
Test status | |
Simulation time | 161458678 ps |
CPU time | 2.81 seconds |
Started | Apr 16 02:20:28 PM PDT 24 |
Finished | Apr 16 02:20:32 PM PDT 24 |
Peak memory | 199256 kb |
Host | smart-c213167a-bb5b-420f-9278-776364eb4ebd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509872380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.509872380 |
Directory | /workspace/11.hmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.818308527 |
Short name | T674 |
Test name | |
Test status | |
Simulation time | 70334372 ps |
CPU time | 1.95 seconds |
Started | Apr 16 02:20:23 PM PDT 24 |
Finished | Apr 16 02:20:26 PM PDT 24 |
Peak memory | 199312 kb |
Host | smart-8ccd913c-3375-4c8a-bb70-d6e55d4f3717 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818308527 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.818308527 |
Directory | /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3694141918 |
Short name | T696 |
Test name | |
Test status | |
Simulation time | 28901949 ps |
CPU time | 0.89 seconds |
Started | Apr 16 02:20:25 PM PDT 24 |
Finished | Apr 16 02:20:27 PM PDT 24 |
Peak memory | 198408 kb |
Host | smart-2260f7b5-ac96-4c00-a3bd-487ae964153b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694141918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3694141918 |
Directory | /workspace/12.hmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.hmac_intr_test.1077031728 |
Short name | T677 |
Test name | |
Test status | |
Simulation time | 31793647 ps |
CPU time | 0.64 seconds |
Started | Apr 16 02:20:29 PM PDT 24 |
Finished | Apr 16 02:20:31 PM PDT 24 |
Peak memory | 194140 kb |
Host | smart-946e337d-cdd0-41cb-9ad7-5eb6bbb085fb |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077031728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1077031728 |
Directory | /workspace/12.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3916861259 |
Short name | T695 |
Test name | |
Test status | |
Simulation time | 93383260 ps |
CPU time | 1.69 seconds |
Started | Apr 16 02:20:23 PM PDT 24 |
Finished | Apr 16 02:20:26 PM PDT 24 |
Peak memory | 198892 kb |
Host | smart-068966e6-f633-4eda-b14b-c4a3d928d4b1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916861259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs r_outstanding.3916861259 |
Directory | /workspace/12.hmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.hmac_tl_errors.617146546 |
Short name | T720 |
Test name | |
Test status | |
Simulation time | 384618411 ps |
CPU time | 3.69 seconds |
Started | Apr 16 02:20:28 PM PDT 24 |
Finished | Apr 16 02:20:32 PM PDT 24 |
Peak memory | 199308 kb |
Host | smart-2f02ae8b-a73a-4b2d-b972-c3bb9cc60c36 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617146546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.617146546 |
Directory | /workspace/12.hmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1757063614 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 261960772 ps |
CPU time | 1.7 seconds |
Started | Apr 16 02:20:26 PM PDT 24 |
Finished | Apr 16 02:20:28 PM PDT 24 |
Peak memory | 199252 kb |
Host | smart-fed175d1-fd1f-4755-bb3c-9873ea668c3e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757063614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1757063614 |
Directory | /workspace/12.hmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2330503989 |
Short name | T665 |
Test name | |
Test status | |
Simulation time | 27109840 ps |
CPU time | 1.56 seconds |
Started | Apr 16 02:20:29 PM PDT 24 |
Finished | Apr 16 02:20:31 PM PDT 24 |
Peak memory | 199232 kb |
Host | smart-7e404cc0-2082-4363-897f-71569377c6e5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330503989 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2330503989 |
Directory | /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2284829571 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 16548701 ps |
CPU time | 0.71 seconds |
Started | Apr 16 02:20:28 PM PDT 24 |
Finished | Apr 16 02:20:29 PM PDT 24 |
Peak memory | 196944 kb |
Host | smart-38615872-e88a-4b45-8d1b-fa706b062ec3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284829571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2284829571 |
Directory | /workspace/13.hmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.hmac_intr_test.2713705877 |
Short name | T627 |
Test name | |
Test status | |
Simulation time | 42038342 ps |
CPU time | 0.59 seconds |
Started | Apr 16 02:20:29 PM PDT 24 |
Finished | Apr 16 02:20:30 PM PDT 24 |
Peak memory | 193912 kb |
Host | smart-5cdb4986-1fde-4045-987b-1a3c44662e18 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713705877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2713705877 |
Directory | /workspace/13.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2151941095 |
Short name | T733 |
Test name | |
Test status | |
Simulation time | 76978810 ps |
CPU time | 1.7 seconds |
Started | Apr 16 02:20:31 PM PDT 24 |
Finished | Apr 16 02:20:34 PM PDT 24 |
Peak memory | 199180 kb |
Host | smart-7df129ee-2a1b-42d6-af69-632074387c3b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151941095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs r_outstanding.2151941095 |
Directory | /workspace/13.hmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3127691224 |
Short name | T620 |
Test name | |
Test status | |
Simulation time | 248730827 ps |
CPU time | 3.12 seconds |
Started | Apr 16 02:20:30 PM PDT 24 |
Finished | Apr 16 02:20:34 PM PDT 24 |
Peak memory | 199304 kb |
Host | smart-ae0939db-0ccc-487b-94fe-8a486db46159 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127691224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3127691224 |
Directory | /workspace/13.hmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.664385630 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 3575424246 ps |
CPU time | 3.18 seconds |
Started | Apr 16 02:20:23 PM PDT 24 |
Finished | Apr 16 02:20:27 PM PDT 24 |
Peak memory | 199348 kb |
Host | smart-ade6ba9e-478d-4d6f-9f7f-576108ed7676 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664385630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.664385630 |
Directory | /workspace/13.hmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2536367156 |
Short name | T728 |
Test name | |
Test status | |
Simulation time | 38598214 ps |
CPU time | 1.15 seconds |
Started | Apr 16 02:20:29 PM PDT 24 |
Finished | Apr 16 02:20:30 PM PDT 24 |
Peak memory | 199196 kb |
Host | smart-0bdd82db-1614-4298-a8cb-7fa8e0e292c9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536367156 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2536367156 |
Directory | /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.hmac_intr_test.2055172472 |
Short name | T604 |
Test name | |
Test status | |
Simulation time | 40199633 ps |
CPU time | 0.62 seconds |
Started | Apr 16 02:20:31 PM PDT 24 |
Finished | Apr 16 02:20:33 PM PDT 24 |
Peak memory | 193944 kb |
Host | smart-3b9ca1d9-e060-465f-a8dc-ccaad82ecbe0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055172472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2055172472 |
Directory | /workspace/14.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.914575301 |
Short name | T638 |
Test name | |
Test status | |
Simulation time | 40115229 ps |
CPU time | 1.14 seconds |
Started | Apr 16 02:20:30 PM PDT 24 |
Finished | Apr 16 02:20:32 PM PDT 24 |
Peak memory | 199188 kb |
Host | smart-1cc0f540-fffb-4594-8af8-d82525492122 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914575301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr _outstanding.914575301 |
Directory | /workspace/14.hmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2517840093 |
Short name | T642 |
Test name | |
Test status | |
Simulation time | 761645205 ps |
CPU time | 2.83 seconds |
Started | Apr 16 02:20:31 PM PDT 24 |
Finished | Apr 16 02:20:34 PM PDT 24 |
Peak memory | 199304 kb |
Host | smart-ae5bbbad-e483-4bf6-9983-3289ad2d3e93 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517840093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2517840093 |
Directory | /workspace/14.hmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2792304187 |
Short name | T675 |
Test name | |
Test status | |
Simulation time | 415368678 ps |
CPU time | 1.75 seconds |
Started | Apr 16 02:20:31 PM PDT 24 |
Finished | Apr 16 02:20:34 PM PDT 24 |
Peak memory | 199256 kb |
Host | smart-aa1d75b4-36b0-4c89-a9d4-07af6f9f05a1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792304187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2792304187 |
Directory | /workspace/14.hmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1202933996 |
Short name | T659 |
Test name | |
Test status | |
Simulation time | 59484608 ps |
CPU time | 1.57 seconds |
Started | Apr 16 02:20:32 PM PDT 24 |
Finished | Apr 16 02:20:34 PM PDT 24 |
Peak memory | 199236 kb |
Host | smart-e412c144-93b5-427d-bef4-348d463cd262 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202933996 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1202933996 |
Directory | /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2040184529 |
Short name | T704 |
Test name | |
Test status | |
Simulation time | 29088413 ps |
CPU time | 0.94 seconds |
Started | Apr 16 02:20:34 PM PDT 24 |
Finished | Apr 16 02:20:36 PM PDT 24 |
Peak memory | 198228 kb |
Host | smart-e832223c-e8ae-439e-84ad-fb4d05b44c71 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040184529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2040184529 |
Directory | /workspace/15.hmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.hmac_intr_test.4168488250 |
Short name | T625 |
Test name | |
Test status | |
Simulation time | 50630715 ps |
CPU time | 0.61 seconds |
Started | Apr 16 02:20:30 PM PDT 24 |
Finished | Apr 16 02:20:31 PM PDT 24 |
Peak memory | 193868 kb |
Host | smart-95002f94-8c8b-41f0-a6a2-8f8cf76a9f99 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168488250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.4168488250 |
Directory | /workspace/15.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.970586639 |
Short name | T633 |
Test name | |
Test status | |
Simulation time | 109034935 ps |
CPU time | 2.19 seconds |
Started | Apr 16 02:20:28 PM PDT 24 |
Finished | Apr 16 02:20:30 PM PDT 24 |
Peak memory | 199080 kb |
Host | smart-a8d2ce99-890d-4e41-a4c2-1b3b1d9bed4d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970586639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr _outstanding.970586639 |
Directory | /workspace/15.hmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.hmac_tl_errors.106764297 |
Short name | T609 |
Test name | |
Test status | |
Simulation time | 75510976 ps |
CPU time | 1.34 seconds |
Started | Apr 16 02:20:26 PM PDT 24 |
Finished | Apr 16 02:20:28 PM PDT 24 |
Peak memory | 199316 kb |
Host | smart-35ad5aee-3c68-427d-85a0-374c2cd6b244 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106764297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.106764297 |
Directory | /workspace/15.hmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2156889977 |
Short name | T643 |
Test name | |
Test status | |
Simulation time | 153661576 ps |
CPU time | 1.84 seconds |
Started | Apr 16 02:20:31 PM PDT 24 |
Finished | Apr 16 02:20:34 PM PDT 24 |
Peak memory | 199344 kb |
Host | smart-5e53deaf-f44e-4439-9a4f-e760d35f9066 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156889977 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2156889977 |
Directory | /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1836691474 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 45778406 ps |
CPU time | 0.78 seconds |
Started | Apr 16 02:20:30 PM PDT 24 |
Finished | Apr 16 02:20:32 PM PDT 24 |
Peak memory | 198404 kb |
Host | smart-c2ee7aec-ad8c-4ae8-987c-3188c75a38b6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836691474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1836691474 |
Directory | /workspace/16.hmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.hmac_intr_test.3844112857 |
Short name | T713 |
Test name | |
Test status | |
Simulation time | 15169597 ps |
CPU time | 0.59 seconds |
Started | Apr 16 02:20:31 PM PDT 24 |
Finished | Apr 16 02:20:33 PM PDT 24 |
Peak memory | 193868 kb |
Host | smart-443023d0-cbdd-46ef-a7b1-ca64c8ec4ab1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844112857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3844112857 |
Directory | /workspace/16.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1143746820 |
Short name | T669 |
Test name | |
Test status | |
Simulation time | 357631610 ps |
CPU time | 2.19 seconds |
Started | Apr 16 02:20:30 PM PDT 24 |
Finished | Apr 16 02:20:33 PM PDT 24 |
Peak memory | 199232 kb |
Host | smart-3a19683c-0ce0-4e00-877c-a89bf7bea961 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143746820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs r_outstanding.1143746820 |
Directory | /workspace/16.hmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.hmac_tl_errors.4180750301 |
Short name | T612 |
Test name | |
Test status | |
Simulation time | 451503864 ps |
CPU time | 2.03 seconds |
Started | Apr 16 02:20:29 PM PDT 24 |
Finished | Apr 16 02:20:32 PM PDT 24 |
Peak memory | 199296 kb |
Host | smart-608397e7-8bdd-4c7a-b366-94a585d5e354 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180750301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.4180750301 |
Directory | /workspace/16.hmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.127149747 |
Short name | T683 |
Test name | |
Test status | |
Simulation time | 175139491 ps |
CPU time | 2.93 seconds |
Started | Apr 16 02:20:30 PM PDT 24 |
Finished | Apr 16 02:20:33 PM PDT 24 |
Peak memory | 199224 kb |
Host | smart-c9535326-77e2-486f-9707-766efc73c40b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127149747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.127149747 |
Directory | /workspace/16.hmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2253865964 |
Short name | T608 |
Test name | |
Test status | |
Simulation time | 360481437 ps |
CPU time | 1.53 seconds |
Started | Apr 16 02:20:30 PM PDT 24 |
Finished | Apr 16 02:20:32 PM PDT 24 |
Peak memory | 199284 kb |
Host | smart-12657e04-6570-412b-97ff-649ab14e10a8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253865964 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2253865964 |
Directory | /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3817295389 |
Short name | T640 |
Test name | |
Test status | |
Simulation time | 17761934 ps |
CPU time | 0.78 seconds |
Started | Apr 16 02:20:30 PM PDT 24 |
Finished | Apr 16 02:20:32 PM PDT 24 |
Peak memory | 198196 kb |
Host | smart-71a838a8-f690-4052-9909-060b2c3ee2c1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817295389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3817295389 |
Directory | /workspace/17.hmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.hmac_intr_test.3153731681 |
Short name | T647 |
Test name | |
Test status | |
Simulation time | 27062092 ps |
CPU time | 0.62 seconds |
Started | Apr 16 02:20:31 PM PDT 24 |
Finished | Apr 16 02:20:33 PM PDT 24 |
Peak memory | 194132 kb |
Host | smart-b57201ce-24e9-437f-bde4-ff8381bfaf81 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153731681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3153731681 |
Directory | /workspace/17.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.945759132 |
Short name | T724 |
Test name | |
Test status | |
Simulation time | 207781572 ps |
CPU time | 1.8 seconds |
Started | Apr 16 02:20:32 PM PDT 24 |
Finished | Apr 16 02:20:34 PM PDT 24 |
Peak memory | 198840 kb |
Host | smart-402ed90b-ad5b-48c7-98a4-6976988dbe64 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945759132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr _outstanding.945759132 |
Directory | /workspace/17.hmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1322139014 |
Short name | T681 |
Test name | |
Test status | |
Simulation time | 311063420 ps |
CPU time | 2.08 seconds |
Started | Apr 16 02:20:34 PM PDT 24 |
Finished | Apr 16 02:20:37 PM PDT 24 |
Peak memory | 198912 kb |
Host | smart-a9959458-4df1-46a4-bcc7-005d1941516d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322139014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1322139014 |
Directory | /workspace/17.hmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.219905139 |
Short name | T678 |
Test name | |
Test status | |
Simulation time | 967295503 ps |
CPU time | 4.28 seconds |
Started | Apr 16 02:20:34 PM PDT 24 |
Finished | Apr 16 02:20:39 PM PDT 24 |
Peak memory | 198848 kb |
Host | smart-527a0e74-b1cc-4997-a0ea-9538c9d3d940 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219905139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.219905139 |
Directory | /workspace/17.hmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3947187349 |
Short name | T680 |
Test name | |
Test status | |
Simulation time | 119320109632 ps |
CPU time | 157.84 seconds |
Started | Apr 16 02:20:36 PM PDT 24 |
Finished | Apr 16 02:23:15 PM PDT 24 |
Peak memory | 215820 kb |
Host | smart-f6bf3f2d-5974-452c-8781-b8c9db1e1b20 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947187349 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3947187349 |
Directory | /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3066058887 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 17121211 ps |
CPU time | 0.91 seconds |
Started | Apr 16 02:20:36 PM PDT 24 |
Finished | Apr 16 02:20:38 PM PDT 24 |
Peak memory | 198612 kb |
Host | smart-6a9097f7-f893-4cbc-8428-7bbdcf8d32ee |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066058887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3066058887 |
Directory | /workspace/18.hmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.hmac_intr_test.4060168835 |
Short name | T602 |
Test name | |
Test status | |
Simulation time | 22667351 ps |
CPU time | 0.57 seconds |
Started | Apr 16 02:20:34 PM PDT 24 |
Finished | Apr 16 02:20:36 PM PDT 24 |
Peak memory | 193808 kb |
Host | smart-32af2d93-4581-4b0d-9bea-e9574af4d22f |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060168835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.4060168835 |
Directory | /workspace/18.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1342569022 |
Short name | T667 |
Test name | |
Test status | |
Simulation time | 132185624 ps |
CPU time | 1.58 seconds |
Started | Apr 16 02:20:35 PM PDT 24 |
Finished | Apr 16 02:20:38 PM PDT 24 |
Peak memory | 198904 kb |
Host | smart-fdc1963e-38eb-4756-bed9-32b0bf381666 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342569022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs r_outstanding.1342569022 |
Directory | /workspace/18.hmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1338314779 |
Short name | T618 |
Test name | |
Test status | |
Simulation time | 785479752 ps |
CPU time | 3.84 seconds |
Started | Apr 16 02:20:35 PM PDT 24 |
Finished | Apr 16 02:20:40 PM PDT 24 |
Peak memory | 199408 kb |
Host | smart-0066eb86-c7d7-4f74-9fdb-857b1f6880ec |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338314779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1338314779 |
Directory | /workspace/18.hmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.962708702 |
Short name | T714 |
Test name | |
Test status | |
Simulation time | 1095861503 ps |
CPU time | 4.59 seconds |
Started | Apr 16 02:20:40 PM PDT 24 |
Finished | Apr 16 02:20:45 PM PDT 24 |
Peak memory | 199268 kb |
Host | smart-13623f01-fff1-49d6-97d5-0de0a6febb2e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962708702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.962708702 |
Directory | /workspace/18.hmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.4145158203 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 25248899389 ps |
CPU time | 387.27 seconds |
Started | Apr 16 02:20:33 PM PDT 24 |
Finished | Apr 16 02:27:02 PM PDT 24 |
Peak memory | 215120 kb |
Host | smart-1882dfcc-f811-42fe-8f8b-8ffb88914c54 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145158203 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.4145158203 |
Directory | /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2939494306 |
Short name | T623 |
Test name | |
Test status | |
Simulation time | 32971844 ps |
CPU time | 0.66 seconds |
Started | Apr 16 02:20:36 PM PDT 24 |
Finished | Apr 16 02:20:38 PM PDT 24 |
Peak memory | 196844 kb |
Host | smart-dab7aeb3-6e38-40d9-af03-ed4a296a6a88 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939494306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2939494306 |
Directory | /workspace/19.hmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.hmac_intr_test.777481847 |
Short name | T622 |
Test name | |
Test status | |
Simulation time | 13487260 ps |
CPU time | 0.56 seconds |
Started | Apr 16 02:20:34 PM PDT 24 |
Finished | Apr 16 02:20:35 PM PDT 24 |
Peak memory | 193872 kb |
Host | smart-48795df1-c8c6-4aa8-9a3c-77d57cf29ec4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777481847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.777481847 |
Directory | /workspace/19.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3071683544 |
Short name | T636 |
Test name | |
Test status | |
Simulation time | 116919972 ps |
CPU time | 1.21 seconds |
Started | Apr 16 02:20:35 PM PDT 24 |
Finished | Apr 16 02:20:38 PM PDT 24 |
Peak memory | 198312 kb |
Host | smart-0fc63ed7-a147-4c8d-a25a-92a377d2d6eb |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071683544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs r_outstanding.3071683544 |
Directory | /workspace/19.hmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1693608171 |
Short name | T613 |
Test name | |
Test status | |
Simulation time | 817480804 ps |
CPU time | 3.5 seconds |
Started | Apr 16 02:20:36 PM PDT 24 |
Finished | Apr 16 02:20:40 PM PDT 24 |
Peak memory | 199532 kb |
Host | smart-ee2fe53d-4a1d-44e7-886d-44637f42b04f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693608171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1693608171 |
Directory | /workspace/19.hmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1667360603 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 227006191 ps |
CPU time | 3.98 seconds |
Started | Apr 16 02:20:36 PM PDT 24 |
Finished | Apr 16 02:20:41 PM PDT 24 |
Peak memory | 199240 kb |
Host | smart-c332efa9-c00b-4a95-af87-022c7ffe1677 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667360603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1667360603 |
Directory | /workspace/19.hmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2832700321 |
Short name | T716 |
Test name | |
Test status | |
Simulation time | 163283746 ps |
CPU time | 8.09 seconds |
Started | Apr 16 02:19:54 PM PDT 24 |
Finished | Apr 16 02:20:03 PM PDT 24 |
Peak memory | 198688 kb |
Host | smart-13442b3a-f869-4f67-b458-4d91223b673f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832700321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.2832700321 |
Directory | /workspace/2.hmac_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3495044871 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 5961299175 ps |
CPU time | 16.37 seconds |
Started | Apr 16 02:19:53 PM PDT 24 |
Finished | Apr 16 02:20:11 PM PDT 24 |
Peak memory | 198352 kb |
Host | smart-94bc0376-b4bc-4037-abe8-121c2b3b105b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495044871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3495044871 |
Directory | /workspace/2.hmac_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1696511822 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 35195629 ps |
CPU time | 0.73 seconds |
Started | Apr 16 02:19:54 PM PDT 24 |
Finished | Apr 16 02:19:56 PM PDT 24 |
Peak memory | 196868 kb |
Host | smart-fce56a30-7477-422b-aa9c-d59233e80d35 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696511822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1696511822 |
Directory | /workspace/2.hmac_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3150886117 |
Short name | T687 |
Test name | |
Test status | |
Simulation time | 37039059613 ps |
CPU time | 282.51 seconds |
Started | Apr 16 02:19:58 PM PDT 24 |
Finished | Apr 16 02:24:41 PM PDT 24 |
Peak memory | 215796 kb |
Host | smart-d77e9105-72ba-4a31-840d-386aa55045c3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150886117 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3150886117 |
Directory | /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2173938055 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 418967496 ps |
CPU time | 0.92 seconds |
Started | Apr 16 02:19:52 PM PDT 24 |
Finished | Apr 16 02:19:53 PM PDT 24 |
Peak memory | 198496 kb |
Host | smart-5be80dc0-7408-4301-842e-078f6266762c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173938055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2173938055 |
Directory | /workspace/2.hmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.hmac_intr_test.3442816364 |
Short name | T624 |
Test name | |
Test status | |
Simulation time | 27644409 ps |
CPU time | 0.65 seconds |
Started | Apr 16 02:19:53 PM PDT 24 |
Finished | Apr 16 02:19:55 PM PDT 24 |
Peak memory | 194036 kb |
Host | smart-dd0dbc78-8ffb-44ca-a12f-17422f9262eb |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442816364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3442816364 |
Directory | /workspace/2.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2923143480 |
Short name | T626 |
Test name | |
Test status | |
Simulation time | 507421328 ps |
CPU time | 1.57 seconds |
Started | Apr 16 02:19:55 PM PDT 24 |
Finished | Apr 16 02:19:58 PM PDT 24 |
Peak memory | 199208 kb |
Host | smart-045b055b-cc9a-4f53-acff-4d72a9f8c2bd |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923143480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr _outstanding.2923143480 |
Directory | /workspace/2.hmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.hmac_tl_errors.257311025 |
Short name | T616 |
Test name | |
Test status | |
Simulation time | 347520364 ps |
CPU time | 2.81 seconds |
Started | Apr 16 02:19:55 PM PDT 24 |
Finished | Apr 16 02:19:59 PM PDT 24 |
Peak memory | 199284 kb |
Host | smart-cf7ba5b9-d699-4f4c-8c1b-b241d3dbf8a7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257311025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.257311025 |
Directory | /workspace/2.hmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.477390141 |
Short name | T648 |
Test name | |
Test status | |
Simulation time | 420221058 ps |
CPU time | 3.93 seconds |
Started | Apr 16 02:19:56 PM PDT 24 |
Finished | Apr 16 02:20:01 PM PDT 24 |
Peak memory | 199200 kb |
Host | smart-b0f998dd-2693-4854-8493-47a5f7fd8dc4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477390141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.477390141 |
Directory | /workspace/2.hmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/20.hmac_intr_test.1147354074 |
Short name | T702 |
Test name | |
Test status | |
Simulation time | 43060766 ps |
CPU time | 0.58 seconds |
Started | Apr 16 02:20:33 PM PDT 24 |
Finished | Apr 16 02:20:34 PM PDT 24 |
Peak memory | 193876 kb |
Host | smart-78a12f9c-efa8-41f2-91e7-0eeb20e7a35c |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147354074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1147354074 |
Directory | /workspace/20.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/21.hmac_intr_test.1203209370 |
Short name | T693 |
Test name | |
Test status | |
Simulation time | 14826030 ps |
CPU time | 0.59 seconds |
Started | Apr 16 02:20:36 PM PDT 24 |
Finished | Apr 16 02:20:37 PM PDT 24 |
Peak memory | 193948 kb |
Host | smart-8f7501c1-8f9b-42c7-9363-90732dbd74f8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203209370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1203209370 |
Directory | /workspace/21.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/22.hmac_intr_test.1932445866 |
Short name | T599 |
Test name | |
Test status | |
Simulation time | 21851338 ps |
CPU time | 0.6 seconds |
Started | Apr 16 02:20:41 PM PDT 24 |
Finished | Apr 16 02:20:43 PM PDT 24 |
Peak memory | 193940 kb |
Host | smart-b39dbe93-5271-4cb4-a857-2b1294dfa283 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932445866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1932445866 |
Directory | /workspace/22.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/23.hmac_intr_test.1050621661 |
Short name | T692 |
Test name | |
Test status | |
Simulation time | 18164481 ps |
CPU time | 0.6 seconds |
Started | Apr 16 02:20:35 PM PDT 24 |
Finished | Apr 16 02:20:37 PM PDT 24 |
Peak memory | 193920 kb |
Host | smart-d45869de-28e8-40bb-827d-5d73641d40c0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050621661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1050621661 |
Directory | /workspace/23.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/24.hmac_intr_test.570837457 |
Short name | T645 |
Test name | |
Test status | |
Simulation time | 13142143 ps |
CPU time | 0.56 seconds |
Started | Apr 16 02:20:34 PM PDT 24 |
Finished | Apr 16 02:20:35 PM PDT 24 |
Peak memory | 193812 kb |
Host | smart-39c30663-fa7b-4d2c-98b5-9e62e01eaceb |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570837457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.570837457 |
Directory | /workspace/24.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/25.hmac_intr_test.714686291 |
Short name | T699 |
Test name | |
Test status | |
Simulation time | 42281616 ps |
CPU time | 0.61 seconds |
Started | Apr 16 02:20:40 PM PDT 24 |
Finished | Apr 16 02:20:41 PM PDT 24 |
Peak memory | 193908 kb |
Host | smart-580c429c-c1d1-4dd9-9d14-6a915062c0c9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714686291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.714686291 |
Directory | /workspace/25.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/26.hmac_intr_test.2135177276 |
Short name | T619 |
Test name | |
Test status | |
Simulation time | 16315028 ps |
CPU time | 0.64 seconds |
Started | Apr 16 02:20:40 PM PDT 24 |
Finished | Apr 16 02:20:41 PM PDT 24 |
Peak memory | 193908 kb |
Host | smart-914b6e97-1aac-41be-9437-60ee2c81bf3f |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135177276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2135177276 |
Directory | /workspace/26.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/27.hmac_intr_test.2034873895 |
Short name | T617 |
Test name | |
Test status | |
Simulation time | 140281281 ps |
CPU time | 0.68 seconds |
Started | Apr 16 02:20:41 PM PDT 24 |
Finished | Apr 16 02:20:43 PM PDT 24 |
Peak memory | 193948 kb |
Host | smart-120c5173-0783-47b5-a144-fca51467226b |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034873895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2034873895 |
Directory | /workspace/27.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/28.hmac_intr_test.49101554 |
Short name | T676 |
Test name | |
Test status | |
Simulation time | 10873711 ps |
CPU time | 0.56 seconds |
Started | Apr 16 02:20:35 PM PDT 24 |
Finished | Apr 16 02:20:37 PM PDT 24 |
Peak memory | 193892 kb |
Host | smart-86e91406-cba2-4830-b491-09292ba09c6d |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49101554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.49101554 |
Directory | /workspace/28.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/29.hmac_intr_test.3755060192 |
Short name | T611 |
Test name | |
Test status | |
Simulation time | 14292838 ps |
CPU time | 0.68 seconds |
Started | Apr 16 02:20:35 PM PDT 24 |
Finished | Apr 16 02:20:37 PM PDT 24 |
Peak memory | 193920 kb |
Host | smart-aba784b1-0c8d-4215-8265-18c6ef5ba2c3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755060192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3755060192 |
Directory | /workspace/29.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1151020296 |
Short name | T670 |
Test name | |
Test status | |
Simulation time | 63375607 ps |
CPU time | 3.15 seconds |
Started | Apr 16 02:19:55 PM PDT 24 |
Finished | Apr 16 02:19:59 PM PDT 24 |
Peak memory | 198184 kb |
Host | smart-0e96d2ff-bb88-426c-9dd4-efba67400066 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151020296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1151020296 |
Directory | /workspace/3.hmac_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2871624233 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 1165006441 ps |
CPU time | 12.23 seconds |
Started | Apr 16 02:19:57 PM PDT 24 |
Finished | Apr 16 02:20:10 PM PDT 24 |
Peak memory | 199108 kb |
Host | smart-9692c1b5-32a8-46d6-95e3-3e825acdfebb |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871624233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2871624233 |
Directory | /workspace/3.hmac_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2576202748 |
Short name | T710 |
Test name | |
Test status | |
Simulation time | 79389401 ps |
CPU time | 0.81 seconds |
Started | Apr 16 02:19:55 PM PDT 24 |
Finished | Apr 16 02:19:57 PM PDT 24 |
Peak memory | 198024 kb |
Host | smart-02308873-efcd-4bdd-8d8c-078ed685013d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576202748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2576202748 |
Directory | /workspace/3.hmac_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2344557723 |
Short name | T700 |
Test name | |
Test status | |
Simulation time | 102422899 ps |
CPU time | 1.71 seconds |
Started | Apr 16 02:19:52 PM PDT 24 |
Finished | Apr 16 02:19:54 PM PDT 24 |
Peak memory | 199284 kb |
Host | smart-d94ec436-644d-496b-8645-67a6f1d167c2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344557723 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2344557723 |
Directory | /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3336376162 |
Short name | T731 |
Test name | |
Test status | |
Simulation time | 16348040 ps |
CPU time | 0.82 seconds |
Started | Apr 16 02:19:54 PM PDT 24 |
Finished | Apr 16 02:19:56 PM PDT 24 |
Peak memory | 198248 kb |
Host | smart-836b5019-f0ea-40bf-959e-55e88db0d0ff |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336376162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3336376162 |
Directory | /workspace/3.hmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.hmac_intr_test.2494874743 |
Short name | T703 |
Test name | |
Test status | |
Simulation time | 25160987 ps |
CPU time | 0.62 seconds |
Started | Apr 16 02:19:54 PM PDT 24 |
Finished | Apr 16 02:19:56 PM PDT 24 |
Peak memory | 193936 kb |
Host | smart-2856788e-fb69-4239-85bb-b550f047780a |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494874743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2494874743 |
Directory | /workspace/3.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.289299718 |
Short name | T652 |
Test name | |
Test status | |
Simulation time | 55895232 ps |
CPU time | 1.56 seconds |
Started | Apr 16 02:19:54 PM PDT 24 |
Finished | Apr 16 02:19:56 PM PDT 24 |
Peak memory | 199208 kb |
Host | smart-3c679378-e250-4604-95ce-f9997d9cbebe |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289299718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_ outstanding.289299718 |
Directory | /workspace/3.hmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1771303468 |
Short name | T673 |
Test name | |
Test status | |
Simulation time | 228647036 ps |
CPU time | 3.85 seconds |
Started | Apr 16 02:19:53 PM PDT 24 |
Finished | Apr 16 02:19:58 PM PDT 24 |
Peak memory | 199200 kb |
Host | smart-d553a1f7-500b-4bc7-b3b3-2fb088f18353 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771303468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1771303468 |
Directory | /workspace/3.hmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/30.hmac_intr_test.4133970367 |
Short name | T600 |
Test name | |
Test status | |
Simulation time | 12849307 ps |
CPU time | 0.59 seconds |
Started | Apr 16 02:20:34 PM PDT 24 |
Finished | Apr 16 02:20:36 PM PDT 24 |
Peak memory | 193876 kb |
Host | smart-e27ec079-f0a0-485d-a23a-14cdc0477883 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133970367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.4133970367 |
Directory | /workspace/30.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/31.hmac_intr_test.2872073533 |
Short name | T598 |
Test name | |
Test status | |
Simulation time | 24197503 ps |
CPU time | 0.58 seconds |
Started | Apr 16 02:20:36 PM PDT 24 |
Finished | Apr 16 02:20:38 PM PDT 24 |
Peak memory | 194140 kb |
Host | smart-0f79d5f5-91a8-4ef2-a340-0a5b554d034e |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872073533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2872073533 |
Directory | /workspace/31.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/32.hmac_intr_test.3324950021 |
Short name | T605 |
Test name | |
Test status | |
Simulation time | 68967243 ps |
CPU time | 0.6 seconds |
Started | Apr 16 02:20:34 PM PDT 24 |
Finished | Apr 16 02:20:36 PM PDT 24 |
Peak memory | 193860 kb |
Host | smart-51ad78ba-c057-4836-b004-2b2441e74eb6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324950021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3324950021 |
Directory | /workspace/32.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/33.hmac_intr_test.120412068 |
Short name | T649 |
Test name | |
Test status | |
Simulation time | 29909255 ps |
CPU time | 0.57 seconds |
Started | Apr 16 02:20:34 PM PDT 24 |
Finished | Apr 16 02:20:36 PM PDT 24 |
Peak memory | 193956 kb |
Host | smart-426ef2ea-0bb4-4afd-9575-8a48590154ed |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120412068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.120412068 |
Directory | /workspace/33.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/34.hmac_intr_test.1450921641 |
Short name | T690 |
Test name | |
Test status | |
Simulation time | 17050392 ps |
CPU time | 0.61 seconds |
Started | Apr 16 02:20:35 PM PDT 24 |
Finished | Apr 16 02:20:37 PM PDT 24 |
Peak memory | 193956 kb |
Host | smart-19cd81ee-c4e8-44ca-91f5-17ef54248524 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450921641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1450921641 |
Directory | /workspace/34.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/35.hmac_intr_test.3609672092 |
Short name | T628 |
Test name | |
Test status | |
Simulation time | 14235960 ps |
CPU time | 0.56 seconds |
Started | Apr 16 02:20:34 PM PDT 24 |
Finished | Apr 16 02:20:36 PM PDT 24 |
Peak memory | 193820 kb |
Host | smart-284efe49-3ce6-4894-95ff-0024c57ad2a0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609672092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3609672092 |
Directory | /workspace/35.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/36.hmac_intr_test.933805476 |
Short name | T686 |
Test name | |
Test status | |
Simulation time | 28979906 ps |
CPU time | 0.61 seconds |
Started | Apr 16 02:20:35 PM PDT 24 |
Finished | Apr 16 02:20:36 PM PDT 24 |
Peak memory | 193912 kb |
Host | smart-c2d539df-027d-4311-ac18-7c57e65d8b30 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933805476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.933805476 |
Directory | /workspace/36.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/37.hmac_intr_test.277159839 |
Short name | T661 |
Test name | |
Test status | |
Simulation time | 49588201 ps |
CPU time | 0.56 seconds |
Started | Apr 16 02:20:37 PM PDT 24 |
Finished | Apr 16 02:20:38 PM PDT 24 |
Peak memory | 194092 kb |
Host | smart-fba9b678-d948-4d65-ba93-a22743f797a7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277159839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.277159839 |
Directory | /workspace/37.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/38.hmac_intr_test.2906460632 |
Short name | T688 |
Test name | |
Test status | |
Simulation time | 13553058 ps |
CPU time | 0.56 seconds |
Started | Apr 16 02:20:38 PM PDT 24 |
Finished | Apr 16 02:20:39 PM PDT 24 |
Peak memory | 194072 kb |
Host | smart-c40a3153-e8f3-4569-9c03-92c08a42f319 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906460632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2906460632 |
Directory | /workspace/38.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/39.hmac_intr_test.836336269 |
Short name | T621 |
Test name | |
Test status | |
Simulation time | 24003207 ps |
CPU time | 0.61 seconds |
Started | Apr 16 02:20:37 PM PDT 24 |
Finished | Apr 16 02:20:38 PM PDT 24 |
Peak memory | 194096 kb |
Host | smart-e3b12f5c-0428-46f1-92ed-7c9dccd8b5e3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836336269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.836336269 |
Directory | /workspace/39.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2267903497 |
Short name | T672 |
Test name | |
Test status | |
Simulation time | 533840765 ps |
CPU time | 5.7 seconds |
Started | Apr 16 02:19:58 PM PDT 24 |
Finished | Apr 16 02:20:05 PM PDT 24 |
Peak memory | 198812 kb |
Host | smart-fdd89221-4768-4d43-9b34-f27cb66d5b1d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267903497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2267903497 |
Directory | /workspace/4.hmac_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2973305318 |
Short name | T729 |
Test name | |
Test status | |
Simulation time | 112626368 ps |
CPU time | 5.54 seconds |
Started | Apr 16 02:19:58 PM PDT 24 |
Finished | Apr 16 02:20:04 PM PDT 24 |
Peak memory | 198320 kb |
Host | smart-9769b6c7-d8e4-4597-aeb9-1e5366c94ccf |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973305318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2973305318 |
Directory | /workspace/4.hmac_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3269508012 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 28707058 ps |
CPU time | 0.76 seconds |
Started | Apr 16 02:20:07 PM PDT 24 |
Finished | Apr 16 02:20:08 PM PDT 24 |
Peak memory | 196920 kb |
Host | smart-b212f868-fbe9-4aa3-82e2-0b16dfb58a65 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269508012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3269508012 |
Directory | /workspace/4.hmac_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3966970648 |
Short name | T685 |
Test name | |
Test status | |
Simulation time | 29081071 ps |
CPU time | 1.8 seconds |
Started | Apr 16 02:20:02 PM PDT 24 |
Finished | Apr 16 02:20:04 PM PDT 24 |
Peak memory | 199296 kb |
Host | smart-7c717e56-4a11-4c02-8c76-926b75f76f01 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966970648 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3966970648 |
Directory | /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3767752410 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 28623449 ps |
CPU time | 0.98 seconds |
Started | Apr 16 02:19:57 PM PDT 24 |
Finished | Apr 16 02:19:59 PM PDT 24 |
Peak memory | 198644 kb |
Host | smart-34044e03-6bb0-41d0-b5cc-e72c0a88c5ce |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767752410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3767752410 |
Directory | /workspace/4.hmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.hmac_intr_test.4215185972 |
Short name | T653 |
Test name | |
Test status | |
Simulation time | 38543899 ps |
CPU time | 0.57 seconds |
Started | Apr 16 02:19:54 PM PDT 24 |
Finished | Apr 16 02:19:55 PM PDT 24 |
Peak memory | 193944 kb |
Host | smart-40d0b3d5-4353-4298-a5a3-fae06f7074ad |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215185972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.4215185972 |
Directory | /workspace/4.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3437266670 |
Short name | T637 |
Test name | |
Test status | |
Simulation time | 169001332 ps |
CPU time | 2.11 seconds |
Started | Apr 16 02:20:03 PM PDT 24 |
Finished | Apr 16 02:20:06 PM PDT 24 |
Peak memory | 199136 kb |
Host | smart-f7888cad-0865-4dfa-8be8-097db780fc93 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437266670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr _outstanding.3437266670 |
Directory | /workspace/4.hmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3985760964 |
Short name | T727 |
Test name | |
Test status | |
Simulation time | 101569221 ps |
CPU time | 2.1 seconds |
Started | Apr 16 02:19:58 PM PDT 24 |
Finished | Apr 16 02:20:01 PM PDT 24 |
Peak memory | 199320 kb |
Host | smart-433874db-4c05-4a09-a419-8daa27560bae |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985760964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3985760964 |
Directory | /workspace/4.hmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2951559115 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 162946221 ps |
CPU time | 4.08 seconds |
Started | Apr 16 02:19:56 PM PDT 24 |
Finished | Apr 16 02:20:01 PM PDT 24 |
Peak memory | 199220 kb |
Host | smart-12a274e7-4cae-49fd-ac84-82578d026296 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951559115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2951559115 |
Directory | /workspace/4.hmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/40.hmac_intr_test.4211223213 |
Short name | T694 |
Test name | |
Test status | |
Simulation time | 17765764 ps |
CPU time | 0.59 seconds |
Started | Apr 16 02:20:34 PM PDT 24 |
Finished | Apr 16 02:20:36 PM PDT 24 |
Peak memory | 193920 kb |
Host | smart-b536a556-e69b-4c82-bec2-85f9862e0d58 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211223213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.4211223213 |
Directory | /workspace/40.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/41.hmac_intr_test.1219022845 |
Short name | T614 |
Test name | |
Test status | |
Simulation time | 14638878 ps |
CPU time | 0.6 seconds |
Started | Apr 16 02:20:35 PM PDT 24 |
Finished | Apr 16 02:20:37 PM PDT 24 |
Peak memory | 194132 kb |
Host | smart-7baaa2c3-4a99-452f-bc17-4e69a481e427 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219022845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1219022845 |
Directory | /workspace/41.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/42.hmac_intr_test.2328365544 |
Short name | T631 |
Test name | |
Test status | |
Simulation time | 44794900 ps |
CPU time | 0.6 seconds |
Started | Apr 16 02:20:41 PM PDT 24 |
Finished | Apr 16 02:20:43 PM PDT 24 |
Peak memory | 193936 kb |
Host | smart-286b2eeb-66ce-4d7d-a334-0b5b0186b134 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328365544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2328365544 |
Directory | /workspace/42.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/43.hmac_intr_test.555497480 |
Short name | T644 |
Test name | |
Test status | |
Simulation time | 29021864 ps |
CPU time | 0.64 seconds |
Started | Apr 16 02:20:34 PM PDT 24 |
Finished | Apr 16 02:20:36 PM PDT 24 |
Peak memory | 193940 kb |
Host | smart-b1ab6561-2f6c-4252-b5fc-613adf763960 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555497480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.555497480 |
Directory | /workspace/43.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/44.hmac_intr_test.1656849131 |
Short name | T726 |
Test name | |
Test status | |
Simulation time | 34320475 ps |
CPU time | 0.59 seconds |
Started | Apr 16 02:20:41 PM PDT 24 |
Finished | Apr 16 02:20:43 PM PDT 24 |
Peak memory | 193940 kb |
Host | smart-c53e98c4-bb2d-4932-8ca6-9d244bbc0ec3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656849131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.1656849131 |
Directory | /workspace/44.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/45.hmac_intr_test.3857346026 |
Short name | T662 |
Test name | |
Test status | |
Simulation time | 36269901 ps |
CPU time | 0.59 seconds |
Started | Apr 16 02:20:36 PM PDT 24 |
Finished | Apr 16 02:20:38 PM PDT 24 |
Peak memory | 194116 kb |
Host | smart-bf348788-d944-42f2-9a04-b3909a12c5a2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857346026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3857346026 |
Directory | /workspace/45.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/46.hmac_intr_test.341897960 |
Short name | T711 |
Test name | |
Test status | |
Simulation time | 26384043 ps |
CPU time | 0.61 seconds |
Started | Apr 16 02:20:36 PM PDT 24 |
Finished | Apr 16 02:20:37 PM PDT 24 |
Peak memory | 194132 kb |
Host | smart-e13f59f6-0d6b-41bb-a0ec-41a573e98b3a |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341897960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.341897960 |
Directory | /workspace/46.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/47.hmac_intr_test.1683166210 |
Short name | T657 |
Test name | |
Test status | |
Simulation time | 45265687 ps |
CPU time | 0.64 seconds |
Started | Apr 16 02:20:42 PM PDT 24 |
Finished | Apr 16 02:20:44 PM PDT 24 |
Peak memory | 193948 kb |
Host | smart-834c96c8-0e16-4ce6-a511-ec755aeb21bd |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683166210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1683166210 |
Directory | /workspace/47.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/48.hmac_intr_test.197585691 |
Short name | T717 |
Test name | |
Test status | |
Simulation time | 31269900 ps |
CPU time | 0.65 seconds |
Started | Apr 16 02:20:41 PM PDT 24 |
Finished | Apr 16 02:20:42 PM PDT 24 |
Peak memory | 194100 kb |
Host | smart-d84142c7-1b40-466a-b3b7-2575654bd0ba |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197585691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.197585691 |
Directory | /workspace/48.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/49.hmac_intr_test.177447766 |
Short name | T601 |
Test name | |
Test status | |
Simulation time | 14490760 ps |
CPU time | 0.61 seconds |
Started | Apr 16 02:20:46 PM PDT 24 |
Finished | Apr 16 02:20:47 PM PDT 24 |
Peak memory | 193904 kb |
Host | smart-f6217230-ef08-48d6-955d-8ce10a324d8f |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177447766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.177447766 |
Directory | /workspace/49.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.326133737 |
Short name | T635 |
Test name | |
Test status | |
Simulation time | 711816184 ps |
CPU time | 2.29 seconds |
Started | Apr 16 02:20:07 PM PDT 24 |
Finished | Apr 16 02:20:10 PM PDT 24 |
Peak memory | 199280 kb |
Host | smart-25ddf479-e02e-468f-9b78-5c0ee007a89f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326133737 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.326133737 |
Directory | /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2099673232 |
Short name | T725 |
Test name | |
Test status | |
Simulation time | 122907708 ps |
CPU time | 0.85 seconds |
Started | Apr 16 02:20:09 PM PDT 24 |
Finished | Apr 16 02:20:10 PM PDT 24 |
Peak memory | 198108 kb |
Host | smart-c1c95865-d96a-482f-bdb9-3984e66d4900 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099673232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2099673232 |
Directory | /workspace/5.hmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.hmac_intr_test.2120117504 |
Short name | T607 |
Test name | |
Test status | |
Simulation time | 33176879 ps |
CPU time | 0.61 seconds |
Started | Apr 16 02:20:02 PM PDT 24 |
Finished | Apr 16 02:20:04 PM PDT 24 |
Peak memory | 193980 kb |
Host | smart-c2428ea1-0c47-4cf6-b176-861e5e904ec4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120117504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2120117504 |
Directory | /workspace/5.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.4049213160 |
Short name | T629 |
Test name | |
Test status | |
Simulation time | 110473698 ps |
CPU time | 1.63 seconds |
Started | Apr 16 02:20:08 PM PDT 24 |
Finished | Apr 16 02:20:10 PM PDT 24 |
Peak memory | 198836 kb |
Host | smart-53071032-b0a4-4871-8a9b-d34f107b71f1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049213160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr _outstanding.4049213160 |
Directory | /workspace/5.hmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3223140044 |
Short name | T682 |
Test name | |
Test status | |
Simulation time | 232364364 ps |
CPU time | 4.76 seconds |
Started | Apr 16 02:20:03 PM PDT 24 |
Finished | Apr 16 02:20:08 PM PDT 24 |
Peak memory | 199336 kb |
Host | smart-0173b57a-2d4c-4134-afcd-646419393ad1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223140044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3223140044 |
Directory | /workspace/5.hmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3828349224 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 272171118 ps |
CPU time | 4.22 seconds |
Started | Apr 16 02:20:03 PM PDT 24 |
Finished | Apr 16 02:20:08 PM PDT 24 |
Peak memory | 199240 kb |
Host | smart-585f59f7-6331-4765-8b40-90e0bc17e603 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828349224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3828349224 |
Directory | /workspace/5.hmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.645088408 |
Short name | T646 |
Test name | |
Test status | |
Simulation time | 537474868 ps |
CPU time | 2.6 seconds |
Started | Apr 16 02:20:13 PM PDT 24 |
Finished | Apr 16 02:20:16 PM PDT 24 |
Peak memory | 199324 kb |
Host | smart-5d81547d-39a7-4d60-a358-c5dc21b91c1f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645088408 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.645088408 |
Directory | /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3346226562 |
Short name | T698 |
Test name | |
Test status | |
Simulation time | 64178648 ps |
CPU time | 0.93 seconds |
Started | Apr 16 02:20:07 PM PDT 24 |
Finished | Apr 16 02:20:08 PM PDT 24 |
Peak memory | 199020 kb |
Host | smart-16432800-7978-45fe-b1cc-44ad15c26e8f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346226562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3346226562 |
Directory | /workspace/6.hmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.hmac_intr_test.3494793975 |
Short name | T664 |
Test name | |
Test status | |
Simulation time | 19723626 ps |
CPU time | 0.67 seconds |
Started | Apr 16 02:20:06 PM PDT 24 |
Finished | Apr 16 02:20:07 PM PDT 24 |
Peak memory | 193900 kb |
Host | smart-8e8ef408-4e48-44df-b3a8-8685badc5f09 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494793975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3494793975 |
Directory | /workspace/6.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2907661599 |
Short name | T697 |
Test name | |
Test status | |
Simulation time | 81917224 ps |
CPU time | 1.79 seconds |
Started | Apr 16 02:20:12 PM PDT 24 |
Finished | Apr 16 02:20:15 PM PDT 24 |
Peak memory | 199184 kb |
Host | smart-bb1e6a78-e5bd-4ccf-8465-de74ea3bf20b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907661599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr _outstanding.2907661599 |
Directory | /workspace/6.hmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.hmac_tl_errors.840382032 |
Short name | T705 |
Test name | |
Test status | |
Simulation time | 615177850 ps |
CPU time | 3.56 seconds |
Started | Apr 16 02:20:07 PM PDT 24 |
Finished | Apr 16 02:20:12 PM PDT 24 |
Peak memory | 199312 kb |
Host | smart-faec6331-da9e-421a-a875-4d7efe22235f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840382032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.840382032 |
Directory | /workspace/6.hmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.590654759 |
Short name | T679 |
Test name | |
Test status | |
Simulation time | 38755982 ps |
CPU time | 1.14 seconds |
Started | Apr 16 02:20:12 PM PDT 24 |
Finished | Apr 16 02:20:13 PM PDT 24 |
Peak memory | 199224 kb |
Host | smart-43f1ddaa-1f26-466a-82dd-aada0fc1ce2f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590654759 -assert nopostproc +UVM_TESTNAME= hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.590654759 |
Directory | /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2223924358 |
Short name | T650 |
Test name | |
Test status | |
Simulation time | 119975133 ps |
CPU time | 0.94 seconds |
Started | Apr 16 02:20:13 PM PDT 24 |
Finished | Apr 16 02:20:15 PM PDT 24 |
Peak memory | 198344 kb |
Host | smart-6078f052-885b-4112-a2d0-4148619dd38b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223924358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2223924358 |
Directory | /workspace/7.hmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.hmac_intr_test.693255268 |
Short name | T651 |
Test name | |
Test status | |
Simulation time | 17510546 ps |
CPU time | 0.67 seconds |
Started | Apr 16 02:20:14 PM PDT 24 |
Finished | Apr 16 02:20:15 PM PDT 24 |
Peak memory | 193880 kb |
Host | smart-b8bc2891-1f6f-4cc4-b3f0-2bfe07e582ba |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693255268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.693255268 |
Directory | /workspace/7.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.838246260 |
Short name | T656 |
Test name | |
Test status | |
Simulation time | 467532045 ps |
CPU time | 2.44 seconds |
Started | Apr 16 02:20:13 PM PDT 24 |
Finished | Apr 16 02:20:16 PM PDT 24 |
Peak memory | 199176 kb |
Host | smart-5fbcd97b-18ce-4c1d-bfcb-9de795744066 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838246260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_ outstanding.838246260 |
Directory | /workspace/7.hmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3514447837 |
Short name | T603 |
Test name | |
Test status | |
Simulation time | 102626513 ps |
CPU time | 1.51 seconds |
Started | Apr 16 02:20:14 PM PDT 24 |
Finished | Apr 16 02:20:16 PM PDT 24 |
Peak memory | 199288 kb |
Host | smart-93ca20d1-9d82-4a7b-a808-2576e8d0eb74 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514447837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3514447837 |
Directory | /workspace/7.hmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1374453318 |
Short name | T721 |
Test name | |
Test status | |
Simulation time | 188371556 ps |
CPU time | 3.09 seconds |
Started | Apr 16 02:20:13 PM PDT 24 |
Finished | Apr 16 02:20:17 PM PDT 24 |
Peak memory | 199220 kb |
Host | smart-c57f185f-c38c-4ce4-96e8-20b1e89feb9e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374453318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1374453318 |
Directory | /workspace/7.hmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1091604155 |
Short name | T606 |
Test name | |
Test status | |
Simulation time | 249739694 ps |
CPU time | 1.85 seconds |
Started | Apr 16 02:20:18 PM PDT 24 |
Finished | Apr 16 02:20:21 PM PDT 24 |
Peak memory | 199284 kb |
Host | smart-e1d615cb-840b-437a-b013-ddb478f2e519 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091604155 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.1091604155 |
Directory | /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.hmac_csr_rw.4202141360 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 26742306 ps |
CPU time | 0.86 seconds |
Started | Apr 16 02:20:20 PM PDT 24 |
Finished | Apr 16 02:20:22 PM PDT 24 |
Peak memory | 198428 kb |
Host | smart-b26f60eb-4866-4824-9748-18071c03a723 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202141360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.4202141360 |
Directory | /workspace/8.hmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.hmac_intr_test.765752339 |
Short name | T708 |
Test name | |
Test status | |
Simulation time | 11699949 ps |
CPU time | 0.6 seconds |
Started | Apr 16 02:20:12 PM PDT 24 |
Finished | Apr 16 02:20:14 PM PDT 24 |
Peak memory | 193876 kb |
Host | smart-26ce91e6-e79c-4f60-93b3-c844bd0e4c83 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765752339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.765752339 |
Directory | /workspace/8.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1359116477 |
Short name | T641 |
Test name | |
Test status | |
Simulation time | 455728536 ps |
CPU time | 2.38 seconds |
Started | Apr 16 02:20:19 PM PDT 24 |
Finished | Apr 16 02:20:22 PM PDT 24 |
Peak memory | 199220 kb |
Host | smart-e87e3813-b7b7-445e-a613-bdfcbd977b41 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359116477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr _outstanding.1359116477 |
Directory | /workspace/8.hmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3222784106 |
Short name | T654 |
Test name | |
Test status | |
Simulation time | 262965267 ps |
CPU time | 1.78 seconds |
Started | Apr 16 02:20:15 PM PDT 24 |
Finished | Apr 16 02:20:18 PM PDT 24 |
Peak memory | 199292 kb |
Host | smart-962cefa2-4c65-49db-b873-7ad924ef2e73 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222784106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3222784106 |
Directory | /workspace/8.hmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1574010539 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 714617348 ps |
CPU time | 3.03 seconds |
Started | Apr 16 02:20:13 PM PDT 24 |
Finished | Apr 16 02:20:17 PM PDT 24 |
Peak memory | 199224 kb |
Host | smart-aac62650-45fa-4cd6-926e-eccf8954bfe0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574010539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1574010539 |
Directory | /workspace/8.hmac_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1768885526 |
Short name | T689 |
Test name | |
Test status | |
Simulation time | 85904615 ps |
CPU time | 2.85 seconds |
Started | Apr 16 02:20:28 PM PDT 24 |
Finished | Apr 16 02:20:32 PM PDT 24 |
Peak memory | 199284 kb |
Host | smart-14912caf-0828-4aa5-bdba-c45ee369611e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768885526 -assert nopostproc +UVM_TESTNAME =hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1768885526 |
Directory | /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1013372304 |
Short name | T723 |
Test name | |
Test status | |
Simulation time | 25378179 ps |
CPU time | 0.88 seconds |
Started | Apr 16 02:20:30 PM PDT 24 |
Finished | Apr 16 02:20:31 PM PDT 24 |
Peak memory | 198588 kb |
Host | smart-49f32df1-6569-406c-8b2a-7584c7bc8d5a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013372304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1013372304 |
Directory | /workspace/9.hmac_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.hmac_intr_test.3880261962 |
Short name | T718 |
Test name | |
Test status | |
Simulation time | 15161539 ps |
CPU time | 0.61 seconds |
Started | Apr 16 02:20:18 PM PDT 24 |
Finished | Apr 16 02:20:19 PM PDT 24 |
Peak memory | 193936 kb |
Host | smart-35d79c90-14b5-49c9-97af-70a2c0abaff0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880261962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3880261962 |
Directory | /workspace/9.hmac_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3195204700 |
Short name | T701 |
Test name | |
Test status | |
Simulation time | 115233001 ps |
CPU time | 2.37 seconds |
Started | Apr 16 02:20:24 PM PDT 24 |
Finished | Apr 16 02:20:27 PM PDT 24 |
Peak memory | 198560 kb |
Host | smart-c23873d3-5ebe-4714-b484-4bda552469b1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195204700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr _outstanding.3195204700 |
Directory | /workspace/9.hmac_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3995362871 |
Short name | T663 |
Test name | |
Test status | |
Simulation time | 32384493 ps |
CPU time | 1.6 seconds |
Started | Apr 16 02:20:20 PM PDT 24 |
Finished | Apr 16 02:20:22 PM PDT 24 |
Peak memory | 199252 kb |
Host | smart-d43c4ffc-5a38-4ffd-9e6f-bf4bf5f36782 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995362871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.3995362871 |
Directory | /workspace/9.hmac_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.407442259 |
Short name | T734 |
Test name | |
Test status | |
Simulation time | 187975858 ps |
CPU time | 3.28 seconds |
Started | Apr 16 02:20:20 PM PDT 24 |
Finished | Apr 16 02:20:23 PM PDT 24 |
Peak memory | 199224 kb |
Host | smart-15669762-f221-45db-aeba-2b0f145f045d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407442259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.407442259 |
Directory | /workspace/9.hmac_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.hmac_alert_test.1721995693 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 39077759 ps |
CPU time | 0.64 seconds |
Started | Apr 16 02:03:29 PM PDT 24 |
Finished | Apr 16 02:03:32 PM PDT 24 |
Peak memory | 195164 kb |
Host | smart-758a892f-7e8b-481b-b463-745b54d70dc9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721995693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1721995693 |
Directory | /workspace/0.hmac_alert_test/latest |
Test location | /workspace/coverage/default/0.hmac_back_pressure.2937149360 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 2047922832 ps |
CPU time | 35.69 seconds |
Started | Apr 16 02:03:31 PM PDT 24 |
Finished | Apr 16 02:04:09 PM PDT 24 |
Peak memory | 207740 kb |
Host | smart-6aee3013-1a07-413f-bf4a-5e787ce1dd3e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2937149360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2937149360 |
Directory | /workspace/0.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/0.hmac_burst_wr.121024758 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 11023698495 ps |
CPU time | 24.45 seconds |
Started | Apr 16 02:03:25 PM PDT 24 |
Finished | Apr 16 02:03:50 PM PDT 24 |
Peak memory | 199676 kb |
Host | smart-6c40ee1a-925a-4f9a-97c8-fb501a887fe6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=121024758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.121024758 |
Directory | /workspace/0.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/0.hmac_datapath_stress.3384483646 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 2048314531 ps |
CPU time | 117.52 seconds |
Started | Apr 16 02:03:17 PM PDT 24 |
Finished | Apr 16 02:05:16 PM PDT 24 |
Peak memory | 199616 kb |
Host | smart-e8c1dfdd-0096-4693-aa32-b08aa9c24ada |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3384483646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3384483646 |
Directory | /workspace/0.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/0.hmac_error.2375599293 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 21749839291 ps |
CPU time | 153.22 seconds |
Started | Apr 16 02:03:29 PM PDT 24 |
Finished | Apr 16 02:06:05 PM PDT 24 |
Peak memory | 199748 kb |
Host | smart-d712fa29-fff7-458f-9440-acd995fb2e28 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375599293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2375599293 |
Directory | /workspace/0.hmac_error/latest |
Test location | /workspace/coverage/default/0.hmac_long_msg.3683733830 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 23894041422 ps |
CPU time | 121.99 seconds |
Started | Apr 16 02:03:35 PM PDT 24 |
Finished | Apr 16 02:05:39 PM PDT 24 |
Peak memory | 199740 kb |
Host | smart-d6a600f0-57b7-413f-a776-811d8054d234 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3683733830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3683733830 |
Directory | /workspace/0.hmac_long_msg/latest |
Test location | /workspace/coverage/default/0.hmac_sec_cm.1225758057 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 34032348 ps |
CPU time | 0.77 seconds |
Started | Apr 16 02:03:20 PM PDT 24 |
Finished | Apr 16 02:03:22 PM PDT 24 |
Peak memory | 218168 kb |
Host | smart-492e4f5a-b678-4684-8cf6-7acd27824816 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225758057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1225758057 |
Directory | /workspace/0.hmac_sec_cm/latest |
Test location | /workspace/coverage/default/0.hmac_smoke.1500219033 |
Short name | T589 |
Test name | |
Test status | |
Simulation time | 2335628447 ps |
CPU time | 1.82 seconds |
Started | Apr 16 02:03:39 PM PDT 24 |
Finished | Apr 16 02:03:42 PM PDT 24 |
Peak memory | 199724 kb |
Host | smart-7a5dcf83-2476-431f-adb0-0a912589dec0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1500219033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1500219033 |
Directory | /workspace/0.hmac_smoke/latest |
Test location | /workspace/coverage/default/0.hmac_test_hmac_vectors.3754308920 |
Short name | T553 |
Test name | |
Test status | |
Simulation time | 156867722 ps |
CPU time | 1.06 seconds |
Started | Apr 16 02:03:27 PM PDT 24 |
Finished | Apr 16 02:03:30 PM PDT 24 |
Peak memory | 198716 kb |
Host | smart-929f54ea-fc96-40e4-80e2-7a914b4dbf09 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754308920 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.hmac_test_hmac_vectors.3754308920 |
Directory | /workspace/0.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/0.hmac_test_sha_vectors.4231803206 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 47154448117 ps |
CPU time | 461.54 seconds |
Started | Apr 16 02:03:23 PM PDT 24 |
Finished | Apr 16 02:11:06 PM PDT 24 |
Peak memory | 199708 kb |
Host | smart-dc69561b-7d7a-4995-9c6a-baa0d6439d14 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231803206 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.4231803206 |
Directory | /workspace/0.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/0.hmac_wipe_secret.3399857076 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 3590487400 ps |
CPU time | 17.85 seconds |
Started | Apr 16 02:03:27 PM PDT 24 |
Finished | Apr 16 02:03:46 PM PDT 24 |
Peak memory | 199744 kb |
Host | smart-886879fd-bb3a-4eb9-92cc-cca92ad73382 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3399857076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3399857076 |
Directory | /workspace/0.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/1.hmac_alert_test.3320554592 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 91409429 ps |
CPU time | 0.57 seconds |
Started | Apr 16 02:03:28 PM PDT 24 |
Finished | Apr 16 02:03:31 PM PDT 24 |
Peak memory | 195264 kb |
Host | smart-10f99d15-615c-4da1-9773-dc7cf543cf4c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320554592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3320554592 |
Directory | /workspace/1.hmac_alert_test/latest |
Test location | /workspace/coverage/default/1.hmac_back_pressure.674339889 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 1219310740 ps |
CPU time | 43.21 seconds |
Started | Apr 16 02:03:29 PM PDT 24 |
Finished | Apr 16 02:04:15 PM PDT 24 |
Peak memory | 207828 kb |
Host | smart-dbdb72d5-d419-417c-8aa8-69f1f0e44788 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=674339889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.674339889 |
Directory | /workspace/1.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/1.hmac_burst_wr.3097981947 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 583386226 ps |
CPU time | 15.28 seconds |
Started | Apr 16 02:03:20 PM PDT 24 |
Finished | Apr 16 02:03:36 PM PDT 24 |
Peak memory | 199564 kb |
Host | smart-79138d3e-e930-4907-8a11-045aa0df80b3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3097981947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3097981947 |
Directory | /workspace/1.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/1.hmac_datapath_stress.2297068342 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 7199901763 ps |
CPU time | 159.13 seconds |
Started | Apr 16 02:03:29 PM PDT 24 |
Finished | Apr 16 02:06:11 PM PDT 24 |
Peak memory | 199728 kb |
Host | smart-3d0f619d-20ed-4e0a-abc8-96cf1ea55e4b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2297068342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2297068342 |
Directory | /workspace/1.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/1.hmac_error.1402892541 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 4232125964 ps |
CPU time | 13.45 seconds |
Started | Apr 16 02:03:27 PM PDT 24 |
Finished | Apr 16 02:03:42 PM PDT 24 |
Peak memory | 199724 kb |
Host | smart-ebc416e9-b671-4e77-a4af-6ffd05e578e4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402892541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1402892541 |
Directory | /workspace/1.hmac_error/latest |
Test location | /workspace/coverage/default/1.hmac_long_msg.3375432242 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 5897051334 ps |
CPU time | 90.11 seconds |
Started | Apr 16 02:03:33 PM PDT 24 |
Finished | Apr 16 02:05:05 PM PDT 24 |
Peak memory | 199712 kb |
Host | smart-68eee21e-87ea-42b2-ae01-048f27ad0e50 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3375432242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3375432242 |
Directory | /workspace/1.hmac_long_msg/latest |
Test location | /workspace/coverage/default/1.hmac_sec_cm.4101773286 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 121777572 ps |
CPU time | 0.78 seconds |
Started | Apr 16 02:03:26 PM PDT 24 |
Finished | Apr 16 02:03:27 PM PDT 24 |
Peak memory | 218184 kb |
Host | smart-cb5c7aea-5b29-4327-9d4b-d810b70ad471 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101773286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.4101773286 |
Directory | /workspace/1.hmac_sec_cm/latest |
Test location | /workspace/coverage/default/1.hmac_smoke.3908831935 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 174082930 ps |
CPU time | 5.26 seconds |
Started | Apr 16 02:03:27 PM PDT 24 |
Finished | Apr 16 02:03:35 PM PDT 24 |
Peak memory | 199524 kb |
Host | smart-787d51eb-8ed1-4c30-9d72-94506487d1ea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3908831935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3908831935 |
Directory | /workspace/1.hmac_smoke/latest |
Test location | /workspace/coverage/default/1.hmac_stress_all.2345965259 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 16184603358 ps |
CPU time | 235.21 seconds |
Started | Apr 16 02:03:34 PM PDT 24 |
Finished | Apr 16 02:07:31 PM PDT 24 |
Peak memory | 199724 kb |
Host | smart-d77bb041-c1be-4ed6-b831-3b027dd9481c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345965259 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2345965259 |
Directory | /workspace/1.hmac_stress_all/latest |
Test location | /workspace/coverage/default/1.hmac_test_hmac_vectors.2693457579 |
Short name | T594 |
Test name | |
Test status | |
Simulation time | 33502242 ps |
CPU time | 1.21 seconds |
Started | Apr 16 02:03:32 PM PDT 24 |
Finished | Apr 16 02:03:35 PM PDT 24 |
Peak memory | 199272 kb |
Host | smart-6ab9f61e-afa8-4900-b952-6dd0c61f5d51 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693457579 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.hmac_test_hmac_vectors.2693457579 |
Directory | /workspace/1.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/1.hmac_test_sha_vectors.2161286779 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 8366111891 ps |
CPU time | 431.81 seconds |
Started | Apr 16 02:03:23 PM PDT 24 |
Finished | Apr 16 02:10:36 PM PDT 24 |
Peak memory | 199680 kb |
Host | smart-a4a4a81e-6237-440f-8853-ffd1cbc34e9c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161286779 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.2161286779 |
Directory | /workspace/1.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/1.hmac_wipe_secret.3998175290 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 1501449917 ps |
CPU time | 54.31 seconds |
Started | Apr 16 02:03:29 PM PDT 24 |
Finished | Apr 16 02:04:25 PM PDT 24 |
Peak memory | 199504 kb |
Host | smart-db1ffbdd-b699-4b92-95a2-245a7181d9b5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3998175290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3998175290 |
Directory | /workspace/1.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/10.hmac_alert_test.2777843406 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 52694137 ps |
CPU time | 0.57 seconds |
Started | Apr 16 02:03:48 PM PDT 24 |
Finished | Apr 16 02:03:50 PM PDT 24 |
Peak memory | 195252 kb |
Host | smart-5da02e49-009f-4c2a-bf71-99d22978dfcc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777843406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2777843406 |
Directory | /workspace/10.hmac_alert_test/latest |
Test location | /workspace/coverage/default/10.hmac_back_pressure.910305394 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 74383970 ps |
CPU time | 2.64 seconds |
Started | Apr 16 02:03:42 PM PDT 24 |
Finished | Apr 16 02:03:46 PM PDT 24 |
Peak memory | 199552 kb |
Host | smart-5d5aaa3b-92fc-4561-8b3f-035e4f56d322 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=910305394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.910305394 |
Directory | /workspace/10.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/10.hmac_burst_wr.2501801742 |
Short name | T531 |
Test name | |
Test status | |
Simulation time | 385630152 ps |
CPU time | 8.24 seconds |
Started | Apr 16 02:03:48 PM PDT 24 |
Finished | Apr 16 02:03:57 PM PDT 24 |
Peak memory | 199576 kb |
Host | smart-305258a3-15c2-479f-a48a-c9945ab97f2d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2501801742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2501801742 |
Directory | /workspace/10.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/10.hmac_datapath_stress.620076862 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 54135712 ps |
CPU time | 0.66 seconds |
Started | Apr 16 02:03:46 PM PDT 24 |
Finished | Apr 16 02:03:48 PM PDT 24 |
Peak memory | 196876 kb |
Host | smart-1370fc8f-514d-4285-a250-db6277bedf36 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=620076862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.620076862 |
Directory | /workspace/10.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/10.hmac_error.970748754 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 19148210133 ps |
CPU time | 47.66 seconds |
Started | Apr 16 02:03:47 PM PDT 24 |
Finished | Apr 16 02:04:36 PM PDT 24 |
Peak memory | 199696 kb |
Host | smart-37c87f25-9395-4f3e-bcbc-dd409e807945 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970748754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.970748754 |
Directory | /workspace/10.hmac_error/latest |
Test location | /workspace/coverage/default/10.hmac_long_msg.2915740665 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 5183066889 ps |
CPU time | 100.7 seconds |
Started | Apr 16 02:03:43 PM PDT 24 |
Finished | Apr 16 02:05:24 PM PDT 24 |
Peak memory | 199720 kb |
Host | smart-bbc5539d-b0a5-4b63-8ac1-2385020b574c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2915740665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2915740665 |
Directory | /workspace/10.hmac_long_msg/latest |
Test location | /workspace/coverage/default/10.hmac_smoke.2900526820 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 329337823 ps |
CPU time | 4.85 seconds |
Started | Apr 16 02:03:42 PM PDT 24 |
Finished | Apr 16 02:03:48 PM PDT 24 |
Peak memory | 199580 kb |
Host | smart-7fdafdc4-8c80-4914-ab91-4819a4df29e2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2900526820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.2900526820 |
Directory | /workspace/10.hmac_smoke/latest |
Test location | /workspace/coverage/default/10.hmac_stress_all.4064228431 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 13740534384 ps |
CPU time | 753.93 seconds |
Started | Apr 16 02:03:49 PM PDT 24 |
Finished | Apr 16 02:16:24 PM PDT 24 |
Peak memory | 199724 kb |
Host | smart-cf20c6db-414b-4298-833d-a0c2a92e9d2c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064228431 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.4064228431 |
Directory | /workspace/10.hmac_stress_all/latest |
Test location | /workspace/coverage/default/10.hmac_test_hmac_vectors.655836498 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 217143178 ps |
CPU time | 1.27 seconds |
Started | Apr 16 02:03:46 PM PDT 24 |
Finished | Apr 16 02:03:48 PM PDT 24 |
Peak memory | 199588 kb |
Host | smart-5596379d-4655-46c8-b3ca-a5384dfd88db |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655836498 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 10.hmac_test_hmac_vectors.655836498 |
Directory | /workspace/10.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/10.hmac_test_sha_vectors.2143872923 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 97932836665 ps |
CPU time | 444.2 seconds |
Started | Apr 16 02:03:47 PM PDT 24 |
Finished | Apr 16 02:11:12 PM PDT 24 |
Peak memory | 199668 kb |
Host | smart-74276384-6f9d-4155-89f0-5de0fc39328f |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143872923 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.2143872923 |
Directory | /workspace/10.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/10.hmac_wipe_secret.1217738976 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 1980092896 ps |
CPU time | 18.62 seconds |
Started | Apr 16 02:03:46 PM PDT 24 |
Finished | Apr 16 02:04:05 PM PDT 24 |
Peak memory | 199596 kb |
Host | smart-b8b72d6d-f739-4579-85c9-311e2fa1f8f8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1217738976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1217738976 |
Directory | /workspace/10.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/11.hmac_alert_test.766357080 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 16930534 ps |
CPU time | 0.59 seconds |
Started | Apr 16 02:03:56 PM PDT 24 |
Finished | Apr 16 02:03:57 PM PDT 24 |
Peak memory | 194060 kb |
Host | smart-f64a2651-980d-46c6-910f-70d87f794972 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766357080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.766357080 |
Directory | /workspace/11.hmac_alert_test/latest |
Test location | /workspace/coverage/default/11.hmac_back_pressure.2816496810 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 1663790159 ps |
CPU time | 29.03 seconds |
Started | Apr 16 02:03:48 PM PDT 24 |
Finished | Apr 16 02:04:18 PM PDT 24 |
Peak memory | 207796 kb |
Host | smart-b2908932-c885-4491-80a1-3911a52562c5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2816496810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2816496810 |
Directory | /workspace/11.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/11.hmac_burst_wr.1262971174 |
Short name | T548 |
Test name | |
Test status | |
Simulation time | 975889984 ps |
CPU time | 16.03 seconds |
Started | Apr 16 02:03:52 PM PDT 24 |
Finished | Apr 16 02:04:09 PM PDT 24 |
Peak memory | 199604 kb |
Host | smart-6a766e97-7bc0-4514-a678-2e98d802278b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1262971174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1262971174 |
Directory | /workspace/11.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/11.hmac_datapath_stress.1631044819 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 8712336541 ps |
CPU time | 128.6 seconds |
Started | Apr 16 02:03:48 PM PDT 24 |
Finished | Apr 16 02:05:58 PM PDT 24 |
Peak memory | 199684 kb |
Host | smart-06434655-f7db-4a17-8d0d-0795be840afc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1631044819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1631044819 |
Directory | /workspace/11.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/11.hmac_error.136849712 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 4452282890 ps |
CPU time | 121.4 seconds |
Started | Apr 16 02:03:54 PM PDT 24 |
Finished | Apr 16 02:05:56 PM PDT 24 |
Peak memory | 199716 kb |
Host | smart-b716a9ec-1fa8-4f67-80e0-f895a9ad19c1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136849712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.136849712 |
Directory | /workspace/11.hmac_error/latest |
Test location | /workspace/coverage/default/11.hmac_long_msg.2555231617 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 474568450 ps |
CPU time | 18.67 seconds |
Started | Apr 16 02:03:52 PM PDT 24 |
Finished | Apr 16 02:04:11 PM PDT 24 |
Peak memory | 199608 kb |
Host | smart-348067a4-b18b-4b1e-a74c-a11919172acd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2555231617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2555231617 |
Directory | /workspace/11.hmac_long_msg/latest |
Test location | /workspace/coverage/default/11.hmac_smoke.514721509 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 2432122730 ps |
CPU time | 5.91 seconds |
Started | Apr 16 02:03:47 PM PDT 24 |
Finished | Apr 16 02:03:54 PM PDT 24 |
Peak memory | 199736 kb |
Host | smart-3d12ed95-aa6e-4851-8711-250c104d1cfa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=514721509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.514721509 |
Directory | /workspace/11.hmac_smoke/latest |
Test location | /workspace/coverage/default/11.hmac_stress_all.3543537546 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 594305581101 ps |
CPU time | 2477.39 seconds |
Started | Apr 16 02:03:58 PM PDT 24 |
Finished | Apr 16 02:45:17 PM PDT 24 |
Peak memory | 212688 kb |
Host | smart-5a635a23-f9fa-4d45-87c8-ab20405060bc |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543537546 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3543537546 |
Directory | /workspace/11.hmac_stress_all/latest |
Test location | /workspace/coverage/default/11.hmac_stress_all_with_rand_reset.2710667880 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 48948770646 ps |
CPU time | 227.59 seconds |
Started | Apr 16 02:03:52 PM PDT 24 |
Finished | Apr 16 02:07:41 PM PDT 24 |
Peak memory | 213196 kb |
Host | smart-794fe14e-0656-49fe-af58-402b129b94ec |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2710667880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all_with_rand_reset.2710667880 |
Directory | /workspace/11.hmac_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/11.hmac_test_hmac_vectors.3939470386 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 151209151 ps |
CPU time | 1.23 seconds |
Started | Apr 16 02:03:50 PM PDT 24 |
Finished | Apr 16 02:03:52 PM PDT 24 |
Peak memory | 199564 kb |
Host | smart-ab3e7e1c-a01a-4d6f-9271-359380998b92 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939470386 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 11.hmac_test_hmac_vectors.3939470386 |
Directory | /workspace/11.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/11.hmac_test_sha_vectors.2203064785 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 69061466727 ps |
CPU time | 463.32 seconds |
Started | Apr 16 02:03:51 PM PDT 24 |
Finished | Apr 16 02:11:36 PM PDT 24 |
Peak memory | 199704 kb |
Host | smart-1596fad8-eeda-41a9-bfbc-37e60cee3548 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203064785 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.2203064785 |
Directory | /workspace/11.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/11.hmac_wipe_secret.494198498 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 7913086301 ps |
CPU time | 65.05 seconds |
Started | Apr 16 02:03:50 PM PDT 24 |
Finished | Apr 16 02:04:56 PM PDT 24 |
Peak memory | 199708 kb |
Host | smart-4287005e-e388-44e4-8b69-27ef7c9e4a45 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=494198498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.494198498 |
Directory | /workspace/11.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/12.hmac_alert_test.2209752206 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 18029396 ps |
CPU time | 0.59 seconds |
Started | Apr 16 02:03:51 PM PDT 24 |
Finished | Apr 16 02:03:53 PM PDT 24 |
Peak memory | 195200 kb |
Host | smart-33ab2c88-8af8-455a-be56-6b5864a02ed6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209752206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2209752206 |
Directory | /workspace/12.hmac_alert_test/latest |
Test location | /workspace/coverage/default/12.hmac_back_pressure.97374170 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 906726609 ps |
CPU time | 39.4 seconds |
Started | Apr 16 02:03:51 PM PDT 24 |
Finished | Apr 16 02:04:32 PM PDT 24 |
Peak memory | 225076 kb |
Host | smart-bce2a22a-ef9b-48bd-87a9-09d55840448d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=97374170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.97374170 |
Directory | /workspace/12.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/12.hmac_burst_wr.109906965 |
Short name | T539 |
Test name | |
Test status | |
Simulation time | 939719437 ps |
CPU time | 43.92 seconds |
Started | Apr 16 02:03:55 PM PDT 24 |
Finished | Apr 16 02:04:40 PM PDT 24 |
Peak memory | 199524 kb |
Host | smart-260eb63e-41fb-4d27-8a05-5be6d44cfb7f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=109906965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.109906965 |
Directory | /workspace/12.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/12.hmac_datapath_stress.1561071661 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 333996715 ps |
CPU time | 19.89 seconds |
Started | Apr 16 02:03:53 PM PDT 24 |
Finished | Apr 16 02:04:14 PM PDT 24 |
Peak memory | 199604 kb |
Host | smart-26ee1fc8-4f87-43fd-9bc6-d76f217909e4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1561071661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1561071661 |
Directory | /workspace/12.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/12.hmac_error.3928876442 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 1566829102 ps |
CPU time | 41.34 seconds |
Started | Apr 16 02:03:51 PM PDT 24 |
Finished | Apr 16 02:04:34 PM PDT 24 |
Peak memory | 199604 kb |
Host | smart-0bb8bdc5-d7bb-4414-814b-d21dc603b782 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928876442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3928876442 |
Directory | /workspace/12.hmac_error/latest |
Test location | /workspace/coverage/default/12.hmac_long_msg.2560855736 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 5042986855 ps |
CPU time | 76.29 seconds |
Started | Apr 16 02:03:56 PM PDT 24 |
Finished | Apr 16 02:05:13 PM PDT 24 |
Peak memory | 199736 kb |
Host | smart-ada2dffa-649e-4ada-844d-de5545555810 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2560855736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2560855736 |
Directory | /workspace/12.hmac_long_msg/latest |
Test location | /workspace/coverage/default/12.hmac_smoke.4105313112 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 2267339520 ps |
CPU time | 6.58 seconds |
Started | Apr 16 02:03:55 PM PDT 24 |
Finished | Apr 16 02:04:03 PM PDT 24 |
Peak memory | 199608 kb |
Host | smart-78c4d0cb-f5dd-4597-b307-ec57a5c9deff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4105313112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.4105313112 |
Directory | /workspace/12.hmac_smoke/latest |
Test location | /workspace/coverage/default/12.hmac_stress_all.1485652973 |
Short name | T522 |
Test name | |
Test status | |
Simulation time | 18170387741 ps |
CPU time | 967.48 seconds |
Started | Apr 16 02:03:55 PM PDT 24 |
Finished | Apr 16 02:20:04 PM PDT 24 |
Peak memory | 229864 kb |
Host | smart-2fb1c406-b726-4ca7-b421-c2ad38a8181e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485652973 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1485652973 |
Directory | /workspace/12.hmac_stress_all/latest |
Test location | /workspace/coverage/default/12.hmac_test_hmac_vectors.938635070 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 145924560 ps |
CPU time | 1.38 seconds |
Started | Apr 16 02:03:58 PM PDT 24 |
Finished | Apr 16 02:04:00 PM PDT 24 |
Peak memory | 199616 kb |
Host | smart-15c24213-461d-4087-82f1-bde05b4359ae |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938635070 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 12.hmac_test_hmac_vectors.938635070 |
Directory | /workspace/12.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/12.hmac_test_sha_vectors.836520247 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 34684910362 ps |
CPU time | 478.72 seconds |
Started | Apr 16 02:03:53 PM PDT 24 |
Finished | Apr 16 02:11:53 PM PDT 24 |
Peak memory | 199712 kb |
Host | smart-7f6964d4-d45b-49e1-8f10-976aad98dd60 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836520247 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.836520247 |
Directory | /workspace/12.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/12.hmac_wipe_secret.182599955 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 14904105790 ps |
CPU time | 94.81 seconds |
Started | Apr 16 02:03:54 PM PDT 24 |
Finished | Apr 16 02:05:29 PM PDT 24 |
Peak memory | 199752 kb |
Host | smart-d5481369-15e8-49ce-847a-f949ed21ecf8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=182599955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.182599955 |
Directory | /workspace/12.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/129.hmac_stress_all_with_rand_reset.606370724 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 116370326127 ps |
CPU time | 1251.37 seconds |
Started | Apr 16 02:05:48 PM PDT 24 |
Finished | Apr 16 02:26:40 PM PDT 24 |
Peak memory | 257156 kb |
Host | smart-01b66e9f-f8fc-4f44-b53e-e5ee28bb0b4d |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=606370724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.hmac_stress_all_with_rand_reset.606370724 |
Directory | /workspace/129.hmac_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/13.hmac_alert_test.1614963306 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 41659381 ps |
CPU time | 0.55 seconds |
Started | Apr 16 02:03:58 PM PDT 24 |
Finished | Apr 16 02:04:00 PM PDT 24 |
Peak memory | 195084 kb |
Host | smart-1edff2bb-e170-472d-a197-a676f3e9304a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614963306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1614963306 |
Directory | /workspace/13.hmac_alert_test/latest |
Test location | /workspace/coverage/default/13.hmac_back_pressure.1848001089 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 6963314172 ps |
CPU time | 77.37 seconds |
Started | Apr 16 02:03:58 PM PDT 24 |
Finished | Apr 16 02:05:17 PM PDT 24 |
Peak memory | 232064 kb |
Host | smart-a3bc691a-f6aa-4898-a5fe-c5f99d2ff6c6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1848001089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1848001089 |
Directory | /workspace/13.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/13.hmac_burst_wr.4268690962 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 3638277896 ps |
CPU time | 14.71 seconds |
Started | Apr 16 02:03:56 PM PDT 24 |
Finished | Apr 16 02:04:11 PM PDT 24 |
Peak memory | 199696 kb |
Host | smart-99253997-3c96-4e80-8253-3b3fde6b3e31 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4268690962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.4268690962 |
Directory | /workspace/13.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/13.hmac_datapath_stress.4063193034 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 8913114459 ps |
CPU time | 134.36 seconds |
Started | Apr 16 02:04:01 PM PDT 24 |
Finished | Apr 16 02:06:16 PM PDT 24 |
Peak memory | 199684 kb |
Host | smart-e056d375-0f8e-494f-b606-249b3bcdbec4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4063193034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.4063193034 |
Directory | /workspace/13.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/13.hmac_error.2871200766 |
Short name | T512 |
Test name | |
Test status | |
Simulation time | 1936716604 ps |
CPU time | 110.59 seconds |
Started | Apr 16 02:03:58 PM PDT 24 |
Finished | Apr 16 02:05:49 PM PDT 24 |
Peak memory | 199616 kb |
Host | smart-0b411698-0030-4905-a7d1-0874f89137df |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871200766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2871200766 |
Directory | /workspace/13.hmac_error/latest |
Test location | /workspace/coverage/default/13.hmac_long_msg.1592570900 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 6219361006 ps |
CPU time | 60.28 seconds |
Started | Apr 16 02:03:54 PM PDT 24 |
Finished | Apr 16 02:04:55 PM PDT 24 |
Peak memory | 199716 kb |
Host | smart-b53df201-c9ae-4e50-8a4c-11987c4c172e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1592570900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1592570900 |
Directory | /workspace/13.hmac_long_msg/latest |
Test location | /workspace/coverage/default/13.hmac_smoke.3849140765 |
Short name | T552 |
Test name | |
Test status | |
Simulation time | 241947239 ps |
CPU time | 1.71 seconds |
Started | Apr 16 02:03:52 PM PDT 24 |
Finished | Apr 16 02:03:55 PM PDT 24 |
Peak memory | 199548 kb |
Host | smart-858a3a6b-e61d-4fd5-a965-f3c5e22d2d8f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3849140765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3849140765 |
Directory | /workspace/13.hmac_smoke/latest |
Test location | /workspace/coverage/default/13.hmac_stress_all.58128422 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 200601091221 ps |
CPU time | 2473.94 seconds |
Started | Apr 16 02:03:58 PM PDT 24 |
Finished | Apr 16 02:45:13 PM PDT 24 |
Peak memory | 199672 kb |
Host | smart-7886a39d-4993-4a65-a654-9e8a7a4d2f3a |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58128422 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.58128422 |
Directory | /workspace/13.hmac_stress_all/latest |
Test location | /workspace/coverage/default/13.hmac_test_hmac_vectors.2880777575 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 133331634 ps |
CPU time | 1.32 seconds |
Started | Apr 16 02:03:58 PM PDT 24 |
Finished | Apr 16 02:04:00 PM PDT 24 |
Peak memory | 199628 kb |
Host | smart-8b776457-44b9-4009-95e1-f2eedf24f6d5 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880777575 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 13.hmac_test_hmac_vectors.2880777575 |
Directory | /workspace/13.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/13.hmac_test_sha_vectors.1199656299 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 37939866040 ps |
CPU time | 481.77 seconds |
Started | Apr 16 02:03:58 PM PDT 24 |
Finished | Apr 16 02:12:00 PM PDT 24 |
Peak memory | 199696 kb |
Host | smart-8426f26c-8319-4767-b874-560071ccaa9b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199656299 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.1199656299 |
Directory | /workspace/13.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/13.hmac_wipe_secret.3010837922 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 1870701240 ps |
CPU time | 80.07 seconds |
Started | Apr 16 02:04:03 PM PDT 24 |
Finished | Apr 16 02:05:25 PM PDT 24 |
Peak memory | 199608 kb |
Host | smart-0571e74b-bab3-4f91-b617-9d61e15e4a2d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3010837922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3010837922 |
Directory | /workspace/13.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/14.hmac_alert_test.2464496799 |
Short name | T560 |
Test name | |
Test status | |
Simulation time | 13019887 ps |
CPU time | 0.57 seconds |
Started | Apr 16 02:03:58 PM PDT 24 |
Finished | Apr 16 02:04:00 PM PDT 24 |
Peak memory | 195196 kb |
Host | smart-87a7981d-7eff-4485-9a9b-2d5bd846c96f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464496799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2464496799 |
Directory | /workspace/14.hmac_alert_test/latest |
Test location | /workspace/coverage/default/14.hmac_back_pressure.2123576548 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 3391854990 ps |
CPU time | 27.67 seconds |
Started | Apr 16 02:03:57 PM PDT 24 |
Finished | Apr 16 02:04:26 PM PDT 24 |
Peak memory | 216088 kb |
Host | smart-a15d1958-6d03-4842-bc76-d1451361dc7c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2123576548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2123576548 |
Directory | /workspace/14.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/14.hmac_burst_wr.3819986092 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 734145535 ps |
CPU time | 37.43 seconds |
Started | Apr 16 02:03:57 PM PDT 24 |
Finished | Apr 16 02:04:35 PM PDT 24 |
Peak memory | 199616 kb |
Host | smart-6f32ffa3-75e2-415c-8cd5-2a5043a4346e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3819986092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3819986092 |
Directory | /workspace/14.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/14.hmac_datapath_stress.4146665882 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 2466869161 ps |
CPU time | 73.98 seconds |
Started | Apr 16 02:03:58 PM PDT 24 |
Finished | Apr 16 02:05:13 PM PDT 24 |
Peak memory | 199728 kb |
Host | smart-b407369b-71de-462d-abf5-456ef2e15090 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4146665882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.4146665882 |
Directory | /workspace/14.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/14.hmac_error.633520549 |
Short name | T571 |
Test name | |
Test status | |
Simulation time | 2127716783 ps |
CPU time | 28 seconds |
Started | Apr 16 02:03:59 PM PDT 24 |
Finished | Apr 16 02:04:28 PM PDT 24 |
Peak memory | 199632 kb |
Host | smart-951469a5-da36-441e-a9ce-16337ac0ef11 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633520549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.633520549 |
Directory | /workspace/14.hmac_error/latest |
Test location | /workspace/coverage/default/14.hmac_long_msg.1711874257 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 5924000884 ps |
CPU time | 116.68 seconds |
Started | Apr 16 02:03:59 PM PDT 24 |
Finished | Apr 16 02:05:56 PM PDT 24 |
Peak memory | 199668 kb |
Host | smart-0c4a9c0d-11db-4363-845e-d550871d2da7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1711874257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1711874257 |
Directory | /workspace/14.hmac_long_msg/latest |
Test location | /workspace/coverage/default/14.hmac_smoke.3050326966 |
Short name | T527 |
Test name | |
Test status | |
Simulation time | 3855335167 ps |
CPU time | 2.98 seconds |
Started | Apr 16 02:03:57 PM PDT 24 |
Finished | Apr 16 02:04:00 PM PDT 24 |
Peak memory | 199708 kb |
Host | smart-60f3dc52-4fa3-4fb4-9e69-d5c98ac839a7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3050326966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3050326966 |
Directory | /workspace/14.hmac_smoke/latest |
Test location | /workspace/coverage/default/14.hmac_stress_all.2024555471 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 2900005328 ps |
CPU time | 41.6 seconds |
Started | Apr 16 02:03:57 PM PDT 24 |
Finished | Apr 16 02:04:39 PM PDT 24 |
Peak memory | 199728 kb |
Host | smart-28681750-c4ee-4715-975f-88e7a5543e3a |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024555471 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2024555471 |
Directory | /workspace/14.hmac_stress_all/latest |
Test location | /workspace/coverage/default/14.hmac_test_hmac_vectors.1884000343 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 37681162 ps |
CPU time | 0.99 seconds |
Started | Apr 16 02:04:00 PM PDT 24 |
Finished | Apr 16 02:04:02 PM PDT 24 |
Peak memory | 199528 kb |
Host | smart-0c9eba26-9c52-4130-9a84-2d245f41d0d7 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884000343 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 14.hmac_test_hmac_vectors.1884000343 |
Directory | /workspace/14.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/14.hmac_test_sha_vectors.2651862461 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 169153550363 ps |
CPU time | 494.23 seconds |
Started | Apr 16 02:03:58 PM PDT 24 |
Finished | Apr 16 02:12:13 PM PDT 24 |
Peak memory | 199680 kb |
Host | smart-5b1c2d4b-eb5c-46f9-9795-ec350f87a292 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651862461 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.2651862461 |
Directory | /workspace/14.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/14.hmac_wipe_secret.2306104543 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 2709070633 ps |
CPU time | 58.2 seconds |
Started | Apr 16 02:03:58 PM PDT 24 |
Finished | Apr 16 02:04:57 PM PDT 24 |
Peak memory | 199752 kb |
Host | smart-82500c87-6a32-4a0c-a03d-7bf72ee833b5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2306104543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2306104543 |
Directory | /workspace/14.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/15.hmac_alert_test.2128096361 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 42069038 ps |
CPU time | 0.57 seconds |
Started | Apr 16 02:04:03 PM PDT 24 |
Finished | Apr 16 02:04:05 PM PDT 24 |
Peak memory | 194120 kb |
Host | smart-79497f79-15ea-4ad9-b414-e6fa7728a6f8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128096361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2128096361 |
Directory | /workspace/15.hmac_alert_test/latest |
Test location | /workspace/coverage/default/15.hmac_back_pressure.3706208140 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 4674446249 ps |
CPU time | 43.8 seconds |
Started | Apr 16 02:03:59 PM PDT 24 |
Finished | Apr 16 02:04:44 PM PDT 24 |
Peak memory | 232524 kb |
Host | smart-201c44b2-9685-4a1d-8d8d-7a5304032052 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3706208140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3706208140 |
Directory | /workspace/15.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/15.hmac_burst_wr.956272903 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 2254538462 ps |
CPU time | 70.14 seconds |
Started | Apr 16 02:03:58 PM PDT 24 |
Finished | Apr 16 02:05:09 PM PDT 24 |
Peak memory | 199656 kb |
Host | smart-21c3b44e-d0e8-4503-88b5-5f169e975071 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=956272903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.956272903 |
Directory | /workspace/15.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/15.hmac_datapath_stress.678476517 |
Short name | T577 |
Test name | |
Test status | |
Simulation time | 918701503 ps |
CPU time | 21.1 seconds |
Started | Apr 16 02:03:57 PM PDT 24 |
Finished | Apr 16 02:04:19 PM PDT 24 |
Peak memory | 199568 kb |
Host | smart-079f6fd0-e0a9-4bb2-b5cc-e19dd9beff28 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=678476517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.678476517 |
Directory | /workspace/15.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/15.hmac_error.1475684629 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 6546569362 ps |
CPU time | 113.38 seconds |
Started | Apr 16 02:03:59 PM PDT 24 |
Finished | Apr 16 02:05:53 PM PDT 24 |
Peak memory | 199744 kb |
Host | smart-41576f56-79e1-4f5a-b592-5a90011bfe12 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475684629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1475684629 |
Directory | /workspace/15.hmac_error/latest |
Test location | /workspace/coverage/default/15.hmac_long_msg.1607276907 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 3104138251 ps |
CPU time | 44.51 seconds |
Started | Apr 16 02:03:57 PM PDT 24 |
Finished | Apr 16 02:04:42 PM PDT 24 |
Peak memory | 199680 kb |
Host | smart-07a03f80-b7e9-4704-b04f-6b8d35eb4508 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1607276907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1607276907 |
Directory | /workspace/15.hmac_long_msg/latest |
Test location | /workspace/coverage/default/15.hmac_smoke.2939606669 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 513549413 ps |
CPU time | 3.78 seconds |
Started | Apr 16 02:04:04 PM PDT 24 |
Finished | Apr 16 02:04:09 PM PDT 24 |
Peak memory | 199588 kb |
Host | smart-8ff96943-886a-4ce4-9ba8-5975cc98b069 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2939606669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2939606669 |
Directory | /workspace/15.hmac_smoke/latest |
Test location | /workspace/coverage/default/15.hmac_stress_all.926463389 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 388015430005 ps |
CPU time | 2284.12 seconds |
Started | Apr 16 02:04:04 PM PDT 24 |
Finished | Apr 16 02:42:09 PM PDT 24 |
Peak memory | 199708 kb |
Host | smart-cb73da26-cdad-468f-866a-d5f59e5cdc51 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926463389 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.926463389 |
Directory | /workspace/15.hmac_stress_all/latest |
Test location | /workspace/coverage/default/15.hmac_test_hmac_vectors.82597375 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 940205381 ps |
CPU time | 1.04 seconds |
Started | Apr 16 02:04:01 PM PDT 24 |
Finished | Apr 16 02:04:02 PM PDT 24 |
Peak memory | 198896 kb |
Host | smart-23db368b-7339-49e1-b57d-92bc529ec119 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82597375 -assert nopostproc +UVM_TESTNAME=hmac_base_t est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 15.hmac_test_hmac_vectors.82597375 |
Directory | /workspace/15.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/15.hmac_test_sha_vectors.3569595502 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 8027550204 ps |
CPU time | 441.53 seconds |
Started | Apr 16 02:04:03 PM PDT 24 |
Finished | Apr 16 02:11:25 PM PDT 24 |
Peak memory | 199732 kb |
Host | smart-4b231432-56dc-40f0-a7dd-444da1f8b37d |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569595502 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.3569595502 |
Directory | /workspace/15.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/15.hmac_wipe_secret.3308775480 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 13510056723 ps |
CPU time | 41.71 seconds |
Started | Apr 16 02:03:59 PM PDT 24 |
Finished | Apr 16 02:04:41 PM PDT 24 |
Peak memory | 199668 kb |
Host | smart-36163e0a-b1ba-4f35-ae4c-563e3b7a4d15 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3308775480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3308775480 |
Directory | /workspace/15.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/150.hmac_stress_all_with_rand_reset.1198848360 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 79330695030 ps |
CPU time | 2538.58 seconds |
Started | Apr 16 02:05:50 PM PDT 24 |
Finished | Apr 16 02:48:09 PM PDT 24 |
Peak memory | 232448 kb |
Host | smart-65c849e5-c7e9-4dd7-b334-9165079c559b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1198848360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.hmac_stress_all_with_rand_reset.1198848360 |
Directory | /workspace/150.hmac_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/157.hmac_stress_all_with_rand_reset.3334006351 |
Short name | T513 |
Test name | |
Test status | |
Simulation time | 71939339013 ps |
CPU time | 452.27 seconds |
Started | Apr 16 02:05:48 PM PDT 24 |
Finished | Apr 16 02:13:22 PM PDT 24 |
Peak memory | 244832 kb |
Host | smart-75867df4-9d14-4d05-bb3e-79c7e1c9ca0e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3334006351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.hmac_stress_all_with_rand_reset.3334006351 |
Directory | /workspace/157.hmac_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/159.hmac_stress_all_with_rand_reset.3389251130 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 238024520834 ps |
CPU time | 2785.18 seconds |
Started | Apr 16 02:05:48 PM PDT 24 |
Finished | Apr 16 02:52:15 PM PDT 24 |
Peak memory | 261120 kb |
Host | smart-85be6823-b296-442e-b93a-fce122321b98 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3389251130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.hmac_stress_all_with_rand_reset.3389251130 |
Directory | /workspace/159.hmac_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/16.hmac_back_pressure.3940158201 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 213387640 ps |
CPU time | 7.37 seconds |
Started | Apr 16 02:04:08 PM PDT 24 |
Finished | Apr 16 02:04:16 PM PDT 24 |
Peak memory | 207772 kb |
Host | smart-5a32caac-f492-428b-be4c-bcc8c20afa10 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3940158201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.3940158201 |
Directory | /workspace/16.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/16.hmac_datapath_stress.3859483553 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 7350186131 ps |
CPU time | 171.59 seconds |
Started | Apr 16 02:04:03 PM PDT 24 |
Finished | Apr 16 02:06:55 PM PDT 24 |
Peak memory | 199748 kb |
Host | smart-8cc06657-71d7-4a14-87f3-acc6d17cb9d8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3859483553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3859483553 |
Directory | /workspace/16.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/16.hmac_error.4155414446 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 10451721196 ps |
CPU time | 32.45 seconds |
Started | Apr 16 02:04:02 PM PDT 24 |
Finished | Apr 16 02:04:35 PM PDT 24 |
Peak memory | 199700 kb |
Host | smart-2fdf4efa-947b-4678-b681-fcdb6b5d3a52 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155414446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.4155414446 |
Directory | /workspace/16.hmac_error/latest |
Test location | /workspace/coverage/default/16.hmac_long_msg.3223886196 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 7968737160 ps |
CPU time | 44.99 seconds |
Started | Apr 16 02:04:02 PM PDT 24 |
Finished | Apr 16 02:04:48 PM PDT 24 |
Peak memory | 199700 kb |
Host | smart-c84fad86-652a-49d6-b7d4-c0cc6812949b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3223886196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3223886196 |
Directory | /workspace/16.hmac_long_msg/latest |
Test location | /workspace/coverage/default/16.hmac_smoke.2907178119 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 1226493586 ps |
CPU time | 7.26 seconds |
Started | Apr 16 02:04:03 PM PDT 24 |
Finished | Apr 16 02:04:11 PM PDT 24 |
Peak memory | 199584 kb |
Host | smart-6cf31c95-b3fa-48b3-ae88-25cd458f4656 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2907178119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2907178119 |
Directory | /workspace/16.hmac_smoke/latest |
Test location | /workspace/coverage/default/16.hmac_stress_all.317902982 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 24439716 ps |
CPU time | 0.64 seconds |
Started | Apr 16 02:04:02 PM PDT 24 |
Finished | Apr 16 02:04:03 PM PDT 24 |
Peak memory | 194840 kb |
Host | smart-ee91f0a0-cf00-45ea-a97a-814bf8223f5b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317902982 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.317902982 |
Directory | /workspace/16.hmac_stress_all/latest |
Test location | /workspace/coverage/default/16.hmac_test_hmac_vectors.3305188770 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 136575435 ps |
CPU time | 1.25 seconds |
Started | Apr 16 02:04:02 PM PDT 24 |
Finished | Apr 16 02:04:04 PM PDT 24 |
Peak memory | 199120 kb |
Host | smart-9b53c0d6-9561-43ba-9fe8-2a413df8bd58 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305188770 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.hmac_test_hmac_vectors.3305188770 |
Directory | /workspace/16.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/16.hmac_test_sha_vectors.2538973620 |
Short name | T592 |
Test name | |
Test status | |
Simulation time | 7564643091 ps |
CPU time | 440.21 seconds |
Started | Apr 16 02:04:03 PM PDT 24 |
Finished | Apr 16 02:11:24 PM PDT 24 |
Peak memory | 199732 kb |
Host | smart-2e6e00b8-2beb-4888-94ff-ca98493f5b51 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538973620 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.2538973620 |
Directory | /workspace/16.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/16.hmac_wipe_secret.1617163648 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 1437828392 ps |
CPU time | 52.08 seconds |
Started | Apr 16 02:04:01 PM PDT 24 |
Finished | Apr 16 02:04:54 PM PDT 24 |
Peak memory | 199588 kb |
Host | smart-ab39ab50-1233-46a3-8f36-2d5a114a7273 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1617163648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1617163648 |
Directory | /workspace/16.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/17.hmac_alert_test.859805288 |
Short name | T528 |
Test name | |
Test status | |
Simulation time | 14869327 ps |
CPU time | 0.6 seconds |
Started | Apr 16 02:04:15 PM PDT 24 |
Finished | Apr 16 02:04:17 PM PDT 24 |
Peak memory | 195180 kb |
Host | smart-904c6207-3714-494a-bd35-d0acdb31baac |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859805288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.859805288 |
Directory | /workspace/17.hmac_alert_test/latest |
Test location | /workspace/coverage/default/17.hmac_back_pressure.2925306871 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 1806738061 ps |
CPU time | 16.79 seconds |
Started | Apr 16 02:04:03 PM PDT 24 |
Finished | Apr 16 02:04:21 PM PDT 24 |
Peak memory | 199636 kb |
Host | smart-adb82812-fa4a-4aa1-bf82-c3179b9e95de |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2925306871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2925306871 |
Directory | /workspace/17.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/17.hmac_burst_wr.272660204 |
Short name | T567 |
Test name | |
Test status | |
Simulation time | 542547800 ps |
CPU time | 25.57 seconds |
Started | Apr 16 02:04:08 PM PDT 24 |
Finished | Apr 16 02:04:34 PM PDT 24 |
Peak memory | 199592 kb |
Host | smart-5677745b-e1f3-4f48-ad14-38bc295bb815 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=272660204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.272660204 |
Directory | /workspace/17.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/17.hmac_datapath_stress.679004362 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 2830432198 ps |
CPU time | 174.71 seconds |
Started | Apr 16 02:04:04 PM PDT 24 |
Finished | Apr 16 02:07:00 PM PDT 24 |
Peak memory | 199672 kb |
Host | smart-1de83ed4-c9a2-406f-918c-2dce5baf0dcd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=679004362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.679004362 |
Directory | /workspace/17.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/17.hmac_error.4080684038 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 3283660776 ps |
CPU time | 97.2 seconds |
Started | Apr 16 02:04:03 PM PDT 24 |
Finished | Apr 16 02:05:42 PM PDT 24 |
Peak memory | 199724 kb |
Host | smart-bfbf837d-3609-465e-b7b4-8d0b3aa82c25 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080684038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.4080684038 |
Directory | /workspace/17.hmac_error/latest |
Test location | /workspace/coverage/default/17.hmac_long_msg.2890221580 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 4583682429 ps |
CPU time | 61.38 seconds |
Started | Apr 16 02:05:13 PM PDT 24 |
Finished | Apr 16 02:06:15 PM PDT 24 |
Peak memory | 199424 kb |
Host | smart-03fc966c-d13a-494e-85c6-59120da7f208 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2890221580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2890221580 |
Directory | /workspace/17.hmac_long_msg/latest |
Test location | /workspace/coverage/default/17.hmac_smoke.486754855 |
Short name | T538 |
Test name | |
Test status | |
Simulation time | 144416945 ps |
CPU time | 1.48 seconds |
Started | Apr 16 02:05:08 PM PDT 24 |
Finished | Apr 16 02:05:13 PM PDT 24 |
Peak memory | 198664 kb |
Host | smart-36d093b0-940b-4e93-b4a7-7a89d03665db |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=486754855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.486754855 |
Directory | /workspace/17.hmac_smoke/latest |
Test location | /workspace/coverage/default/17.hmac_stress_all.2302988837 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 712658057468 ps |
CPU time | 2381.49 seconds |
Started | Apr 16 02:04:11 PM PDT 24 |
Finished | Apr 16 02:43:54 PM PDT 24 |
Peak memory | 199760 kb |
Host | smart-34d843aa-62b6-4898-9682-5f598d229866 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302988837 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2302988837 |
Directory | /workspace/17.hmac_stress_all/latest |
Test location | /workspace/coverage/default/17.hmac_test_hmac_vectors.3054761110 |
Short name | T562 |
Test name | |
Test status | |
Simulation time | 256507290 ps |
CPU time | 0.99 seconds |
Started | Apr 16 02:04:13 PM PDT 24 |
Finished | Apr 16 02:04:15 PM PDT 24 |
Peak memory | 198100 kb |
Host | smart-537ad664-dc98-4c60-806e-9f4f71d39388 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054761110 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.hmac_test_hmac_vectors.3054761110 |
Directory | /workspace/17.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/17.hmac_test_sha_vectors.1153889109 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 105950158233 ps |
CPU time | 468.94 seconds |
Started | Apr 16 02:04:12 PM PDT 24 |
Finished | Apr 16 02:12:02 PM PDT 24 |
Peak memory | 199636 kb |
Host | smart-f2f69734-0ca5-4b1f-b634-4414fee22cef |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153889109 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.1153889109 |
Directory | /workspace/17.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/17.hmac_wipe_secret.569272853 |
Short name | T510 |
Test name | |
Test status | |
Simulation time | 5536627423 ps |
CPU time | 78.75 seconds |
Started | Apr 16 02:04:04 PM PDT 24 |
Finished | Apr 16 02:05:24 PM PDT 24 |
Peak memory | 199696 kb |
Host | smart-c9f56cb5-ec79-417f-8501-2b802b0c468a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=569272853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.569272853 |
Directory | /workspace/17.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/18.hmac_alert_test.4254535446 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 12483598 ps |
CPU time | 0.6 seconds |
Started | Apr 16 02:04:10 PM PDT 24 |
Finished | Apr 16 02:04:11 PM PDT 24 |
Peak memory | 194132 kb |
Host | smart-0f1b82f8-ab5e-4d80-bb2a-05b9f8e910d6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254535446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.4254535446 |
Directory | /workspace/18.hmac_alert_test/latest |
Test location | /workspace/coverage/default/18.hmac_back_pressure.1136332844 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 7370627533 ps |
CPU time | 53.09 seconds |
Started | Apr 16 02:04:15 PM PDT 24 |
Finished | Apr 16 02:05:09 PM PDT 24 |
Peak memory | 216036 kb |
Host | smart-4c3dd429-bf57-49af-a7e1-5a65643685f6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1136332844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1136332844 |
Directory | /workspace/18.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/18.hmac_burst_wr.2384427450 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 8475089635 ps |
CPU time | 60.04 seconds |
Started | Apr 16 02:04:12 PM PDT 24 |
Finished | Apr 16 02:05:13 PM PDT 24 |
Peak memory | 199712 kb |
Host | smart-5c73ac0d-bd7f-400c-a326-b3d6a79124b5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2384427450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.2384427450 |
Directory | /workspace/18.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/18.hmac_datapath_stress.162542010 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 3607101613 ps |
CPU time | 99.81 seconds |
Started | Apr 16 02:04:10 PM PDT 24 |
Finished | Apr 16 02:05:50 PM PDT 24 |
Peak memory | 199740 kb |
Host | smart-e5791cf3-e0ec-4760-9f15-26227ac01f97 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=162542010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.162542010 |
Directory | /workspace/18.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/18.hmac_long_msg.1982448081 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 421853492 ps |
CPU time | 8.76 seconds |
Started | Apr 16 02:04:12 PM PDT 24 |
Finished | Apr 16 02:04:21 PM PDT 24 |
Peak memory | 199576 kb |
Host | smart-362e904a-2a4c-44a9-b16f-816524d0ef9a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1982448081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1982448081 |
Directory | /workspace/18.hmac_long_msg/latest |
Test location | /workspace/coverage/default/18.hmac_smoke.3260624457 |
Short name | T536 |
Test name | |
Test status | |
Simulation time | 36608528 ps |
CPU time | 1.34 seconds |
Started | Apr 16 02:04:11 PM PDT 24 |
Finished | Apr 16 02:04:13 PM PDT 24 |
Peak memory | 199524 kb |
Host | smart-cd0682df-d0fe-4472-bbe7-fd07ffe1f96d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3260624457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3260624457 |
Directory | /workspace/18.hmac_smoke/latest |
Test location | /workspace/coverage/default/18.hmac_stress_all.1685575343 |
Short name | T596 |
Test name | |
Test status | |
Simulation time | 105087104728 ps |
CPU time | 704.87 seconds |
Started | Apr 16 02:04:20 PM PDT 24 |
Finished | Apr 16 02:16:07 PM PDT 24 |
Peak memory | 199732 kb |
Host | smart-1df1c43c-2827-4477-b106-0b00168d3376 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685575343 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1685575343 |
Directory | /workspace/18.hmac_stress_all/latest |
Test location | /workspace/coverage/default/18.hmac_test_hmac_vectors.868345706 |
Short name | T520 |
Test name | |
Test status | |
Simulation time | 115377189 ps |
CPU time | 1.22 seconds |
Started | Apr 16 02:04:11 PM PDT 24 |
Finished | Apr 16 02:04:13 PM PDT 24 |
Peak memory | 199612 kb |
Host | smart-26829607-0e5a-472b-b0ed-0d54761c943c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868345706 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 18.hmac_test_hmac_vectors.868345706 |
Directory | /workspace/18.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/18.hmac_test_sha_vectors.1085246443 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 254371168315 ps |
CPU time | 526.48 seconds |
Started | Apr 16 02:04:17 PM PDT 24 |
Finished | Apr 16 02:13:04 PM PDT 24 |
Peak memory | 199720 kb |
Host | smart-969e8033-e6a5-4c70-a34d-1220e7de9893 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085246443 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.1085246443 |
Directory | /workspace/18.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/18.hmac_wipe_secret.4157750933 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 4303776593 ps |
CPU time | 39.5 seconds |
Started | Apr 16 02:04:10 PM PDT 24 |
Finished | Apr 16 02:04:50 PM PDT 24 |
Peak memory | 199708 kb |
Host | smart-442d3a01-8148-4513-90b9-0c22b233ee1e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4157750933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.4157750933 |
Directory | /workspace/18.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/19.hmac_alert_test.2965821984 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 76903466 ps |
CPU time | 0.57 seconds |
Started | Apr 16 02:04:11 PM PDT 24 |
Finished | Apr 16 02:04:12 PM PDT 24 |
Peak memory | 194868 kb |
Host | smart-52deac21-dda3-4b5e-baac-618490cb867f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965821984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2965821984 |
Directory | /workspace/19.hmac_alert_test/latest |
Test location | /workspace/coverage/default/19.hmac_back_pressure.1176686 |
Short name | T525 |
Test name | |
Test status | |
Simulation time | 305480038 ps |
CPU time | 3.03 seconds |
Started | Apr 16 02:04:12 PM PDT 24 |
Finished | Apr 16 02:04:16 PM PDT 24 |
Peak memory | 199624 kb |
Host | smart-903746b5-8f38-4b1a-b816-685234b64a91 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1176686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.1176686 |
Directory | /workspace/19.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/19.hmac_burst_wr.217755940 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 634153468 ps |
CPU time | 31.38 seconds |
Started | Apr 16 02:04:13 PM PDT 24 |
Finished | Apr 16 02:04:45 PM PDT 24 |
Peak memory | 199584 kb |
Host | smart-26a565de-ccb1-48a1-99b4-fb5fe7347972 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=217755940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.217755940 |
Directory | /workspace/19.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/19.hmac_datapath_stress.2342904646 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 5371138684 ps |
CPU time | 146.33 seconds |
Started | Apr 16 02:04:20 PM PDT 24 |
Finished | Apr 16 02:06:48 PM PDT 24 |
Peak memory | 199728 kb |
Host | smart-72a8f551-ee76-42ba-bec2-eab737eda7a2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2342904646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2342904646 |
Directory | /workspace/19.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/19.hmac_error.2543562141 |
Short name | T566 |
Test name | |
Test status | |
Simulation time | 6784814637 ps |
CPU time | 90.54 seconds |
Started | Apr 16 02:04:11 PM PDT 24 |
Finished | Apr 16 02:05:43 PM PDT 24 |
Peak memory | 199732 kb |
Host | smart-7ff7ad10-6c1b-4c62-bc1c-48a6d67414ed |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543562141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2543562141 |
Directory | /workspace/19.hmac_error/latest |
Test location | /workspace/coverage/default/19.hmac_long_msg.1566847588 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 2738318594 ps |
CPU time | 75.6 seconds |
Started | Apr 16 02:04:12 PM PDT 24 |
Finished | Apr 16 02:05:29 PM PDT 24 |
Peak memory | 199732 kb |
Host | smart-70f8168b-0a18-47d7-9f98-c84c694fb0ca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1566847588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1566847588 |
Directory | /workspace/19.hmac_long_msg/latest |
Test location | /workspace/coverage/default/19.hmac_smoke.1853473321 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 517375286 ps |
CPU time | 4.1 seconds |
Started | Apr 16 02:04:10 PM PDT 24 |
Finished | Apr 16 02:04:14 PM PDT 24 |
Peak memory | 199548 kb |
Host | smart-5d36f416-efb4-4790-9380-cd80954e45ba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1853473321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1853473321 |
Directory | /workspace/19.hmac_smoke/latest |
Test location | /workspace/coverage/default/19.hmac_stress_all.3859572513 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 84569588373 ps |
CPU time | 1433.53 seconds |
Started | Apr 16 02:04:09 PM PDT 24 |
Finished | Apr 16 02:28:03 PM PDT 24 |
Peak memory | 199704 kb |
Host | smart-929d982f-d254-4a69-85df-ad1da0a0e88e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859572513 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3859572513 |
Directory | /workspace/19.hmac_stress_all/latest |
Test location | /workspace/coverage/default/19.hmac_test_hmac_vectors.1984762023 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 64932101 ps |
CPU time | 1.22 seconds |
Started | Apr 16 02:04:10 PM PDT 24 |
Finished | Apr 16 02:04:12 PM PDT 24 |
Peak memory | 199560 kb |
Host | smart-72b3b621-223f-4cfd-a63a-7602aca90490 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984762023 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.hmac_test_hmac_vectors.1984762023 |
Directory | /workspace/19.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/19.hmac_test_sha_vectors.4048431817 |
Short name | T530 |
Test name | |
Test status | |
Simulation time | 137494543274 ps |
CPU time | 496.21 seconds |
Started | Apr 16 02:04:16 PM PDT 24 |
Finished | Apr 16 02:12:33 PM PDT 24 |
Peak memory | 199728 kb |
Host | smart-c828a25a-1e7f-4b89-88b2-0aaf7b882239 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048431817 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.4048431817 |
Directory | /workspace/19.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/19.hmac_wipe_secret.858513499 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 3963284439 ps |
CPU time | 37.4 seconds |
Started | Apr 16 02:04:12 PM PDT 24 |
Finished | Apr 16 02:04:51 PM PDT 24 |
Peak memory | 199720 kb |
Host | smart-c976be53-e175-47c3-8992-fa40aa11971b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=858513499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.858513499 |
Directory | /workspace/19.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/191.hmac_stress_all_with_rand_reset.3815834593 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 60308569829 ps |
CPU time | 3271.59 seconds |
Started | Apr 16 02:06:00 PM PDT 24 |
Finished | Apr 16 03:00:32 PM PDT 24 |
Peak memory | 257148 kb |
Host | smart-7ac76a66-709a-42a4-98f2-54883dc39478 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3815834593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.hmac_stress_all_with_rand_reset.3815834593 |
Directory | /workspace/191.hmac_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/2.hmac_alert_test.1255856650 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 13470543 ps |
CPU time | 0.61 seconds |
Started | Apr 16 02:03:39 PM PDT 24 |
Finished | Apr 16 02:03:41 PM PDT 24 |
Peak memory | 194860 kb |
Host | smart-b7b30b90-68eb-473a-b5af-8b8f8789d6b1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255856650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1255856650 |
Directory | /workspace/2.hmac_alert_test/latest |
Test location | /workspace/coverage/default/2.hmac_back_pressure.2491645301 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 416011802 ps |
CPU time | 18.18 seconds |
Started | Apr 16 02:03:26 PM PDT 24 |
Finished | Apr 16 02:03:45 PM PDT 24 |
Peak memory | 222044 kb |
Host | smart-93037cb3-b8d1-4c52-ad2b-542ee26ab1cd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2491645301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.2491645301 |
Directory | /workspace/2.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/2.hmac_burst_wr.3244234755 |
Short name | T514 |
Test name | |
Test status | |
Simulation time | 883650984 ps |
CPU time | 19.32 seconds |
Started | Apr 16 02:03:26 PM PDT 24 |
Finished | Apr 16 02:03:46 PM PDT 24 |
Peak memory | 199520 kb |
Host | smart-4f8b72cc-5087-4dd2-8cef-a8ae1598e712 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3244234755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3244234755 |
Directory | /workspace/2.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/2.hmac_datapath_stress.56632155 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 4297949465 ps |
CPU time | 39.85 seconds |
Started | Apr 16 02:03:29 PM PDT 24 |
Finished | Apr 16 02:04:12 PM PDT 24 |
Peak memory | 199712 kb |
Host | smart-13ed96ca-1db3-4079-8ae4-3aa9717879b5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=56632155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.56632155 |
Directory | /workspace/2.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/2.hmac_error.4202347781 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 20515925522 ps |
CPU time | 88.62 seconds |
Started | Apr 16 02:03:23 PM PDT 24 |
Finished | Apr 16 02:04:53 PM PDT 24 |
Peak memory | 199672 kb |
Host | smart-1e3e99e4-7692-475c-9060-f119e3ac3fe1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202347781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.4202347781 |
Directory | /workspace/2.hmac_error/latest |
Test location | /workspace/coverage/default/2.hmac_long_msg.1613146181 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 759000390 ps |
CPU time | 43.14 seconds |
Started | Apr 16 02:03:25 PM PDT 24 |
Finished | Apr 16 02:04:09 PM PDT 24 |
Peak memory | 199592 kb |
Host | smart-5f4b865d-75ae-47f9-961a-e56c8caf12e7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1613146181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1613146181 |
Directory | /workspace/2.hmac_long_msg/latest |
Test location | /workspace/coverage/default/2.hmac_sec_cm.1208208996 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 107373662 ps |
CPU time | 0.97 seconds |
Started | Apr 16 02:03:33 PM PDT 24 |
Finished | Apr 16 02:03:36 PM PDT 24 |
Peak memory | 219236 kb |
Host | smart-36fc3253-5406-46c4-879a-13eb9f0685e2 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208208996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1208208996 |
Directory | /workspace/2.hmac_sec_cm/latest |
Test location | /workspace/coverage/default/2.hmac_smoke.3587030054 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 5205815388 ps |
CPU time | 7.16 seconds |
Started | Apr 16 02:03:37 PM PDT 24 |
Finished | Apr 16 02:03:45 PM PDT 24 |
Peak memory | 199732 kb |
Host | smart-53ecdee2-c9ff-4900-859c-8c6a7dc5f8e9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3587030054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3587030054 |
Directory | /workspace/2.hmac_smoke/latest |
Test location | /workspace/coverage/default/2.hmac_stress_all.2043678423 |
Short name | T570 |
Test name | |
Test status | |
Simulation time | 25735697450 ps |
CPU time | 488.54 seconds |
Started | Apr 16 02:03:28 PM PDT 24 |
Finished | Apr 16 02:11:39 PM PDT 24 |
Peak memory | 207940 kb |
Host | smart-746ed49a-8629-45eb-8f52-ae99cda868f0 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043678423 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2043678423 |
Directory | /workspace/2.hmac_stress_all/latest |
Test location | /workspace/coverage/default/2.hmac_test_hmac_vectors.3124692205 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 34648602 ps |
CPU time | 1.23 seconds |
Started | Apr 16 02:03:28 PM PDT 24 |
Finished | Apr 16 02:03:32 PM PDT 24 |
Peak memory | 199548 kb |
Host | smart-63a60b15-d946-4fb4-8bc7-6c22bcdfb749 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124692205 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.hmac_test_hmac_vectors.3124692205 |
Directory | /workspace/2.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/2.hmac_test_sha_vectors.604182057 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 53308216044 ps |
CPU time | 469.41 seconds |
Started | Apr 16 02:03:34 PM PDT 24 |
Finished | Apr 16 02:11:26 PM PDT 24 |
Peak memory | 199708 kb |
Host | smart-72ad52cd-062e-47cc-b7af-920b850770a6 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604182057 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.604182057 |
Directory | /workspace/2.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/2.hmac_wipe_secret.1532344257 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 3415011604 ps |
CPU time | 75.26 seconds |
Started | Apr 16 02:03:20 PM PDT 24 |
Finished | Apr 16 02:04:36 PM PDT 24 |
Peak memory | 199704 kb |
Host | smart-0e6579e6-f28b-4339-91ac-d5a7284a50b5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1532344257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1532344257 |
Directory | /workspace/2.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/20.hmac_alert_test.1929955663 |
Short name | T533 |
Test name | |
Test status | |
Simulation time | 49602750 ps |
CPU time | 0.61 seconds |
Started | Apr 16 02:04:15 PM PDT 24 |
Finished | Apr 16 02:04:16 PM PDT 24 |
Peak memory | 195204 kb |
Host | smart-a81f70c3-acb9-43e0-8ba0-35c4f1893d17 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929955663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1929955663 |
Directory | /workspace/20.hmac_alert_test/latest |
Test location | /workspace/coverage/default/20.hmac_back_pressure.2733279230 |
Short name | T543 |
Test name | |
Test status | |
Simulation time | 4437150512 ps |
CPU time | 37 seconds |
Started | Apr 16 02:04:13 PM PDT 24 |
Finished | Apr 16 02:04:51 PM PDT 24 |
Peak memory | 224276 kb |
Host | smart-df73d9e8-eaa1-4913-9fae-83366d96c993 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2733279230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2733279230 |
Directory | /workspace/20.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/20.hmac_burst_wr.45728124 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 8803356598 ps |
CPU time | 39.18 seconds |
Started | Apr 16 02:04:10 PM PDT 24 |
Finished | Apr 16 02:04:49 PM PDT 24 |
Peak memory | 199696 kb |
Host | smart-d1d0720c-f1b9-4463-b612-b37a23be9754 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=45728124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.45728124 |
Directory | /workspace/20.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/20.hmac_datapath_stress.2229299405 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 714832411 ps |
CPU time | 44.21 seconds |
Started | Apr 16 02:04:13 PM PDT 24 |
Finished | Apr 16 02:04:58 PM PDT 24 |
Peak memory | 199636 kb |
Host | smart-27f16919-72d6-41d7-8ace-52b5825113cf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2229299405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2229299405 |
Directory | /workspace/20.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/20.hmac_error.1590930735 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 18151783015 ps |
CPU time | 81.37 seconds |
Started | Apr 16 02:04:10 PM PDT 24 |
Finished | Apr 16 02:05:32 PM PDT 24 |
Peak memory | 199724 kb |
Host | smart-273f2bcb-737f-4564-8465-edc352d6f943 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590930735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1590930735 |
Directory | /workspace/20.hmac_error/latest |
Test location | /workspace/coverage/default/20.hmac_long_msg.206295281 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 28800486980 ps |
CPU time | 113.21 seconds |
Started | Apr 16 02:04:14 PM PDT 24 |
Finished | Apr 16 02:06:08 PM PDT 24 |
Peak memory | 199684 kb |
Host | smart-a209c491-2f11-4fab-8c1e-bf5ba0e8cf21 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=206295281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.206295281 |
Directory | /workspace/20.hmac_long_msg/latest |
Test location | /workspace/coverage/default/20.hmac_smoke.233841694 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 621496271 ps |
CPU time | 6.76 seconds |
Started | Apr 16 02:04:18 PM PDT 24 |
Finished | Apr 16 02:04:26 PM PDT 24 |
Peak memory | 199652 kb |
Host | smart-32630302-2f0f-4dea-a937-4b354c779b4b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=233841694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.233841694 |
Directory | /workspace/20.hmac_smoke/latest |
Test location | /workspace/coverage/default/20.hmac_stress_all.3169776506 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 92149223884 ps |
CPU time | 1242.52 seconds |
Started | Apr 16 02:04:16 PM PDT 24 |
Finished | Apr 16 02:24:59 PM PDT 24 |
Peak memory | 199684 kb |
Host | smart-0f2085c2-6be3-498a-a874-e91b0c8ead63 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169776506 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3169776506 |
Directory | /workspace/20.hmac_stress_all/latest |
Test location | /workspace/coverage/default/20.hmac_test_hmac_vectors.1664666996 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 118969802 ps |
CPU time | 0.94 seconds |
Started | Apr 16 02:04:11 PM PDT 24 |
Finished | Apr 16 02:04:13 PM PDT 24 |
Peak memory | 198188 kb |
Host | smart-0fbf2596-0a0f-4c91-99d9-43841c3a6098 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664666996 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 20.hmac_test_hmac_vectors.1664666996 |
Directory | /workspace/20.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/20.hmac_test_sha_vectors.2675319500 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 30195436037 ps |
CPU time | 407.16 seconds |
Started | Apr 16 02:04:13 PM PDT 24 |
Finished | Apr 16 02:11:01 PM PDT 24 |
Peak memory | 199700 kb |
Host | smart-ad3445f6-d9ca-498a-994a-3876677b95db |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675319500 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.2675319500 |
Directory | /workspace/20.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/20.hmac_wipe_secret.1315380236 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 78315732690 ps |
CPU time | 84.88 seconds |
Started | Apr 16 02:04:14 PM PDT 24 |
Finished | Apr 16 02:05:39 PM PDT 24 |
Peak memory | 199740 kb |
Host | smart-36d85c72-7b17-4e6a-bf50-b891dfef4c3e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1315380236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1315380236 |
Directory | /workspace/20.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/21.hmac_alert_test.1436666949 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 28102594 ps |
CPU time | 0.57 seconds |
Started | Apr 16 02:04:20 PM PDT 24 |
Finished | Apr 16 02:04:22 PM PDT 24 |
Peak memory | 195204 kb |
Host | smart-c1deaceb-1bd9-4708-ae71-2c540041e7db |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436666949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1436666949 |
Directory | /workspace/21.hmac_alert_test/latest |
Test location | /workspace/coverage/default/21.hmac_back_pressure.3785199169 |
Short name | T576 |
Test name | |
Test status | |
Simulation time | 5806139385 ps |
CPU time | 45.55 seconds |
Started | Apr 16 02:04:15 PM PDT 24 |
Finished | Apr 16 02:05:01 PM PDT 24 |
Peak memory | 207976 kb |
Host | smart-72e4f61c-e12d-4385-9dd5-487b92ca5cdf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3785199169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3785199169 |
Directory | /workspace/21.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/21.hmac_burst_wr.901457747 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 4158101147 ps |
CPU time | 50.06 seconds |
Started | Apr 16 02:04:20 PM PDT 24 |
Finished | Apr 16 02:05:12 PM PDT 24 |
Peak memory | 199716 kb |
Host | smart-736704bf-d407-4cea-b77d-7edde83510b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=901457747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.901457747 |
Directory | /workspace/21.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/21.hmac_datapath_stress.2717185268 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 950318836 ps |
CPU time | 53.75 seconds |
Started | Apr 16 02:04:16 PM PDT 24 |
Finished | Apr 16 02:05:10 PM PDT 24 |
Peak memory | 199572 kb |
Host | smart-8065deeb-f652-46c7-b0b7-2191679e57b6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2717185268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2717185268 |
Directory | /workspace/21.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/21.hmac_error.2241041017 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 4743021914 ps |
CPU time | 136.88 seconds |
Started | Apr 16 02:04:15 PM PDT 24 |
Finished | Apr 16 02:06:32 PM PDT 24 |
Peak memory | 199676 kb |
Host | smart-2a3b23fe-bde5-46b6-8095-75db13134bba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241041017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2241041017 |
Directory | /workspace/21.hmac_error/latest |
Test location | /workspace/coverage/default/21.hmac_long_msg.2468780205 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 3546214253 ps |
CPU time | 48.8 seconds |
Started | Apr 16 02:05:19 PM PDT 24 |
Finished | Apr 16 02:06:09 PM PDT 24 |
Peak memory | 199520 kb |
Host | smart-cc87c47c-2758-4a9b-bbd4-2c7a03ab048a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2468780205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2468780205 |
Directory | /workspace/21.hmac_long_msg/latest |
Test location | /workspace/coverage/default/21.hmac_smoke.2276346973 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 263270272 ps |
CPU time | 1.79 seconds |
Started | Apr 16 02:04:13 PM PDT 24 |
Finished | Apr 16 02:04:15 PM PDT 24 |
Peak memory | 199552 kb |
Host | smart-951f8509-f545-4aa4-86c6-28fdfbbb62c2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2276346973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2276346973 |
Directory | /workspace/21.hmac_smoke/latest |
Test location | /workspace/coverage/default/21.hmac_stress_all.772009940 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 3030325901 ps |
CPU time | 154.67 seconds |
Started | Apr 16 02:04:19 PM PDT 24 |
Finished | Apr 16 02:06:54 PM PDT 24 |
Peak memory | 240656 kb |
Host | smart-f77b5841-2903-48b6-b1e8-da309555143f |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772009940 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.772009940 |
Directory | /workspace/21.hmac_stress_all/latest |
Test location | /workspace/coverage/default/21.hmac_test_hmac_vectors.6137673 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 211188433 ps |
CPU time | 0.97 seconds |
Started | Apr 16 02:04:15 PM PDT 24 |
Finished | Apr 16 02:04:16 PM PDT 24 |
Peak memory | 199144 kb |
Host | smart-a6948db3-2d2d-485b-ad1f-0c952cca6ea4 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6137673 -assert nopostproc +UVM_TESTNAME=hmac_base_te st +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 21.hmac_test_hmac_vectors.6137673 |
Directory | /workspace/21.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/21.hmac_test_sha_vectors.1742044488 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 181608945022 ps |
CPU time | 549.26 seconds |
Started | Apr 16 02:04:19 PM PDT 24 |
Finished | Apr 16 02:13:30 PM PDT 24 |
Peak memory | 199684 kb |
Host | smart-ba3e41ab-032c-4dcf-a7b1-40eb15036c40 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742044488 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.1742044488 |
Directory | /workspace/21.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/21.hmac_wipe_secret.2567013974 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 369013782 ps |
CPU time | 10.74 seconds |
Started | Apr 16 02:04:20 PM PDT 24 |
Finished | Apr 16 02:04:32 PM PDT 24 |
Peak memory | 199548 kb |
Host | smart-9da9559f-38df-4e82-9010-d3c93dfffa8a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2567013974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2567013974 |
Directory | /workspace/21.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/22.hmac_alert_test.855041603 |
Short name | T578 |
Test name | |
Test status | |
Simulation time | 31920979 ps |
CPU time | 0.58 seconds |
Started | Apr 16 02:04:21 PM PDT 24 |
Finished | Apr 16 02:04:23 PM PDT 24 |
Peak memory | 194148 kb |
Host | smart-111abe60-f288-4b32-ad8f-e1a054fa441b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855041603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.855041603 |
Directory | /workspace/22.hmac_alert_test/latest |
Test location | /workspace/coverage/default/22.hmac_back_pressure.2499204137 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 5441739151 ps |
CPU time | 50.29 seconds |
Started | Apr 16 02:04:17 PM PDT 24 |
Finished | Apr 16 02:05:08 PM PDT 24 |
Peak memory | 212176 kb |
Host | smart-c27a3613-62fb-4e34-a044-258722403c6b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2499204137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2499204137 |
Directory | /workspace/22.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/22.hmac_burst_wr.470170303 |
Short name | T509 |
Test name | |
Test status | |
Simulation time | 313487701 ps |
CPU time | 15.89 seconds |
Started | Apr 16 02:04:18 PM PDT 24 |
Finished | Apr 16 02:04:35 PM PDT 24 |
Peak memory | 199568 kb |
Host | smart-ab044366-74c2-422f-9d64-8bf925ce38e0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=470170303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.470170303 |
Directory | /workspace/22.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/22.hmac_datapath_stress.2872859702 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 618491488 ps |
CPU time | 9.56 seconds |
Started | Apr 16 02:04:17 PM PDT 24 |
Finished | Apr 16 02:04:27 PM PDT 24 |
Peak memory | 199604 kb |
Host | smart-ecebbf81-6b3d-4dfe-833a-6ddd1c7bacfb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2872859702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2872859702 |
Directory | /workspace/22.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/22.hmac_error.3410889917 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 6131295500 ps |
CPU time | 103.78 seconds |
Started | Apr 16 02:04:19 PM PDT 24 |
Finished | Apr 16 02:06:04 PM PDT 24 |
Peak memory | 199752 kb |
Host | smart-13955059-b3c7-4534-98e9-eeb394bbc1a3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410889917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3410889917 |
Directory | /workspace/22.hmac_error/latest |
Test location | /workspace/coverage/default/22.hmac_long_msg.754985026 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 8346285333 ps |
CPU time | 128.23 seconds |
Started | Apr 16 02:04:21 PM PDT 24 |
Finished | Apr 16 02:06:30 PM PDT 24 |
Peak memory | 199728 kb |
Host | smart-315edde1-6f9b-4686-add9-5c6b4b91eded |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=754985026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.754985026 |
Directory | /workspace/22.hmac_long_msg/latest |
Test location | /workspace/coverage/default/22.hmac_smoke.1373157487 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 3172646416 ps |
CPU time | 7.06 seconds |
Started | Apr 16 02:04:19 PM PDT 24 |
Finished | Apr 16 02:04:27 PM PDT 24 |
Peak memory | 199752 kb |
Host | smart-889fd802-ba42-480f-bbec-eeed0aaedd62 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1373157487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1373157487 |
Directory | /workspace/22.hmac_smoke/latest |
Test location | /workspace/coverage/default/22.hmac_stress_all.1529683599 |
Short name | T502 |
Test name | |
Test status | |
Simulation time | 78719811342 ps |
CPU time | 1046.68 seconds |
Started | Apr 16 02:04:17 PM PDT 24 |
Finished | Apr 16 02:21:45 PM PDT 24 |
Peak memory | 240492 kb |
Host | smart-bf5a024b-c2e4-4e82-a9c2-e51454989621 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529683599 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1529683599 |
Directory | /workspace/22.hmac_stress_all/latest |
Test location | /workspace/coverage/default/22.hmac_test_hmac_vectors.1299683777 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 243007729 ps |
CPU time | 1.23 seconds |
Started | Apr 16 02:04:20 PM PDT 24 |
Finished | Apr 16 02:04:23 PM PDT 24 |
Peak memory | 199428 kb |
Host | smart-4c2c3716-0ac6-4974-9781-86ba47c57a14 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299683777 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 22.hmac_test_hmac_vectors.1299683777 |
Directory | /workspace/22.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/22.hmac_test_sha_vectors.1103808227 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 31608412128 ps |
CPU time | 458.69 seconds |
Started | Apr 16 02:04:21 PM PDT 24 |
Finished | Apr 16 02:12:01 PM PDT 24 |
Peak memory | 199748 kb |
Host | smart-d16a4d3b-4f0a-434d-90ef-980cc816ca8e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103808227 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.1103808227 |
Directory | /workspace/22.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/22.hmac_wipe_secret.2720753497 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 22438078428 ps |
CPU time | 100.75 seconds |
Started | Apr 16 02:04:17 PM PDT 24 |
Finished | Apr 16 02:05:59 PM PDT 24 |
Peak memory | 199736 kb |
Host | smart-2f57f2f4-4c5d-432b-bb9b-47e55eea9cf8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2720753497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2720753497 |
Directory | /workspace/22.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/23.hmac_alert_test.4189469079 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 18773178 ps |
CPU time | 0.61 seconds |
Started | Apr 16 02:04:17 PM PDT 24 |
Finished | Apr 16 02:04:19 PM PDT 24 |
Peak memory | 195184 kb |
Host | smart-de8a244c-06a0-4777-8c56-5dcd1f6a89e1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189469079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.4189469079 |
Directory | /workspace/23.hmac_alert_test/latest |
Test location | /workspace/coverage/default/23.hmac_back_pressure.1102914676 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 1427996661 ps |
CPU time | 55.83 seconds |
Started | Apr 16 02:04:16 PM PDT 24 |
Finished | Apr 16 02:05:13 PM PDT 24 |
Peak memory | 219184 kb |
Host | smart-c58e877f-9815-4f1a-b9ed-362a5afaaa1a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1102914676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1102914676 |
Directory | /workspace/23.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/23.hmac_burst_wr.4101778159 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 1106256284 ps |
CPU time | 14.06 seconds |
Started | Apr 16 02:04:15 PM PDT 24 |
Finished | Apr 16 02:04:30 PM PDT 24 |
Peak memory | 199552 kb |
Host | smart-31fb3d97-c6f4-439b-88b4-8141a096d0d6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4101778159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.4101778159 |
Directory | /workspace/23.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/23.hmac_datapath_stress.1389952265 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 8664347782 ps |
CPU time | 125.53 seconds |
Started | Apr 16 02:04:19 PM PDT 24 |
Finished | Apr 16 02:06:26 PM PDT 24 |
Peak memory | 199764 kb |
Host | smart-2b0fda0e-d25b-402c-ae9b-69c6ba079330 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1389952265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1389952265 |
Directory | /workspace/23.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/23.hmac_error.2709317637 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 9556676816 ps |
CPU time | 167.89 seconds |
Started | Apr 16 02:04:17 PM PDT 24 |
Finished | Apr 16 02:07:06 PM PDT 24 |
Peak memory | 199732 kb |
Host | smart-cf6e4b5c-76f1-42f7-aa55-2da57b8b037c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709317637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2709317637 |
Directory | /workspace/23.hmac_error/latest |
Test location | /workspace/coverage/default/23.hmac_long_msg.3116644141 |
Short name | T568 |
Test name | |
Test status | |
Simulation time | 27816869273 ps |
CPU time | 116.3 seconds |
Started | Apr 16 02:04:19 PM PDT 24 |
Finished | Apr 16 02:06:16 PM PDT 24 |
Peak memory | 199732 kb |
Host | smart-c0ba02c8-8ed2-455b-ae6b-ab0dd82f6ea0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3116644141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3116644141 |
Directory | /workspace/23.hmac_long_msg/latest |
Test location | /workspace/coverage/default/23.hmac_smoke.2800483481 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 724926367 ps |
CPU time | 3.13 seconds |
Started | Apr 16 02:04:17 PM PDT 24 |
Finished | Apr 16 02:04:21 PM PDT 24 |
Peak memory | 199580 kb |
Host | smart-1fa70a77-95c8-4d45-8c8d-11c813a3a9ab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2800483481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2800483481 |
Directory | /workspace/23.hmac_smoke/latest |
Test location | /workspace/coverage/default/23.hmac_stress_all.4191878178 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 73444380710 ps |
CPU time | 375.87 seconds |
Started | Apr 16 02:04:17 PM PDT 24 |
Finished | Apr 16 02:10:34 PM PDT 24 |
Peak memory | 232400 kb |
Host | smart-1cc1fd21-261d-424b-bc08-2273c7083d10 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191878178 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.4191878178 |
Directory | /workspace/23.hmac_stress_all/latest |
Test location | /workspace/coverage/default/23.hmac_test_hmac_vectors.1651690462 |
Short name | T555 |
Test name | |
Test status | |
Simulation time | 59030607 ps |
CPU time | 1.24 seconds |
Started | Apr 16 02:04:22 PM PDT 24 |
Finished | Apr 16 02:04:24 PM PDT 24 |
Peak memory | 199536 kb |
Host | smart-b232a5c7-1fd9-45ee-b43f-76c58e98f6ff |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651690462 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 23.hmac_test_hmac_vectors.1651690462 |
Directory | /workspace/23.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/23.hmac_test_sha_vectors.758933239 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 115664360132 ps |
CPU time | 525.47 seconds |
Started | Apr 16 02:04:22 PM PDT 24 |
Finished | Apr 16 02:13:09 PM PDT 24 |
Peak memory | 199616 kb |
Host | smart-69372901-e195-48c1-98bc-d396e022c7cf |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758933239 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.758933239 |
Directory | /workspace/23.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/23.hmac_wipe_secret.2418456044 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 4560994752 ps |
CPU time | 54.07 seconds |
Started | Apr 16 02:04:16 PM PDT 24 |
Finished | Apr 16 02:05:11 PM PDT 24 |
Peak memory | 199700 kb |
Host | smart-9b758e59-0e90-4e97-a7bb-a4c2df783391 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2418456044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2418456044 |
Directory | /workspace/23.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/24.hmac_alert_test.3679008392 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 66556060 ps |
CPU time | 0.61 seconds |
Started | Apr 16 02:04:22 PM PDT 24 |
Finished | Apr 16 02:04:24 PM PDT 24 |
Peak memory | 195176 kb |
Host | smart-5edbd915-b6b2-44e3-83cb-81aca1099ae8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679008392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3679008392 |
Directory | /workspace/24.hmac_alert_test/latest |
Test location | /workspace/coverage/default/24.hmac_back_pressure.1128496237 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 3557814836 ps |
CPU time | 7.38 seconds |
Started | Apr 16 02:04:19 PM PDT 24 |
Finished | Apr 16 02:04:27 PM PDT 24 |
Peak memory | 211592 kb |
Host | smart-d0e87ab8-66de-4af6-a1f7-f2cc92160104 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1128496237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1128496237 |
Directory | /workspace/24.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/24.hmac_burst_wr.4134122171 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 2227151468 ps |
CPU time | 9.17 seconds |
Started | Apr 16 02:04:17 PM PDT 24 |
Finished | Apr 16 02:04:27 PM PDT 24 |
Peak memory | 199608 kb |
Host | smart-0a3eeb35-8e45-46a0-8e03-fc7f99d16c5e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4134122171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.4134122171 |
Directory | /workspace/24.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/24.hmac_datapath_stress.4107292289 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 5822588893 ps |
CPU time | 68.67 seconds |
Started | Apr 16 02:04:22 PM PDT 24 |
Finished | Apr 16 02:05:32 PM PDT 24 |
Peak memory | 199688 kb |
Host | smart-c5b3a499-a041-4487-9569-a4b22083f17e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4107292289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.4107292289 |
Directory | /workspace/24.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/24.hmac_error.3837251225 |
Short name | T541 |
Test name | |
Test status | |
Simulation time | 52138550786 ps |
CPU time | 149.85 seconds |
Started | Apr 16 02:04:19 PM PDT 24 |
Finished | Apr 16 02:06:50 PM PDT 24 |
Peak memory | 199676 kb |
Host | smart-e0443dc8-8125-407f-a4b9-eddd9cd31931 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837251225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3837251225 |
Directory | /workspace/24.hmac_error/latest |
Test location | /workspace/coverage/default/24.hmac_long_msg.2338250204 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 15312746792 ps |
CPU time | 47.07 seconds |
Started | Apr 16 02:04:17 PM PDT 24 |
Finished | Apr 16 02:05:04 PM PDT 24 |
Peak memory | 199648 kb |
Host | smart-3587f10e-c1b3-402d-86a1-326a0322787c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2338250204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2338250204 |
Directory | /workspace/24.hmac_long_msg/latest |
Test location | /workspace/coverage/default/24.hmac_smoke.2410920765 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 2046635062 ps |
CPU time | 3.72 seconds |
Started | Apr 16 02:04:17 PM PDT 24 |
Finished | Apr 16 02:04:22 PM PDT 24 |
Peak memory | 199584 kb |
Host | smart-f3d753f4-fc1e-4be9-846e-053af89b9a80 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2410920765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2410920765 |
Directory | /workspace/24.hmac_smoke/latest |
Test location | /workspace/coverage/default/24.hmac_stress_all.1753545834 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 60440362703 ps |
CPU time | 756.85 seconds |
Started | Apr 16 02:04:19 PM PDT 24 |
Finished | Apr 16 02:16:57 PM PDT 24 |
Peak memory | 199768 kb |
Host | smart-b2054663-bc71-40cd-8946-0b7d7e7d8891 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753545834 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1753545834 |
Directory | /workspace/24.hmac_stress_all/latest |
Test location | /workspace/coverage/default/24.hmac_test_hmac_vectors.4006818937 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 327322843 ps |
CPU time | 1.35 seconds |
Started | Apr 16 02:04:21 PM PDT 24 |
Finished | Apr 16 02:04:23 PM PDT 24 |
Peak memory | 199548 kb |
Host | smart-8d47dbe8-461c-4379-b650-6c090c9c5342 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006818937 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 24.hmac_test_hmac_vectors.4006818937 |
Directory | /workspace/24.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/24.hmac_test_sha_vectors.2409418358 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 7953622493 ps |
CPU time | 409.09 seconds |
Started | Apr 16 02:04:21 PM PDT 24 |
Finished | Apr 16 02:11:11 PM PDT 24 |
Peak memory | 199672 kb |
Host | smart-aaea0576-650b-4bb4-a0a5-1d88fa386885 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409418358 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.2409418358 |
Directory | /workspace/24.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/24.hmac_wipe_secret.1254086191 |
Short name | T580 |
Test name | |
Test status | |
Simulation time | 1652010493 ps |
CPU time | 24.79 seconds |
Started | Apr 16 02:04:19 PM PDT 24 |
Finished | Apr 16 02:04:44 PM PDT 24 |
Peak memory | 199584 kb |
Host | smart-0fc0c7a7-9848-4230-8573-778290dd6340 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1254086191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1254086191 |
Directory | /workspace/24.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/25.hmac_alert_test.3837157629 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 11133862 ps |
CPU time | 0.56 seconds |
Started | Apr 16 02:04:19 PM PDT 24 |
Finished | Apr 16 02:04:21 PM PDT 24 |
Peak memory | 195144 kb |
Host | smart-b671faf3-e5f9-4b8a-8759-15cf95a395f5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837157629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3837157629 |
Directory | /workspace/25.hmac_alert_test/latest |
Test location | /workspace/coverage/default/25.hmac_back_pressure.792166474 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 1980752119 ps |
CPU time | 58.22 seconds |
Started | Apr 16 02:04:24 PM PDT 24 |
Finished | Apr 16 02:05:22 PM PDT 24 |
Peak memory | 223360 kb |
Host | smart-2f791ed0-ad2e-4c16-a720-18b52e81a244 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=792166474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.792166474 |
Directory | /workspace/25.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/25.hmac_burst_wr.2015400933 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 79891620 ps |
CPU time | 3.85 seconds |
Started | Apr 16 02:04:22 PM PDT 24 |
Finished | Apr 16 02:04:27 PM PDT 24 |
Peak memory | 199580 kb |
Host | smart-8e6c711b-a238-451d-bff1-11b205baf8ab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2015400933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2015400933 |
Directory | /workspace/25.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/25.hmac_datapath_stress.1566112190 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 7157807496 ps |
CPU time | 101.49 seconds |
Started | Apr 16 02:04:22 PM PDT 24 |
Finished | Apr 16 02:06:05 PM PDT 24 |
Peak memory | 199756 kb |
Host | smart-b7c0d982-ae00-4183-8639-535565de7804 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1566112190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1566112190 |
Directory | /workspace/25.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/25.hmac_error.4128253312 |
Short name | T526 |
Test name | |
Test status | |
Simulation time | 179285532464 ps |
CPU time | 208.63 seconds |
Started | Apr 16 02:04:21 PM PDT 24 |
Finished | Apr 16 02:07:51 PM PDT 24 |
Peak memory | 199740 kb |
Host | smart-f2ade2d4-4347-4670-aa00-94450223f648 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128253312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.4128253312 |
Directory | /workspace/25.hmac_error/latest |
Test location | /workspace/coverage/default/25.hmac_long_msg.2838295615 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 1933766378 ps |
CPU time | 64.49 seconds |
Started | Apr 16 02:04:22 PM PDT 24 |
Finished | Apr 16 02:05:28 PM PDT 24 |
Peak memory | 199552 kb |
Host | smart-b54d0222-4e6c-414f-90a8-b9da77dd1401 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2838295615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2838295615 |
Directory | /workspace/25.hmac_long_msg/latest |
Test location | /workspace/coverage/default/25.hmac_smoke.3190316877 |
Short name | T563 |
Test name | |
Test status | |
Simulation time | 1439384548 ps |
CPU time | 5.47 seconds |
Started | Apr 16 02:04:22 PM PDT 24 |
Finished | Apr 16 02:04:28 PM PDT 24 |
Peak memory | 199616 kb |
Host | smart-d55c3030-5352-4a6c-9122-97f25291f178 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3190316877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3190316877 |
Directory | /workspace/25.hmac_smoke/latest |
Test location | /workspace/coverage/default/25.hmac_stress_all.1513353053 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 21388507673 ps |
CPU time | 1058.21 seconds |
Started | Apr 16 02:04:22 PM PDT 24 |
Finished | Apr 16 02:22:01 PM PDT 24 |
Peak memory | 248160 kb |
Host | smart-78290ea3-23ce-46f7-a41d-bd55a2cd9b0b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513353053 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1513353053 |
Directory | /workspace/25.hmac_stress_all/latest |
Test location | /workspace/coverage/default/25.hmac_test_hmac_vectors.2958438979 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 60237402 ps |
CPU time | 1.23 seconds |
Started | Apr 16 02:04:20 PM PDT 24 |
Finished | Apr 16 02:04:22 PM PDT 24 |
Peak memory | 199604 kb |
Host | smart-b3f43599-452f-4460-b4fd-20a7fa52e499 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958438979 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 25.hmac_test_hmac_vectors.2958438979 |
Directory | /workspace/25.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/25.hmac_test_sha_vectors.2892713437 |
Short name | T519 |
Test name | |
Test status | |
Simulation time | 8631090677 ps |
CPU time | 462.59 seconds |
Started | Apr 16 02:04:23 PM PDT 24 |
Finished | Apr 16 02:12:06 PM PDT 24 |
Peak memory | 199684 kb |
Host | smart-5569d234-789c-48c8-804a-e57a6aaaf2b6 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892713437 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.2892713437 |
Directory | /workspace/25.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/25.hmac_wipe_secret.264997702 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 1348415038 ps |
CPU time | 59.43 seconds |
Started | Apr 16 02:04:22 PM PDT 24 |
Finished | Apr 16 02:05:22 PM PDT 24 |
Peak memory | 199600 kb |
Host | smart-c23640b7-17d2-41b5-beff-fc29758cecd1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=264997702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.264997702 |
Directory | /workspace/25.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/26.hmac_alert_test.1790195279 |
Short name | T582 |
Test name | |
Test status | |
Simulation time | 18786413 ps |
CPU time | 0.54 seconds |
Started | Apr 16 02:05:34 PM PDT 24 |
Finished | Apr 16 02:05:36 PM PDT 24 |
Peak memory | 194932 kb |
Host | smart-c78874b3-e331-4137-a1ca-956ccc413a22 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790195279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1790195279 |
Directory | /workspace/26.hmac_alert_test/latest |
Test location | /workspace/coverage/default/26.hmac_back_pressure.1340530668 |
Short name | T529 |
Test name | |
Test status | |
Simulation time | 2889140892 ps |
CPU time | 59.02 seconds |
Started | Apr 16 02:04:25 PM PDT 24 |
Finished | Apr 16 02:05:25 PM PDT 24 |
Peak memory | 226276 kb |
Host | smart-b6f54b12-0a0d-4391-8115-ca0745518ede |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1340530668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1340530668 |
Directory | /workspace/26.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/26.hmac_burst_wr.734180260 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 869852795 ps |
CPU time | 41.64 seconds |
Started | Apr 16 02:04:20 PM PDT 24 |
Finished | Apr 16 02:05:03 PM PDT 24 |
Peak memory | 199588 kb |
Host | smart-f9b62977-5548-4fbe-aad6-67f21e1ac19c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=734180260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.734180260 |
Directory | /workspace/26.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/26.hmac_datapath_stress.3604858238 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 442433405 ps |
CPU time | 11.89 seconds |
Started | Apr 16 02:05:34 PM PDT 24 |
Finished | Apr 16 02:05:47 PM PDT 24 |
Peak memory | 199372 kb |
Host | smart-32ad6a09-5e77-4c70-9717-482fdca46007 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3604858238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3604858238 |
Directory | /workspace/26.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/26.hmac_error.1073323713 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 6244040630 ps |
CPU time | 111.26 seconds |
Started | Apr 16 02:04:21 PM PDT 24 |
Finished | Apr 16 02:06:14 PM PDT 24 |
Peak memory | 199696 kb |
Host | smart-1bc69475-fbb2-414d-9118-1b6770496e10 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073323713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1073323713 |
Directory | /workspace/26.hmac_error/latest |
Test location | /workspace/coverage/default/26.hmac_long_msg.2242045302 |
Short name | T584 |
Test name | |
Test status | |
Simulation time | 39280337850 ps |
CPU time | 104.24 seconds |
Started | Apr 16 02:04:19 PM PDT 24 |
Finished | Apr 16 02:06:04 PM PDT 24 |
Peak memory | 199724 kb |
Host | smart-b985e50c-360a-443d-ad9a-ac9f60fb09c0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2242045302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2242045302 |
Directory | /workspace/26.hmac_long_msg/latest |
Test location | /workspace/coverage/default/26.hmac_smoke.4259837337 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 1136590058 ps |
CPU time | 6.99 seconds |
Started | Apr 16 02:04:20 PM PDT 24 |
Finished | Apr 16 02:04:28 PM PDT 24 |
Peak memory | 199604 kb |
Host | smart-d3aff245-400c-4ba4-b9d7-42b10116dccb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4259837337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.4259837337 |
Directory | /workspace/26.hmac_smoke/latest |
Test location | /workspace/coverage/default/26.hmac_stress_all.515238991 |
Short name | T554 |
Test name | |
Test status | |
Simulation time | 23786250244 ps |
CPU time | 317.43 seconds |
Started | Apr 16 02:04:19 PM PDT 24 |
Finished | Apr 16 02:09:38 PM PDT 24 |
Peak memory | 225140 kb |
Host | smart-1efc1f2a-4447-47be-8388-0513af85c82a |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515238991 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.515238991 |
Directory | /workspace/26.hmac_stress_all/latest |
Test location | /workspace/coverage/default/26.hmac_test_hmac_vectors.581818845 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 217424745 ps |
CPU time | 1.25 seconds |
Started | Apr 16 02:04:23 PM PDT 24 |
Finished | Apr 16 02:04:25 PM PDT 24 |
Peak memory | 199508 kb |
Host | smart-f28ab247-0fe7-4094-ab42-994bbe6e5dce |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581818845 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 26.hmac_test_hmac_vectors.581818845 |
Directory | /workspace/26.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/26.hmac_test_sha_vectors.652174528 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 115675875018 ps |
CPU time | 579.37 seconds |
Started | Apr 16 02:04:23 PM PDT 24 |
Finished | Apr 16 02:14:03 PM PDT 24 |
Peak memory | 199676 kb |
Host | smart-fe772404-cd87-41ae-a6d1-02a99feff127 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652174528 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.652174528 |
Directory | /workspace/26.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/26.hmac_wipe_secret.929395991 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 831731699 ps |
CPU time | 2.23 seconds |
Started | Apr 16 02:04:21 PM PDT 24 |
Finished | Apr 16 02:04:25 PM PDT 24 |
Peak memory | 199604 kb |
Host | smart-e1cf2d0e-b96c-45a3-80eb-17d7fddcb3c4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=929395991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.929395991 |
Directory | /workspace/26.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/27.hmac_alert_test.1715199948 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 34991366 ps |
CPU time | 0.53 seconds |
Started | Apr 16 02:05:33 PM PDT 24 |
Finished | Apr 16 02:05:34 PM PDT 24 |
Peak memory | 193908 kb |
Host | smart-2d7d4427-3478-4380-93d6-79df7df64595 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715199948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1715199948 |
Directory | /workspace/27.hmac_alert_test/latest |
Test location | /workspace/coverage/default/27.hmac_back_pressure.2167302754 |
Short name | T550 |
Test name | |
Test status | |
Simulation time | 376358114 ps |
CPU time | 3.62 seconds |
Started | Apr 16 02:04:30 PM PDT 24 |
Finished | Apr 16 02:04:34 PM PDT 24 |
Peak memory | 199588 kb |
Host | smart-45b5ed43-964e-47ad-b428-0640f9d298ce |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2167302754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2167302754 |
Directory | /workspace/27.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/27.hmac_burst_wr.2546163901 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 1233676088 ps |
CPU time | 10.35 seconds |
Started | Apr 16 02:04:26 PM PDT 24 |
Finished | Apr 16 02:04:37 PM PDT 24 |
Peak memory | 199588 kb |
Host | smart-1a857436-8194-4581-9bbe-d9c9be87c07f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2546163901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2546163901 |
Directory | /workspace/27.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/27.hmac_datapath_stress.449913592 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 18936666194 ps |
CPU time | 70.61 seconds |
Started | Apr 16 02:04:28 PM PDT 24 |
Finished | Apr 16 02:05:40 PM PDT 24 |
Peak memory | 199696 kb |
Host | smart-d0027461-0c22-4cb4-82e4-6b49bf284c44 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=449913592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.449913592 |
Directory | /workspace/27.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/27.hmac_error.3082574480 |
Short name | T505 |
Test name | |
Test status | |
Simulation time | 198397990 ps |
CPU time | 11.88 seconds |
Started | Apr 16 02:04:28 PM PDT 24 |
Finished | Apr 16 02:04:41 PM PDT 24 |
Peak memory | 199492 kb |
Host | smart-3eb316c5-db80-44e9-802f-a89682f64141 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082574480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3082574480 |
Directory | /workspace/27.hmac_error/latest |
Test location | /workspace/coverage/default/27.hmac_long_msg.361461456 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 20725688052 ps |
CPU time | 99.67 seconds |
Started | Apr 16 02:04:20 PM PDT 24 |
Finished | Apr 16 02:06:01 PM PDT 24 |
Peak memory | 199680 kb |
Host | smart-94f09436-c2b6-42ef-80cd-4034814e49e8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=361461456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.361461456 |
Directory | /workspace/27.hmac_long_msg/latest |
Test location | /workspace/coverage/default/27.hmac_smoke.1473204528 |
Short name | T544 |
Test name | |
Test status | |
Simulation time | 220353233 ps |
CPU time | 1.93 seconds |
Started | Apr 16 02:04:20 PM PDT 24 |
Finished | Apr 16 02:04:23 PM PDT 24 |
Peak memory | 199608 kb |
Host | smart-7c293a85-edce-46b9-90e4-5b7024c5058b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1473204528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1473204528 |
Directory | /workspace/27.hmac_smoke/latest |
Test location | /workspace/coverage/default/27.hmac_stress_all.2223900550 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 22939259225 ps |
CPU time | 667.6 seconds |
Started | Apr 16 02:04:23 PM PDT 24 |
Finished | Apr 16 02:15:31 PM PDT 24 |
Peak memory | 199740 kb |
Host | smart-1ec9bf4b-471b-4409-b544-bc731116e202 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223900550 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2223900550 |
Directory | /workspace/27.hmac_stress_all/latest |
Test location | /workspace/coverage/default/27.hmac_stress_all_with_rand_reset.2296524201 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 219382326730 ps |
CPU time | 1771.01 seconds |
Started | Apr 16 02:04:27 PM PDT 24 |
Finished | Apr 16 02:33:59 PM PDT 24 |
Peak memory | 257988 kb |
Host | smart-287e6549-c044-4c7d-b38a-43d09524bf97 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2296524201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all_with_rand_reset.2296524201 |
Directory | /workspace/27.hmac_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/27.hmac_test_hmac_vectors.1900828556 |
Short name | T558 |
Test name | |
Test status | |
Simulation time | 106616645 ps |
CPU time | 1.29 seconds |
Started | Apr 16 02:04:28 PM PDT 24 |
Finished | Apr 16 02:04:30 PM PDT 24 |
Peak memory | 199536 kb |
Host | smart-7bdce783-bb12-4525-8212-3175f3f48549 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900828556 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 27.hmac_test_hmac_vectors.1900828556 |
Directory | /workspace/27.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/27.hmac_test_sha_vectors.998414567 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 156891580774 ps |
CPU time | 439.44 seconds |
Started | Apr 16 02:05:34 PM PDT 24 |
Finished | Apr 16 02:12:55 PM PDT 24 |
Peak memory | 199476 kb |
Host | smart-d7ec4b4c-1c6b-4695-8e42-dfe74420cef9 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998414567 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.998414567 |
Directory | /workspace/27.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/28.hmac_alert_test.2579005608 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 41439175 ps |
CPU time | 0.59 seconds |
Started | Apr 16 02:04:31 PM PDT 24 |
Finished | Apr 16 02:04:32 PM PDT 24 |
Peak memory | 195036 kb |
Host | smart-5f6b8add-8a6e-48d6-9b09-39b4f6506199 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579005608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2579005608 |
Directory | /workspace/28.hmac_alert_test/latest |
Test location | /workspace/coverage/default/28.hmac_back_pressure.4098930073 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 754726436 ps |
CPU time | 14.58 seconds |
Started | Apr 16 02:04:28 PM PDT 24 |
Finished | Apr 16 02:04:43 PM PDT 24 |
Peak memory | 215308 kb |
Host | smart-6aa9e172-6d02-4a2f-bcce-a62c7e74b89d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4098930073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.4098930073 |
Directory | /workspace/28.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/28.hmac_burst_wr.3197032019 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 153685541 ps |
CPU time | 7.55 seconds |
Started | Apr 16 02:04:28 PM PDT 24 |
Finished | Apr 16 02:04:36 PM PDT 24 |
Peak memory | 199608 kb |
Host | smart-9ec8de9e-3253-40c4-a1bb-032b46e3a3c2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3197032019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3197032019 |
Directory | /workspace/28.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/28.hmac_datapath_stress.2254992815 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 8260037797 ps |
CPU time | 118.29 seconds |
Started | Apr 16 02:04:27 PM PDT 24 |
Finished | Apr 16 02:06:27 PM PDT 24 |
Peak memory | 199720 kb |
Host | smart-6457cf22-58ad-4984-816e-3d9f898a19f7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2254992815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2254992815 |
Directory | /workspace/28.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/28.hmac_error.1826121780 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 29665142153 ps |
CPU time | 185.37 seconds |
Started | Apr 16 02:04:32 PM PDT 24 |
Finished | Apr 16 02:07:38 PM PDT 24 |
Peak memory | 199744 kb |
Host | smart-cf36c964-a718-4162-9a16-72fba69109da |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826121780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1826121780 |
Directory | /workspace/28.hmac_error/latest |
Test location | /workspace/coverage/default/28.hmac_long_msg.3804350014 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 1907800255 ps |
CPU time | 110.88 seconds |
Started | Apr 16 02:04:31 PM PDT 24 |
Finished | Apr 16 02:06:23 PM PDT 24 |
Peak memory | 199544 kb |
Host | smart-fa158e12-ef03-408a-899d-882f6eeb97b0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3804350014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3804350014 |
Directory | /workspace/28.hmac_long_msg/latest |
Test location | /workspace/coverage/default/28.hmac_smoke.3467167258 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 76138049 ps |
CPU time | 1.31 seconds |
Started | Apr 16 02:04:18 PM PDT 24 |
Finished | Apr 16 02:04:21 PM PDT 24 |
Peak memory | 199512 kb |
Host | smart-50054a45-b7a0-40f7-8bc0-07cd05cc3928 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3467167258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3467167258 |
Directory | /workspace/28.hmac_smoke/latest |
Test location | /workspace/coverage/default/28.hmac_stress_all.1308213786 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 235759804454 ps |
CPU time | 1513.54 seconds |
Started | Apr 16 02:04:28 PM PDT 24 |
Finished | Apr 16 02:29:43 PM PDT 24 |
Peak memory | 240668 kb |
Host | smart-8e789396-66e3-4664-b046-50fa6a402611 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308213786 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.1308213786 |
Directory | /workspace/28.hmac_stress_all/latest |
Test location | /workspace/coverage/default/28.hmac_test_hmac_vectors.730156792 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 28394675 ps |
CPU time | 0.97 seconds |
Started | Apr 16 02:04:29 PM PDT 24 |
Finished | Apr 16 02:04:31 PM PDT 24 |
Peak memory | 197744 kb |
Host | smart-879c9dcd-b542-4235-beac-2ffdce8307d2 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730156792 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 28.hmac_test_hmac_vectors.730156792 |
Directory | /workspace/28.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/28.hmac_test_sha_vectors.3319536157 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 37178281828 ps |
CPU time | 503.07 seconds |
Started | Apr 16 02:04:25 PM PDT 24 |
Finished | Apr 16 02:12:49 PM PDT 24 |
Peak memory | 199668 kb |
Host | smart-e781cb49-11f6-42c7-9676-cd4dbd61268b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319536157 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.3319536157 |
Directory | /workspace/28.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/28.hmac_wipe_secret.2951803574 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 8892214347 ps |
CPU time | 29.3 seconds |
Started | Apr 16 02:04:26 PM PDT 24 |
Finished | Apr 16 02:04:56 PM PDT 24 |
Peak memory | 199712 kb |
Host | smart-b5112158-8197-4e18-acf8-0d7b1e533a7d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2951803574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2951803574 |
Directory | /workspace/28.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/29.hmac_alert_test.1153652242 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 31656712 ps |
CPU time | 0.54 seconds |
Started | Apr 16 02:04:26 PM PDT 24 |
Finished | Apr 16 02:04:27 PM PDT 24 |
Peak memory | 195088 kb |
Host | smart-c94ab772-9964-4808-bc48-549c58bbcece |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153652242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1153652242 |
Directory | /workspace/29.hmac_alert_test/latest |
Test location | /workspace/coverage/default/29.hmac_back_pressure.792593947 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 40152714 ps |
CPU time | 1.66 seconds |
Started | Apr 16 02:04:27 PM PDT 24 |
Finished | Apr 16 02:04:30 PM PDT 24 |
Peak memory | 199600 kb |
Host | smart-0c3cdd16-1af1-49a4-82f8-910bde5252ec |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=792593947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.792593947 |
Directory | /workspace/29.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/29.hmac_burst_wr.3021484299 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 58721450 ps |
CPU time | 3.21 seconds |
Started | Apr 16 02:04:31 PM PDT 24 |
Finished | Apr 16 02:04:35 PM PDT 24 |
Peak memory | 199404 kb |
Host | smart-40650dbf-cc15-4966-8620-9d4e02788bed |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3021484299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3021484299 |
Directory | /workspace/29.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/29.hmac_datapath_stress.3325305013 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 5126233527 ps |
CPU time | 66.13 seconds |
Started | Apr 16 02:04:26 PM PDT 24 |
Finished | Apr 16 02:05:33 PM PDT 24 |
Peak memory | 199708 kb |
Host | smart-5f5f873d-fd9e-47cc-bff0-49ef4a37d289 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3325305013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3325305013 |
Directory | /workspace/29.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/29.hmac_error.505620824 |
Short name | T546 |
Test name | |
Test status | |
Simulation time | 1632191751 ps |
CPU time | 98.98 seconds |
Started | Apr 16 02:04:26 PM PDT 24 |
Finished | Apr 16 02:06:05 PM PDT 24 |
Peak memory | 199624 kb |
Host | smart-7a05f277-5225-46dc-b7fd-775a5a186bbe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505620824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.505620824 |
Directory | /workspace/29.hmac_error/latest |
Test location | /workspace/coverage/default/29.hmac_long_msg.1070609825 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 12604488712 ps |
CPU time | 32.98 seconds |
Started | Apr 16 02:04:28 PM PDT 24 |
Finished | Apr 16 02:05:02 PM PDT 24 |
Peak memory | 199668 kb |
Host | smart-6f08080a-5a03-4f37-847b-28bc4f1c062c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1070609825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1070609825 |
Directory | /workspace/29.hmac_long_msg/latest |
Test location | /workspace/coverage/default/29.hmac_smoke.3656098632 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 385332099 ps |
CPU time | 4.8 seconds |
Started | Apr 16 02:04:27 PM PDT 24 |
Finished | Apr 16 02:04:33 PM PDT 24 |
Peak memory | 199596 kb |
Host | smart-11670a13-ac8f-4d86-bd38-557b3e9ff07e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3656098632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.3656098632 |
Directory | /workspace/29.hmac_smoke/latest |
Test location | /workspace/coverage/default/29.hmac_stress_all.1202057579 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 14741971170 ps |
CPU time | 116.01 seconds |
Started | Apr 16 02:04:25 PM PDT 24 |
Finished | Apr 16 02:06:22 PM PDT 24 |
Peak memory | 199716 kb |
Host | smart-472cfbd9-9f64-4acd-97b6-e9280e997cc3 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202057579 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1202057579 |
Directory | /workspace/29.hmac_stress_all/latest |
Test location | /workspace/coverage/default/29.hmac_test_hmac_vectors.1017887095 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 408052191 ps |
CPU time | 1.34 seconds |
Started | Apr 16 02:04:25 PM PDT 24 |
Finished | Apr 16 02:04:26 PM PDT 24 |
Peak memory | 199588 kb |
Host | smart-8243c6b7-f600-4438-b23b-4c932fe93445 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017887095 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 29.hmac_test_hmac_vectors.1017887095 |
Directory | /workspace/29.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/29.hmac_test_sha_vectors.491728041 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 28826800411 ps |
CPU time | 481.72 seconds |
Started | Apr 16 02:04:27 PM PDT 24 |
Finished | Apr 16 02:12:30 PM PDT 24 |
Peak memory | 199744 kb |
Host | smart-c2412da5-d3ae-4c95-9d65-98f14dd50cd7 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491728041 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.491728041 |
Directory | /workspace/29.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/29.hmac_wipe_secret.3050504698 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 7665692042 ps |
CPU time | 40.39 seconds |
Started | Apr 16 02:04:28 PM PDT 24 |
Finished | Apr 16 02:05:09 PM PDT 24 |
Peak memory | 199680 kb |
Host | smart-ebd2963f-5c37-4b40-8ef6-f9824c5f977f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3050504698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3050504698 |
Directory | /workspace/29.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/3.hmac_alert_test.1764808581 |
Short name | T515 |
Test name | |
Test status | |
Simulation time | 15534581 ps |
CPU time | 0.56 seconds |
Started | Apr 16 02:03:31 PM PDT 24 |
Finished | Apr 16 02:03:34 PM PDT 24 |
Peak memory | 194096 kb |
Host | smart-f8a4a65f-fb75-43ec-964c-bc9e9b55d830 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764808581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1764808581 |
Directory | /workspace/3.hmac_alert_test/latest |
Test location | /workspace/coverage/default/3.hmac_back_pressure.2182491561 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 867043692 ps |
CPU time | 31.13 seconds |
Started | Apr 16 02:03:29 PM PDT 24 |
Finished | Apr 16 02:04:03 PM PDT 24 |
Peak memory | 207812 kb |
Host | smart-ce1e73c9-5ec4-4028-9825-22c5f4742e24 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2182491561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2182491561 |
Directory | /workspace/3.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/3.hmac_burst_wr.728769624 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 1966432716 ps |
CPU time | 48.11 seconds |
Started | Apr 16 02:03:27 PM PDT 24 |
Finished | Apr 16 02:04:18 PM PDT 24 |
Peak memory | 199608 kb |
Host | smart-5b232b91-d983-4da1-b8f0-e9dede19e724 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=728769624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.728769624 |
Directory | /workspace/3.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/3.hmac_datapath_stress.438867852 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 12012148215 ps |
CPU time | 156.86 seconds |
Started | Apr 16 02:03:28 PM PDT 24 |
Finished | Apr 16 02:06:08 PM PDT 24 |
Peak memory | 199768 kb |
Host | smart-0d877e39-1904-4983-8269-978a715ff5f4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=438867852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.438867852 |
Directory | /workspace/3.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/3.hmac_error.3172531004 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 8830266416 ps |
CPU time | 115.53 seconds |
Started | Apr 16 02:03:27 PM PDT 24 |
Finished | Apr 16 02:05:24 PM PDT 24 |
Peak memory | 199748 kb |
Host | smart-b003b27e-19c1-456d-bee0-2f244caf0db1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172531004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.3172531004 |
Directory | /workspace/3.hmac_error/latest |
Test location | /workspace/coverage/default/3.hmac_long_msg.2585866897 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 8552054850 ps |
CPU time | 104.74 seconds |
Started | Apr 16 02:03:23 PM PDT 24 |
Finished | Apr 16 02:05:09 PM PDT 24 |
Peak memory | 199752 kb |
Host | smart-406503b1-0504-4637-9659-c4cf5e22e9e8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2585866897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2585866897 |
Directory | /workspace/3.hmac_long_msg/latest |
Test location | /workspace/coverage/default/3.hmac_smoke.3025463663 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 114397750 ps |
CPU time | 1.99 seconds |
Started | Apr 16 02:03:24 PM PDT 24 |
Finished | Apr 16 02:03:27 PM PDT 24 |
Peak memory | 199612 kb |
Host | smart-6a0e73e2-9572-4012-ba77-338f22cfb7c7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3025463663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3025463663 |
Directory | /workspace/3.hmac_smoke/latest |
Test location | /workspace/coverage/default/3.hmac_stress_all.2696022021 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 256538863770 ps |
CPU time | 891.36 seconds |
Started | Apr 16 02:03:33 PM PDT 24 |
Finished | Apr 16 02:18:26 PM PDT 24 |
Peak memory | 207908 kb |
Host | smart-07b743cd-9218-420c-a21d-f14fdbceef19 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696022021 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.2696022021 |
Directory | /workspace/3.hmac_stress_all/latest |
Test location | /workspace/coverage/default/3.hmac_test_hmac_vectors.2882596253 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 53509332 ps |
CPU time | 1.2 seconds |
Started | Apr 16 02:03:29 PM PDT 24 |
Finished | Apr 16 02:03:33 PM PDT 24 |
Peak memory | 199640 kb |
Host | smart-9ff2107b-b805-447d-9f2e-73a9b7cbe1b5 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882596253 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 3.hmac_test_hmac_vectors.2882596253 |
Directory | /workspace/3.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/3.hmac_test_sha_vectors.912625765 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 280323476524 ps |
CPU time | 489 seconds |
Started | Apr 16 02:03:28 PM PDT 24 |
Finished | Apr 16 02:11:40 PM PDT 24 |
Peak memory | 199712 kb |
Host | smart-ecc8426b-d710-4fb3-b69b-a8939174a54c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912625765 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.912625765 |
Directory | /workspace/3.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/3.hmac_wipe_secret.3884740864 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 15896945198 ps |
CPU time | 57.83 seconds |
Started | Apr 16 02:03:28 PM PDT 24 |
Finished | Apr 16 02:04:28 PM PDT 24 |
Peak memory | 199744 kb |
Host | smart-0e1a4a43-5a5f-48af-9871-85f01ddb9d1d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3884740864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3884740864 |
Directory | /workspace/3.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/30.hmac_alert_test.2568151189 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 28386896 ps |
CPU time | 0.54 seconds |
Started | Apr 16 02:04:34 PM PDT 24 |
Finished | Apr 16 02:04:35 PM PDT 24 |
Peak memory | 195168 kb |
Host | smart-d7e09a43-0e0e-4e5f-8015-f4bcd550ae1c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568151189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2568151189 |
Directory | /workspace/30.hmac_alert_test/latest |
Test location | /workspace/coverage/default/30.hmac_back_pressure.3282849987 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 572139316 ps |
CPU time | 23.14 seconds |
Started | Apr 16 02:04:37 PM PDT 24 |
Finished | Apr 16 02:05:01 PM PDT 24 |
Peak memory | 215580 kb |
Host | smart-aee1ea12-3a6a-4e01-b459-d572d3efdd27 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3282849987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3282849987 |
Directory | /workspace/30.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/30.hmac_burst_wr.3962656333 |
Short name | T535 |
Test name | |
Test status | |
Simulation time | 2010446116 ps |
CPU time | 51.56 seconds |
Started | Apr 16 02:04:35 PM PDT 24 |
Finished | Apr 16 02:05:27 PM PDT 24 |
Peak memory | 199624 kb |
Host | smart-b521f45b-d9d3-4120-9062-5bce5fb7fdb4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3962656333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3962656333 |
Directory | /workspace/30.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/30.hmac_datapath_stress.3321370210 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 1499050811 ps |
CPU time | 44.66 seconds |
Started | Apr 16 02:04:34 PM PDT 24 |
Finished | Apr 16 02:05:20 PM PDT 24 |
Peak memory | 199588 kb |
Host | smart-89fe9943-d86d-42f4-8ebb-ffa363fd661d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3321370210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3321370210 |
Directory | /workspace/30.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/30.hmac_error.3067427621 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 4309072722 ps |
CPU time | 95.95 seconds |
Started | Apr 16 02:04:33 PM PDT 24 |
Finished | Apr 16 02:06:09 PM PDT 24 |
Peak memory | 199760 kb |
Host | smart-f9a31ae8-62b3-4fea-9243-20f05cd603b4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067427621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3067427621 |
Directory | /workspace/30.hmac_error/latest |
Test location | /workspace/coverage/default/30.hmac_long_msg.1384778106 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 10329207487 ps |
CPU time | 37.58 seconds |
Started | Apr 16 02:04:36 PM PDT 24 |
Finished | Apr 16 02:05:14 PM PDT 24 |
Peak memory | 199708 kb |
Host | smart-350e37e2-a332-4f8c-8ff4-561d97022ffe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1384778106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1384778106 |
Directory | /workspace/30.hmac_long_msg/latest |
Test location | /workspace/coverage/default/30.hmac_smoke.3736274107 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 320669953 ps |
CPU time | 4.89 seconds |
Started | Apr 16 02:04:26 PM PDT 24 |
Finished | Apr 16 02:04:31 PM PDT 24 |
Peak memory | 199512 kb |
Host | smart-b333988c-ae43-4a4a-886d-ff0db466982a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3736274107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3736274107 |
Directory | /workspace/30.hmac_smoke/latest |
Test location | /workspace/coverage/default/30.hmac_stress_all.4125662264 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 67259188856 ps |
CPU time | 961 seconds |
Started | Apr 16 02:04:36 PM PDT 24 |
Finished | Apr 16 02:20:38 PM PDT 24 |
Peak memory | 231508 kb |
Host | smart-3fc45e4e-b2bc-4acc-acfc-99592d321b09 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125662264 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.4125662264 |
Directory | /workspace/30.hmac_stress_all/latest |
Test location | /workspace/coverage/default/30.hmac_test_hmac_vectors.1473500184 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 143629309 ps |
CPU time | 1.04 seconds |
Started | Apr 16 02:04:33 PM PDT 24 |
Finished | Apr 16 02:04:35 PM PDT 24 |
Peak memory | 198504 kb |
Host | smart-ea0a9818-e514-4899-8a76-a988f55ba653 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473500184 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 30.hmac_test_hmac_vectors.1473500184 |
Directory | /workspace/30.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/30.hmac_test_sha_vectors.1170935757 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 120235775825 ps |
CPU time | 476.35 seconds |
Started | Apr 16 02:04:42 PM PDT 24 |
Finished | Apr 16 02:12:39 PM PDT 24 |
Peak memory | 199740 kb |
Host | smart-af11ad17-376c-4532-9761-110d55c00792 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170935757 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.1170935757 |
Directory | /workspace/30.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/30.hmac_wipe_secret.724236353 |
Short name | T506 |
Test name | |
Test status | |
Simulation time | 20592840456 ps |
CPU time | 75.25 seconds |
Started | Apr 16 02:04:37 PM PDT 24 |
Finished | Apr 16 02:05:53 PM PDT 24 |
Peak memory | 199732 kb |
Host | smart-150942f4-d55a-453d-88ce-79676a80d56e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=724236353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.724236353 |
Directory | /workspace/30.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/31.hmac_alert_test.692817604 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 44181414 ps |
CPU time | 0.59 seconds |
Started | Apr 16 02:04:38 PM PDT 24 |
Finished | Apr 16 02:04:39 PM PDT 24 |
Peak memory | 195120 kb |
Host | smart-d89aeefd-7c9a-4884-9e40-afe76ebaa4d0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692817604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.692817604 |
Directory | /workspace/31.hmac_alert_test/latest |
Test location | /workspace/coverage/default/31.hmac_back_pressure.586232829 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 1539210406 ps |
CPU time | 35.42 seconds |
Started | Apr 16 02:04:34 PM PDT 24 |
Finished | Apr 16 02:05:10 PM PDT 24 |
Peak memory | 207796 kb |
Host | smart-207e058d-2ed7-4bbb-8327-b8590a1a057d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=586232829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.586232829 |
Directory | /workspace/31.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/31.hmac_burst_wr.4061783328 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 930057340 ps |
CPU time | 43.84 seconds |
Started | Apr 16 02:04:32 PM PDT 24 |
Finished | Apr 16 02:05:16 PM PDT 24 |
Peak memory | 199516 kb |
Host | smart-18eda6fc-fa88-43d1-879e-3df309ded778 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4061783328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.4061783328 |
Directory | /workspace/31.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/31.hmac_datapath_stress.3985965184 |
Short name | T587 |
Test name | |
Test status | |
Simulation time | 1200439989 ps |
CPU time | 71.29 seconds |
Started | Apr 16 02:04:33 PM PDT 24 |
Finished | Apr 16 02:05:46 PM PDT 24 |
Peak memory | 199556 kb |
Host | smart-b9ae0b29-5253-4221-a2d2-651d6253ef95 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3985965184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3985965184 |
Directory | /workspace/31.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/31.hmac_error.1263155132 |
Short name | T549 |
Test name | |
Test status | |
Simulation time | 24663140124 ps |
CPU time | 92.99 seconds |
Started | Apr 16 02:04:33 PM PDT 24 |
Finished | Apr 16 02:06:07 PM PDT 24 |
Peak memory | 199740 kb |
Host | smart-20336082-7b4c-4e5e-b940-0cb053a86ea3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263155132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1263155132 |
Directory | /workspace/31.hmac_error/latest |
Test location | /workspace/coverage/default/31.hmac_long_msg.2336331475 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 12151051130 ps |
CPU time | 45.93 seconds |
Started | Apr 16 02:04:34 PM PDT 24 |
Finished | Apr 16 02:05:21 PM PDT 24 |
Peak memory | 199744 kb |
Host | smart-88fd8512-4f9c-43b1-a90e-a643decb6915 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2336331475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.2336331475 |
Directory | /workspace/31.hmac_long_msg/latest |
Test location | /workspace/coverage/default/31.hmac_smoke.2647082305 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 700285229 ps |
CPU time | 5.81 seconds |
Started | Apr 16 02:04:36 PM PDT 24 |
Finished | Apr 16 02:04:42 PM PDT 24 |
Peak memory | 199616 kb |
Host | smart-a0c8f41b-4c7b-4610-a82b-c759d0cae3e3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2647082305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2647082305 |
Directory | /workspace/31.hmac_smoke/latest |
Test location | /workspace/coverage/default/31.hmac_stress_all.1203626858 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 82371970551 ps |
CPU time | 612.41 seconds |
Started | Apr 16 02:04:33 PM PDT 24 |
Finished | Apr 16 02:14:47 PM PDT 24 |
Peak memory | 199672 kb |
Host | smart-e88ac4e2-f2c0-4446-a966-22db4435bdfa |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203626858 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1203626858 |
Directory | /workspace/31.hmac_stress_all/latest |
Test location | /workspace/coverage/default/31.hmac_test_hmac_vectors.1035188700 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 29370741 ps |
CPU time | 1 seconds |
Started | Apr 16 02:04:42 PM PDT 24 |
Finished | Apr 16 02:04:44 PM PDT 24 |
Peak memory | 198000 kb |
Host | smart-474e0b38-b1ce-4d63-bd4c-1e215287248b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035188700 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 31.hmac_test_hmac_vectors.1035188700 |
Directory | /workspace/31.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/31.hmac_test_sha_vectors.1652649265 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 41638301719 ps |
CPU time | 529.33 seconds |
Started | Apr 16 02:04:37 PM PDT 24 |
Finished | Apr 16 02:13:27 PM PDT 24 |
Peak memory | 199708 kb |
Host | smart-d527688b-6f8a-45fc-a431-4079884fa0bf |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652649265 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.1652649265 |
Directory | /workspace/31.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/31.hmac_wipe_secret.3429533177 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 801710459 ps |
CPU time | 4.47 seconds |
Started | Apr 16 02:04:33 PM PDT 24 |
Finished | Apr 16 02:04:39 PM PDT 24 |
Peak memory | 199636 kb |
Host | smart-5e5183e9-7506-4336-b3fb-0cfdf20720c2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3429533177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.3429533177 |
Directory | /workspace/31.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/32.hmac_alert_test.1332964154 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 20881410 ps |
CPU time | 0.59 seconds |
Started | Apr 16 02:04:42 PM PDT 24 |
Finished | Apr 16 02:04:43 PM PDT 24 |
Peak memory | 195172 kb |
Host | smart-9e4bf535-cc73-4e8f-84b6-dbd5de30508f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332964154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1332964154 |
Directory | /workspace/32.hmac_alert_test/latest |
Test location | /workspace/coverage/default/32.hmac_back_pressure.1624468672 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 6193449283 ps |
CPU time | 65.96 seconds |
Started | Apr 16 02:04:38 PM PDT 24 |
Finished | Apr 16 02:05:44 PM PDT 24 |
Peak memory | 221168 kb |
Host | smart-46c1998f-c580-4ea3-b724-82c16df1f2a5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1624468672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1624468672 |
Directory | /workspace/32.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/32.hmac_burst_wr.1372936950 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 3328120466 ps |
CPU time | 24.32 seconds |
Started | Apr 16 02:04:37 PM PDT 24 |
Finished | Apr 16 02:05:02 PM PDT 24 |
Peak memory | 199740 kb |
Host | smart-55109781-35c7-4138-bc84-5ef9e9d1a448 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1372936950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1372936950 |
Directory | /workspace/32.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/32.hmac_datapath_stress.1042300626 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 33613897 ps |
CPU time | 1.58 seconds |
Started | Apr 16 02:04:34 PM PDT 24 |
Finished | Apr 16 02:04:37 PM PDT 24 |
Peak memory | 199624 kb |
Host | smart-9390a873-a95c-473e-a0ec-e2e19475caff |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1042300626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1042300626 |
Directory | /workspace/32.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/32.hmac_error.1384994612 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 72678466984 ps |
CPU time | 187.39 seconds |
Started | Apr 16 02:04:35 PM PDT 24 |
Finished | Apr 16 02:07:44 PM PDT 24 |
Peak memory | 199764 kb |
Host | smart-eafa9c51-bc79-497a-95be-7fd64d6faeed |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384994612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1384994612 |
Directory | /workspace/32.hmac_error/latest |
Test location | /workspace/coverage/default/32.hmac_long_msg.320231638 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 1160536519 ps |
CPU time | 73.56 seconds |
Started | Apr 16 02:04:42 PM PDT 24 |
Finished | Apr 16 02:05:57 PM PDT 24 |
Peak memory | 199600 kb |
Host | smart-1aed8361-2577-4157-9e56-e060074f7340 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=320231638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.320231638 |
Directory | /workspace/32.hmac_long_msg/latest |
Test location | /workspace/coverage/default/32.hmac_smoke.1989120699 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 1911614051 ps |
CPU time | 1.85 seconds |
Started | Apr 16 02:04:35 PM PDT 24 |
Finished | Apr 16 02:04:38 PM PDT 24 |
Peak memory | 199644 kb |
Host | smart-0a04c5fd-e4a4-4a1b-b4ca-a4556bc4f2df |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1989120699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1989120699 |
Directory | /workspace/32.hmac_smoke/latest |
Test location | /workspace/coverage/default/32.hmac_stress_all.3211966355 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 1781766926 ps |
CPU time | 6.84 seconds |
Started | Apr 16 02:04:37 PM PDT 24 |
Finished | Apr 16 02:04:45 PM PDT 24 |
Peak memory | 199584 kb |
Host | smart-d984e830-2d9b-4d2c-9b96-89ac48494790 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211966355 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.3211966355 |
Directory | /workspace/32.hmac_stress_all/latest |
Test location | /workspace/coverage/default/32.hmac_test_hmac_vectors.3596887790 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 51528537 ps |
CPU time | 1.1 seconds |
Started | Apr 16 02:04:34 PM PDT 24 |
Finished | Apr 16 02:04:36 PM PDT 24 |
Peak memory | 198856 kb |
Host | smart-ee748eb9-e7ac-46af-bb30-fa7ccdf28642 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596887790 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 32.hmac_test_hmac_vectors.3596887790 |
Directory | /workspace/32.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/32.hmac_test_sha_vectors.3164364556 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 29283252688 ps |
CPU time | 520.01 seconds |
Started | Apr 16 02:04:33 PM PDT 24 |
Finished | Apr 16 02:13:14 PM PDT 24 |
Peak memory | 199696 kb |
Host | smart-40eb7718-8482-4b59-b244-aab1d4162217 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164364556 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.3164364556 |
Directory | /workspace/32.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/32.hmac_wipe_secret.2501891856 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 5787425547 ps |
CPU time | 19.5 seconds |
Started | Apr 16 02:04:32 PM PDT 24 |
Finished | Apr 16 02:04:52 PM PDT 24 |
Peak memory | 199708 kb |
Host | smart-aec26f57-5f9a-4c00-aa3d-9d1a45a3c744 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2501891856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.2501891856 |
Directory | /workspace/32.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/33.hmac_alert_test.3499114114 |
Short name | T504 |
Test name | |
Test status | |
Simulation time | 147591555 ps |
CPU time | 0.58 seconds |
Started | Apr 16 02:04:40 PM PDT 24 |
Finished | Apr 16 02:04:42 PM PDT 24 |
Peak memory | 194880 kb |
Host | smart-c25b6e7c-432b-4dc9-9af7-bfaca206fea7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499114114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3499114114 |
Directory | /workspace/33.hmac_alert_test/latest |
Test location | /workspace/coverage/default/33.hmac_back_pressure.4129292993 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 4903052860 ps |
CPU time | 26.58 seconds |
Started | Apr 16 02:04:42 PM PDT 24 |
Finished | Apr 16 02:05:10 PM PDT 24 |
Peak memory | 215864 kb |
Host | smart-3ac09f65-cbea-45f5-a62a-f400a26dbe71 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4129292993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.4129292993 |
Directory | /workspace/33.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/33.hmac_burst_wr.3643012413 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 276252708 ps |
CPU time | 13.5 seconds |
Started | Apr 16 02:04:39 PM PDT 24 |
Finished | Apr 16 02:04:54 PM PDT 24 |
Peak memory | 199600 kb |
Host | smart-b94d3a62-6e9c-4673-93f8-42062d775244 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3643012413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3643012413 |
Directory | /workspace/33.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/33.hmac_datapath_stress.3403250282 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 784571894 ps |
CPU time | 43.66 seconds |
Started | Apr 16 02:04:38 PM PDT 24 |
Finished | Apr 16 02:05:22 PM PDT 24 |
Peak memory | 199556 kb |
Host | smart-3ab6e7e0-ddcc-4121-836e-2250fa078b39 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3403250282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3403250282 |
Directory | /workspace/33.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/33.hmac_error.3570123380 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 18617693214 ps |
CPU time | 180.06 seconds |
Started | Apr 16 02:04:42 PM PDT 24 |
Finished | Apr 16 02:07:43 PM PDT 24 |
Peak memory | 199704 kb |
Host | smart-7ce3bc3c-5723-48ad-a906-5e733036c7f5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570123380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.3570123380 |
Directory | /workspace/33.hmac_error/latest |
Test location | /workspace/coverage/default/33.hmac_long_msg.3214188749 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 465894429 ps |
CPU time | 28.84 seconds |
Started | Apr 16 02:04:37 PM PDT 24 |
Finished | Apr 16 02:05:07 PM PDT 24 |
Peak memory | 199592 kb |
Host | smart-b45596ff-47b9-4f0d-a82e-dc5d40dedf1e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3214188749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3214188749 |
Directory | /workspace/33.hmac_long_msg/latest |
Test location | /workspace/coverage/default/33.hmac_smoke.4142539971 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 398534559 ps |
CPU time | 5.78 seconds |
Started | Apr 16 02:04:38 PM PDT 24 |
Finished | Apr 16 02:04:45 PM PDT 24 |
Peak memory | 199564 kb |
Host | smart-30d7baae-583a-4241-8536-ccbc380dbaec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4142539971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.4142539971 |
Directory | /workspace/33.hmac_smoke/latest |
Test location | /workspace/coverage/default/33.hmac_stress_all.1258722227 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 1045434997497 ps |
CPU time | 832.68 seconds |
Started | Apr 16 02:04:43 PM PDT 24 |
Finished | Apr 16 02:18:36 PM PDT 24 |
Peak memory | 199736 kb |
Host | smart-3edf4abd-91de-47c3-8917-614ddc1d86a9 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258722227 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.1258722227 |
Directory | /workspace/33.hmac_stress_all/latest |
Test location | /workspace/coverage/default/33.hmac_test_hmac_vectors.4215889848 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 35345563 ps |
CPU time | 1.25 seconds |
Started | Apr 16 02:04:40 PM PDT 24 |
Finished | Apr 16 02:04:43 PM PDT 24 |
Peak memory | 199592 kb |
Host | smart-14380503-b31b-4193-a220-8160d911cd9c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215889848 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 33.hmac_test_hmac_vectors.4215889848 |
Directory | /workspace/33.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/33.hmac_test_sha_vectors.878380728 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 223227133046 ps |
CPU time | 462.1 seconds |
Started | Apr 16 02:04:39 PM PDT 24 |
Finished | Apr 16 02:12:23 PM PDT 24 |
Peak memory | 199696 kb |
Host | smart-e5c92f86-c6bd-4bb9-a2f1-39c71f25da4c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878380728 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.878380728 |
Directory | /workspace/33.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/33.hmac_wipe_secret.2148029229 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 11199353841 ps |
CPU time | 55.86 seconds |
Started | Apr 16 02:04:41 PM PDT 24 |
Finished | Apr 16 02:05:38 PM PDT 24 |
Peak memory | 199728 kb |
Host | smart-1ce4f2fc-e07d-4703-b420-3ea4436ab22a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2148029229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2148029229 |
Directory | /workspace/33.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/34.hmac_alert_test.1628091545 |
Short name | T547 |
Test name | |
Test status | |
Simulation time | 43996743 ps |
CPU time | 0.59 seconds |
Started | Apr 16 02:04:39 PM PDT 24 |
Finished | Apr 16 02:04:41 PM PDT 24 |
Peak memory | 195176 kb |
Host | smart-012ec4be-7e17-43f3-b527-949676e2fceb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628091545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1628091545 |
Directory | /workspace/34.hmac_alert_test/latest |
Test location | /workspace/coverage/default/34.hmac_back_pressure.3702148524 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 1336263765 ps |
CPU time | 10.77 seconds |
Started | Apr 16 02:04:40 PM PDT 24 |
Finished | Apr 16 02:04:52 PM PDT 24 |
Peak memory | 199600 kb |
Host | smart-7d405316-db3b-4066-9fa1-6c23da587910 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3702148524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3702148524 |
Directory | /workspace/34.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/34.hmac_burst_wr.514946921 |
Short name | T511 |
Test name | |
Test status | |
Simulation time | 2629658416 ps |
CPU time | 39.86 seconds |
Started | Apr 16 02:04:40 PM PDT 24 |
Finished | Apr 16 02:05:21 PM PDT 24 |
Peak memory | 199724 kb |
Host | smart-4fd8292e-93fb-4f6f-b57d-e6ad19df2f7c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=514946921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.514946921 |
Directory | /workspace/34.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/34.hmac_datapath_stress.1802866167 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 9526292185 ps |
CPU time | 116.84 seconds |
Started | Apr 16 02:04:39 PM PDT 24 |
Finished | Apr 16 02:06:37 PM PDT 24 |
Peak memory | 199728 kb |
Host | smart-f4edd9b4-a6d7-4e3c-b348-5c1ad0fdd4fc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1802866167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1802866167 |
Directory | /workspace/34.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/34.hmac_error.1513398847 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 8508870665 ps |
CPU time | 33.43 seconds |
Started | Apr 16 02:04:40 PM PDT 24 |
Finished | Apr 16 02:05:14 PM PDT 24 |
Peak memory | 199720 kb |
Host | smart-49621db5-8bc8-4c9f-8983-ef2d1f7e9dea |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513398847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1513398847 |
Directory | /workspace/34.hmac_error/latest |
Test location | /workspace/coverage/default/34.hmac_long_msg.3668964414 |
Short name | T572 |
Test name | |
Test status | |
Simulation time | 4603356195 ps |
CPU time | 62.5 seconds |
Started | Apr 16 02:04:38 PM PDT 24 |
Finished | Apr 16 02:05:42 PM PDT 24 |
Peak memory | 199700 kb |
Host | smart-c98aa000-9ec7-403d-9214-d899407bab69 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3668964414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3668964414 |
Directory | /workspace/34.hmac_long_msg/latest |
Test location | /workspace/coverage/default/34.hmac_smoke.3036445294 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 123103340 ps |
CPU time | 2.04 seconds |
Started | Apr 16 02:04:40 PM PDT 24 |
Finished | Apr 16 02:04:44 PM PDT 24 |
Peak memory | 199548 kb |
Host | smart-9510f14e-856a-4570-aa6a-076e91b3506d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3036445294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3036445294 |
Directory | /workspace/34.hmac_smoke/latest |
Test location | /workspace/coverage/default/34.hmac_stress_all.2202141064 |
Short name | T516 |
Test name | |
Test status | |
Simulation time | 43984870648 ps |
CPU time | 827.14 seconds |
Started | Apr 16 02:04:42 PM PDT 24 |
Finished | Apr 16 02:18:30 PM PDT 24 |
Peak memory | 240692 kb |
Host | smart-c362076b-a0bd-4c85-9162-c4df0353be6e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202141064 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2202141064 |
Directory | /workspace/34.hmac_stress_all/latest |
Test location | /workspace/coverage/default/34.hmac_stress_all_with_rand_reset.3839274454 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 34800811911 ps |
CPU time | 651.3 seconds |
Started | Apr 16 02:04:40 PM PDT 24 |
Finished | Apr 16 02:15:32 PM PDT 24 |
Peak memory | 240756 kb |
Host | smart-afc9286d-e1d3-4e76-88f8-dda722f3769d |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3839274454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all_with_rand_reset.3839274454 |
Directory | /workspace/34.hmac_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/34.hmac_test_hmac_vectors.4197808788 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 39568160 ps |
CPU time | 1.02 seconds |
Started | Apr 16 02:04:41 PM PDT 24 |
Finished | Apr 16 02:04:43 PM PDT 24 |
Peak memory | 198004 kb |
Host | smart-2f893912-30d3-4949-b4d4-822c6e731e83 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197808788 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 34.hmac_test_hmac_vectors.4197808788 |
Directory | /workspace/34.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/34.hmac_test_sha_vectors.241133252 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 46558930484 ps |
CPU time | 439.93 seconds |
Started | Apr 16 02:04:39 PM PDT 24 |
Finished | Apr 16 02:12:00 PM PDT 24 |
Peak memory | 199704 kb |
Host | smart-fa48fca0-2c0a-4428-8e1f-0c50f2b3ae5c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241133252 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.241133252 |
Directory | /workspace/34.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/34.hmac_wipe_secret.1857810678 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 2356704203 ps |
CPU time | 42.96 seconds |
Started | Apr 16 02:04:38 PM PDT 24 |
Finished | Apr 16 02:05:22 PM PDT 24 |
Peak memory | 199744 kb |
Host | smart-c5e208f9-df25-4bf2-8761-2beba6e71ee3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1857810678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1857810678 |
Directory | /workspace/34.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/35.hmac_alert_test.2584559267 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 30743221 ps |
CPU time | 0.61 seconds |
Started | Apr 16 02:04:52 PM PDT 24 |
Finished | Apr 16 02:04:53 PM PDT 24 |
Peak memory | 195104 kb |
Host | smart-33782b66-d094-4e15-9ca6-39be92f12094 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584559267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2584559267 |
Directory | /workspace/35.hmac_alert_test/latest |
Test location | /workspace/coverage/default/35.hmac_back_pressure.352408220 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 1568128614 ps |
CPU time | 28.8 seconds |
Started | Apr 16 02:04:40 PM PDT 24 |
Finished | Apr 16 02:05:10 PM PDT 24 |
Peak memory | 220212 kb |
Host | smart-bdef3c4f-ff97-4aab-be7c-c77fce121ae8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=352408220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.352408220 |
Directory | /workspace/35.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/35.hmac_burst_wr.3293908967 |
Short name | T564 |
Test name | |
Test status | |
Simulation time | 3091075589 ps |
CPU time | 64.45 seconds |
Started | Apr 16 02:04:40 PM PDT 24 |
Finished | Apr 16 02:05:46 PM PDT 24 |
Peak memory | 199724 kb |
Host | smart-5254c7de-9f1e-44cc-b065-c0266c5ae40c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3293908967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3293908967 |
Directory | /workspace/35.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/35.hmac_datapath_stress.3701965015 |
Short name | T574 |
Test name | |
Test status | |
Simulation time | 700647845 ps |
CPU time | 41.97 seconds |
Started | Apr 16 02:04:37 PM PDT 24 |
Finished | Apr 16 02:05:20 PM PDT 24 |
Peak memory | 199580 kb |
Host | smart-7db6f99d-d5a2-4bf4-8a91-a256c9aac159 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3701965015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3701965015 |
Directory | /workspace/35.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/35.hmac_error.2875610606 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 40749401830 ps |
CPU time | 280.54 seconds |
Started | Apr 16 02:04:40 PM PDT 24 |
Finished | Apr 16 02:09:22 PM PDT 24 |
Peak memory | 199744 kb |
Host | smart-e1031beb-7a1f-4a83-932a-f62c941ae79c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875610606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2875610606 |
Directory | /workspace/35.hmac_error/latest |
Test location | /workspace/coverage/default/35.hmac_long_msg.2422177465 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 239391249 ps |
CPU time | 7.12 seconds |
Started | Apr 16 02:04:39 PM PDT 24 |
Finished | Apr 16 02:04:47 PM PDT 24 |
Peak memory | 199540 kb |
Host | smart-51a52397-0afa-4f37-bd98-c9db0f93e96d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2422177465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.2422177465 |
Directory | /workspace/35.hmac_long_msg/latest |
Test location | /workspace/coverage/default/35.hmac_smoke.1424204998 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 2133958615 ps |
CPU time | 3.01 seconds |
Started | Apr 16 02:04:37 PM PDT 24 |
Finished | Apr 16 02:04:41 PM PDT 24 |
Peak memory | 199604 kb |
Host | smart-bdb0f345-33bf-4bcb-8cbe-2471f20f52de |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1424204998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.1424204998 |
Directory | /workspace/35.hmac_smoke/latest |
Test location | /workspace/coverage/default/35.hmac_stress_all.2267165080 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 21821134792 ps |
CPU time | 602.25 seconds |
Started | Apr 16 02:04:51 PM PDT 24 |
Finished | Apr 16 02:14:55 PM PDT 24 |
Peak memory | 199672 kb |
Host | smart-4f80895e-45b9-4a38-8016-e9e2ded61b81 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267165080 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2267165080 |
Directory | /workspace/35.hmac_stress_all/latest |
Test location | /workspace/coverage/default/35.hmac_test_hmac_vectors.1172276173 |
Short name | T551 |
Test name | |
Test status | |
Simulation time | 112136849 ps |
CPU time | 1.22 seconds |
Started | Apr 16 02:04:50 PM PDT 24 |
Finished | Apr 16 02:04:52 PM PDT 24 |
Peak memory | 199292 kb |
Host | smart-3ff06dfe-c6ad-420d-b128-813296bbbf31 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172276173 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 35.hmac_test_hmac_vectors.1172276173 |
Directory | /workspace/35.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/35.hmac_test_sha_vectors.4154484562 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 29142895974 ps |
CPU time | 501.83 seconds |
Started | Apr 16 02:04:53 PM PDT 24 |
Finished | Apr 16 02:13:16 PM PDT 24 |
Peak memory | 199700 kb |
Host | smart-02c44521-84b0-4fda-b0f1-70e2e838649b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154484562 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.4154484562 |
Directory | /workspace/35.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/35.hmac_wipe_secret.2816304035 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 10178127763 ps |
CPU time | 48.21 seconds |
Started | Apr 16 02:04:39 PM PDT 24 |
Finished | Apr 16 02:05:28 PM PDT 24 |
Peak memory | 199708 kb |
Host | smart-d2ca9d1f-4b70-4dac-a64c-48692852ff89 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2816304035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2816304035 |
Directory | /workspace/35.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/36.hmac_alert_test.117524883 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 16596945 ps |
CPU time | 0.59 seconds |
Started | Apr 16 02:04:52 PM PDT 24 |
Finished | Apr 16 02:04:54 PM PDT 24 |
Peak memory | 195192 kb |
Host | smart-cedd6e75-e735-4c55-b4da-5178c71d2892 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117524883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.117524883 |
Directory | /workspace/36.hmac_alert_test/latest |
Test location | /workspace/coverage/default/36.hmac_back_pressure.4084314593 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 1626001846 ps |
CPU time | 6.33 seconds |
Started | Apr 16 02:04:52 PM PDT 24 |
Finished | Apr 16 02:05:00 PM PDT 24 |
Peak memory | 199616 kb |
Host | smart-adcecb36-361a-4bfd-9c28-386fa8e390b6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4084314593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.4084314593 |
Directory | /workspace/36.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/36.hmac_burst_wr.3529932185 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 9900943573 ps |
CPU time | 40.47 seconds |
Started | Apr 16 02:04:52 PM PDT 24 |
Finished | Apr 16 02:05:34 PM PDT 24 |
Peak memory | 199716 kb |
Host | smart-32c631de-e2be-48bb-9efc-edcb7fdb07a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3529932185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3529932185 |
Directory | /workspace/36.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/36.hmac_datapath_stress.3078402258 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 1530714424 ps |
CPU time | 65.63 seconds |
Started | Apr 16 02:04:53 PM PDT 24 |
Finished | Apr 16 02:06:00 PM PDT 24 |
Peak memory | 199600 kb |
Host | smart-63ea8c06-571c-4932-9a15-96fbb202e1d0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3078402258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3078402258 |
Directory | /workspace/36.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/36.hmac_error.3676441832 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 38492877075 ps |
CPU time | 141.63 seconds |
Started | Apr 16 02:04:49 PM PDT 24 |
Finished | Apr 16 02:07:11 PM PDT 24 |
Peak memory | 199700 kb |
Host | smart-ffc32261-143d-4667-b43a-fbe206a32c91 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676441832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3676441832 |
Directory | /workspace/36.hmac_error/latest |
Test location | /workspace/coverage/default/36.hmac_long_msg.1967192572 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 5232643230 ps |
CPU time | 87.37 seconds |
Started | Apr 16 02:04:51 PM PDT 24 |
Finished | Apr 16 02:06:19 PM PDT 24 |
Peak memory | 199696 kb |
Host | smart-bb221641-c9e8-4ed7-aab6-7a9dbf1a0646 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1967192572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1967192572 |
Directory | /workspace/36.hmac_long_msg/latest |
Test location | /workspace/coverage/default/36.hmac_smoke.3333324738 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 192559011 ps |
CPU time | 5.98 seconds |
Started | Apr 16 02:04:52 PM PDT 24 |
Finished | Apr 16 02:05:00 PM PDT 24 |
Peak memory | 199620 kb |
Host | smart-a24b21d3-a9a7-474e-a33f-ccc1df7814a5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3333324738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.3333324738 |
Directory | /workspace/36.hmac_smoke/latest |
Test location | /workspace/coverage/default/36.hmac_test_hmac_vectors.3957085509 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 34520257 ps |
CPU time | 1.22 seconds |
Started | Apr 16 02:04:53 PM PDT 24 |
Finished | Apr 16 02:04:56 PM PDT 24 |
Peak memory | 199536 kb |
Host | smart-76c84063-47a8-4f65-821d-40ba152bcc2f |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957085509 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 36.hmac_test_hmac_vectors.3957085509 |
Directory | /workspace/36.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/36.hmac_test_sha_vectors.3602199812 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 40915606600 ps |
CPU time | 527.86 seconds |
Started | Apr 16 02:04:51 PM PDT 24 |
Finished | Apr 16 02:13:41 PM PDT 24 |
Peak memory | 199712 kb |
Host | smart-5ca8e598-b5c8-47a3-a7bb-85cca5238288 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602199812 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.3602199812 |
Directory | /workspace/36.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/36.hmac_wipe_secret.2976469252 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 10015832772 ps |
CPU time | 25.16 seconds |
Started | Apr 16 02:04:53 PM PDT 24 |
Finished | Apr 16 02:05:20 PM PDT 24 |
Peak memory | 199736 kb |
Host | smart-281f6b1d-13b8-4a70-83be-fad865f0eab6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2976469252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2976469252 |
Directory | /workspace/36.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/37.hmac_alert_test.2732069787 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 43810716 ps |
CPU time | 0.58 seconds |
Started | Apr 16 02:04:52 PM PDT 24 |
Finished | Apr 16 02:04:53 PM PDT 24 |
Peak memory | 194844 kb |
Host | smart-3bfc0429-e951-4cb0-bbaf-b5720fa906b8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732069787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2732069787 |
Directory | /workspace/37.hmac_alert_test/latest |
Test location | /workspace/coverage/default/37.hmac_back_pressure.166020254 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 1472213778 ps |
CPU time | 36.38 seconds |
Started | Apr 16 02:04:51 PM PDT 24 |
Finished | Apr 16 02:05:28 PM PDT 24 |
Peak memory | 215664 kb |
Host | smart-eccc52b8-717e-4616-81fe-d043d9c25d3f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=166020254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.166020254 |
Directory | /workspace/37.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/37.hmac_burst_wr.3478538424 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 458244731 ps |
CPU time | 11.3 seconds |
Started | Apr 16 02:04:51 PM PDT 24 |
Finished | Apr 16 02:05:04 PM PDT 24 |
Peak memory | 199600 kb |
Host | smart-e69e8b60-50c7-4d64-857f-8c3510d889ba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3478538424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3478538424 |
Directory | /workspace/37.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/37.hmac_datapath_stress.1190890832 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 372702886 ps |
CPU time | 19.85 seconds |
Started | Apr 16 02:04:51 PM PDT 24 |
Finished | Apr 16 02:05:12 PM PDT 24 |
Peak memory | 199584 kb |
Host | smart-3e1a8a2e-d3ba-4077-a7ab-68ac9e98fc92 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1190890832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1190890832 |
Directory | /workspace/37.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/37.hmac_error.4243823815 |
Short name | T556 |
Test name | |
Test status | |
Simulation time | 26820938412 ps |
CPU time | 75.61 seconds |
Started | Apr 16 02:04:53 PM PDT 24 |
Finished | Apr 16 02:06:10 PM PDT 24 |
Peak memory | 199752 kb |
Host | smart-d9b5ad1e-1983-45ac-bc68-1c1ab36d65d0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243823815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.4243823815 |
Directory | /workspace/37.hmac_error/latest |
Test location | /workspace/coverage/default/37.hmac_long_msg.1102677024 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 1080251228 ps |
CPU time | 11.26 seconds |
Started | Apr 16 02:04:50 PM PDT 24 |
Finished | Apr 16 02:05:02 PM PDT 24 |
Peak memory | 199584 kb |
Host | smart-1a332e1c-993f-4eb6-a58b-45793caa16ef |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1102677024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1102677024 |
Directory | /workspace/37.hmac_long_msg/latest |
Test location | /workspace/coverage/default/37.hmac_smoke.3028133097 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 1575784693 ps |
CPU time | 4.98 seconds |
Started | Apr 16 02:04:51 PM PDT 24 |
Finished | Apr 16 02:04:58 PM PDT 24 |
Peak memory | 199592 kb |
Host | smart-112a1c80-7b83-4d3d-9283-ed8417642294 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3028133097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3028133097 |
Directory | /workspace/37.hmac_smoke/latest |
Test location | /workspace/coverage/default/37.hmac_stress_all.3169996511 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 100213376943 ps |
CPU time | 441.77 seconds |
Started | Apr 16 02:04:53 PM PDT 24 |
Finished | Apr 16 02:12:16 PM PDT 24 |
Peak memory | 199752 kb |
Host | smart-4f6709ca-05d3-4d17-a9a8-2064921fabf0 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169996511 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3169996511 |
Directory | /workspace/37.hmac_stress_all/latest |
Test location | /workspace/coverage/default/37.hmac_test_hmac_vectors.1350059248 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 108987824 ps |
CPU time | 1.26 seconds |
Started | Apr 16 02:04:53 PM PDT 24 |
Finished | Apr 16 02:04:56 PM PDT 24 |
Peak memory | 199596 kb |
Host | smart-72501941-3c0f-40d9-aae6-85239e5a0abe |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350059248 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 37.hmac_test_hmac_vectors.1350059248 |
Directory | /workspace/37.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/37.hmac_test_sha_vectors.320234328 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 115013573724 ps |
CPU time | 561.16 seconds |
Started | Apr 16 02:04:55 PM PDT 24 |
Finished | Apr 16 02:14:17 PM PDT 24 |
Peak memory | 199744 kb |
Host | smart-5a1d39cd-8d22-4904-b37c-ac3947dca4be |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320234328 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.320234328 |
Directory | /workspace/37.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/37.hmac_wipe_secret.906894848 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 3183845103 ps |
CPU time | 43.7 seconds |
Started | Apr 16 02:04:54 PM PDT 24 |
Finished | Apr 16 02:05:39 PM PDT 24 |
Peak memory | 199712 kb |
Host | smart-54017001-469a-4862-8a32-77f869f5b86f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=906894848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.906894848 |
Directory | /workspace/37.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/38.hmac_alert_test.4162233569 |
Short name | T579 |
Test name | |
Test status | |
Simulation time | 23169893 ps |
CPU time | 0.58 seconds |
Started | Apr 16 02:04:54 PM PDT 24 |
Finished | Apr 16 02:04:56 PM PDT 24 |
Peak memory | 194104 kb |
Host | smart-ff9524d2-11a8-4686-a632-eaa0707309fa |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162233569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.4162233569 |
Directory | /workspace/38.hmac_alert_test/latest |
Test location | /workspace/coverage/default/38.hmac_back_pressure.2562039147 |
Short name | T561 |
Test name | |
Test status | |
Simulation time | 160386605 ps |
CPU time | 4.75 seconds |
Started | Apr 16 02:04:52 PM PDT 24 |
Finished | Apr 16 02:04:58 PM PDT 24 |
Peak memory | 199584 kb |
Host | smart-f1e257d8-13f6-498f-b39b-250579ab12cf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2562039147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2562039147 |
Directory | /workspace/38.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/38.hmac_burst_wr.2166579889 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 24746837139 ps |
CPU time | 38.75 seconds |
Started | Apr 16 02:04:51 PM PDT 24 |
Finished | Apr 16 02:05:32 PM PDT 24 |
Peak memory | 199648 kb |
Host | smart-51851d43-9b88-4410-88e8-3ee4bce32b47 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2166579889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.2166579889 |
Directory | /workspace/38.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/38.hmac_datapath_stress.2147869778 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 1152511245 ps |
CPU time | 66.47 seconds |
Started | Apr 16 02:04:52 PM PDT 24 |
Finished | Apr 16 02:06:00 PM PDT 24 |
Peak memory | 199580 kb |
Host | smart-b9aeb309-0518-44b1-bb1f-00025033121d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2147869778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2147869778 |
Directory | /workspace/38.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/38.hmac_error.2016137646 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 41854088776 ps |
CPU time | 92.5 seconds |
Started | Apr 16 02:04:54 PM PDT 24 |
Finished | Apr 16 02:06:28 PM PDT 24 |
Peak memory | 199752 kb |
Host | smart-f055d345-10be-4244-8f20-a7381a1b1daa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016137646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2016137646 |
Directory | /workspace/38.hmac_error/latest |
Test location | /workspace/coverage/default/38.hmac_long_msg.513784299 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 1216258926 ps |
CPU time | 75.36 seconds |
Started | Apr 16 02:04:54 PM PDT 24 |
Finished | Apr 16 02:06:11 PM PDT 24 |
Peak memory | 199584 kb |
Host | smart-ec9691a5-ed04-491c-80d3-284d8411a120 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=513784299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.513784299 |
Directory | /workspace/38.hmac_long_msg/latest |
Test location | /workspace/coverage/default/38.hmac_smoke.699391880 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 79068386 ps |
CPU time | 2.5 seconds |
Started | Apr 16 02:04:50 PM PDT 24 |
Finished | Apr 16 02:04:53 PM PDT 24 |
Peak memory | 199548 kb |
Host | smart-86d23b42-b75d-4b15-b3f5-bf1f15566312 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=699391880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.699391880 |
Directory | /workspace/38.hmac_smoke/latest |
Test location | /workspace/coverage/default/38.hmac_stress_all.301199662 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 110962059998 ps |
CPU time | 683.67 seconds |
Started | Apr 16 02:04:50 PM PDT 24 |
Finished | Apr 16 02:16:15 PM PDT 24 |
Peak memory | 199716 kb |
Host | smart-d529039e-3e04-41f4-91b0-e8697f7944d7 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301199662 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.301199662 |
Directory | /workspace/38.hmac_stress_all/latest |
Test location | /workspace/coverage/default/38.hmac_test_hmac_vectors.2983147803 |
Short name | T508 |
Test name | |
Test status | |
Simulation time | 76601691 ps |
CPU time | 1.04 seconds |
Started | Apr 16 02:04:50 PM PDT 24 |
Finished | Apr 16 02:04:52 PM PDT 24 |
Peak memory | 198828 kb |
Host | smart-030280e2-d021-4661-8286-50d825362bb7 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983147803 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 38.hmac_test_hmac_vectors.2983147803 |
Directory | /workspace/38.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/38.hmac_test_sha_vectors.1867179285 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 8266881004 ps |
CPU time | 473.12 seconds |
Started | Apr 16 02:04:50 PM PDT 24 |
Finished | Apr 16 02:12:44 PM PDT 24 |
Peak memory | 199760 kb |
Host | smart-a7e935ef-ac6d-4c99-9ce5-84d47a42d495 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867179285 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.1867179285 |
Directory | /workspace/38.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/38.hmac_wipe_secret.534438247 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 874405823 ps |
CPU time | 42.36 seconds |
Started | Apr 16 02:04:50 PM PDT 24 |
Finished | Apr 16 02:05:33 PM PDT 24 |
Peak memory | 199556 kb |
Host | smart-c7c0a759-a3a5-404f-b98f-d1cf596c43b7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=534438247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.534438247 |
Directory | /workspace/38.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/39.hmac_alert_test.1677263495 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 31514353 ps |
CPU time | 0.63 seconds |
Started | Apr 16 02:04:56 PM PDT 24 |
Finished | Apr 16 02:04:57 PM PDT 24 |
Peak memory | 195148 kb |
Host | smart-f49145ca-70e8-4874-9b2a-fce85b0034b1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677263495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1677263495 |
Directory | /workspace/39.hmac_alert_test/latest |
Test location | /workspace/coverage/default/39.hmac_back_pressure.1171935055 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 1049014770 ps |
CPU time | 37.12 seconds |
Started | Apr 16 02:04:50 PM PDT 24 |
Finished | Apr 16 02:05:28 PM PDT 24 |
Peak memory | 215932 kb |
Host | smart-e75606ac-d4e2-4655-a786-95e58ecb995c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1171935055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1171935055 |
Directory | /workspace/39.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/39.hmac_burst_wr.2692408525 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 6083594707 ps |
CPU time | 30.66 seconds |
Started | Apr 16 02:04:56 PM PDT 24 |
Finished | Apr 16 02:05:28 PM PDT 24 |
Peak memory | 199704 kb |
Host | smart-4fc470b1-5279-4d85-8931-3c3f778a82ce |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2692408525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2692408525 |
Directory | /workspace/39.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/39.hmac_datapath_stress.1687540169 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 2313059873 ps |
CPU time | 128.33 seconds |
Started | Apr 16 02:04:49 PM PDT 24 |
Finished | Apr 16 02:06:58 PM PDT 24 |
Peak memory | 199720 kb |
Host | smart-03eacea5-822c-4aa1-b2a5-0ea176ac2334 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1687540169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1687540169 |
Directory | /workspace/39.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/39.hmac_error.280507272 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 1842089631 ps |
CPU time | 34.41 seconds |
Started | Apr 16 02:04:52 PM PDT 24 |
Finished | Apr 16 02:05:27 PM PDT 24 |
Peak memory | 199600 kb |
Host | smart-18e831c1-18cc-40b3-97d9-34ee3842eb5c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280507272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.280507272 |
Directory | /workspace/39.hmac_error/latest |
Test location | /workspace/coverage/default/39.hmac_long_msg.2692137013 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 20948951573 ps |
CPU time | 63.43 seconds |
Started | Apr 16 02:04:52 PM PDT 24 |
Finished | Apr 16 02:05:57 PM PDT 24 |
Peak memory | 199720 kb |
Host | smart-8bb4d75b-e468-468d-8534-7c518d4f9280 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2692137013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.2692137013 |
Directory | /workspace/39.hmac_long_msg/latest |
Test location | /workspace/coverage/default/39.hmac_smoke.1039530793 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 712390886 ps |
CPU time | 5.87 seconds |
Started | Apr 16 02:04:54 PM PDT 24 |
Finished | Apr 16 02:05:01 PM PDT 24 |
Peak memory | 199556 kb |
Host | smart-6e27f93f-c912-4724-82f8-ad95ddf7d7ca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1039530793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1039530793 |
Directory | /workspace/39.hmac_smoke/latest |
Test location | /workspace/coverage/default/39.hmac_stress_all.3732553477 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 10231375294 ps |
CPU time | 116.15 seconds |
Started | Apr 16 02:04:54 PM PDT 24 |
Finished | Apr 16 02:06:52 PM PDT 24 |
Peak memory | 199724 kb |
Host | smart-525b9e4b-c169-4a07-8798-04b3044ad4fe |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732553477 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3732553477 |
Directory | /workspace/39.hmac_stress_all/latest |
Test location | /workspace/coverage/default/39.hmac_test_hmac_vectors.4231734486 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 64627817 ps |
CPU time | 1.18 seconds |
Started | Apr 16 02:05:02 PM PDT 24 |
Finished | Apr 16 02:05:05 PM PDT 24 |
Peak memory | 199528 kb |
Host | smart-42f5d35e-fe23-4c7f-9ab0-9558ad041a85 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231734486 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 39.hmac_test_hmac_vectors.4231734486 |
Directory | /workspace/39.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/39.hmac_test_sha_vectors.1724686301 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 31086940265 ps |
CPU time | 408.23 seconds |
Started | Apr 16 02:04:55 PM PDT 24 |
Finished | Apr 16 02:11:45 PM PDT 24 |
Peak memory | 199704 kb |
Host | smart-45629f3a-9705-4cce-a986-31d9885b2f29 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724686301 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.1724686301 |
Directory | /workspace/39.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/39.hmac_wipe_secret.2992432145 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 20387917225 ps |
CPU time | 95.46 seconds |
Started | Apr 16 02:04:50 PM PDT 24 |
Finished | Apr 16 02:06:26 PM PDT 24 |
Peak memory | 199736 kb |
Host | smart-d559e17a-2ba4-458c-bb2b-60235ac9b645 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2992432145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2992432145 |
Directory | /workspace/39.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/4.hmac_alert_test.4049391063 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 11495129 ps |
CPU time | 0.57 seconds |
Started | Apr 16 02:03:25 PM PDT 24 |
Finished | Apr 16 02:03:27 PM PDT 24 |
Peak memory | 195076 kb |
Host | smart-0dba9400-93b0-4ff5-b560-473bee173e9e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049391063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.4049391063 |
Directory | /workspace/4.hmac_alert_test/latest |
Test location | /workspace/coverage/default/4.hmac_back_pressure.1815504871 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 4279405292 ps |
CPU time | 39.65 seconds |
Started | Apr 16 02:03:31 PM PDT 24 |
Finished | Apr 16 02:04:13 PM PDT 24 |
Peak memory | 214320 kb |
Host | smart-524d1850-48b7-45a3-96d4-26e35f38086c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1815504871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1815504871 |
Directory | /workspace/4.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/4.hmac_burst_wr.2122812884 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 5170515376 ps |
CPU time | 64.34 seconds |
Started | Apr 16 02:03:28 PM PDT 24 |
Finished | Apr 16 02:04:34 PM PDT 24 |
Peak memory | 199752 kb |
Host | smart-89f2c9a3-e6ec-463d-a3f3-e9b32e0f59ac |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2122812884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2122812884 |
Directory | /workspace/4.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/4.hmac_datapath_stress.2528714413 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 4490808763 ps |
CPU time | 129.68 seconds |
Started | Apr 16 02:03:34 PM PDT 24 |
Finished | Apr 16 02:05:45 PM PDT 24 |
Peak memory | 199712 kb |
Host | smart-226e816e-1d8e-430f-8bc5-075fa64fd165 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2528714413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2528714413 |
Directory | /workspace/4.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/4.hmac_error.657188129 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 6389155220 ps |
CPU time | 84.64 seconds |
Started | Apr 16 02:03:25 PM PDT 24 |
Finished | Apr 16 02:04:51 PM PDT 24 |
Peak memory | 199700 kb |
Host | smart-13bf6414-f931-41b8-a783-b9ac53f9890b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657188129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.657188129 |
Directory | /workspace/4.hmac_error/latest |
Test location | /workspace/coverage/default/4.hmac_long_msg.1410606622 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 12222590912 ps |
CPU time | 82.53 seconds |
Started | Apr 16 02:03:27 PM PDT 24 |
Finished | Apr 16 02:04:52 PM PDT 24 |
Peak memory | 199664 kb |
Host | smart-94a76993-979d-4449-b4b5-30d884aec02d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1410606622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1410606622 |
Directory | /workspace/4.hmac_long_msg/latest |
Test location | /workspace/coverage/default/4.hmac_sec_cm.2846513900 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 131891418 ps |
CPU time | 0.82 seconds |
Started | Apr 16 02:03:27 PM PDT 24 |
Finished | Apr 16 02:03:31 PM PDT 24 |
Peak memory | 218192 kb |
Host | smart-2745bf3e-e34d-44ab-8f50-4ac5855b6056 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846513900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2846513900 |
Directory | /workspace/4.hmac_sec_cm/latest |
Test location | /workspace/coverage/default/4.hmac_smoke.2322463887 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 53798890 ps |
CPU time | 0.9 seconds |
Started | Apr 16 02:03:27 PM PDT 24 |
Finished | Apr 16 02:03:31 PM PDT 24 |
Peak memory | 199384 kb |
Host | smart-98a40456-fb68-47dd-80c7-7629f82523f2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2322463887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2322463887 |
Directory | /workspace/4.hmac_smoke/latest |
Test location | /workspace/coverage/default/4.hmac_stress_all.4249320482 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 36169937823 ps |
CPU time | 247.47 seconds |
Started | Apr 16 02:03:40 PM PDT 24 |
Finished | Apr 16 02:07:49 PM PDT 24 |
Peak memory | 199716 kb |
Host | smart-6dffb345-a4d4-4c2e-bb4e-ab27e3b0927b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249320482 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.4249320482 |
Directory | /workspace/4.hmac_stress_all/latest |
Test location | /workspace/coverage/default/4.hmac_test_hmac_vectors.309376645 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 30482357 ps |
CPU time | 1.1 seconds |
Started | Apr 16 02:03:28 PM PDT 24 |
Finished | Apr 16 02:03:31 PM PDT 24 |
Peak memory | 198580 kb |
Host | smart-bbea6cc2-f1d4-4284-b4ff-449d70fca397 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309376645 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 4.hmac_test_hmac_vectors.309376645 |
Directory | /workspace/4.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/4.hmac_test_sha_vectors.3367125023 |
Short name | T559 |
Test name | |
Test status | |
Simulation time | 159480698957 ps |
CPU time | 467.59 seconds |
Started | Apr 16 02:03:29 PM PDT 24 |
Finished | Apr 16 02:11:19 PM PDT 24 |
Peak memory | 199724 kb |
Host | smart-3442f916-01fc-4847-a35d-4866858161ce |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367125023 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.3367125023 |
Directory | /workspace/4.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/4.hmac_wipe_secret.495388663 |
Short name | T597 |
Test name | |
Test status | |
Simulation time | 3736259513 ps |
CPU time | 76.63 seconds |
Started | Apr 16 02:03:31 PM PDT 24 |
Finished | Apr 16 02:04:50 PM PDT 24 |
Peak memory | 199576 kb |
Host | smart-d872906e-0e50-4215-8c6a-b9986b1aefa9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=495388663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.495388663 |
Directory | /workspace/4.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/40.hmac_alert_test.3808257168 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 16721397 ps |
CPU time | 0.55 seconds |
Started | Apr 16 02:04:56 PM PDT 24 |
Finished | Apr 16 02:04:58 PM PDT 24 |
Peak memory | 194076 kb |
Host | smart-4ae67479-8eb9-4425-9cbd-93837a0b7308 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808257168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3808257168 |
Directory | /workspace/40.hmac_alert_test/latest |
Test location | /workspace/coverage/default/40.hmac_back_pressure.1206936583 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 2648700538 ps |
CPU time | 58.17 seconds |
Started | Apr 16 02:04:57 PM PDT 24 |
Finished | Apr 16 02:05:55 PM PDT 24 |
Peak memory | 225344 kb |
Host | smart-191e8a8c-9f7c-4ca3-ba7a-7887016632ed |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1206936583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1206936583 |
Directory | /workspace/40.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/40.hmac_burst_wr.1830752216 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 75149778 ps |
CPU time | 3.88 seconds |
Started | Apr 16 02:04:56 PM PDT 24 |
Finished | Apr 16 02:05:01 PM PDT 24 |
Peak memory | 199564 kb |
Host | smart-73245de9-45d6-43c3-aebb-2ca720158072 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1830752216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1830752216 |
Directory | /workspace/40.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/40.hmac_datapath_stress.3967167205 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 3740357025 ps |
CPU time | 65.77 seconds |
Started | Apr 16 02:04:56 PM PDT 24 |
Finished | Apr 16 02:06:02 PM PDT 24 |
Peak memory | 199468 kb |
Host | smart-f212326d-efd3-498c-96e5-c5f9b4780e34 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3967167205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3967167205 |
Directory | /workspace/40.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/40.hmac_error.3874006451 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 12239111790 ps |
CPU time | 215.73 seconds |
Started | Apr 16 02:04:53 PM PDT 24 |
Finished | Apr 16 02:08:31 PM PDT 24 |
Peak memory | 199740 kb |
Host | smart-0533c9c5-369f-48ee-b4ef-713abb767bdc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874006451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3874006451 |
Directory | /workspace/40.hmac_error/latest |
Test location | /workspace/coverage/default/40.hmac_long_msg.1942584156 |
Short name | T523 |
Test name | |
Test status | |
Simulation time | 5153236934 ps |
CPU time | 96.94 seconds |
Started | Apr 16 02:05:02 PM PDT 24 |
Finished | Apr 16 02:06:40 PM PDT 24 |
Peak memory | 199736 kb |
Host | smart-dfb89a2a-b1c4-4cb6-8be8-cf97ce0153c1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1942584156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1942584156 |
Directory | /workspace/40.hmac_long_msg/latest |
Test location | /workspace/coverage/default/40.hmac_smoke.3275417705 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 2103873613 ps |
CPU time | 6.33 seconds |
Started | Apr 16 02:04:56 PM PDT 24 |
Finished | Apr 16 02:05:03 PM PDT 24 |
Peak memory | 199616 kb |
Host | smart-e75d991f-c109-4051-b8f5-269d09e6a882 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3275417705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.3275417705 |
Directory | /workspace/40.hmac_smoke/latest |
Test location | /workspace/coverage/default/40.hmac_stress_all.936162446 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 74063348359 ps |
CPU time | 2025.34 seconds |
Started | Apr 16 02:04:56 PM PDT 24 |
Finished | Apr 16 02:38:42 PM PDT 24 |
Peak memory | 199708 kb |
Host | smart-e0ebfec3-44bc-4708-916e-56ca9d61e2e2 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936162446 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.936162446 |
Directory | /workspace/40.hmac_stress_all/latest |
Test location | /workspace/coverage/default/40.hmac_test_hmac_vectors.3431638025 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 26132900 ps |
CPU time | 0.97 seconds |
Started | Apr 16 02:05:01 PM PDT 24 |
Finished | Apr 16 02:05:03 PM PDT 24 |
Peak memory | 198552 kb |
Host | smart-541d6e47-5721-4995-8f18-56202c6bca17 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431638025 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 40.hmac_test_hmac_vectors.3431638025 |
Directory | /workspace/40.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/40.hmac_test_sha_vectors.3740938362 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 35541234569 ps |
CPU time | 441.05 seconds |
Started | Apr 16 02:04:59 PM PDT 24 |
Finished | Apr 16 02:12:20 PM PDT 24 |
Peak memory | 199708 kb |
Host | smart-c734797b-0775-415a-bd62-ec6938f1daee |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740938362 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.3740938362 |
Directory | /workspace/40.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/40.hmac_wipe_secret.3497199585 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 196055385 ps |
CPU time | 2.72 seconds |
Started | Apr 16 02:04:55 PM PDT 24 |
Finished | Apr 16 02:04:59 PM PDT 24 |
Peak memory | 199620 kb |
Host | smart-5ed008a3-bef4-4ea6-880a-f299a57ffad6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3497199585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.3497199585 |
Directory | /workspace/40.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/41.hmac_alert_test.2742120918 |
Short name | T532 |
Test name | |
Test status | |
Simulation time | 27554004 ps |
CPU time | 0.58 seconds |
Started | Apr 16 02:05:03 PM PDT 24 |
Finished | Apr 16 02:05:05 PM PDT 24 |
Peak memory | 194860 kb |
Host | smart-cfc1955a-b93e-4cb4-8574-53da00013f24 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742120918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2742120918 |
Directory | /workspace/41.hmac_alert_test/latest |
Test location | /workspace/coverage/default/41.hmac_back_pressure.2118746059 |
Short name | T590 |
Test name | |
Test status | |
Simulation time | 291544108 ps |
CPU time | 5.72 seconds |
Started | Apr 16 02:05:01 PM PDT 24 |
Finished | Apr 16 02:05:08 PM PDT 24 |
Peak memory | 207792 kb |
Host | smart-6520fe74-abcc-4543-af3d-23ffd8da5583 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2118746059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2118746059 |
Directory | /workspace/41.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/41.hmac_burst_wr.2454621928 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 11214113390 ps |
CPU time | 41.73 seconds |
Started | Apr 16 02:04:58 PM PDT 24 |
Finished | Apr 16 02:05:40 PM PDT 24 |
Peak memory | 199652 kb |
Host | smart-1b331696-5c66-4543-88c8-cfc968763765 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2454621928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2454621928 |
Directory | /workspace/41.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/41.hmac_datapath_stress.2971419847 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 9162593465 ps |
CPU time | 103.54 seconds |
Started | Apr 16 02:05:00 PM PDT 24 |
Finished | Apr 16 02:06:45 PM PDT 24 |
Peak memory | 199940 kb |
Host | smart-5fcc9856-eb3e-4a2b-a875-bdecfc23850e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2971419847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2971419847 |
Directory | /workspace/41.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/41.hmac_error.4174100226 |
Short name | T565 |
Test name | |
Test status | |
Simulation time | 61483592739 ps |
CPU time | 199.62 seconds |
Started | Apr 16 02:05:00 PM PDT 24 |
Finished | Apr 16 02:08:20 PM PDT 24 |
Peak memory | 199760 kb |
Host | smart-09e3444d-c6ca-4244-93d3-6bac34835f19 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174100226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.4174100226 |
Directory | /workspace/41.hmac_error/latest |
Test location | /workspace/coverage/default/41.hmac_long_msg.3671118763 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 7746388004 ps |
CPU time | 13.31 seconds |
Started | Apr 16 02:04:56 PM PDT 24 |
Finished | Apr 16 02:05:10 PM PDT 24 |
Peak memory | 199392 kb |
Host | smart-35c9f703-8e33-496d-8195-49db8b2e57be |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3671118763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3671118763 |
Directory | /workspace/41.hmac_long_msg/latest |
Test location | /workspace/coverage/default/41.hmac_smoke.3297023818 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 1430027084 ps |
CPU time | 4.36 seconds |
Started | Apr 16 02:04:54 PM PDT 24 |
Finished | Apr 16 02:04:59 PM PDT 24 |
Peak memory | 199588 kb |
Host | smart-c06bfd95-ff1f-4dd3-a0fe-237933463e74 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3297023818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3297023818 |
Directory | /workspace/41.hmac_smoke/latest |
Test location | /workspace/coverage/default/41.hmac_stress_all.299228978 |
Short name | T518 |
Test name | |
Test status | |
Simulation time | 84175884626 ps |
CPU time | 1144.15 seconds |
Started | Apr 16 02:05:00 PM PDT 24 |
Finished | Apr 16 02:24:06 PM PDT 24 |
Peak memory | 240696 kb |
Host | smart-538b75f1-d1d4-4917-8d29-9943e5c78dbf |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299228978 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.299228978 |
Directory | /workspace/41.hmac_stress_all/latest |
Test location | /workspace/coverage/default/41.hmac_stress_all_with_rand_reset.1174448715 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 38754897071 ps |
CPU time | 2090.7 seconds |
Started | Apr 16 02:05:07 PM PDT 24 |
Finished | Apr 16 02:40:00 PM PDT 24 |
Peak memory | 248544 kb |
Host | smart-e26e668d-bcf3-483b-9c3b-420f788f1e5e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1174448715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all_with_rand_reset.1174448715 |
Directory | /workspace/41.hmac_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/41.hmac_test_hmac_vectors.2194524981 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 49747960 ps |
CPU time | 1.03 seconds |
Started | Apr 16 02:05:03 PM PDT 24 |
Finished | Apr 16 02:05:05 PM PDT 24 |
Peak memory | 199032 kb |
Host | smart-9d4a93e4-dbaf-4b80-87fb-45a8512bd71d |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194524981 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 41.hmac_test_hmac_vectors.2194524981 |
Directory | /workspace/41.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/41.hmac_test_sha_vectors.3866593749 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 8402818119 ps |
CPU time | 493.13 seconds |
Started | Apr 16 02:05:02 PM PDT 24 |
Finished | Apr 16 02:13:17 PM PDT 24 |
Peak memory | 199732 kb |
Host | smart-9c4b4094-d8ad-4d07-8f82-8cb12215e4b9 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866593749 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.3866593749 |
Directory | /workspace/41.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/41.hmac_wipe_secret.2833733950 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 101896132 ps |
CPU time | 2.5 seconds |
Started | Apr 16 02:04:56 PM PDT 24 |
Finished | Apr 16 02:04:59 PM PDT 24 |
Peak memory | 199580 kb |
Host | smart-10e03d15-0072-46c5-b95c-9eba5a11dbda |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2833733950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2833733950 |
Directory | /workspace/41.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/42.hmac_alert_test.3319564170 |
Short name | T534 |
Test name | |
Test status | |
Simulation time | 21915510 ps |
CPU time | 0.57 seconds |
Started | Apr 16 02:05:08 PM PDT 24 |
Finished | Apr 16 02:05:10 PM PDT 24 |
Peak memory | 195388 kb |
Host | smart-cd277a47-d70f-4123-9a5a-9d911d80e2f8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319564170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3319564170 |
Directory | /workspace/42.hmac_alert_test/latest |
Test location | /workspace/coverage/default/42.hmac_back_pressure.1151255920 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 3103009510 ps |
CPU time | 57.48 seconds |
Started | Apr 16 02:05:03 PM PDT 24 |
Finished | Apr 16 02:06:02 PM PDT 24 |
Peak memory | 232484 kb |
Host | smart-0783b54a-560c-4cf2-9270-6f9bb5ff7e3d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1151255920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1151255920 |
Directory | /workspace/42.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/42.hmac_burst_wr.2313010763 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 3268965832 ps |
CPU time | 42.64 seconds |
Started | Apr 16 02:05:01 PM PDT 24 |
Finished | Apr 16 02:05:45 PM PDT 24 |
Peak memory | 199736 kb |
Host | smart-5cdd5de2-150e-42f9-adb1-92b98fa9f922 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2313010763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2313010763 |
Directory | /workspace/42.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/42.hmac_datapath_stress.3964023939 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 2290720649 ps |
CPU time | 136.72 seconds |
Started | Apr 16 02:05:02 PM PDT 24 |
Finished | Apr 16 02:07:20 PM PDT 24 |
Peak memory | 199648 kb |
Host | smart-ca14f6d4-b6c0-4ccc-92a3-4f92ac61091c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3964023939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3964023939 |
Directory | /workspace/42.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/42.hmac_error.1634559785 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 119747717 ps |
CPU time | 0.95 seconds |
Started | Apr 16 02:05:04 PM PDT 24 |
Finished | Apr 16 02:05:06 PM PDT 24 |
Peak memory | 198312 kb |
Host | smart-4afad14d-e4c6-4adf-81a7-fbf47ed86051 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634559785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.1634559785 |
Directory | /workspace/42.hmac_error/latest |
Test location | /workspace/coverage/default/42.hmac_long_msg.1237900937 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 5349814486 ps |
CPU time | 78.79 seconds |
Started | Apr 16 02:05:01 PM PDT 24 |
Finished | Apr 16 02:06:22 PM PDT 24 |
Peak memory | 199732 kb |
Host | smart-34d57d0d-a45a-437f-ae99-e08cd3f1c7b6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1237900937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1237900937 |
Directory | /workspace/42.hmac_long_msg/latest |
Test location | /workspace/coverage/default/42.hmac_smoke.920371057 |
Short name | T585 |
Test name | |
Test status | |
Simulation time | 1575270044 ps |
CPU time | 5.44 seconds |
Started | Apr 16 02:05:04 PM PDT 24 |
Finished | Apr 16 02:05:10 PM PDT 24 |
Peak memory | 199604 kb |
Host | smart-b8648f82-1244-40b0-b546-c46625c49842 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=920371057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.920371057 |
Directory | /workspace/42.hmac_smoke/latest |
Test location | /workspace/coverage/default/42.hmac_stress_all.51079949 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 49106894528 ps |
CPU time | 908.85 seconds |
Started | Apr 16 02:05:04 PM PDT 24 |
Finished | Apr 16 02:20:14 PM PDT 24 |
Peak memory | 199728 kb |
Host | smart-d5659314-690b-4d99-bfd9-10d37053569e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51079949 -assert nopostp roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.51079949 |
Directory | /workspace/42.hmac_stress_all/latest |
Test location | /workspace/coverage/default/42.hmac_test_hmac_vectors.410186738 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 48192503 ps |
CPU time | 0.93 seconds |
Started | Apr 16 02:05:01 PM PDT 24 |
Finished | Apr 16 02:05:03 PM PDT 24 |
Peak memory | 198016 kb |
Host | smart-7b1ee95c-f65d-425a-a056-e172dbc45425 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410186738 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 42.hmac_test_hmac_vectors.410186738 |
Directory | /workspace/42.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/42.hmac_test_sha_vectors.2491284469 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 37425018824 ps |
CPU time | 503.13 seconds |
Started | Apr 16 02:05:08 PM PDT 24 |
Finished | Apr 16 02:13:33 PM PDT 24 |
Peak memory | 199908 kb |
Host | smart-e55fe7b7-6822-4087-9dd3-e68b9590e003 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491284469 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.2491284469 |
Directory | /workspace/42.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/42.hmac_wipe_secret.3125370686 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 3103821943 ps |
CPU time | 45.83 seconds |
Started | Apr 16 02:05:05 PM PDT 24 |
Finished | Apr 16 02:05:52 PM PDT 24 |
Peak memory | 199684 kb |
Host | smart-80a92834-ceff-4e50-be9e-095bfc0de20a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3125370686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3125370686 |
Directory | /workspace/42.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/43.hmac_alert_test.1577118473 |
Short name | T575 |
Test name | |
Test status | |
Simulation time | 118821500 ps |
CPU time | 0.61 seconds |
Started | Apr 16 02:05:03 PM PDT 24 |
Finished | Apr 16 02:05:05 PM PDT 24 |
Peak memory | 195156 kb |
Host | smart-4606ecc9-0083-4462-a8e5-e1e18c010de0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577118473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1577118473 |
Directory | /workspace/43.hmac_alert_test/latest |
Test location | /workspace/coverage/default/43.hmac_back_pressure.2563774119 |
Short name | T588 |
Test name | |
Test status | |
Simulation time | 7297033294 ps |
CPU time | 26.91 seconds |
Started | Apr 16 02:05:04 PM PDT 24 |
Finished | Apr 16 02:05:32 PM PDT 24 |
Peak memory | 215636 kb |
Host | smart-38ffbdfb-04cf-4cae-8f64-cd1fde02695b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2563774119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2563774119 |
Directory | /workspace/43.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/43.hmac_burst_wr.373962992 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 2721425706 ps |
CPU time | 33.92 seconds |
Started | Apr 16 02:05:01 PM PDT 24 |
Finished | Apr 16 02:05:36 PM PDT 24 |
Peak memory | 199672 kb |
Host | smart-6b8b79d8-b82a-46ed-8c1a-59b77235b574 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=373962992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.373962992 |
Directory | /workspace/43.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/43.hmac_datapath_stress.2311536244 |
Short name | T542 |
Test name | |
Test status | |
Simulation time | 1963310508 ps |
CPU time | 57.36 seconds |
Started | Apr 16 02:05:05 PM PDT 24 |
Finished | Apr 16 02:06:03 PM PDT 24 |
Peak memory | 199628 kb |
Host | smart-f6331dda-5b57-4daf-9fc7-606fa9de4b3c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2311536244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2311536244 |
Directory | /workspace/43.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/43.hmac_error.1308539949 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 7919735728 ps |
CPU time | 34.96 seconds |
Started | Apr 16 02:05:01 PM PDT 24 |
Finished | Apr 16 02:05:38 PM PDT 24 |
Peak memory | 199704 kb |
Host | smart-21eb38b2-36af-43f6-8ccb-735ba877940f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308539949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1308539949 |
Directory | /workspace/43.hmac_error/latest |
Test location | /workspace/coverage/default/43.hmac_smoke.2027659075 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 809120158 ps |
CPU time | 6.69 seconds |
Started | Apr 16 02:05:03 PM PDT 24 |
Finished | Apr 16 02:05:11 PM PDT 24 |
Peak memory | 199628 kb |
Host | smart-9afca231-43f5-4124-a02b-0971a6d44658 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027659075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2027659075 |
Directory | /workspace/43.hmac_smoke/latest |
Test location | /workspace/coverage/default/43.hmac_stress_all.1997450739 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 75182382138 ps |
CPU time | 657.5 seconds |
Started | Apr 16 02:05:08 PM PDT 24 |
Finished | Apr 16 02:16:07 PM PDT 24 |
Peak memory | 237808 kb |
Host | smart-e0e9edf0-b303-425b-893b-33f336e31e59 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997450739 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1997450739 |
Directory | /workspace/43.hmac_stress_all/latest |
Test location | /workspace/coverage/default/43.hmac_test_hmac_vectors.4184730956 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 142408119 ps |
CPU time | 1.27 seconds |
Started | Apr 16 02:05:00 PM PDT 24 |
Finished | Apr 16 02:05:03 PM PDT 24 |
Peak memory | 199568 kb |
Host | smart-f1bd249b-4c4e-47dd-aa71-a45459652347 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184730956 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 43.hmac_test_hmac_vectors.4184730956 |
Directory | /workspace/43.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/43.hmac_test_sha_vectors.581717296 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 81414023432 ps |
CPU time | 535.09 seconds |
Started | Apr 16 02:05:01 PM PDT 24 |
Finished | Apr 16 02:13:58 PM PDT 24 |
Peak memory | 199680 kb |
Host | smart-f8c0629c-8342-4c86-82a1-1a8d2e15ecf5 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581717296 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.581717296 |
Directory | /workspace/43.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/43.hmac_wipe_secret.3053168217 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 1669983010 ps |
CPU time | 80.64 seconds |
Started | Apr 16 02:05:04 PM PDT 24 |
Finished | Apr 16 02:06:26 PM PDT 24 |
Peak memory | 199580 kb |
Host | smart-d89a7278-de78-4e69-986c-779363e0e67f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3053168217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3053168217 |
Directory | /workspace/43.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/44.hmac_alert_test.2554545676 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 15194477 ps |
CPU time | 0.6 seconds |
Started | Apr 16 02:05:08 PM PDT 24 |
Finished | Apr 16 02:05:11 PM PDT 24 |
Peak memory | 195108 kb |
Host | smart-af34f7e5-8a16-40a5-8fea-d0ab9d87e856 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554545676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2554545676 |
Directory | /workspace/44.hmac_alert_test/latest |
Test location | /workspace/coverage/default/44.hmac_back_pressure.2047703457 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 2547386500 ps |
CPU time | 32.08 seconds |
Started | Apr 16 02:05:03 PM PDT 24 |
Finished | Apr 16 02:05:36 PM PDT 24 |
Peak memory | 207876 kb |
Host | smart-795ec79d-f2ff-4e0d-be93-efa361b39690 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2047703457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2047703457 |
Directory | /workspace/44.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/44.hmac_burst_wr.3764049098 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 4137179253 ps |
CPU time | 33.33 seconds |
Started | Apr 16 02:05:06 PM PDT 24 |
Finished | Apr 16 02:05:41 PM PDT 24 |
Peak memory | 199736 kb |
Host | smart-68e41884-ab3d-4614-afff-a091ac7bd12a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3764049098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3764049098 |
Directory | /workspace/44.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/44.hmac_datapath_stress.979639550 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 2943294156 ps |
CPU time | 87.59 seconds |
Started | Apr 16 02:05:09 PM PDT 24 |
Finished | Apr 16 02:06:38 PM PDT 24 |
Peak memory | 199680 kb |
Host | smart-8f603ab2-b176-46d2-ac89-90ae705f43f6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=979639550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.979639550 |
Directory | /workspace/44.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/44.hmac_error.921932615 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 5763405358 ps |
CPU time | 100.29 seconds |
Started | Apr 16 02:05:08 PM PDT 24 |
Finished | Apr 16 02:06:50 PM PDT 24 |
Peak memory | 199764 kb |
Host | smart-fcffe738-b1da-407a-b81b-47f032752eb0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921932615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.921932615 |
Directory | /workspace/44.hmac_error/latest |
Test location | /workspace/coverage/default/44.hmac_long_msg.3224159622 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 3081847411 ps |
CPU time | 90.15 seconds |
Started | Apr 16 02:05:04 PM PDT 24 |
Finished | Apr 16 02:06:35 PM PDT 24 |
Peak memory | 199708 kb |
Host | smart-5fcb8765-4b56-47ee-b0d4-3a65f9294f64 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3224159622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3224159622 |
Directory | /workspace/44.hmac_long_msg/latest |
Test location | /workspace/coverage/default/44.hmac_smoke.1820511804 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 959546770 ps |
CPU time | 4.24 seconds |
Started | Apr 16 02:05:08 PM PDT 24 |
Finished | Apr 16 02:05:14 PM PDT 24 |
Peak memory | 199812 kb |
Host | smart-226a29a4-9b83-4aab-a728-96a933e4b9a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1820511804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1820511804 |
Directory | /workspace/44.hmac_smoke/latest |
Test location | /workspace/coverage/default/44.hmac_stress_all.1459924630 |
Short name | T593 |
Test name | |
Test status | |
Simulation time | 6960517704 ps |
CPU time | 369.26 seconds |
Started | Apr 16 02:05:08 PM PDT 24 |
Finished | Apr 16 02:11:19 PM PDT 24 |
Peak memory | 215916 kb |
Host | smart-63bbb379-041c-42dd-9ac5-983fe287d57d |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459924630 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1459924630 |
Directory | /workspace/44.hmac_stress_all/latest |
Test location | /workspace/coverage/default/44.hmac_test_hmac_vectors.1873438972 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 62241254 ps |
CPU time | 1.16 seconds |
Started | Apr 16 02:05:08 PM PDT 24 |
Finished | Apr 16 02:05:11 PM PDT 24 |
Peak memory | 199056 kb |
Host | smart-fb3b228b-d201-44f3-9390-89a9204d8600 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873438972 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 44.hmac_test_hmac_vectors.1873438972 |
Directory | /workspace/44.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/44.hmac_test_sha_vectors.1216878966 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 65360755827 ps |
CPU time | 447.12 seconds |
Started | Apr 16 02:05:06 PM PDT 24 |
Finished | Apr 16 02:12:34 PM PDT 24 |
Peak memory | 199752 kb |
Host | smart-29aba7e6-e919-4b68-8423-359d1d1e056e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216878966 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.1216878966 |
Directory | /workspace/44.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/44.hmac_wipe_secret.87010268 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 17746295362 ps |
CPU time | 90.51 seconds |
Started | Apr 16 02:05:08 PM PDT 24 |
Finished | Apr 16 02:06:40 PM PDT 24 |
Peak memory | 199708 kb |
Host | smart-9055788c-c85d-47dd-8d44-bdae85bf3c38 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=87010268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.87010268 |
Directory | /workspace/44.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/45.hmac_alert_test.1231562282 |
Short name | T507 |
Test name | |
Test status | |
Simulation time | 43974387 ps |
CPU time | 0.57 seconds |
Started | Apr 16 02:05:08 PM PDT 24 |
Finished | Apr 16 02:05:10 PM PDT 24 |
Peak memory | 194896 kb |
Host | smart-0a85ec50-9668-4ad1-a1ce-0a124a05ac0d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231562282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1231562282 |
Directory | /workspace/45.hmac_alert_test/latest |
Test location | /workspace/coverage/default/45.hmac_back_pressure.1071058594 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 1238902548 ps |
CPU time | 47.29 seconds |
Started | Apr 16 02:05:06 PM PDT 24 |
Finished | Apr 16 02:05:54 PM PDT 24 |
Peak memory | 215552 kb |
Host | smart-0c399441-bdcb-4873-8967-32ec9f766eda |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1071058594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1071058594 |
Directory | /workspace/45.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/45.hmac_burst_wr.1453803568 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 6100984504 ps |
CPU time | 25.1 seconds |
Started | Apr 16 02:05:07 PM PDT 24 |
Finished | Apr 16 02:05:33 PM PDT 24 |
Peak memory | 199708 kb |
Host | smart-a6a3c35f-5e9b-40b6-96cb-9fb7a9bea99f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1453803568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.1453803568 |
Directory | /workspace/45.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/45.hmac_datapath_stress.1439152977 |
Short name | T557 |
Test name | |
Test status | |
Simulation time | 10793134610 ps |
CPU time | 141.9 seconds |
Started | Apr 16 02:05:06 PM PDT 24 |
Finished | Apr 16 02:07:29 PM PDT 24 |
Peak memory | 199728 kb |
Host | smart-197bf084-9074-4114-bc9a-b14cd4cdce69 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1439152977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1439152977 |
Directory | /workspace/45.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/45.hmac_error.1557567278 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 36975142186 ps |
CPU time | 123.11 seconds |
Started | Apr 16 02:05:06 PM PDT 24 |
Finished | Apr 16 02:07:10 PM PDT 24 |
Peak memory | 199724 kb |
Host | smart-16221a85-9968-41ce-8f8d-0d838c27b30b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557567278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1557567278 |
Directory | /workspace/45.hmac_error/latest |
Test location | /workspace/coverage/default/45.hmac_long_msg.1536907754 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 5063507273 ps |
CPU time | 87.88 seconds |
Started | Apr 16 02:05:07 PM PDT 24 |
Finished | Apr 16 02:06:35 PM PDT 24 |
Peak memory | 199700 kb |
Host | smart-bc9c76e3-59b6-43e7-8619-b3039154145d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1536907754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1536907754 |
Directory | /workspace/45.hmac_long_msg/latest |
Test location | /workspace/coverage/default/45.hmac_smoke.3790979581 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 23666985 ps |
CPU time | 0.68 seconds |
Started | Apr 16 02:05:06 PM PDT 24 |
Finished | Apr 16 02:05:08 PM PDT 24 |
Peak memory | 196680 kb |
Host | smart-05b350d8-fbd2-40ca-bfa6-3fe82ab7bdfe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3790979581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3790979581 |
Directory | /workspace/45.hmac_smoke/latest |
Test location | /workspace/coverage/default/45.hmac_stress_all.1089760864 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 82637324023 ps |
CPU time | 1015.77 seconds |
Started | Apr 16 02:05:07 PM PDT 24 |
Finished | Apr 16 02:22:04 PM PDT 24 |
Peak memory | 247480 kb |
Host | smart-98c572f7-e887-490e-be0d-f7fe84a501ff |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089760864 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1089760864 |
Directory | /workspace/45.hmac_stress_all/latest |
Test location | /workspace/coverage/default/45.hmac_test_hmac_vectors.936274990 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 50860307 ps |
CPU time | 1.14 seconds |
Started | Apr 16 02:05:08 PM PDT 24 |
Finished | Apr 16 02:05:10 PM PDT 24 |
Peak memory | 199256 kb |
Host | smart-0de8c1da-776d-42b2-9d93-78dd80313279 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936274990 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 45.hmac_test_hmac_vectors.936274990 |
Directory | /workspace/45.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/45.hmac_test_sha_vectors.1666551902 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 166286928486 ps |
CPU time | 556.14 seconds |
Started | Apr 16 02:05:08 PM PDT 24 |
Finished | Apr 16 02:14:25 PM PDT 24 |
Peak memory | 199676 kb |
Host | smart-0f7036ca-405b-4f2f-b749-61eb8d0ba1da |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666551902 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.1666551902 |
Directory | /workspace/45.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/45.hmac_wipe_secret.1887732109 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 10451676595 ps |
CPU time | 102.87 seconds |
Started | Apr 16 02:05:07 PM PDT 24 |
Finished | Apr 16 02:06:51 PM PDT 24 |
Peak memory | 199708 kb |
Host | smart-4ec82a24-55ff-4037-b60d-39966c839d37 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1887732109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1887732109 |
Directory | /workspace/45.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/46.hmac_alert_test.2213619821 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 48144426 ps |
CPU time | 0.59 seconds |
Started | Apr 16 02:05:12 PM PDT 24 |
Finished | Apr 16 02:05:14 PM PDT 24 |
Peak memory | 194128 kb |
Host | smart-73e946a6-ef44-4a5c-816b-425891c412c2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213619821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2213619821 |
Directory | /workspace/46.hmac_alert_test/latest |
Test location | /workspace/coverage/default/46.hmac_back_pressure.598172722 |
Short name | T545 |
Test name | |
Test status | |
Simulation time | 227156694 ps |
CPU time | 4.03 seconds |
Started | Apr 16 02:05:12 PM PDT 24 |
Finished | Apr 16 02:05:17 PM PDT 24 |
Peak memory | 199592 kb |
Host | smart-f8a0ff69-3598-4036-b5c4-d1b5f1a077c3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=598172722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.598172722 |
Directory | /workspace/46.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/46.hmac_burst_wr.453209995 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 5118312541 ps |
CPU time | 65.92 seconds |
Started | Apr 16 02:05:14 PM PDT 24 |
Finished | Apr 16 02:06:21 PM PDT 24 |
Peak memory | 199740 kb |
Host | smart-04b4ebdc-f1a7-4792-97f7-cdc2f3669f37 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=453209995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.453209995 |
Directory | /workspace/46.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/46.hmac_datapath_stress.242609449 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 4045679562 ps |
CPU time | 120.26 seconds |
Started | Apr 16 02:05:11 PM PDT 24 |
Finished | Apr 16 02:07:13 PM PDT 24 |
Peak memory | 199708 kb |
Host | smart-b3aaacff-e145-410b-b125-50d720bc551e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=242609449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.242609449 |
Directory | /workspace/46.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/46.hmac_error.2160909735 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 3200906418 ps |
CPU time | 61.79 seconds |
Started | Apr 16 02:05:16 PM PDT 24 |
Finished | Apr 16 02:06:19 PM PDT 24 |
Peak memory | 199704 kb |
Host | smart-16599947-3df9-4ae7-a28c-2ba23ab6248d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160909735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2160909735 |
Directory | /workspace/46.hmac_error/latest |
Test location | /workspace/coverage/default/46.hmac_long_msg.1019270953 |
Short name | T521 |
Test name | |
Test status | |
Simulation time | 3943034672 ps |
CPU time | 53.16 seconds |
Started | Apr 16 02:05:13 PM PDT 24 |
Finished | Apr 16 02:06:07 PM PDT 24 |
Peak memory | 199724 kb |
Host | smart-a9e4d68a-18c5-422e-94b2-bb9a085bf9ed |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1019270953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1019270953 |
Directory | /workspace/46.hmac_long_msg/latest |
Test location | /workspace/coverage/default/46.hmac_smoke.4248855166 |
Short name | T586 |
Test name | |
Test status | |
Simulation time | 194326213 ps |
CPU time | 1.73 seconds |
Started | Apr 16 02:05:06 PM PDT 24 |
Finished | Apr 16 02:05:09 PM PDT 24 |
Peak memory | 199604 kb |
Host | smart-569fd79b-4c0b-41a6-9936-1b51b0ac4f2e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4248855166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.4248855166 |
Directory | /workspace/46.hmac_smoke/latest |
Test location | /workspace/coverage/default/46.hmac_stress_all.1523960493 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 178384390074 ps |
CPU time | 2289.2 seconds |
Started | Apr 16 02:05:11 PM PDT 24 |
Finished | Apr 16 02:43:22 PM PDT 24 |
Peak memory | 232452 kb |
Host | smart-1cca662c-ccf6-4687-bd61-c56151ae1bd6 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523960493 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1523960493 |
Directory | /workspace/46.hmac_stress_all/latest |
Test location | /workspace/coverage/default/46.hmac_test_hmac_vectors.2854696084 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 33322702 ps |
CPU time | 1.26 seconds |
Started | Apr 16 02:05:15 PM PDT 24 |
Finished | Apr 16 02:05:16 PM PDT 24 |
Peak memory | 199548 kb |
Host | smart-30659baa-ba49-44d6-8e6f-6fbc64e3d785 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854696084 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 46.hmac_test_hmac_vectors.2854696084 |
Directory | /workspace/46.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/46.hmac_test_sha_vectors.110928372 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 205167987093 ps |
CPU time | 525.79 seconds |
Started | Apr 16 02:05:12 PM PDT 24 |
Finished | Apr 16 02:13:58 PM PDT 24 |
Peak memory | 199696 kb |
Host | smart-18f12eb1-ca21-4d43-b70f-be36e5ee0eb9 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110928372 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.110928372 |
Directory | /workspace/46.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/46.hmac_wipe_secret.2878452458 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 5578506650 ps |
CPU time | 88.88 seconds |
Started | Apr 16 02:05:12 PM PDT 24 |
Finished | Apr 16 02:06:42 PM PDT 24 |
Peak memory | 199716 kb |
Host | smart-fff700b1-6b26-46e8-af84-7320aafd3965 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2878452458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2878452458 |
Directory | /workspace/46.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/47.hmac_alert_test.3989069787 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 18414645 ps |
CPU time | 0.56 seconds |
Started | Apr 16 02:05:13 PM PDT 24 |
Finished | Apr 16 02:05:14 PM PDT 24 |
Peak memory | 194860 kb |
Host | smart-98296b71-5601-4d80-b0cd-0dfb3f763969 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989069787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3989069787 |
Directory | /workspace/47.hmac_alert_test/latest |
Test location | /workspace/coverage/default/47.hmac_back_pressure.3008346385 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 903531517 ps |
CPU time | 8.07 seconds |
Started | Apr 16 02:05:14 PM PDT 24 |
Finished | Apr 16 02:05:23 PM PDT 24 |
Peak memory | 215528 kb |
Host | smart-eabeb426-a4d6-4856-b5ec-ff235aad0897 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3008346385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3008346385 |
Directory | /workspace/47.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/47.hmac_burst_wr.802922125 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 305980473 ps |
CPU time | 1.84 seconds |
Started | Apr 16 02:05:14 PM PDT 24 |
Finished | Apr 16 02:05:17 PM PDT 24 |
Peak memory | 199500 kb |
Host | smart-47a27675-448f-4520-85ea-b8a5bc9a2e29 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=802922125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.802922125 |
Directory | /workspace/47.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/47.hmac_datapath_stress.3617574701 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 7818724029 ps |
CPU time | 87.73 seconds |
Started | Apr 16 02:05:12 PM PDT 24 |
Finished | Apr 16 02:06:41 PM PDT 24 |
Peak memory | 199704 kb |
Host | smart-9dc1bf4e-2071-4223-a012-4762c7a3c944 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3617574701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3617574701 |
Directory | /workspace/47.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/47.hmac_error.2842542811 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 10509100555 ps |
CPU time | 198.8 seconds |
Started | Apr 16 02:05:12 PM PDT 24 |
Finished | Apr 16 02:08:32 PM PDT 24 |
Peak memory | 199748 kb |
Host | smart-8c74e5b2-78ee-4c9e-8567-8e8a280283be |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842542811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2842542811 |
Directory | /workspace/47.hmac_error/latest |
Test location | /workspace/coverage/default/47.hmac_long_msg.2377284468 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 49497942735 ps |
CPU time | 128.86 seconds |
Started | Apr 16 02:05:13 PM PDT 24 |
Finished | Apr 16 02:07:23 PM PDT 24 |
Peak memory | 199736 kb |
Host | smart-49cf4e5b-329a-4315-b98d-0d057dd6815a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2377284468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2377284468 |
Directory | /workspace/47.hmac_long_msg/latest |
Test location | /workspace/coverage/default/47.hmac_smoke.1288776202 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 490944424 ps |
CPU time | 6.21 seconds |
Started | Apr 16 02:05:12 PM PDT 24 |
Finished | Apr 16 02:05:19 PM PDT 24 |
Peak memory | 199608 kb |
Host | smart-cb26a736-123e-4197-bf2f-d0d0311fb698 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1288776202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1288776202 |
Directory | /workspace/47.hmac_smoke/latest |
Test location | /workspace/coverage/default/47.hmac_stress_all.3529780043 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 132144085502 ps |
CPU time | 1822.12 seconds |
Started | Apr 16 02:05:13 PM PDT 24 |
Finished | Apr 16 02:35:36 PM PDT 24 |
Peak memory | 232044 kb |
Host | smart-e25cb387-76bf-4504-8516-ed8aa899035d |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529780043 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3529780043 |
Directory | /workspace/47.hmac_stress_all/latest |
Test location | /workspace/coverage/default/47.hmac_test_hmac_vectors.2301046901 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 92224329 ps |
CPU time | 1.09 seconds |
Started | Apr 16 02:05:12 PM PDT 24 |
Finished | Apr 16 02:05:14 PM PDT 24 |
Peak memory | 198956 kb |
Host | smart-5ad13636-15a7-4c16-a53a-5743efc6bd96 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301046901 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 47.hmac_test_hmac_vectors.2301046901 |
Directory | /workspace/47.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/47.hmac_test_sha_vectors.3645474206 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 30079650635 ps |
CPU time | 427.65 seconds |
Started | Apr 16 02:05:13 PM PDT 24 |
Finished | Apr 16 02:12:22 PM PDT 24 |
Peak memory | 199728 kb |
Host | smart-ca56915a-1369-4025-9c9b-aab406cc0c73 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645474206 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.3645474206 |
Directory | /workspace/47.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/47.hmac_wipe_secret.1772991062 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 12998829683 ps |
CPU time | 95.89 seconds |
Started | Apr 16 02:05:13 PM PDT 24 |
Finished | Apr 16 02:06:50 PM PDT 24 |
Peak memory | 199680 kb |
Host | smart-8fe2e874-da09-4366-8c5e-9f7ed229b73b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1772991062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1772991062 |
Directory | /workspace/47.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/48.hmac_alert_test.1024351190 |
Short name | T581 |
Test name | |
Test status | |
Simulation time | 12511644 ps |
CPU time | 0.58 seconds |
Started | Apr 16 02:05:20 PM PDT 24 |
Finished | Apr 16 02:05:21 PM PDT 24 |
Peak memory | 194012 kb |
Host | smart-fed1701e-611d-4ac6-99b1-d44cd67e1712 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024351190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1024351190 |
Directory | /workspace/48.hmac_alert_test/latest |
Test location | /workspace/coverage/default/48.hmac_back_pressure.331809150 |
Short name | T573 |
Test name | |
Test status | |
Simulation time | 3607109671 ps |
CPU time | 31.61 seconds |
Started | Apr 16 02:05:22 PM PDT 24 |
Finished | Apr 16 02:05:54 PM PDT 24 |
Peak memory | 215752 kb |
Host | smart-7fbdac4c-5367-4303-b6fb-5c378a56962a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=331809150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.331809150 |
Directory | /workspace/48.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/48.hmac_burst_wr.3491615482 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 396939886 ps |
CPU time | 5.96 seconds |
Started | Apr 16 02:05:20 PM PDT 24 |
Finished | Apr 16 02:05:27 PM PDT 24 |
Peak memory | 199564 kb |
Host | smart-e6384e18-543e-4a71-9cc5-2855f116522d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3491615482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3491615482 |
Directory | /workspace/48.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/48.hmac_datapath_stress.2206404964 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 1977486747 ps |
CPU time | 122.39 seconds |
Started | Apr 16 02:05:17 PM PDT 24 |
Finished | Apr 16 02:07:21 PM PDT 24 |
Peak memory | 199604 kb |
Host | smart-cc8d01df-0d98-441d-8c16-47d2a8559647 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2206404964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2206404964 |
Directory | /workspace/48.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/48.hmac_error.3871229298 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 31433518394 ps |
CPU time | 146.44 seconds |
Started | Apr 16 02:05:17 PM PDT 24 |
Finished | Apr 16 02:07:45 PM PDT 24 |
Peak memory | 199672 kb |
Host | smart-ebc59eb0-ef7a-420d-a1a2-a82441f18404 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871229298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3871229298 |
Directory | /workspace/48.hmac_error/latest |
Test location | /workspace/coverage/default/48.hmac_long_msg.2258524788 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 1453779345 ps |
CPU time | 23.93 seconds |
Started | Apr 16 02:05:14 PM PDT 24 |
Finished | Apr 16 02:05:39 PM PDT 24 |
Peak memory | 199532 kb |
Host | smart-c74b5e12-9352-4cee-9cbe-413bca8ebf05 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2258524788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2258524788 |
Directory | /workspace/48.hmac_long_msg/latest |
Test location | /workspace/coverage/default/48.hmac_smoke.1954557372 |
Short name | T591 |
Test name | |
Test status | |
Simulation time | 418365768 ps |
CPU time | 6.46 seconds |
Started | Apr 16 02:05:13 PM PDT 24 |
Finished | Apr 16 02:05:21 PM PDT 24 |
Peak memory | 199544 kb |
Host | smart-390b6081-2c85-425f-b1cf-c0cb15745c53 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1954557372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1954557372 |
Directory | /workspace/48.hmac_smoke/latest |
Test location | /workspace/coverage/default/48.hmac_stress_all.3307135607 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 58442263171 ps |
CPU time | 1037.64 seconds |
Started | Apr 16 02:05:18 PM PDT 24 |
Finished | Apr 16 02:22:37 PM PDT 24 |
Peak memory | 199756 kb |
Host | smart-a52578fc-d041-40d3-8911-9accabd2213f |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307135607 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3307135607 |
Directory | /workspace/48.hmac_stress_all/latest |
Test location | /workspace/coverage/default/48.hmac_test_hmac_vectors.2170958268 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 282550381 ps |
CPU time | 1.38 seconds |
Started | Apr 16 02:05:18 PM PDT 24 |
Finished | Apr 16 02:05:21 PM PDT 24 |
Peak memory | 199528 kb |
Host | smart-a900975d-1c1f-4e18-9498-8c22fbcf901f |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170958268 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 48.hmac_test_hmac_vectors.2170958268 |
Directory | /workspace/48.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/48.hmac_test_sha_vectors.860863882 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 125164952997 ps |
CPU time | 566.63 seconds |
Started | Apr 16 02:05:18 PM PDT 24 |
Finished | Apr 16 02:14:45 PM PDT 24 |
Peak memory | 199668 kb |
Host | smart-fc3b8fe2-04b4-4473-af94-b75d44926b40 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860863882 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.860863882 |
Directory | /workspace/48.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/48.hmac_wipe_secret.350401367 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 8299672716 ps |
CPU time | 40.02 seconds |
Started | Apr 16 02:05:19 PM PDT 24 |
Finished | Apr 16 02:06:00 PM PDT 24 |
Peak memory | 199728 kb |
Host | smart-e95a5a7b-c7d1-4124-86bb-81e5dc527287 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=350401367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.350401367 |
Directory | /workspace/48.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/49.hmac_alert_test.2235037848 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 32259611 ps |
CPU time | 0.57 seconds |
Started | Apr 16 02:05:17 PM PDT 24 |
Finished | Apr 16 02:05:19 PM PDT 24 |
Peak memory | 194164 kb |
Host | smart-09a2919b-8997-44d6-92b8-719be9df5c86 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235037848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2235037848 |
Directory | /workspace/49.hmac_alert_test/latest |
Test location | /workspace/coverage/default/49.hmac_back_pressure.474880342 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 1266285883 ps |
CPU time | 45.6 seconds |
Started | Apr 16 02:05:18 PM PDT 24 |
Finished | Apr 16 02:06:04 PM PDT 24 |
Peak memory | 227292 kb |
Host | smart-9d95b633-6029-48e8-81e6-27f3f8adc809 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=474880342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.474880342 |
Directory | /workspace/49.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/49.hmac_burst_wr.726682177 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 2149354882 ps |
CPU time | 42.4 seconds |
Started | Apr 16 02:05:18 PM PDT 24 |
Finished | Apr 16 02:06:01 PM PDT 24 |
Peak memory | 199668 kb |
Host | smart-c9581470-c596-43b1-89ce-92c5d3c7a25c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=726682177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.726682177 |
Directory | /workspace/49.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/49.hmac_datapath_stress.3467858801 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 925265432 ps |
CPU time | 56.93 seconds |
Started | Apr 16 02:05:19 PM PDT 24 |
Finished | Apr 16 02:06:16 PM PDT 24 |
Peak memory | 199596 kb |
Host | smart-17a4fdd1-c9d5-4569-a741-ca3115c74e36 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3467858801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3467858801 |
Directory | /workspace/49.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/49.hmac_error.2131869730 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 48715016794 ps |
CPU time | 179.73 seconds |
Started | Apr 16 02:05:16 PM PDT 24 |
Finished | Apr 16 02:08:16 PM PDT 24 |
Peak memory | 199748 kb |
Host | smart-fca4249a-2f2f-4e89-97f0-f7909044ecaa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131869730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2131869730 |
Directory | /workspace/49.hmac_error/latest |
Test location | /workspace/coverage/default/49.hmac_long_msg.1032405195 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 23755090491 ps |
CPU time | 111.52 seconds |
Started | Apr 16 02:05:20 PM PDT 24 |
Finished | Apr 16 02:07:12 PM PDT 24 |
Peak memory | 199720 kb |
Host | smart-52c21603-a693-475c-8767-470277d42ed3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1032405195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1032405195 |
Directory | /workspace/49.hmac_long_msg/latest |
Test location | /workspace/coverage/default/49.hmac_smoke.1488078129 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 64140202 ps |
CPU time | 2.21 seconds |
Started | Apr 16 02:05:17 PM PDT 24 |
Finished | Apr 16 02:05:20 PM PDT 24 |
Peak memory | 199592 kb |
Host | smart-ff849db1-6940-4117-90d5-377a5ef0ba96 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1488078129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1488078129 |
Directory | /workspace/49.hmac_smoke/latest |
Test location | /workspace/coverage/default/49.hmac_stress_all.909269117 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 758790683 ps |
CPU time | 2.79 seconds |
Started | Apr 16 02:05:23 PM PDT 24 |
Finished | Apr 16 02:05:26 PM PDT 24 |
Peak memory | 199580 kb |
Host | smart-a1b53fee-9524-431b-8396-4491943fc649 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909269117 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.909269117 |
Directory | /workspace/49.hmac_stress_all/latest |
Test location | /workspace/coverage/default/49.hmac_test_hmac_vectors.765809027 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 184629653 ps |
CPU time | 1.05 seconds |
Started | Apr 16 02:05:20 PM PDT 24 |
Finished | Apr 16 02:05:22 PM PDT 24 |
Peak memory | 199128 kb |
Host | smart-5634d774-94ad-479e-817b-cb0ec54d97ac |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765809027 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 49.hmac_test_hmac_vectors.765809027 |
Directory | /workspace/49.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/49.hmac_test_sha_vectors.4270287904 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 66381205633 ps |
CPU time | 447.9 seconds |
Started | Apr 16 02:05:19 PM PDT 24 |
Finished | Apr 16 02:12:48 PM PDT 24 |
Peak memory | 199732 kb |
Host | smart-d27e6699-2069-4d10-872d-dac0264c844c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270287904 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.4270287904 |
Directory | /workspace/49.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/49.hmac_wipe_secret.648441232 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 24439785965 ps |
CPU time | 37.6 seconds |
Started | Apr 16 02:05:18 PM PDT 24 |
Finished | Apr 16 02:05:56 PM PDT 24 |
Peak memory | 199660 kb |
Host | smart-aec7cab5-1c74-420d-83fb-647156232e6d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=648441232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.648441232 |
Directory | /workspace/49.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/5.hmac_alert_test.1550104901 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 16199994 ps |
CPU time | 0.58 seconds |
Started | Apr 16 02:03:38 PM PDT 24 |
Finished | Apr 16 02:03:40 PM PDT 24 |
Peak memory | 195248 kb |
Host | smart-34cf0c94-ddcc-4fd6-92b6-67f26ee48f2a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550104901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1550104901 |
Directory | /workspace/5.hmac_alert_test/latest |
Test location | /workspace/coverage/default/5.hmac_back_pressure.3929465511 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 3299250653 ps |
CPU time | 37.4 seconds |
Started | Apr 16 02:03:38 PM PDT 24 |
Finished | Apr 16 02:04:17 PM PDT 24 |
Peak memory | 232908 kb |
Host | smart-692c661b-20b6-47b9-ba25-0d95627efdca |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3929465511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3929465511 |
Directory | /workspace/5.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/5.hmac_burst_wr.955521339 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 2870110923 ps |
CPU time | 27.62 seconds |
Started | Apr 16 02:03:38 PM PDT 24 |
Finished | Apr 16 02:04:07 PM PDT 24 |
Peak memory | 199648 kb |
Host | smart-8eff5f9b-0bba-4752-a66c-8e623b41677b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=955521339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.955521339 |
Directory | /workspace/5.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/5.hmac_datapath_stress.1762145950 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 10195691526 ps |
CPU time | 66.06 seconds |
Started | Apr 16 02:03:36 PM PDT 24 |
Finished | Apr 16 02:04:43 PM PDT 24 |
Peak memory | 199656 kb |
Host | smart-f61516ec-83f2-4b2c-9ac8-cf118f93c6fb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1762145950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1762145950 |
Directory | /workspace/5.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/5.hmac_error.3921065526 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 16878115116 ps |
CPU time | 51.68 seconds |
Started | Apr 16 02:03:30 PM PDT 24 |
Finished | Apr 16 02:04:24 PM PDT 24 |
Peak memory | 199700 kb |
Host | smart-e7739b0e-b3ce-4da6-8467-252a728f25a3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921065526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3921065526 |
Directory | /workspace/5.hmac_error/latest |
Test location | /workspace/coverage/default/5.hmac_long_msg.1596997736 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 1751424182 ps |
CPU time | 107.67 seconds |
Started | Apr 16 02:03:39 PM PDT 24 |
Finished | Apr 16 02:05:28 PM PDT 24 |
Peak memory | 199604 kb |
Host | smart-3d6bbe80-5eb6-4bfb-8531-6baba4f81c41 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1596997736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1596997736 |
Directory | /workspace/5.hmac_long_msg/latest |
Test location | /workspace/coverage/default/5.hmac_smoke.2589752616 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 101913612 ps |
CPU time | 3.05 seconds |
Started | Apr 16 02:03:28 PM PDT 24 |
Finished | Apr 16 02:03:34 PM PDT 24 |
Peak memory | 199612 kb |
Host | smart-4a87e9d8-68d3-4352-9699-4393bcab46c1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2589752616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2589752616 |
Directory | /workspace/5.hmac_smoke/latest |
Test location | /workspace/coverage/default/5.hmac_stress_all.1252038019 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 1496977271 ps |
CPU time | 76.04 seconds |
Started | Apr 16 02:03:39 PM PDT 24 |
Finished | Apr 16 02:04:57 PM PDT 24 |
Peak memory | 199600 kb |
Host | smart-a91e22a1-4a17-49a4-b4a4-80026f4bd815 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252038019 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1252038019 |
Directory | /workspace/5.hmac_stress_all/latest |
Test location | /workspace/coverage/default/5.hmac_test_hmac_vectors.1275389246 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 119439881 ps |
CPU time | 1.32 seconds |
Started | Apr 16 02:03:32 PM PDT 24 |
Finished | Apr 16 02:03:35 PM PDT 24 |
Peak memory | 199572 kb |
Host | smart-face35d1-0486-4568-a207-0d16522ef784 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275389246 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.hmac_test_hmac_vectors.1275389246 |
Directory | /workspace/5.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/5.hmac_test_sha_vectors.1608780153 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 26588812763 ps |
CPU time | 471.43 seconds |
Started | Apr 16 02:03:37 PM PDT 24 |
Finished | Apr 16 02:11:30 PM PDT 24 |
Peak memory | 199664 kb |
Host | smart-2188d37b-d9b2-4184-947c-235965292158 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608780153 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.1608780153 |
Directory | /workspace/5.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/5.hmac_wipe_secret.1454749054 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 2445149144 ps |
CPU time | 26.96 seconds |
Started | Apr 16 02:03:35 PM PDT 24 |
Finished | Apr 16 02:04:03 PM PDT 24 |
Peak memory | 199720 kb |
Host | smart-1047edc2-0f8f-4934-b3ef-945ebd8ec9b0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1454749054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.1454749054 |
Directory | /workspace/5.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/6.hmac_alert_test.3616819432 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 28728226 ps |
CPU time | 0.66 seconds |
Started | Apr 16 02:03:41 PM PDT 24 |
Finished | Apr 16 02:03:43 PM PDT 24 |
Peak memory | 195148 kb |
Host | smart-2e926fe6-788d-45e4-888a-5ec1c3f34f36 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616819432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.3616819432 |
Directory | /workspace/6.hmac_alert_test/latest |
Test location | /workspace/coverage/default/6.hmac_back_pressure.3666493102 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 1627631495 ps |
CPU time | 60.21 seconds |
Started | Apr 16 02:03:33 PM PDT 24 |
Finished | Apr 16 02:04:36 PM PDT 24 |
Peak memory | 207804 kb |
Host | smart-802ba86b-cef9-421c-898a-2584c16e6c4f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3666493102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3666493102 |
Directory | /workspace/6.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/6.hmac_burst_wr.956010832 |
Short name | T583 |
Test name | |
Test status | |
Simulation time | 429358305 ps |
CPU time | 22.72 seconds |
Started | Apr 16 02:03:39 PM PDT 24 |
Finished | Apr 16 02:04:04 PM PDT 24 |
Peak memory | 199632 kb |
Host | smart-8c2395c6-7f59-4ea0-8ee7-d7e4af7de2b3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=956010832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.956010832 |
Directory | /workspace/6.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/6.hmac_datapath_stress.1118995638 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 3058419861 ps |
CPU time | 87.21 seconds |
Started | Apr 16 02:03:39 PM PDT 24 |
Finished | Apr 16 02:05:08 PM PDT 24 |
Peak memory | 199696 kb |
Host | smart-c0c1395f-4c1f-41ae-9926-d58f8529e7b1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1118995638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1118995638 |
Directory | /workspace/6.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/6.hmac_error.1831842453 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 5710196601 ps |
CPU time | 70.63 seconds |
Started | Apr 16 02:03:42 PM PDT 24 |
Finished | Apr 16 02:04:54 PM PDT 24 |
Peak memory | 199664 kb |
Host | smart-e9d1292e-836d-4372-bc41-1608929e7956 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831842453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1831842453 |
Directory | /workspace/6.hmac_error/latest |
Test location | /workspace/coverage/default/6.hmac_long_msg.4254430919 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 1597434009 ps |
CPU time | 3.23 seconds |
Started | Apr 16 02:03:31 PM PDT 24 |
Finished | Apr 16 02:03:36 PM PDT 24 |
Peak memory | 199616 kb |
Host | smart-e82be2d7-869b-434a-b71d-3f675168b2d6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4254430919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.4254430919 |
Directory | /workspace/6.hmac_long_msg/latest |
Test location | /workspace/coverage/default/6.hmac_smoke.2400692482 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 405406299 ps |
CPU time | 3.22 seconds |
Started | Apr 16 02:03:32 PM PDT 24 |
Finished | Apr 16 02:03:37 PM PDT 24 |
Peak memory | 199636 kb |
Host | smart-f99d6a19-f588-4db7-bfbf-c41f79fb0fe6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2400692482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2400692482 |
Directory | /workspace/6.hmac_smoke/latest |
Test location | /workspace/coverage/default/6.hmac_stress_all.4105426277 |
Short name | T537 |
Test name | |
Test status | |
Simulation time | 501356182082 ps |
CPU time | 1716.61 seconds |
Started | Apr 16 02:03:37 PM PDT 24 |
Finished | Apr 16 02:32:15 PM PDT 24 |
Peak memory | 240704 kb |
Host | smart-107d9ecd-c757-4dcd-b116-70d77f328a39 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105426277 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.4105426277 |
Directory | /workspace/6.hmac_stress_all/latest |
Test location | /workspace/coverage/default/6.hmac_test_hmac_vectors.3859684963 |
Short name | T569 |
Test name | |
Test status | |
Simulation time | 53916795 ps |
CPU time | 1.06 seconds |
Started | Apr 16 02:03:37 PM PDT 24 |
Finished | Apr 16 02:03:39 PM PDT 24 |
Peak memory | 198236 kb |
Host | smart-431b7fd6-099b-411c-bbd6-3da6782b9c25 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859684963 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 6.hmac_test_hmac_vectors.3859684963 |
Directory | /workspace/6.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/6.hmac_test_sha_vectors.4005174498 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 181668172534 ps |
CPU time | 508.62 seconds |
Started | Apr 16 02:03:41 PM PDT 24 |
Finished | Apr 16 02:12:11 PM PDT 24 |
Peak memory | 199692 kb |
Host | smart-2c3f8bcd-2c3b-4bc0-af61-963df22fdb14 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005174498 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.4005174498 |
Directory | /workspace/6.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/6.hmac_wipe_secret.3579788037 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 869931309 ps |
CPU time | 9.95 seconds |
Started | Apr 16 02:03:34 PM PDT 24 |
Finished | Apr 16 02:03:46 PM PDT 24 |
Peak memory | 199616 kb |
Host | smart-cd12425a-4492-417b-92f5-ffbda7b7bad0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3579788037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3579788037 |
Directory | /workspace/6.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/7.hmac_alert_test.3792274459 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 12234247 ps |
CPU time | 0.63 seconds |
Started | Apr 16 02:03:39 PM PDT 24 |
Finished | Apr 16 02:03:41 PM PDT 24 |
Peak memory | 194108 kb |
Host | smart-e05f772b-81b4-4d25-af42-ef2525423a33 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792274459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3792274459 |
Directory | /workspace/7.hmac_alert_test/latest |
Test location | /workspace/coverage/default/7.hmac_back_pressure.2975564388 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 1014007688 ps |
CPU time | 38.43 seconds |
Started | Apr 16 02:03:40 PM PDT 24 |
Finished | Apr 16 02:04:20 PM PDT 24 |
Peak memory | 215876 kb |
Host | smart-3c4d70e5-86c1-47f2-805e-89bd4be861e3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2975564388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2975564388 |
Directory | /workspace/7.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/7.hmac_burst_wr.1571216377 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 6370252750 ps |
CPU time | 21.46 seconds |
Started | Apr 16 02:03:41 PM PDT 24 |
Finished | Apr 16 02:04:04 PM PDT 24 |
Peak memory | 199648 kb |
Host | smart-bba180f9-76cc-4e0b-ad3d-b5a1d3793343 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1571216377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1571216377 |
Directory | /workspace/7.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/7.hmac_datapath_stress.3332750638 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 1930439747 ps |
CPU time | 110.45 seconds |
Started | Apr 16 02:03:40 PM PDT 24 |
Finished | Apr 16 02:05:32 PM PDT 24 |
Peak memory | 199560 kb |
Host | smart-016252ca-3418-45bf-9f88-0944ffd10a54 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3332750638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3332750638 |
Directory | /workspace/7.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/7.hmac_error.957024461 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 13775754245 ps |
CPU time | 48.54 seconds |
Started | Apr 16 02:03:36 PM PDT 24 |
Finished | Apr 16 02:04:26 PM PDT 24 |
Peak memory | 199704 kb |
Host | smart-0359f5d0-df5b-4aeb-aea8-fa0c379f23fd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957024461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.957024461 |
Directory | /workspace/7.hmac_error/latest |
Test location | /workspace/coverage/default/7.hmac_long_msg.2491628503 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 3281292787 ps |
CPU time | 45.87 seconds |
Started | Apr 16 02:03:39 PM PDT 24 |
Finished | Apr 16 02:04:26 PM PDT 24 |
Peak memory | 199704 kb |
Host | smart-10d96367-2963-4605-a9ba-4c0af03cf158 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2491628503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2491628503 |
Directory | /workspace/7.hmac_long_msg/latest |
Test location | /workspace/coverage/default/7.hmac_smoke.3937710892 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 1396518638 ps |
CPU time | 5.15 seconds |
Started | Apr 16 02:03:39 PM PDT 24 |
Finished | Apr 16 02:03:46 PM PDT 24 |
Peak memory | 199608 kb |
Host | smart-aeb64254-ebb6-4566-b702-9b00de73d7ad |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3937710892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3937710892 |
Directory | /workspace/7.hmac_smoke/latest |
Test location | /workspace/coverage/default/7.hmac_stress_all.248605620 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 112580055406 ps |
CPU time | 1679.81 seconds |
Started | Apr 16 02:03:38 PM PDT 24 |
Finished | Apr 16 02:31:39 PM PDT 24 |
Peak memory | 239592 kb |
Host | smart-71aec3d5-e8e8-48d1-b051-0d69b357900c |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248605620 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.248605620 |
Directory | /workspace/7.hmac_stress_all/latest |
Test location | /workspace/coverage/default/7.hmac_test_hmac_vectors.1953722054 |
Short name | T524 |
Test name | |
Test status | |
Simulation time | 172176992 ps |
CPU time | 1 seconds |
Started | Apr 16 02:03:38 PM PDT 24 |
Finished | Apr 16 02:03:40 PM PDT 24 |
Peak memory | 198980 kb |
Host | smart-bd369a21-5439-4144-9e37-87363ca7eaa6 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953722054 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.hmac_test_hmac_vectors.1953722054 |
Directory | /workspace/7.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/7.hmac_test_sha_vectors.1966934216 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 29079708626 ps |
CPU time | 419.55 seconds |
Started | Apr 16 02:03:39 PM PDT 24 |
Finished | Apr 16 02:10:41 PM PDT 24 |
Peak memory | 199736 kb |
Host | smart-9eed071d-ba2a-42fe-a5b6-3add7eba38ec |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966934216 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.1966934216 |
Directory | /workspace/7.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/7.hmac_wipe_secret.3480256725 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 1425076065 ps |
CPU time | 18.98 seconds |
Started | Apr 16 02:03:41 PM PDT 24 |
Finished | Apr 16 02:04:02 PM PDT 24 |
Peak memory | 199608 kb |
Host | smart-5126e034-813f-44cf-a990-a994fc22e357 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3480256725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3480256725 |
Directory | /workspace/7.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/8.hmac_alert_test.900808016 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 36744593 ps |
CPU time | 0.57 seconds |
Started | Apr 16 02:03:39 PM PDT 24 |
Finished | Apr 16 02:03:42 PM PDT 24 |
Peak memory | 194104 kb |
Host | smart-6d5f93ca-d499-4caf-8764-e87e4f8c14f2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900808016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.900808016 |
Directory | /workspace/8.hmac_alert_test/latest |
Test location | /workspace/coverage/default/8.hmac_back_pressure.945830913 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 637614050 ps |
CPU time | 25.08 seconds |
Started | Apr 16 02:03:42 PM PDT 24 |
Finished | Apr 16 02:04:08 PM PDT 24 |
Peak memory | 220032 kb |
Host | smart-f87a3756-7e5b-486e-b696-4f47759ef6c7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=945830913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.945830913 |
Directory | /workspace/8.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/8.hmac_burst_wr.1335380608 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 6260252008 ps |
CPU time | 56.04 seconds |
Started | Apr 16 02:03:34 PM PDT 24 |
Finished | Apr 16 02:04:32 PM PDT 24 |
Peak memory | 199684 kb |
Host | smart-600e48a5-06dd-4891-97b3-38d4612ba5e5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1335380608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1335380608 |
Directory | /workspace/8.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/8.hmac_datapath_stress.3404029693 |
Short name | T517 |
Test name | |
Test status | |
Simulation time | 345454400 ps |
CPU time | 20.97 seconds |
Started | Apr 16 02:03:41 PM PDT 24 |
Finished | Apr 16 02:04:03 PM PDT 24 |
Peak memory | 199548 kb |
Host | smart-4d6282f1-c255-4167-9e84-16e1b89e06ec |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3404029693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3404029693 |
Directory | /workspace/8.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/8.hmac_error.1625353783 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 101665354 ps |
CPU time | 2.14 seconds |
Started | Apr 16 02:03:41 PM PDT 24 |
Finished | Apr 16 02:03:45 PM PDT 24 |
Peak memory | 199436 kb |
Host | smart-ea25bdcb-f7cd-41f7-888b-43cf40c9663a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625353783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1625353783 |
Directory | /workspace/8.hmac_error/latest |
Test location | /workspace/coverage/default/8.hmac_long_msg.608182555 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 85622446506 ps |
CPU time | 105.92 seconds |
Started | Apr 16 02:03:42 PM PDT 24 |
Finished | Apr 16 02:05:29 PM PDT 24 |
Peak memory | 199736 kb |
Host | smart-784eba02-8f0a-48fc-905c-63dd15c54138 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=608182555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.608182555 |
Directory | /workspace/8.hmac_long_msg/latest |
Test location | /workspace/coverage/default/8.hmac_smoke.1696791566 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 761384163 ps |
CPU time | 6.48 seconds |
Started | Apr 16 02:03:34 PM PDT 24 |
Finished | Apr 16 02:03:42 PM PDT 24 |
Peak memory | 199604 kb |
Host | smart-b693b3a6-9de3-48cb-9b04-5b23f8167bb8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1696791566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1696791566 |
Directory | /workspace/8.hmac_smoke/latest |
Test location | /workspace/coverage/default/8.hmac_stress_all.1583154942 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 48894318881 ps |
CPU time | 444.68 seconds |
Started | Apr 16 02:03:41 PM PDT 24 |
Finished | Apr 16 02:11:07 PM PDT 24 |
Peak memory | 199704 kb |
Host | smart-c3f79721-bfc7-4650-96a1-b2fe0130d88f |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583154942 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1583154942 |
Directory | /workspace/8.hmac_stress_all/latest |
Test location | /workspace/coverage/default/8.hmac_test_hmac_vectors.4106735694 |
Short name | T503 |
Test name | |
Test status | |
Simulation time | 49207363 ps |
CPU time | 1 seconds |
Started | Apr 16 02:03:40 PM PDT 24 |
Finished | Apr 16 02:03:42 PM PDT 24 |
Peak memory | 197876 kb |
Host | smart-4bf3550b-4313-4a9f-a5ab-9bca76372c5b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106735694 -assert nopostproc +UVM_TESTNAME=hmac_base _test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.hmac_test_hmac_vectors.4106735694 |
Directory | /workspace/8.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/8.hmac_test_sha_vectors.2835294660 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 26048829978 ps |
CPU time | 508.07 seconds |
Started | Apr 16 02:03:42 PM PDT 24 |
Finished | Apr 16 02:12:11 PM PDT 24 |
Peak memory | 199692 kb |
Host | smart-964cc7d9-2400-4fc1-8fe3-5993d43f135b |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835294660 -assert nopos tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.2835294660 |
Directory | /workspace/8.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/8.hmac_wipe_secret.3800476358 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 4292813568 ps |
CPU time | 84.55 seconds |
Started | Apr 16 02:03:37 PM PDT 24 |
Finished | Apr 16 02:05:03 PM PDT 24 |
Peak memory | 199724 kb |
Host | smart-961948e8-a736-444b-ba56-b929c5e3d3f6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3800476358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3800476358 |
Directory | /workspace/8.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/81.hmac_stress_all_with_rand_reset.3844397927 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 25093480170 ps |
CPU time | 503.94 seconds |
Started | Apr 16 02:05:30 PM PDT 24 |
Finished | Apr 16 02:13:54 PM PDT 24 |
Peak memory | 207960 kb |
Host | smart-afc0659a-1bbf-49a0-a497-7371ecec590f |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3844397927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.hmac_stress_all_with_rand_reset.3844397927 |
Directory | /workspace/81.hmac_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/9.hmac_alert_test.1236018436 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 13496124 ps |
CPU time | 0.56 seconds |
Started | Apr 16 02:03:39 PM PDT 24 |
Finished | Apr 16 02:03:41 PM PDT 24 |
Peak memory | 195188 kb |
Host | smart-c5643c92-277a-48c3-aad0-bcd27ac135bd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236018436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1236018436 |
Directory | /workspace/9.hmac_alert_test/latest |
Test location | /workspace/coverage/default/9.hmac_back_pressure.784083895 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 777556646 ps |
CPU time | 24.16 seconds |
Started | Apr 16 02:03:40 PM PDT 24 |
Finished | Apr 16 02:04:06 PM PDT 24 |
Peak memory | 224216 kb |
Host | smart-90da4a2b-8d79-4a62-bb79-b4de21248348 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=784083895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.784083895 |
Directory | /workspace/9.hmac_back_pressure/latest |
Test location | /workspace/coverage/default/9.hmac_burst_wr.556622536 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 860210092 ps |
CPU time | 20.28 seconds |
Started | Apr 16 02:03:38 PM PDT 24 |
Finished | Apr 16 02:04:00 PM PDT 24 |
Peak memory | 199588 kb |
Host | smart-865aed79-a199-4eb9-b263-fa87e4a537a8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=556622536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.556622536 |
Directory | /workspace/9.hmac_burst_wr/latest |
Test location | /workspace/coverage/default/9.hmac_datapath_stress.2031392974 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 4172018443 ps |
CPU time | 37.02 seconds |
Started | Apr 16 02:03:39 PM PDT 24 |
Finished | Apr 16 02:04:17 PM PDT 24 |
Peak memory | 199712 kb |
Host | smart-9b801820-f6c7-4caa-a6e7-b83d351b83cd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2031392974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2031392974 |
Directory | /workspace/9.hmac_datapath_stress/latest |
Test location | /workspace/coverage/default/9.hmac_error.732730630 |
Short name | T540 |
Test name | |
Test status | |
Simulation time | 5322353672 ps |
CPU time | 72.82 seconds |
Started | Apr 16 02:03:39 PM PDT 24 |
Finished | Apr 16 02:04:53 PM PDT 24 |
Peak memory | 199748 kb |
Host | smart-71c9d418-b950-4bc4-8d54-a4dd81a8bbd9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732730630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.732730630 |
Directory | /workspace/9.hmac_error/latest |
Test location | /workspace/coverage/default/9.hmac_long_msg.815409644 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 842876123 ps |
CPU time | 50.55 seconds |
Started | Apr 16 02:03:41 PM PDT 24 |
Finished | Apr 16 02:04:33 PM PDT 24 |
Peak memory | 199568 kb |
Host | smart-968d93ab-5d59-4972-99aa-641f7c139004 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=815409644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.815409644 |
Directory | /workspace/9.hmac_long_msg/latest |
Test location | /workspace/coverage/default/9.hmac_smoke.3219094902 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 358111498 ps |
CPU time | 3.05 seconds |
Started | Apr 16 02:03:41 PM PDT 24 |
Finished | Apr 16 02:03:46 PM PDT 24 |
Peak memory | 199616 kb |
Host | smart-1758a12c-0ced-4776-9462-615c75d9bd31 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3219094902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3219094902 |
Directory | /workspace/9.hmac_smoke/latest |
Test location | /workspace/coverage/default/9.hmac_stress_all.610047877 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 47885293237 ps |
CPU time | 514.19 seconds |
Started | Apr 16 02:03:39 PM PDT 24 |
Finished | Apr 16 02:12:15 PM PDT 24 |
Peak memory | 199736 kb |
Host | smart-05f38dcf-2435-49f5-9975-63ef82fbf59e |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610047877 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.610047877 |
Directory | /workspace/9.hmac_stress_all/latest |
Test location | /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.599525347 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 42788587434 ps |
CPU time | 1822.05 seconds |
Started | Apr 16 02:03:40 PM PDT 24 |
Finished | Apr 16 02:34:04 PM PDT 24 |
Peak memory | 248952 kb |
Host | smart-8396c4a4-2201-4eec-9f43-1100978a963f |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=599525347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.599525347 |
Directory | /workspace/9.hmac_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/9.hmac_test_hmac_vectors.530769153 |
Short name | T501 |
Test name | |
Test status | |
Simulation time | 59145492 ps |
CPU time | 1.26 seconds |
Started | Apr 16 02:03:41 PM PDT 24 |
Finished | Apr 16 02:03:44 PM PDT 24 |
Peak memory | 199504 kb |
Host | smart-bffea876-f5e1-4e75-b532-9f3f49d6f066 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530769153 -assert nopostproc +UVM_TESTNAME=hmac_base_ test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 9.hmac_test_hmac_vectors.530769153 |
Directory | /workspace/9.hmac_test_hmac_vectors/latest |
Test location | /workspace/coverage/default/9.hmac_test_sha_vectors.503533689 |
Short name | T595 |
Test name | |
Test status | |
Simulation time | 51386565340 ps |
CPU time | 493.51 seconds |
Started | Apr 16 02:03:43 PM PDT 24 |
Finished | Apr 16 02:11:57 PM PDT 24 |
Peak memory | 199664 kb |
Host | smart-650b2760-b2bf-4cb8-92ba-4db2abfc73a7 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503533689 -assert nopost proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.503533689 |
Directory | /workspace/9.hmac_test_sha_vectors/latest |
Test location | /workspace/coverage/default/9.hmac_wipe_secret.543908715 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 9740249221 ps |
CPU time | 46.13 seconds |
Started | Apr 16 02:03:44 PM PDT 24 |
Finished | Apr 16 02:04:31 PM PDT 24 |
Peak memory | 199736 kb |
Host | smart-d5e1db8a-7383-40d4-9720-a79f09b8ed26 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=543908715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.543908715 |
Directory | /workspace/9.hmac_wipe_secret/latest |
Test location | /workspace/coverage/default/95.hmac_stress_all_with_rand_reset.1170283466 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 38247967637 ps |
CPU time | 1988.61 seconds |
Started | Apr 16 02:05:38 PM PDT 24 |
Finished | Apr 16 02:38:48 PM PDT 24 |
Peak memory | 256184 kb |
Host | smart-cdda993a-af65-44f0-8da9-4f7db4b1b5b9 |
User | root |
Command | /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1170283466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.hmac_stress_all_with_rand_reset.1170283466 |
Directory | /workspace/95.hmac_stress_all_with_rand_reset/latest |
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