Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	12797752	1			T1	32626		T2	11945		T3	648
all_values[1]	12797752	1			T1	32626		T2	11945		T3	648
all_values[2]	12797752	1			T1	32626		T2	11945		T3	648

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

89660

1

T1

1087

T6

19

T7

1403

auto[1]

38303596

1

T1

96791

T2

35835

T3

1944

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36355285

1

T1

79252

T2

35799

T3

1305

auto[1]

2037971

1

T1

18626

T2

36

T3

639

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	35167	1			T1	1087		T6	17		T7	1401
all_values[0]	auto[0]	auto[1]	444	1			T6	2		T7	2		T72	2
all_values[0]	auto[1]	auto[0]	12719677	1			T1	31521		T2	11909		T3	648
all_values[0]	auto[1]	auto[1]	42464	1			T1	18		T2	36		T4	4
all_values[1]	auto[0]	auto[0]	23346	1			T66	924		T96	993		T14	2286
all_values[1]	auto[0]	auto[1]	155	1			T17	1		T14	2		T20	1
all_values[1]	auto[1]	auto[0]	12773925	1			T1	32626		T2	11945		T3	648
all_values[1]	auto[1]	auto[1]	326	1			T17	3		T14	3		T20	1
all_values[2]	auto[0]	auto[0]	24901	1			T19	2		T64	279		T17	2
all_values[2]	auto[0]	auto[1]	5647	1			T14	4		T20	1		T15	1313
all_values[2]	auto[1]	auto[0]	10778269	1			T1	14018		T2	11945		T3	9
all_values[2]	auto[1]	auto[1]	1988935	1			T1	18608		T3	639		T7	10872