Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6122230

1

T1

4050

T2

8142

T3

3

auto[1]

2163521

1

T1

5127

T2

3449

T3

2

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2239497

1

T1

3777

T2

7782

T3

2

auto[1]

6046254

1

T1

5400

T2

3809

T3

3

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5436058

1

T1

3898

T3

4

T5

243

auto[1]

2849693

1

T1

5279

T2

11591

T3

1

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	5544267	1			T1	7154		T2	4139		T3	5
fifo_depth[1]	392407	1			T1	445		T2	796		T4	2
fifo_depth[2]	318646	1			T1	466		T2	858		T4	3
fifo_depth[3]	260474	1			T1	388		T2	842		T4	1
fifo_depth[4]	227723	1			T1	251		T2	810		T4	2
fifo_depth[5]	202938	1			T1	185		T2	815		T4	3
fifo_depth[6]	195180	1			T1	121		T2	814		T4	3
fifo_depth[7]	171888	1			T1	82		T2	770		T4	2
fifo_depth[8]	155556	1			T1	42		T2	649		T5	1
fifo_depth[9]	106494	1			T1	20		T2	486		T7	85
fifo_depth[10]	79736	1			T1	14		T2	292		T7	34
fifo_depth[11]	47438	1			T1	5		T2	165		T7	16
fifo_depth[12]	46864	1			T1	3		T2	87		T7	11
fifo_depth[13]	21743	1			T1	1		T2	43		T7	1
fifo_depth[14]	28377	1			T2	16		T7	2		T13	9
fifo_depth[15]	16599	1			T2	6		T7	1		T13	4
fifo_depth[16]	70066	1			T2	2		T13	3		T28	3

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2823553

1

T1

2023

T2

7452

T4

16

auto[1]

5462198

1

T1

7154

T2

4139

T3

5

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8203682

1

T1

9177

T2

11591

T3

5

auto[1]

82069

1

T19

7

T20

2547

T21

1

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

187531

1

T1

290

T5

9

T7

483

auto[0]

auto[0]

auto[0]

auto[1]

196353

1

T1

10

T5

8

T26

1

auto[0]

auto[0]

auto[1]

auto[0]

815417

1

T1

160

T5

10

T7

447

auto[0]

auto[0]

auto[1]

auto[1]

165099

1

T1

287

T5

16

T7

96

auto[0]

auto[1]

auto[0]

auto[0]

380298

1

T1

161

T2

3614

T5

12

auto[0]

auto[1]

auto[0]

auto[1]

369266

1

T1

654

T2

1379

T5

23

auto[0]

auto[1]

auto[1]

auto[0]

347237

1

T1

257

T2

1596

T4

16

auto[0]

auto[1]

auto[1]

auto[1]

362352

1

T1

204

T2

863

T5

27

auto[1]

auto[0]

auto[0]

auto[0]

206533

1

T1

408

T3

1

T5

33

auto[1]

auto[0]

auto[0]

auto[1]

199991

1

T1

52

T3

1

T5

31

auto[1]

auto[0]

auto[1]

auto[0]

3480397

1

T1

893

T3

2

T5

91

auto[1]

auto[0]

auto[1]

auto[1]

184737

1

T1

1798

T5

45

T6

25

auto[1]

auto[1]

auto[0]

auto[0]

361657

1

T1

904

T2

2051

T5

31

auto[1]

auto[1]

auto[0]

auto[1]

337868

1

T1

1298

T2

738

T5

274

auto[1]

auto[1]

auto[1]

auto[0]

343160

1

T1

977

T2

881

T4

8

auto[1]

auto[1]

auto[1]

auto[1]

347855

1

T1

824

T2

469

T3

1

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

386109

1

T1

698

T3

1

T5

42

auto[0]

auto[0]

auto[0]

auto[1]

385990

1

T1

62

T3

1

T5

39

auto[0]

auto[0]

auto[1]

auto[0]

4287953

1

T1

1053

T3

2

T5

101

auto[0]

auto[0]

auto[1]

auto[1]

339997

1

T1

2085

T5

61

T6

25

auto[0]

auto[1]

auto[0]

auto[0]

732154

1

T1

1065

T2

5665

T5

43

auto[0]

auto[1]

auto[0]

auto[1]

698840

1

T1

1952

T2

2117

T5

297

auto[0]

auto[1]

auto[1]

auto[0]

679521

1

T1

1234

T2

2477

T4

24

auto[0]

auto[1]

auto[1]

auto[1]

693118

1

T1

1028

T2

1332

T3

1

auto[1]

auto[0]

auto[0]

auto[0]

7955

1

T19

2

T20

60

T56

1

auto[1]

auto[0]

auto[0]

auto[1]

10354

1

T20

341

T22

2

T59

168

auto[1]

auto[0]

auto[1]

auto[0]

7861

1

T19

2

T20

334

T56

2

auto[1]

auto[0]

auto[1]

auto[1]

9839

1

T20

622

T21

1

T57

1

auto[1]

auto[1]

auto[0]

auto[0]

9801

1

T19

1

T20

630

T56

1

auto[1]

auto[1]

auto[0]

auto[1]

8294

1

T19

1

T20

12

T56

1

auto[1]

auto[1]

auto[1]

auto[0]

10876

1

T20

136

T22

1

T59

395

auto[1]

auto[1]

auto[1]

auto[1]

17089

1

T19

1

T20

412

T57

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	214488	1			T1	408		T3	1		T5	33
fifo_depth[0]	auto[0]	auto[0]	auto[1]	210345	1			T1	52		T3	1		T5	31
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3488258	1			T1	893		T3	2		T5	91
fifo_depth[0]	auto[0]	auto[1]	auto[1]	194576	1			T1	1798		T5	45		T6	25
fifo_depth[0]	auto[1]	auto[0]	auto[0]	371458	1			T1	904		T2	2051		T5	31
fifo_depth[0]	auto[1]	auto[0]	auto[1]	346162	1			T1	1298		T2	738		T5	274
fifo_depth[0]	auto[1]	auto[1]	auto[0]	354036	1			T1	977		T2	881		T4	8
fifo_depth[0]	auto[1]	auto[1]	auto[1]	364944	1			T1	824		T2	469		T3	1
fifo_depth[1]	auto[0]	auto[0]	auto[0]	16919	1			T1	45		T5	2		T7	55
fifo_depth[1]	auto[0]	auto[0]	auto[1]	16772	1			T1	3		T28	129		T120	15
fifo_depth[1]	auto[0]	auto[1]	auto[0]	188985	1			T1	43		T7	54		T13	2526
fifo_depth[1]	auto[0]	auto[1]	auto[1]	15162	1			T1	29		T7	36		T28	85
fifo_depth[1]	auto[1]	auto[0]	auto[0]	40462	1			T1	55		T2	388		T5	3
fifo_depth[1]	auto[1]	auto[0]	auto[1]	38228	1			T1	122		T2	134		T5	16
fifo_depth[1]	auto[1]	auto[1]	auto[0]	37290	1			T1	85		T2	176		T4	2
fifo_depth[1]	auto[1]	auto[1]	auto[1]	38589	1			T1	63		T2	98		T5	5
fifo_depth[2]	auto[0]	auto[0]	auto[0]	14640	1			T1	52		T5	2		T7	53
fifo_depth[2]	auto[0]	auto[0]	auto[1]	14544	1			T1	4		T26	1		T28	129
fifo_depth[2]	auto[0]	auto[1]	auto[0]	136842	1			T1	42		T7	61		T13	2336
fifo_depth[2]	auto[0]	auto[1]	auto[1]	13306	1			T1	42		T5	7		T7	24
fifo_depth[2]	auto[1]	auto[0]	auto[0]	37145	1			T1	49		T2	411		T5	3
fifo_depth[2]	auto[1]	auto[0]	auto[1]	34258	1			T1	125		T2	160		T5	6
fifo_depth[2]	auto[1]	auto[1]	auto[0]	33032	1			T1	78		T2	196		T4	3
fifo_depth[2]	auto[1]	auto[1]	auto[1]	34879	1			T1	74		T2	91		T5	8
fifo_depth[3]	auto[0]	auto[0]	auto[0]	12466	1			T1	48		T5	3		T7	56
fifo_depth[3]	auto[0]	auto[0]	auto[1]	11888	1			T1	2		T28	139		T120	15
fifo_depth[3]	auto[0]	auto[1]	auto[0]	100267	1			T1	34		T5	1		T7	42
fifo_depth[3]	auto[0]	auto[1]	auto[1]	11085	1			T1	35		T7	28		T28	83
fifo_depth[3]	auto[1]	auto[0]	auto[0]	32903	1			T1	37		T2	415		T5	2
fifo_depth[3]	auto[1]	auto[0]	auto[1]	31112	1			T1	119		T2	144		T5	1
fifo_depth[3]	auto[1]	auto[1]	auto[0]	29543	1			T1	61		T2	197		T4	1
fifo_depth[3]	auto[1]	auto[1]	auto[1]	31210	1			T1	52		T2	86		T5	6
fifo_depth[4]	auto[0]	auto[0]	auto[0]	11798	1			T1	44		T5	1		T7	52
fifo_depth[4]	auto[0]	auto[0]	auto[1]	11550	1			T1	1		T5	6		T28	123
fifo_depth[4]	auto[0]	auto[1]	auto[0]	72771	1			T1	18		T5	9		T7	50
fifo_depth[4]	auto[0]	auto[1]	auto[1]	10737	1			T1	35		T5	7		T7	8
fifo_depth[4]	auto[1]	auto[0]	auto[0]	32108	1			T1	16		T2	381		T5	1
fifo_depth[4]	auto[1]	auto[0]	auto[1]	30026	1			T1	98		T2	159		T26	1
fifo_depth[4]	auto[1]	auto[1]	auto[0]	28042	1			T1	28		T2	184		T4	2
fifo_depth[4]	auto[1]	auto[1]	auto[1]	30691	1			T1	11		T2	86		T5	3
fifo_depth[5]	auto[0]	auto[0]	auto[0]	10665	1			T1	38		T5	1		T7	54
fifo_depth[5]	auto[0]	auto[0]	auto[1]	10324	1			T28	126		T120	11		T18	3
fifo_depth[5]	auto[0]	auto[1]	auto[0]	59183	1			T1	12		T7	45		T13	1001
fifo_depth[5]	auto[0]	auto[1]	auto[1]	9736	1			T1	38		T28	88		T120	6
fifo_depth[5]	auto[1]	auto[0]	auto[0]	30247	1			T1	4		T2	405		T5	2
fifo_depth[5]	auto[1]	auto[0]	auto[1]	28049	1			T1	84		T2	164		T26	1
fifo_depth[5]	auto[1]	auto[1]	auto[0]	25985	1			T1	5		T2	168		T4	3
fifo_depth[5]	auto[1]	auto[1]	auto[1]	28749	1			T1	4		T2	78		T5	3
fifo_depth[6]	auto[0]	auto[0]	auto[0]	10601	1			T1	29		T7	58		T28	78
fifo_depth[6]	auto[0]	auto[0]	auto[1]	10628	1			T5	1		T28	122		T120	2
fifo_depth[6]	auto[0]	auto[1]	auto[0]	51862	1			T1	7		T7	40		T13	896
fifo_depth[6]	auto[0]	auto[1]	auto[1]	9620	1			T1	28		T5	2		T28	82
fifo_depth[6]	auto[1]	auto[0]	auto[0]	30350	1			T2	385		T5	1		T28	96
fifo_depth[6]	auto[1]	auto[0]	auto[1]	28129	1			T1	57		T2	165		T28	32
fifo_depth[6]	auto[1]	auto[1]	auto[0]	25926	1			T2	160		T4	3		T7	41
fifo_depth[6]	auto[1]	auto[1]	auto[1]	28064	1			T2	104		T5	2		T28	95
fifo_depth[7]	auto[0]	auto[0]	auto[0]	9770	1			T1	20		T7	46		T28	90
fifo_depth[7]	auto[0]	auto[0]	auto[1]	9431	1			T28	133		T120	2		T64	32
fifo_depth[7]	auto[0]	auto[1]	auto[0]	41477	1			T1	3		T7	45		T13	679
fifo_depth[7]	auto[0]	auto[1]	auto[1]	8586	1			T1	25		T28	76		T120	4
fifo_depth[7]	auto[1]	auto[0]	auto[0]	27582	1			T2	383		T28	84		T72	4
fifo_depth[7]	auto[1]	auto[0]	auto[1]	25656	1			T1	34		T2	141		T28	24
fifo_depth[7]	auto[1]	auto[1]	auto[0]	23670	1			T2	149		T4	2		T7	24
fifo_depth[7]	auto[1]	auto[1]	auto[1]	25716	1			T2	97		T28	86		T120	4
fifo_depth[8]	auto[0]	auto[0]	auto[0]	9696	1			T1	10		T7	43		T28	69
fifo_depth[8]	auto[0]	auto[0]	auto[1]	9323	1			T5	1		T28	106		T72	5
fifo_depth[8]	auto[0]	auto[1]	auto[0]	32312	1			T1	1		T7	35		T13	431
fifo_depth[8]	auto[0]	auto[1]	auto[1]	8406	1			T1	19		T28	58		T120	11
fifo_depth[8]	auto[1]	auto[0]	auto[0]	25336	1			T2	317		T28	88		T120	4
fifo_depth[8]	auto[1]	auto[0]	auto[1]	24126	1			T1	12		T2	123		T26	1
fifo_depth[8]	auto[1]	auto[1]	auto[0]	22703	1			T2	134		T7	11		T28	29
fifo_depth[8]	auto[1]	auto[1]	auto[1]	23654	1			T2	75		T28	65		T120	2
fifo_depth[9]	auto[0]	auto[0]	auto[0]	6551	1			T1	2		T7	36		T28	41
fifo_depth[9]	auto[0]	auto[0]	auto[1]	6210	1			T28	68		T18	2		T64	27
fifo_depth[9]	auto[0]	auto[1]	auto[0]	21540	1			T7	42		T13	281		T28	52
fifo_depth[9]	auto[0]	auto[1]	auto[1]	5711	1			T1	17		T28	36		T120	1
fifo_depth[9]	auto[1]	auto[0]	auto[0]	18027	1			T2	239		T28	61		T72	1
fifo_depth[9]	auto[1]	auto[0]	auto[1]	16374	1			T1	1		T2	78		T28	16
fifo_depth[9]	auto[1]	auto[1]	auto[0]	15640	1			T2	100		T7	7		T28	21
fifo_depth[9]	auto[1]	auto[1]	auto[1]	16441	1			T2	69		T28	60		T72	1
fifo_depth[10]	auto[0]	auto[0]	auto[0]	5331	1			T1	2		T7	16		T28	26
fifo_depth[10]	auto[0]	auto[0]	auto[1]	5033	1			T28	52		T72	2		T64	17
fifo_depth[10]	auto[0]	auto[1]	auto[0]	14661	1			T7	17		T13	174		T28	45
fifo_depth[10]	auto[0]	auto[1]	auto[1]	4200	1			T1	10		T28	25		T119	12
fifo_depth[10]	auto[1]	auto[0]	auto[0]	13519	1			T2	140		T28	35		T120	1
fifo_depth[10]	auto[1]	auto[0]	auto[1]	12650	1			T1	2		T2	58		T28	13
fifo_depth[10]	auto[1]	auto[1]	auto[0]	11228	1			T2	62		T7	1		T28	17
fifo_depth[10]	auto[1]	auto[1]	auto[1]	13114	1			T2	32		T28	30		T18	17
fifo_depth[11]	auto[0]	auto[0]	auto[0]	3567	1			T7	9		T28	10		T64	16
fifo_depth[11]	auto[0]	auto[0]	auto[1]	3138	1			T28	28		T18	2		T64	12
fifo_depth[11]	auto[0]	auto[1]	auto[0]	8565	1			T7	6		T13	88		T28	27
fifo_depth[11]	auto[0]	auto[1]	auto[1]	2843	1			T1	5		T28	15		T120	1
fifo_depth[11]	auto[1]	auto[0]	auto[0]	7985	1			T2	78		T28	21		T119	3
fifo_depth[11]	auto[1]	auto[0]	auto[1]	7204	1			T2	31		T26	1		T28	8
fifo_depth[11]	auto[1]	auto[1]	auto[0]	6943	1			T2	33		T7	1		T28	8
fifo_depth[11]	auto[1]	auto[1]	auto[1]	7193	1			T2	23		T28	19		T120	2
fifo_depth[12]	auto[0]	auto[0]	auto[0]	4480	1			T7	4		T28	5		T64	5
fifo_depth[12]	auto[0]	auto[0]	auto[1]	4253	1			T28	13		T64	10		T95	1
fifo_depth[12]	auto[0]	auto[1]	auto[0]	6745	1			T7	7		T13	35		T28	12
fifo_depth[12]	auto[0]	auto[1]	auto[1]	3297	1			T1	3		T28	4		T119	3
fifo_depth[12]	auto[1]	auto[0]	auto[0]	6962	1			T2	40		T28	13		T119	1
fifo_depth[12]	auto[1]	auto[0]	auto[1]	7588	1			T2	14		T28	3		T63	9
fifo_depth[12]	auto[1]	auto[1]	auto[0]	6801	1			T2	19		T28	5		T120	1
fifo_depth[12]	auto[1]	auto[1]	auto[1]	6738	1			T2	14		T28	8		T18	5
fifo_depth[13]	auto[0]	auto[0]	auto[0]	2291	1			T28	2		T64	2		T20	2
fifo_depth[13]	auto[0]	auto[0]	auto[1]	1695	1			T28	12		T20	15		T56	3
fifo_depth[13]	auto[0]	auto[1]	auto[0]	2907	1			T7	1		T13	16		T28	6
fifo_depth[13]	auto[0]	auto[1]	auto[1]	1851	1			T1	1		T28	4		T64	3
fifo_depth[13]	auto[1]	auto[0]	auto[0]	3432	1			T2	24		T28	2		T119	2
fifo_depth[13]	auto[1]	auto[0]	auto[1]	3336	1			T2	5		T28	1		T63	4
fifo_depth[13]	auto[1]	auto[1]	auto[0]	3294	1			T2	8		T28	2		T63	2
fifo_depth[13]	auto[1]	auto[1]	auto[1]	2937	1			T2	6		T28	2		T18	3
fifo_depth[14]	auto[0]	auto[0]	auto[0]	3261	1			T28	1		T64	1		T20	3
fifo_depth[14]	auto[0]	auto[0]	auto[1]	2879	1			T28	5		T20	6		T133	1
fifo_depth[14]	auto[0]	auto[1]	auto[0]	3222	1			T7	2		T13	9		T28	3
fifo_depth[14]	auto[0]	auto[1]	auto[1]	2619	1			T28	2		T119	1		T64	1
fifo_depth[14]	auto[1]	auto[0]	auto[0]	3951	1			T2	4		T28	4		T119	1
fifo_depth[14]	auto[1]	auto[0]	auto[1]	4637	1			T2	2		T63	2		T64	1
fifo_depth[14]	auto[1]	auto[1]	auto[0]	3415	1			T2	8		T63	1		T64	1
fifo_depth[14]	auto[1]	auto[1]	auto[1]	4393	1			T2	2		T28	1		T18	1
fifo_depth[15]	auto[0]	auto[0]	auto[0]	1922	1			T7	1		T64	1		T59	74
fifo_depth[15]	auto[0]	auto[0]	auto[1]	1604	1			T20	2		T56	2		T133	1
fifo_depth[15]	auto[0]	auto[1]	auto[0]	1443	1			T13	4		T28	2		T20	45
fifo_depth[15]	auto[0]	auto[1]	auto[1]	2109	1			T95	1		T20	2		T133	1
fifo_depth[15]	auto[1]	auto[0]	auto[0]	2332	1			T2	2		T28	1		T119	2
fifo_depth[15]	auto[1]	auto[0]	auto[1]	2720	1			T2	1		T95	1		T96	6
fifo_depth[15]	auto[1]	auto[1]	auto[0]	2427	1			T2	1		T96	3		T20	136
fifo_depth[15]	auto[1]	auto[1]	auto[1]	2042	1			T2	2		T28	1		T119	2
fifo_depth[16]	auto[0]	auto[0]	auto[0]	9499	1			T28	1		T59	240		T61	1762
fifo_depth[16]	auto[0]	auto[0]	auto[1]	9557	1			T20	7		T56	1		T133	1
fifo_depth[16]	auto[0]	auto[1]	auto[0]	10250	1			T13	3		T20	478		T56	3
fifo_depth[16]	auto[0]	auto[1]	auto[1]	7719	1			T20	4		T56	2		T59	4
fifo_depth[16]	auto[1]	auto[0]	auto[0]	8305	1			T2	2		T28	2		T66	1
fifo_depth[16]	auto[1]	auto[0]	auto[1]	8914	1			T20	137		T56	2		T134	1
fifo_depth[16]	auto[1]	auto[1]	auto[0]	10912	1			T66	1		T96	2		T20	157
fifo_depth[16]	auto[1]	auto[1]	auto[1]	4910	1			T66	1		T95	1		T20	314